diff --git a/README.md b/README.md index 6369453955..95e7b8a772 100644 --- a/README.md +++ b/README.md @@ -68,6 +68,7 @@ STMicroelectronics: * [Nucleo-F334R8](https://developer.mbed.org/platforms/ST-Nucleo-F334R8/) (Cortex-M4F) * [Nucleo-F401RE](https://developer.mbed.org/platforms/ST-Nucleo-F401RE/) (Cortex-M4F) * [Nucleo-F411RE](https://developer.mbed.org/platforms/ST-Nucleo-F411RE/) (Cortex-M4F) +* [Nucleo-L476RG](https://developer.mbed.org/platforms/ST-Nucleo-L476RG/) (Cortex-M4F) * STM32F4XX (Cortex-M4F) * STM32F3XX (Cortex-M4F) * STM32F0-Discovery (Cortex-M0) @@ -76,6 +77,7 @@ STMicroelectronics: * STM32F4-Discovery (Cortex-M4F) * STM32F429-Discovery (Cortex-M4F) * STM32L0-Discovery (Cortex-M0+) +* [STM32L4-Discovery](https://developer.mbed.org/platforms/ST-Discovery-L476VG/) (Cortex-M4F) * [Arch Max](https://developer.mbed.org/platforms/Seeed-Arch-Max/) (Cortex-M4F) diff --git a/docs/BUILDING.md b/docs/BUILDING.md index 85743b0865..68ccb74c33 100644 --- a/docs/BUILDING.md +++ b/docs/BUILDING.md @@ -135,11 +135,11 @@ LICENSE MANIFEST.in README.md libraries setup.py travis workspace_tools ``` Directory structure we are interested in: ``` - mbed/workspace_tools/ - test suite scripts, build scripts etc. - mbed/library/tests/ - mbed SDK tests, - mbed/library/tests/mbed/ - tests for mbed SDK and peripherals tests, - mbed/library/tests/net/echo/ - tests for Ethernet interface, - mbed/library/tests/rtos/mbed/ - tests for RTOS. + mbed/workspace_tools/ - test suite scripts, build scripts etc. + mbed/libraries/tests/ - mbed SDK tests, + mbed/libraries/tests/mbed/ - tests for mbed SDK and peripherals tests, + mbed/libraries/tests/net/echo/ - tests for Ethernet interface, + mbed/libraries/tests/rtos/mbed/ - tests for RTOS. ``` ### Workspace tools @@ -334,7 +334,7 @@ Build successes: * If you’re unsure which platforms and toolchains are supported please use switch ```-S``` to print simple matrix of platform to compiler dependencies. ``` -$ python python build.py -S +$ python build.py -S +-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+ | Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB | +-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+ diff --git a/docs/COMMITTERS.md b/docs/COMMITTERS.md index ecb092dad8..3cedede8df 100644 --- a/docs/COMMITTERS.md +++ b/docs/COMMITTERS.md @@ -1,6 +1,6 @@ # Committing changes to mbedmicro/mbed * Our current branching model is very simple. We are using ```master``` branch to merge all pull requests. -* Based on stable ```SHA``` version of ```master``` branch we decide to release and att he same time ```tag``` our build release. +* Based on stable ```SHA``` version of ```master``` branch we decide to release and at the same time ```tag``` our build release. * Our current release versioning follows simple integer version: ```94```, ```95```, ```96``` etc. # Committer Guide diff --git a/docs/TESTING.md b/docs/TESTING.md index 9d17e4d90d..dfbd5c0d2e 100644 --- a/docs/TESTING.md +++ b/docs/TESTING.md @@ -8,7 +8,7 @@ Each test is supervised by python script called “host test” which will at le ## What is host test? Test suite supports test supervisor concept. This concept is realized by separate Python script called ```host test```. Host tests can be found in ```mbed/workspace_tools/host_tests/``` directory. Note: In newer mbed versions (mbed OS) host tests will be separate library. -Host test script is executed in parallel with test runner to monitor test execution. Basic host test just monitors device's default serial port for test results returned by test runner. Simple tests will print test result on serial port. In other cases host tests can for example judge by test results returned by test runner is test passed or failed. It all depends on test itself. +Host test script is executed in parallel with test runner to monitor test execution. Basic host test just monitors device's default serial port for test results returned by test runner. Simple tests will print test result on serial port. In other cases host tests can for example judge by test results returned by test runner if test passed or failed. It all depends on test itself. In some cases host test can be TCP server echoing packets from test runner and judging packet loss. In other cases it can just check if values returned from accelerometer are actually valid (sane). @@ -37,7 +37,7 @@ After connecting boards to our host machine (PC) we can check which serial ports * ```NUCLEO_F103RB``` serial port is on ```COM11``` and disk drive is ```I:```. If you are working under Linux your port and disk could look like /dev/ttyACM5 and /media/usb5. -This information is needed to create ```muts_all.json``` configuration file. You can create in in ```mbed/workspace_tools/``` directory: +This information is needed to create ```muts_all.json``` configuration file. You can create it in ```mbed/workspace_tools/``` directory: ``` $ touch muts_all.json ``` @@ -289,13 +289,13 @@ $ python singletest.py -R -f RTOS ``` * Shuffle your tests. We strongly encourage you to shuffle your test order each time you execute test suite script. -Rationale: It is probable that tests executed in one particular order will pass and in other will fail. To shuffle your tests’ order please use option ```–u``` (or ```--shuffle```): +Rationale: It is probable that tests executed in one particular order will pass and in other will fail. To shuffle your tests’ order please use option ```-u``` (or ```--shuffle```): ``` $ python singletest.py -i test_spec.json -M muts_all.json --shuffle ``` -Above command with force test script to randomly generate shuffle seed and shuffle test order execution. Note: Shuffle seed is float in ```[0.0, 1.0)```. +Above command will force test script to randomly generate shuffle seed and shuffle test order execution. Note: Shuffle seed is float in ```[0.0, 1.0)```. -You can always recreate particular test order by forcing shuffle (```-u``` or ```--shuffle```} switch) and passing shuffle seed back to test suite using ```--shuffle-seed``` switch: +You can always recreate particular test order by forcing shuffle (```-u``` or ```--shuffle``` switch) and passing shuffle seed back to test suite using ```--shuffle-seed``` switch: ``` $ python singletest.py -i test_spec.json -M muts_all.json --shuffle --shuffle-seed 0.4041028336 ``` @@ -311,7 +311,7 @@ Shuffle Seed: 0.4041028336 Completed in 234.85 sec ``` -### Exmple of device configuration (one device connected to host computer) +### Example of device configuration (one device connected to host computer) This example will show you how to configure single device, run general tests or only peripheral tests. We will also show some real test result examples. @@ -597,7 +597,7 @@ Note: In dependency section we've added library ```CPPUTEST_LIBRARY``` which is ### Tests are now divided into two types: #### 'Hello world' tests -First type of test cases we call 'hello world' tests. They do not dependent on CppUTest library and are monolithic programs usually composed of one main function. Yo can find this tests in below example directories: +First type of test cases we call 'hello world' tests. They do not dependent on CppUTest library and are monolithic programs usually composed of one main function. You can find this tests in below example directories: * ```mbed/libraries/tests/mbed/``` * ```mbed/libraries/tests/net/``` @@ -767,12 +767,12 @@ TEST(BusOut_digitalout_write, led_1_nc_2_nc_nc_3) ``` ## Example -In below example we will run two example unit tests that are now available. tests ```UT_1``` and ```UT_2``` are unit tests used for now only to check if mbed SDK works with CppUTest library and if tests are being executed. In future number of unit tests will increase, nothing is also should stop you from writing and executing your own unit tests! +In below example we will run two example unit tests that are now available. tests ```UT_1``` and ```UT_2``` are unit tests used for now only to check if mbed SDK works with CppUTest library and if tests are being executed. In future number of unit tests will increase, nothing is also stopping you from writing and executing your own unit tests! ### Example configuration By default unit tests ```UT_1``` and ```UT_2``` are not automated - simply test suite will ignore them. Also we do not want to create dependency to CppUTest library each time someone executes automation. -Note: To compile ```UT_1``` and ```UT_2``` tests CppUTest library described above installation is needed and not all users wish to add UT libs to their project. Also new to mbed users may find it difficult. This is why unit testing is an extra feature active only after you deliberately install and enable needed components. +Note: To compile ```UT_1``` and ```UT_2``` tests CppUTest library described above, installation is needed and not all users wish to add UT libs to their project. Also new to mbed users may find it difficult. This is why unit testing is an extra feature active only after you deliberately install and enable needed components. Bellow snippet shows how to modify 'automated' flag so test suite will consider unit tests ```UT_1``` and ```UT_2``` as part of "automated test portfolio". Just change flag 'automated' from ```False``` to ```True```. diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c index 0b1b7da656..732b3d8f1c 100644 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c @@ -199,7 +199,6 @@ static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index); static void chk_iso_td_done(genelal_ed_t *p_g_ed); static int32_t chk_iso_ed(genelal_ed_t *p_g_ed); static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index); -static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed); static void iso_trans(genelal_ed_t *p_g_ed); #endif static void connect_check(void); @@ -215,6 +214,7 @@ static usb_ohci_reg_t *p_usb_reg = &usb_reg; static usbisr_fnc_t *p_usbisr_cb = NULL; static osSemaphoreId semid_cb = NULL; static uint32_t connect_change = 0xFFFFFFFF; +static uint32_t connect_status = 0; static uint32_t init_end = 0; static genelal_ed_t ctl_ed; static genelal_ed_t blk_ed; @@ -283,13 +283,13 @@ osThreadDef(int_ed_task_4, osPriorityNormal, 512); static void iso_ed_task_1(void const * argument) { iso_ed_task(argument); } -osThreadDef(iso_ed_task_1, osPriorityNormal, 512); +osThreadDef(iso_ed_task_1, osPriorityAboveNormal, 512); #endif #if (ISO_TRANS_MAX_NUM >= 2) static void iso_ed_task_2(void const * argument) { iso_ed_task(argument); } -osThreadDef(iso_ed_task_2, osPriorityNormal, 512); +osThreadDef(iso_ed_task_2, osPriorityAboveNormal, 512); #endif void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc) { @@ -878,25 +878,28 @@ static void control_trans(genelal_ed_t *p_g_ed) { p_g_ed->pipe_no = USB_HOST_PIPE0; p_g_ed->trans_wait = 1; - - if (td_info.direction == 0) { - uint16_t Req = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0]; - uint16_t Val = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2]; - uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4]; - uint16_t Len = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6]; - - g_usbx_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd; - usbx_host_SetupStage(Req, Val, Indx, Len); - } else if (td_info.direction == 1) { - usbx_host_CtrlWriteStart(td_info.count, p_td->currBufPtr); + if (connect_status == 0) { + ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING); } else { - usbx_host_CtrlReadStart(td_info.count, p_td->currBufPtr); - } + if (td_info.direction == 0) { + uint16_t Req = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0]; + uint16_t Val = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2]; + uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4]; + uint16_t Len = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6]; - (void)osSemaphoreWait(p_g_ed->semid_wait, CTL_TRANS_TIMEOUT); - if (p_g_ed->trans_wait == 1) { - p_g_ed->trans_wait = 0; - RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); + g_usbx_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd; + usbx_host_SetupStage(Req, Val, Indx, Len); + } else if (td_info.direction == 1) { + usbx_host_CtrlWriteStart(td_info.count, p_td->currBufPtr); + } else { + usbx_host_CtrlReadStart(td_info.count, p_td->currBufPtr); + } + + (void)osSemaphoreWait(p_g_ed->semid_wait, CTL_TRANS_TIMEOUT); + if (p_g_ed->trans_wait == 1) { + p_g_ed->trans_wait = 0; + RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC); + } } g_usbx_host_CmdStage &= (~USB_HOST_CMD_FIELD); @@ -928,14 +931,18 @@ static void bulk_trans(genelal_ed_t *p_g_ed) { set_togle(p_g_ed->pipe_no, p_td, p_ed); p_g_ed->trans_wait = 1; - if (td_info.direction == 1) { - usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + if (connect_status == 0) { + ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING); } else { - usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); - } + if (td_info.direction == 1) { + usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + } else { + usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + } - (void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT); - usbx_host_stop_transfer(p_g_ed->pipe_no); + (void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT); + usbx_host_stop_transfer(p_g_ed->pipe_no); + } } static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) { @@ -1023,10 +1030,14 @@ static void int_trans(genelal_ed_t *p_g_ed) { get_td_info(p_g_ed, &td_info); p_g_ed->trans_wait = 1; - if (td_info.direction == 1) { - usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + if (connect_status == 0) { + ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING); } else { - usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + if (td_info.direction == 1) { + usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + } else { + usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr); + } } } @@ -1089,7 +1100,6 @@ static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) { static void iso_ed_task(void const * argument) { genelal_ed_t *p_iso_ed = &iso_ed[(uint32_t)argument]; uint32_t wait_cnt = 0; - uint32_t wait_time = 0; hcca_t *p_hcca; hced_t *p_ed; @@ -1115,17 +1125,26 @@ static void iso_ed_task(void const * argument) { if (p_iso_ed->p_curr_ed != NULL) { while ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0) { if (chk_iso_ed(p_iso_ed) != 0) { - wait_time = iso_chk_starting_frame(p_iso_ed); - if (wait_time != 0) { - osDelay(wait_time); - p_usb_reg->HcFmNumber += wait_time; - p_usb_reg->HcFmNumber &= 0x0000FFFF; + hcisotd_t *p_isotd = (hcisotd_t *)p_iso_ed->p_curr_td; + uint32_t starting_frame = p_isotd->control & 0x0000FFFF; + uint32_t wait_time = 0; + uint32_t wk_HcFmNumber = p_usb_reg->HcFmNumber; + + if (starting_frame > wk_HcFmNumber) { + wait_time = starting_frame - wk_HcFmNumber; + } else { + wait_time = (0xFFFF - wk_HcFmNumber) + starting_frame; + } + if ((wait_time >= 2) && (wait_time <= 1000)) { + for (int cnt = 0; cnt < (wait_time - 1); cnt++) { + osDelay(1); + p_usb_reg->HcFmNumber = (wk_HcFmNumber + cnt) & 0x0000FFFF; + } } p_iso_ed->psw_idx = 0; iso_trans(p_iso_ed); (void)osSemaphoreWait(p_iso_ed->semid_wait, osWaitForever); - usbx_host_stop_transfer(p_iso_ed->pipe_no); - wait_cnt = 1; + wait_cnt = 8; } else { if (wait_cnt > 0) { wait_cnt--; @@ -1234,18 +1253,6 @@ static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) { usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table); } -static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed) { - hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td; - uint32_t starting_frame = p_isotd->control & 0x0000FFFF; - uint32_t wait_time = 0; - - if ((p_g_ed->psw_idx == 0) && (starting_frame > p_usb_reg->HcFmNumber)) { - wait_time = starting_frame - p_usb_reg->HcFmNumber; - } - - return wait_time; -} - static void iso_trans(genelal_ed_t *p_g_ed) { hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td; tdinfo_t td_info; @@ -1268,10 +1275,14 @@ static void iso_trans(genelal_ed_t *p_g_ed) { get_td_info(p_g_ed, &td_info); p_g_ed->trans_wait = 1; - if (td_info.direction == 1) { - usbx_host_start_send_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr); + if (connect_status == 0) { + ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING); } else { - usbx_host_start_receive_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr); + if (td_info.direction == 1) { + usbx_host_start_send_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr); + } else { + usbx_host_start_receive_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr); + } } } #endif @@ -1326,6 +1337,7 @@ static void connect_check(void) { void ohciwrapp_loc_Connect(uint32_t type) { uint32_t cnt; + connect_status = type; connect_change = type; if (type == 0) { if (ctl_ed.trans_wait == 1) { @@ -1445,11 +1457,7 @@ void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) { if (p_isotd != NULL) { usbx_host_stop_transfer(pipe); - if (p_usb_reg->HcFmNumber < 0x0000FFFF) { - p_usb_reg->HcFmNumber++; - } else { - p_usb_reg->HcFmNumber = 0; - } + p_usb_reg->HcFmNumber = ((p_isotd->control & 0x0000FFFF) + p_wait_ed->psw_idx) & 0x0000FFFF; /* Size of packet */ p_isotd->offsetPSW[p_wait_ed->psw_idx] -= g_usbx_host_data_count[pipe]; @@ -1469,10 +1477,8 @@ void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) { p_wait_ed->psw_idx++; } if (chk_iso_ed(p_wait_ed) != 0) { - if (iso_chk_starting_frame(p_wait_ed) == 0) { - iso_trans(p_wait_ed); - next_trans = 1; - } + iso_trans(p_wait_ed); + next_trans = 1; } if (next_trans == 0) { p_wait_ed->trans_wait = 0; diff --git a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c index 2a6d126ddc..44dcd88670 100644 --- a/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c +++ b/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c @@ -51,12 +51,12 @@ Exported global variables and functions (to be accessed by other files) /* Endpoint Configuration Data Format */ /********************************************************************************************************/ /* LINE1: Pipe Window Select Register */ -/* CPU Access PIPE : PIPE1 to PIPE9 [ ### SET ### ] */ +/* CPU Access PIPE : USB_HOST_PIPE1 to USB_HOST_PIPE9 [ ### SET ### ] */ /* LINE2: Pipe Configuration Register */ /* Transfer Type : USB_HOST_NONE [ USB_HOST_NONE ] */ /* Buffer Ready interrupt : USB_HOST_NONE [ USB_HOST_NONE ] */ -/* Double Buffer Mode : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */ -/* Continuous Transmit: : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */ +/* Double Buffer Mode : USB_HOST_DBLBON / USB_HOST_DBLBOFF [ ### SET ### ] */ +/* Continuous Transmit: : USB_HOST_CNTMDON / USB_HOST_CNTMDOFF [ ### SET ### ] */ /* Short NAK : USB_HOST_NONE [ USB_HOST_NONE ] */ /* Transfer Direction : USB_HOST_NONE [ USB_HOST_NONE ] */ /* Endpoint Number : USB_HOST_NONE [ USB_HOST_NONE ] */ @@ -72,8 +72,7 @@ Exported global variables and functions (to be accessed by other files) /* LINE6: use FIFO port */ /* : USB_HOST_CUSE [ ### SET ### ] */ /* : USB_HOST_D0USE / USB_HOST_D1USE */ -/* : USB_HOST_D0DMA / USB_HOST_D0DMA */ -/* LINE7: use FIFO port Endian : USB_HOST_FIFO_BIG / USB_HOST_FIFO_LITTLE [ #SET# ] */ +/* : USB_HOST_D0DMA / USB_HOST_D0DMA */ /********************************************************************************************************/ /* Device Address 1 */ @@ -105,7 +104,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] = { USB_HOST_PIPE6, /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40), USB_HOST_NONE, USB_HOST_NONE, @@ -115,7 +114,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] = { USB_HOST_PIPE7, /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41), USB_HOST_NONE, USB_HOST_NONE, @@ -125,7 +124,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] = { USB_HOST_PIPE8, /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42), USB_HOST_NONE, USB_HOST_NONE, @@ -135,7 +134,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] = { USB_HOST_PIPE9, /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43), USB_HOST_NONE, USB_HOST_NONE, @@ -158,7 +157,7 @@ USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[ ] = { USB_HOST_PIPE1, /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(44), USB_HOST_NONE, USB_HOST_NONE, @@ -168,8 +167,8 @@ USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[ ] = { USB_HOST_PIPE2, /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */ - USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, - (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(60), + USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE, + (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(76), USB_HOST_NONE, USB_HOST_NONE, USB_HOST_D1USE diff --git a/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp b/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp index 38213c76a2..354dbc6c54 100644 --- a/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp +++ b/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp @@ -261,17 +261,7 @@ void USBHALHost::UsbIrqhandler() { //Root device disconnected else { - - if (!(int_status & OR_INTR_STATUS_WDH)) { - usb_hcca->DoneHead = 0; - } - deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE); - - if (int_status & OR_INTR_STATUS_WDH) { - usb_hcca->DoneHead = 0; - ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH); - } } } ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC); diff --git a/libraries/mbed/.yotta_ignore b/libraries/mbed/.yotta_ignore new file mode 100644 index 0000000000..91d629dd18 --- /dev/null +++ b/libraries/mbed/.yotta_ignore @@ -0,0 +1,14 @@ +# ignore files for targets that aren't supported by the yotta build (to +# minimise the size of the published module) + +TARGET_ARM_SSG +TARGET_Freescale +TARGET_RENESAS +TARGET_Silicon_Labs +TARGET_Atmel +TARGET_Maxim +TARGET_NXP +TARGET_STM +TARGET_WIZNET +TOOLCHAIN_IAR + diff --git a/libraries/mbed/api/mbed.h b/libraries/mbed/api/mbed.h index b408c4d893..868b93f519 100644 --- a/libraries/mbed/api/mbed.h +++ b/libraries/mbed/api/mbed.h @@ -16,7 +16,7 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 106 +#define MBED_LIBRARY_VERSION 109 #include "platform.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h new file mode 100644 index 0000000000..6c1b55ec69 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h @@ -0,0 +1,769 @@ +/**************************************************************************//** + * @file CMSDK_BEID.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * CMSDK_BEID Device + * @version V3.02 + * @date 15. November 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef CMSDK_BEID_H +#define CMSDK_BEID_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ---------------------- CMSDK_BEID Specific Interrupt Numbers ------------------ */ + UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ + UARTRX3_IRQn = 6, /* Was PORT0_ALL_IRQn Port 1 combined Interrupt */ + UARTTX3_IRQn = 7, /* Was PORT1_ALL_IRQn Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ + SPI_IRQn = 11, /* SPI Interrupt */ + UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /* Ethernet Interrupt */ + I2S_IRQn = 14, /* I2S Interrupt */ + TSC_IRQn = 15, /* Touch Screen Interrupt */ +// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ + PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ + PORT0_1_IRQn = 17, /* There are 16 pins in total */ + PORT0_2_IRQn = 18, + PORT0_3_IRQn = 19, + PORT0_4_IRQn = 20, + PORT0_5_IRQn = 21, + PORT0_6_IRQn = 22, + PORT0_7_IRQn = 23, + PORT0_8_IRQn = 24, + PORT0_9_IRQn = 25, + PORT0_10_IRQn = 26, + PORT0_11_IRQn = 27, + PORT0_12_IRQn = 28, + PORT0_13_IRQn = 29, + PORT0_14_IRQn = 30, + PORT0_15_IRQn = 31, +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ +#define __CM3_REV 0x0201 /* Core revision r2p1 */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include /* Processor and core peripherals */ +#include "system_CMSDK_BEID.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined ( __CC_ARM ) + #pragma push +#pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ + uint32_t RESERVED0[3]; + __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */ + __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */ + uint32_t RESERVED1[2]; + __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */ + __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */ + uint32_t RESERVED2[2]; + __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */ + __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */ + __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */ + __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */ + __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */ + __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */ + uint32_t RESERVED3[10]; + __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */ + __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */ + __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */ + __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */ + __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */ + __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */ + uint32_t RESERVED4[2]; + __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */ + __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */ + __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */ + __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */ + __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */ + __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */ + uint32_t RESERVED5[2]; + __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */ + __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */ + __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */ + __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */ + __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */ + __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */ + __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */ + __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */ + __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */ + __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */ + uint32_t RESERVED6[2]; + __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */ + __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */ + __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */ + uint32_t RESERVED7[1]; + __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */ + __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */ + __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ + +} CMSDK_PL230_TypeDef; + +#define PL230_DMA_CHNL_BITS 0 + +#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ +#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ +#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ + +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ + +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ + +#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ +#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ +#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ + +#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ +#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ + +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ + +#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ +#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ +#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ +#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ +#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ +#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ +#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ + +#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ +#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined ( __CC_ARM ) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) +#define CMSDK_SRAM_BASE (0x20000000UL) +#define CMSDK_PERIPH_BASE (0x40000000UL) + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) +#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) + + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_BEID_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h new file mode 100644 index 0000000000..a0c3199080 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h @@ -0,0 +1,616 @@ +/* + * Copyright: + * ---------------------------------------------------------------- + * This confidential and proprietary software may be used only as + * authorised by a licensing agreement from ARM Limited + * (C) COPYRIGHT 2014 ARM Limited + * ALL RIGHTS RESERVED + * The entire notice above must be reproduced on all authorised + * copies and copies may only be made to the extent permitted + * by a licensing agreement from ARM Limited. + * ---------------------------------------------------------------- + * File: smm_mps2.h + * Release: Version 1.0 + * ---------------------------------------------------------------- + */ + +#ifndef __SMM_MPS2_H +#define __SMM_MPS2_H + +#include "peripherallink.h" /* device specific header file */ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* FPGA System Register declaration */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS +} MPS2_FPGAIO_TypeDef; + +// MISC register bit definitions + +#define CLCD_CS_Pos 0 +#define CLCD_CS_Msk (1UL< CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error + }; + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT +} MPS2_I2S_TypeDef; + +#define I2S_CONTROL_TXEN_Pos 0 +#define I2S_CONTROL_TXEN_Msk (1UL<> (lsb)) +#define INSERT_BITS(arg, msb, lsb, value) \ + ((arg) = ((arg) & ~CREATE_MASK(msb, lsb)) | (((value) << (lsb)) & CREATE_MASK(msb, lsb))) + +#define MASK_FIELD(arg, field) MASK_BITS(arg, field##_MSB, field##_LSB) +#define EXTRACT_FIELD(arg, field) EXTRACT_BITS(arg, field##_MSB, field##_LSB) +#define INSERT_FIELD(arg, field, value) INSERT_BITS(arg, field##_MSB, field##_LSB, value) + +#define SET_BIT(arg, bit) ((arg) |= (1 << (bit))) +#define CLEAR_BIT(arg, bit) ((arg) &= ~(1 << (bit))) +#define TEST_BIT(arg, bit) ((arg) & (1 << (bit))) + +#ifndef NoOfElements +#define NoOfElements(array) (sizeof(array) / sizeof(array[0])) +#endif + +#endif /* __SMM_MPS2_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct new file mode 100644 index 0000000000..2afd726abe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* + + LR_IROM1 0x00000000 0x00400000 { ; load region size_region + ER_IROM1 +0 { ; load address = execution address + *.o (RESET, +FIRST) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 +0 { ; RW data + .ANY (+RW +ZI) + } + } + diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s new file mode 100644 index 0000000000..e67bee5a75 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s @@ -0,0 +1,291 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM3.s +; * @brief CMSIS Core Device Startup File for +; * CMSDK_CM3 Device +; * @version V3.02 +; * @date 15. November 2013 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2013 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h new file mode 100644 index 0000000000..f34873c269 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h @@ -0,0 +1,14 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC1768 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_BEID.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c new file mode 100644 index 0000000000..6b8c4a27d5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c @@ -0,0 +1,30 @@ +/* mbed Microcontroller Library - cmsis_nvic for LCP1768 + * Copyright (c) 2009-2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h new file mode 100644 index 0000000000..600de99554 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h @@ -0,0 +1,26 @@ +/* mbed Microcontroller Library - cmsis_nvic + * Copyright (c) 2009-2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_NUM_VECTORS (16 + 32) +#define NVIC_USER_IRQ_OFFSET 16 + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h new file mode 100644 index 0000000000..6f031cd4ae --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h @@ -0,0 +1,34 @@ +/*----------------------------------------------------------------------------- + * Name: Device.h + * Purpose: Include the correct device header file + *----------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2013 KEIL - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#elif defined CMSDK_BEID + #include "CMSDK_BEID.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c new file mode 100644 index 0000000000..02946c0cfe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c @@ -0,0 +1,95 @@ +/**************************************************************************//** + * @file system_CMSDK_BEID.c + * @brief CMSIS Device System Source File for + * CMSDK_M3 Device + * @version V3.02 + * @date 15. November 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#include "CMSDK_BEID.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (50000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (__XTAL / 2) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = __SYSTEM_CLOCK; + + // Enable AHB and APB clock + CMSDK_SYSCON->AHBCLKCFG0SET = 0xF; // GPIO + CMSDK_SYSCON->APBCLKCFG0SET = 0x37; // UART0, UART1, TIMER0, TIMER1, DUAL TIMER +} diff --git a/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h new file mode 100644 index 0000000000..c61fc631f5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file system_CMSDK_BEID.h + * @brief CMSIS Device Peripheral Access Layer Header File for + * CMSDK_BEID Device + * @version V3.02 + * @date 15. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_CMSDK_BEID_H +#define SYSTEM_CMSDK_BEID_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_BEID_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct new file mode 100644 index 0000000000..ae0aa0031d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct @@ -0,0 +1,19 @@ +;SAMD21G18A +;256KB FLASH (0x40000) @ 0x000000000 +;2KB RAM (0x8000) @ 0x20000000 + + +;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment + RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s new file mode 100644 index 0000000000..1b8b9ba547 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_STD/SAMD21G18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_STD/SAMD21G18A.sct new file mode 100644 index 0000000000..ae0aa0031d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_STD/SAMD21G18A.sct @@ -0,0 +1,19 @@ +;SAMD21G18A +;256KB FLASH (0x40000) @ 0x000000000 +;2KB RAM (0x8000) @ 0x20000000 + + +;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment + RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_STD/startup_SAMD21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_STD/startup_SAMD21.s new file mode 100644 index 0000000000..1b8b9ba547 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_STD/startup_SAMD21.s @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/samd21g18a.ld b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/samd21g18a.ld new file mode 100644 index 0000000000..b8c2983cd6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/samd21g18a.ld @@ -0,0 +1,118 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY { + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4 + } + + /* The stack size used by the application. NOTE: you need to adjust according to your application. */ + STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + + /* Section Definitions */ + SECTIONS { +.text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); +.ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + +.relocate : + AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + .heap (NOLOAD) : + { + . = ALIGN(4); + __end__ = . ; + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/startup_samd21.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/startup_samd21.c diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_IAR/startup_samd21.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_IAR/startup_samd21.c diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct new file mode 100644 index 0000000000..2fa9c77d26 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct @@ -0,0 +1,19 @@ +;SAMD21J18A +;256KB FLASH (0x40000) @ 0x000000000 +;2KB RAM (0x8000) @ 0x20000000 + + +;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment + RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s new file mode 100644 index 0000000000..1b8b9ba547 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/SAMD21J18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/SAMD21J18A.sct new file mode 100644 index 0000000000..2fa9c77d26 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/SAMD21J18A.sct @@ -0,0 +1,19 @@ +;SAMD21J18A +;256KB FLASH (0x40000) @ 0x000000000 +;2KB RAM (0x8000) @ 0x20000000 + + +;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment + RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/startup_SAMD21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/startup_SAMD21.s new file mode 100644 index 0000000000..1b8b9ba547 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/startup_SAMD21.s @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld similarity index 77% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld index 218f7deedc..b8c2983cd6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld @@ -3,19 +3,17 @@ OUTPUT_ARCH(arm) SEARCH_DIR(.) /* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 -} +MEMORY { + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4 + } -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + /* The stack size used by the application. NOTE: you need to adjust according to your application. */ + STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; -/* Section Definitions */ -SECTIONS -{ - .text : + /* Section Definitions */ + SECTIONS { +.text : { . = ALIGN(4); _sfixed = .; @@ -66,23 +64,17 @@ SECTIONS /* .ARM.exidx is sorted, so has to go in its own output section. */ PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : +.ARM.exidx : { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > rom PROVIDE_HIDDEN (__exidx_end = .); . = ALIGN(4); _etext = .; - - .dvectors (NOLOAD) : - { - _sdvectors = .; - . = . + 0xB0; - _edvectors = .; - } > ram - .relocate : AT (_etext) +.relocate : + AT (_etext) { . = ALIGN(4); _srelocate = .; @@ -105,12 +97,12 @@ SECTIONS _ezero = .; } > ram - .heap (NOLOAD) : - { - . = ALIGN(4); - __end__ = . ; - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - } > ram + .heap (NOLOAD) : + { + . = ALIGN(4); + __end__ = . ; + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + } > ram /* stack section */ .stack (NOLOAD): diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c new file mode 100644 index 0000000000..cb64012fe8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c @@ -0,0 +1,158 @@ +#include "samd21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + (void*) (&_estack), + + (void*) Reset_Handler, + (void*) NMI_Handler, + (void*) HardFault_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) SVC_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) PendSV_Handler, + (void*) SysTick_Handler, + + /* Configurable interrupts */ + (void*) PM_Handler, /* 0 Power Manager */ + (void*) SYSCTRL_Handler, /* 1 System Control */ + (void*) WDT_Handler, /* 2 Watchdog Timer */ + (void*) RTC_Handler, /* 3 Real-Time Counter */ + (void*) EIC_Handler, /* 4 External Interrupt Controller */ + (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ + (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ + (void*) USB_Handler, /* 7 Universal Serial Bus */ + (void*) EVSYS_Handler, /* 8 Event System Interface */ + (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ + (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ + (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ + (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ + (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ + (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ + (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ + (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ + (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ + (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ + (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ + (void*) ADC_Handler, /* 23 Analog Digital Converter */ + (void*) AC_Handler, /* 24 Analog Comparators */ + (void*) DAC_Handler, /* 25 Digital Analog Converter */ + (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ + (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ // expected to be done by MBED OS + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c new file mode 100644 index 0000000000..9476ec86ed --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c @@ -0,0 +1,173 @@ +#include "samd21.h" + +void __iar_program_start(void); +int __low_level_init(void); + +void Dummy_Handler(void); +void Reset_Handler(void); + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} + +/* Cortex-M0+ core handlers */ +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* Cortex-M0+ core handlers */ +#pragma weak NMI_Handler = Dummy_Handler +#pragma weak HardFault_Handler = Dummy_Handler +#pragma weak SVC_Handler = Dummy_Handler +#pragma weak PendSV_Handler = Dummy_Handler +#pragma weak SysTick_Handler = Dummy_Handler + +/* Peripherals handlers */ +#pragma weak PM_Handler = Dummy_Handler +#pragma weak SYSCTRL_Handler = Dummy_Handler +#pragma weak WDT_Handler = Dummy_Handler +#pragma weak RTC_Handler = Dummy_Handler +#pragma weak EIC_Handler = Dummy_Handler +#pragma weak NVMCTRL_Handler = Dummy_Handler +#pragma weak DMAC_Handler = Dummy_Handler +#pragma weak USB_Handler = Dummy_Handler +#pragma weak EVSYS_Handler = Dummy_Handler +#pragma weak SERCOM0_Handler = Dummy_Handler +#pragma weak SERCOM1_Handler = Dummy_Handler +#pragma weak SERCOM2_Handler = Dummy_Handler +#pragma weak SERCOM3_Handler = Dummy_Handler +#pragma weak SERCOM4_Handler = Dummy_Handler +#pragma weak SERCOM5_Handler = Dummy_Handler +#pragma weak TCC0_Handler = Dummy_Handler +#pragma weak TCC1_Handler = Dummy_Handler +#pragma weak TCC2_Handler = Dummy_Handler +#pragma weak TC3_Handler = Dummy_Handler +#pragma weak TC4_Handler = Dummy_Handler +#pragma weak TC5_Handler = Dummy_Handler +#pragma weak TC6_Handler = Dummy_Handler +#pragma weak TC7_Handler = Dummy_Handler +#pragma weak ADC_Handler = Dummy_Handler +#pragma weak AC_Handler = Dummy_Handler +#pragma weak DAC_Handler = Dummy_Handler +#pragma weak PTC_Handler = Dummy_Handler +#pragma weak I2S_Handler = Dummy_Handler + +/* Exception Table */ +#pragma language=extended +#pragma segment="CSTACK" + +/* The name "__vector_table" has special meaning for C-SPY: */ +/* it is where the SP start value is found, and the NVIC vector */ +/* table register (VTOR) is initialized to this address if != 0 */ + +#pragma section = ".intvec" +#pragma location = ".intvec" +//! [startup_vector_table] +const DeviceVectors __vector_table[] = { + __sfe("CSTACK"), + (void*) __iar_program_start, + (void*) NMI_Handler, + (void*) HardFault_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) SVC_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) PendSV_Handler, + (void*) SysTick_Handler, + + /* Configurable interrupts */ + (void*) PM_Handler, /* 0 Power Manager */ + (void*) SYSCTRL_Handler, /* 1 System Control */ + (void*) WDT_Handler, /* 2 Watchdog Timer */ + (void*) RTC_Handler, /* 3 Real-Time Counter */ + (void*) EIC_Handler, /* 4 External Interrupt Controller */ + (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ + (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ + (void*) USB_Handler, /* 7 Universal Serial Bus */ + (void*) EVSYS_Handler, /* 8 Event System Interface */ + (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ + (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ + (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ + (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ + (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ + (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ + (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ + (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ + (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ + (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ + (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ + (void*) ADC_Handler, /* 23 Analog Digital Converter */ + (void*) AC_Handler, /* 24 Analog Comparators */ + (void*) DAC_Handler, /* 25 Digital Analog Converter */ + (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ + (void*) I2S_Handler /* 27 Inter-IC Sound Interface */ +}; +//! [startup_vector_table] + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +int __low_level_init(void) +{ + uint32_t *pSrc = __section_begin(".intvec"); + + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + return 1; /* if return 0, the data sections will not be initialized */ +} + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __iar_program_start(); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/cmsis.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/cmsis.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/cmsis.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/cmsis_nvic.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/cmsis_nvic.c rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/cmsis_nvic.c diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/cmsis_nvic.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/cmsis_nvic.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/cmsis_nvic.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct new file mode 100644 index 0000000000..eb079ebbc0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct @@ -0,0 +1,29 @@ +; +SAML21J18A +; +256KB FLASH (0x40000) @ 0x000000000 +; +2KB RAM (0x8000) @ 0x20000000 + + +; +SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; + load region size_region + ER_IROM1 0x00000000 0x40000 { ; + load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; + [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment + RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) + { + ; + RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/startup_SAML21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/startup_SAML21.s new file mode 100644 index 0000000000..ee5d73740b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/startup_SAML21.s @@ -0,0 +1,194 @@ +;/**************************************************************************//** +; * @file startup_SAML21.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Atmel SAML21 Device Series +; * @version V1.00 +; * @date 10. February 2015 +; * +; * @note +; * Copyright (C) 2015 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ;Top of RAM + + PRESERVE8 + THUMB + + +;Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ;Top of Stack + DCD Reset_Handler ;Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator + DCD WDT_Handler ;1 Watchdog Timer + DCD RTC_Handler ;2 Real-Time Counter + DCD EIC_Handler ;3 External Interrupt Controller + DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller + DCD DMAC_Handler ;5 Direct Memory Access Controller + DCD USB_Handler ;6 Universal Serial Bus + DCD EVSYS_Handler ;7 Event System Interface + DCD SERCOM0_Handler ;8 Serial Communication Interface 0 + DCD SERCOM1_Handler ;9 Serial Communication Interface 1 + DCD SERCOM2_Handler ;10 Serial Communication Interface 2 + DCD SERCOM3_Handler ;11 Serial Communication Interface 3 + DCD SERCOM4_Handler ;12 Serial Communication Interface 4 + DCD SERCOM5_Handler ;13 Serial Communication Interface 5 + DCD TCC0_Handler ;14 Timer Counter Control 0 + DCD TCC1_Handler ;15 Timer Counter Control 1 + DCD TCC2_Handler ;16 Timer Counter Control 2 + DCD TC0_Handler ;17 Basic Timer Counter 0 + DCD TC1_Handler ;18 Basic Timer Counter 1 + DCD TC2_Handler ;19 Basic Timer Counter 2 + DCD TC3_Handler ;20 Basic Timer Counter 3 + DCD TC4_Handler ;21 Basic Timer Counter 4 + DCD ADC_Handler ;22 Analog Digital Converter + DCD AC_Handler ;23 Analog Comparators + DCD DAC_Handler ;24 Digital-to-Analog Converter + DCD PTC_Handler ;25 Peripheral Touch Controller + DCD AES_Handler ;26 Advanced Encryption Standard + DCD TRNG_Handler ;27 True Random Generator + DCD PICOP_Handler ;28 PicoProcessor +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +;Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +;Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT SYSTEM_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT AES_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + EXPORT PICOP_Handler [WEAK] + +SYSTEM_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +AES_Handler +TRNG_Handler +PICOP_Handler + B . + ENDP + + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/SAML21J18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/SAML21J18A.sct new file mode 100644 index 0000000000..eb079ebbc0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/SAML21J18A.sct @@ -0,0 +1,29 @@ +; +SAML21J18A +; +256KB FLASH (0x40000) @ 0x000000000 +; +2KB RAM (0x8000) @ 0x20000000 + + +; +SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; + load region size_region + ER_IROM1 0x00000000 0x40000 { ; + load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; + [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment + RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) + { + ; + RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/startup_SAML21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/startup_SAML21.s new file mode 100644 index 0000000000..ee5d73740b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/startup_SAML21.s @@ -0,0 +1,194 @@ +;/**************************************************************************//** +; * @file startup_SAML21.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Atmel SAML21 Device Series +; * @version V1.00 +; * @date 10. February 2015 +; * +; * @note +; * Copyright (C) 2015 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ;Top of RAM + + PRESERVE8 + THUMB + + +;Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ;Top of Stack + DCD Reset_Handler ;Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator + DCD WDT_Handler ;1 Watchdog Timer + DCD RTC_Handler ;2 Real-Time Counter + DCD EIC_Handler ;3 External Interrupt Controller + DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller + DCD DMAC_Handler ;5 Direct Memory Access Controller + DCD USB_Handler ;6 Universal Serial Bus + DCD EVSYS_Handler ;7 Event System Interface + DCD SERCOM0_Handler ;8 Serial Communication Interface 0 + DCD SERCOM1_Handler ;9 Serial Communication Interface 1 + DCD SERCOM2_Handler ;10 Serial Communication Interface 2 + DCD SERCOM3_Handler ;11 Serial Communication Interface 3 + DCD SERCOM4_Handler ;12 Serial Communication Interface 4 + DCD SERCOM5_Handler ;13 Serial Communication Interface 5 + DCD TCC0_Handler ;14 Timer Counter Control 0 + DCD TCC1_Handler ;15 Timer Counter Control 1 + DCD TCC2_Handler ;16 Timer Counter Control 2 + DCD TC0_Handler ;17 Basic Timer Counter 0 + DCD TC1_Handler ;18 Basic Timer Counter 1 + DCD TC2_Handler ;19 Basic Timer Counter 2 + DCD TC3_Handler ;20 Basic Timer Counter 3 + DCD TC4_Handler ;21 Basic Timer Counter 4 + DCD ADC_Handler ;22 Analog Digital Converter + DCD AC_Handler ;23 Analog Comparators + DCD DAC_Handler ;24 Digital-to-Analog Converter + DCD PTC_Handler ;25 Peripheral Touch Controller + DCD AES_Handler ;26 Advanced Encryption Standard + DCD TRNG_Handler ;27 True Random Generator + DCD PICOP_Handler ;28 PicoProcessor +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +;Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +;Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT SYSTEM_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT AES_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + EXPORT PICOP_Handler [WEAK] + +SYSTEM_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +AES_Handler +TRNG_Handler +PICOP_Handler + B . + ENDP + + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_GCC_ARM/saml21j18a.ld b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_GCC_ARM/saml21j18a.ld new file mode 100644 index 0000000000..b8c2983cd6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_GCC_ARM/saml21j18a.ld @@ -0,0 +1,118 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY { + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4 + } + + /* The stack size used by the application. NOTE: you need to adjust according to your application. */ + STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + + /* Section Definitions */ + SECTIONS { +.text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); +.ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + +.relocate : + AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + .heap (NOLOAD) : + { + . = ALIGN(4); + __end__ = . ; + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_GCC_ARM/startup_saml21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_GCC_ARM/startup_saml21.c new file mode 100644 index 0000000000..d7e53ee06a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_GCC_ARM/startup_saml21.c @@ -0,0 +1,281 @@ +/** + * \file + * + * \brief gcc starttup file for SAML21 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "saml21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */ +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_USB +void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_SERCOM4 +void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM5 +void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_TC2 +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC3 +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_ADC +void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AC +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_DAC +void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PTC +void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AES +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TRNG +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PICOP +void PICOP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + (void*) (&_estack), + + (void*) Reset_Handler, + (void*) NMI_Handler, + (void*) HardFault_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) SVC_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) PendSV_Handler, + (void*) SysTick_Handler, + + /* Configurable interrupts */ + (void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + (void*) WDT_Handler, /* 1 Watchdog Timer */ + (void*) RTC_Handler, /* 2 Real-Time Counter */ + (void*) EIC_Handler, /* 3 External Interrupt Controller */ + (void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */ + (void*) DMAC_Handler, /* 5 Direct Memory Access Controller */ +#ifdef ID_USB + (void*) USB_Handler, /* 6 Universal Serial Bus */ +#else + (void*) (0UL), /* Reserved */ +#endif + (void*) EVSYS_Handler, /* 7 Event System Interface */ + (void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */ + (void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */ + (void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */ + (void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + (void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */ +#else + (void*) (0UL), /* Reserved */ +#endif +#ifdef ID_SERCOM5 + (void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */ +#else + (void*) (0UL), /* Reserved */ +#endif + (void*) TCC0_Handler, /* 14 Timer Counter Control 0 */ + (void*) TCC1_Handler, /* 15 Timer Counter Control 1 */ + (void*) TCC2_Handler, /* 16 Timer Counter Control 2 */ + (void*) TC0_Handler, /* 17 Basic Timer Counter 0 */ + (void*) TC1_Handler, /* 18 Basic Timer Counter 1 */ +#ifdef ID_TC2 + (void*) TC2_Handler, /* 19 Basic Timer Counter 2 */ +#else + (void*) (0UL), /* Reserved */ +#endif +#ifdef ID_TC3 + (void*) TC3_Handler, /* 20 Basic Timer Counter 3 */ +#else + (void*) (0UL), /* Reserved */ +#endif + (void*) TC4_Handler, /* 21 Basic Timer Counter 4 */ +#ifdef ID_ADC + (void*) ADC_Handler, /* 22 Analog Digital Converter */ +#else + (void*) (0UL), /* Reserved */ +#endif +#ifdef ID_AC + (void*) AC_Handler, /* 23 Analog Comparators */ +#else + (void*) (0UL), /* Reserved */ +#endif +#ifdef ID_DAC + (void*) DAC_Handler, /* 24 Digital-to-Analog Converter */ +#else + (void*) (0UL), /* Reserved */ +#endif +#ifdef ID_PTC + (void*) PTC_Handler, /* 25 Peripheral Touch Controller */ +#else + (void*) (0UL), /* Reserved */ +#endif +#ifdef ID_AES + (void*) AES_Handler, /* 26 Advanced Encryption Standard */ +#else + (void*) (0UL), /* Reserved */ +#endif +#ifdef ID_TRNG + (void*) TRNG_Handler, /* 27 True Random Generator */ +#else + (void*) (0UL), /* Reserved */ +#endif +#ifdef ID_PICOP + (void*) PICOP_Handler /* 28 PicoProcessor */ +#else + (void*) (0UL) /* Reserved */ +#endif +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ + NVMCTRL->CTRLB.bit.MANW = 1; + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_IAR/startup_saml21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_IAR/startup_saml21.c new file mode 100644 index 0000000000..6158596211 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_IAR/startup_saml21.c @@ -0,0 +1,261 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "saml21.h" + +typedef void (*intfunc) (void); +typedef union { + intfunc __fun; + void * __ptr; +} intvec_elem; + +void __iar_program_start(void); +int __low_level_init(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +#pragma weak NMI_Handler = Dummy_Handler +#pragma weak HardFault_Handler = Dummy_Handler +#pragma weak SVC_Handler = Dummy_Handler +#pragma weak PendSV_Handler = Dummy_Handler +#pragma weak SysTick_Handler = Dummy_Handler + +/* Peripherals handlers */ +#pragma weak SYSTEM_Handler = Dummy_Handler /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */ +#pragma weak WDT_Handler = Dummy_Handler +#pragma weak RTC_Handler = Dummy_Handler +#pragma weak EIC_Handler = Dummy_Handler +#pragma weak NVMCTRL_Handler = Dummy_Handler +#pragma weak DMAC_Handler = Dummy_Handler +#ifdef ID_USB +#pragma weak USB_Handler = Dummy_Handler +#endif +#pragma weak EVSYS_Handler = Dummy_Handler +#pragma weak SERCOM0_Handler = Dummy_Handler +#pragma weak SERCOM1_Handler = Dummy_Handler +#pragma weak SERCOM2_Handler = Dummy_Handler +#pragma weak SERCOM3_Handler = Dummy_Handler +#ifdef ID_SERCOM4 +#pragma weak SERCOM4_Handler = Dummy_Handler +#endif +#ifdef ID_SERCOM5 +#pragma weak SERCOM5_Handler = Dummy_Handler +#endif +#pragma weak TCC0_Handler = Dummy_Handler +#pragma weak TCC1_Handler = Dummy_Handler +#pragma weak TCC2_Handler = Dummy_Handler +#pragma weak TC0_Handler = Dummy_Handler +#pragma weak TC1_Handler = Dummy_Handler +#ifdef ID_TC2 +#pragma weak TC2_Handler = Dummy_Handler +#endif +#ifdef ID_TC3 +#pragma weak TC3_Handler = Dummy_Handler +#endif +#pragma weak TC4_Handler = Dummy_Handler +#ifdef ID_ADC +#pragma weak ADC_Handler = Dummy_Handler +#endif +#ifdef ID_AC +#pragma weak AC_Handler = Dummy_Handler +#endif +#ifdef ID_DAC +#pragma weak DAC_Handler = Dummy_Handler +#endif +#ifdef ID_PTC +#pragma weak PTC_Handler = Dummy_Handler +#endif +#ifdef ID_AES +#pragma weak AES_Handler = Dummy_Handler +#endif +#ifdef ID_TRNG +#pragma weak TRNG_Handler = Dummy_Handler +#endif +#ifdef ID_PICOP +#pragma weak PICOP_Handler = Dummy_Handler +#endif + +/* Exception Table */ +#pragma language = extended +#pragma segment = "CSTACK" + +/* The name "__vector_table" has special meaning for C-SPY: */ +/* it is where the SP start value is found, and the NVIC vector */ +/* table register (VTOR) is initialized to this address if != 0 */ + +#pragma section = ".intvec" +#pragma location = ".intvec" +const DeviceVectors __vector_table[] = { + __sfe("CSTACK"), + (void*) __iar_program_start, + (void*) NMI_Handler, + (void*) HardFault_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) SVC_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) PendSV_Handler, + (void*) SysTick_Handler, + + /* Configurable interrupts */ + (void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + (void*) WDT_Handler, /* 1 Watchdog Timer */ + (void*) RTC_Handler, /* 2 Real-Time Counter */ + (void*) EIC_Handler, /* 3 External Interrupt Controller */ + (void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */ + (void*) DMAC_Handler, /* 5 Direct Memory Access Controller */ +#ifdef ID_USB + (void*) USB_Handler, /* 6 Universal Serial Bus */ +#else + (void*) (0UL), /* Reserved*/ +#endif + (void*) EVSYS_Handler, /* 7 Event System Interface */ + (void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */ + (void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */ + (void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */ + (void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + (void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */ +#else + (void*) (0UL), /* Reserved*/ +#endif +#ifdef ID_SERCOM5 + (void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */ +#else + (void*) (0UL), /* Reserved*/ +#endif + (void*) TCC0_Handler, /* 14 Timer Counter Control 0 */ + (void*) TCC1_Handler, /* 15 Timer Counter Control 1 */ + (void*) TCC2_Handler, /* 16 Timer Counter Control 2 */ + (void*) TC0_Handler, /* 17 Basic Timer Counter 0 */ + (void*) TC1_Handler, /* 18 Basic Timer Counter 1 */ +#ifdef ID_TC2 + (void*) TC2_Handler, /* 19 Basic Timer Counter 2 */ +#else + (void*) (0UL), /* Reserved*/ +#endif +#ifdef ID_TC3 + (void*) TC3_Handler, /* 20 Basic Timer Counter 3 */ +#else + (void*) (0UL), /* Reserved*/ +#endif + (void*) TC4_Handler, /* 21 Basic Timer Counter 4 */ +#ifdef ID_ADC + (void*) ADC_Handler, /* 22 Analog Digital Converter */ +#else + (void*) (0UL), /* Reserved*/ +#endif +#ifdef ID_AC + (void*) AC_Handler, /* 23 Analog Comparators */ +#else + (void*) (0UL), /* Reserved*/ +#endif +#ifdef ID_DAC + (void*) DAC_Handler, /* 24 Digital-to-Analog Converter */ +#else + (void*) (0UL), /* Reserved*/ +#endif +#ifdef ID_PTC + (void*) PTC_Handler, /* 25 Peripheral Touch Controller */ +#else + (void*) (0UL), /* Reserved*/ +#endif +#ifdef ID_AES + (void*) AES_Handler, /* 26 Advanced Encryption Standard */ +#else + (void*) (0UL), /* Reserved*/ +#endif +#ifdef ID_TRNG + (void*) TRNG_Handler, /* 27 True Random Generator */ +#else + (void*) (0UL), /* Reserved*/ +#endif +#ifdef ID_PICOP + (void*) PICOP_Handler /* 28 PicoProcessor */ +#else + (void*) (0UL) /* Reserved*/ +#endif +}; + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +int __low_level_init(void) +{ + uint32_t *pSrc = __section_begin(".intvec"); + + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + return 1; /* if return 0, the data sections will not be initialized */ +} + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ + NVMCTRL->CTRLB.bit.MANW = 1; + + __iar_program_start(); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis.h new file mode 100644 index 0000000000..116f676c15 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in samr21j18a specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "saml21.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis_nvic.c similarity index 91% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis_nvic.c rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis_nvic.c index 472279d186..c9e1799d28 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis_nvic.c @@ -30,8 +30,8 @@ */ #include "cmsis_nvic.h" -//#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM -extern uint32_t _sdvectors; +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +//extern uint32_t _sdvectors; #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) @@ -42,11 +42,11 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) // Copy and switch to dynamic vectors if the first time called if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { uint32_t *old_vectors = vectors; - vectors = (uint32_t*)&_sdvectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; for (i=0; iVTOR = (uint32_t)&_sdvectors; + SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; } vectors[IRQn + 16] = vector; } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis_nvic.h new file mode 100644 index 0000000000..ce2eff93d3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis_nvic.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 +29) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct new file mode 100644 index 0000000000..669d9fe7a7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct @@ -0,0 +1,19 @@ +;SAMR21G18A +;256KB FLASH (0x40000) @ 0x000000000 +;2KB RAM (0x8000) @ 0x20000000 + + +;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment + RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s new file mode 100644 index 0000000000..f1ffe2f76f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s @@ -0,0 +1,189 @@ +;/***************************************************************************** +; * @file startup_SAMR21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMR21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/SAMR21G18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/SAMR21G18A.sct new file mode 100644 index 0000000000..669d9fe7a7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/SAMR21G18A.sct @@ -0,0 +1,19 @@ +;SAMR21G18A +;256KB FLASH (0x40000) @ 0x000000000 +;2KB RAM (0x8000) @ 0x20000000 + + +;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment + RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/startup_SAMR21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/startup_SAMR21.s new file mode 100644 index 0000000000..f1ffe2f76f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/startup_SAMR21.s @@ -0,0 +1,189 @@ +;/***************************************************************************** +; * @file startup_SAMR21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMR21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld similarity index 77% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld index 218f7deedc..21479a889e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld @@ -3,19 +3,17 @@ OUTPUT_ARCH(arm) SEARCH_DIR(.) /* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 -} +MEMORY { + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000 + 0xB0, LENGTH = 0x00008000 - 0xB0 + } -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + /* The stack size used by the application. NOTE: you need to adjust according to your application. */ + STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; -/* Section Definitions */ -SECTIONS -{ - .text : + /* Section Definitions */ + SECTIONS { +.text : { . = ALIGN(4); _sfixed = .; @@ -66,23 +64,17 @@ SECTIONS /* .ARM.exidx is sorted, so has to go in its own output section. */ PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : +.ARM.exidx : { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > rom PROVIDE_HIDDEN (__exidx_end = .); . = ALIGN(4); _etext = .; - - .dvectors (NOLOAD) : - { - _sdvectors = .; - . = . + 0xB0; - _edvectors = .; - } > ram - .relocate : AT (_etext) +.relocate : + AT (_etext) { . = ALIGN(4); _srelocate = .; @@ -105,12 +97,12 @@ SECTIONS _ezero = .; } > ram - .heap (NOLOAD) : - { - . = ALIGN(4); - __end__ = . ; - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - } > ram + .heap (NOLOAD) : + { + . = ALIGN(4); + __end__ = . ; + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + } > ram /* stack section */ .stack (NOLOAD): diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c similarity index 58% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c index 297ef249c4..8fab8a8ea9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c @@ -42,7 +42,10 @@ #include "samr21.h" typedef void (*intfunc) (void); -typedef union { intfunc __fun; void * __ptr; } intvec_elem; +typedef union { + intfunc __fun; + void * __ptr; +} intvec_elem; void __iar_program_start(void); int __low_level_init(void); @@ -116,89 +119,89 @@ void Dummy_Handler(void); #pragma section = ".intvec" #pragma location = ".intvec" const DeviceVectors __vector_table[] = { - __sfe("CSTACK"), - (void*) __iar_program_start, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, + __sfe("CSTACK"), + (void*) __iar_program_start, + (void*) NMI_Handler, + (void*) HardFault_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) SVC_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) PendSV_Handler, + (void*) SysTick_Handler, - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ + /* Configurable interrupts */ + (void*) PM_Handler, /* 0 Power Manager */ + (void*) SYSCTRL_Handler, /* 1 System Control */ + (void*) WDT_Handler, /* 2 Watchdog Timer */ + (void*) RTC_Handler, /* 3 Real-Time Counter */ + (void*) EIC_Handler, /* 4 External Interrupt Controller */ + (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ + (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ #ifdef ID_USB - (void*) USB_Handler, /* 7 Universal Serial Bus */ + (void*) USB_Handler, /* 7 Universal Serial Bus */ #else - (void*) (0UL), /* Reserved*/ + (void*) (0UL), /* Reserved*/ #endif - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ + (void*) EVSYS_Handler, /* 8 Event System Interface */ + (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ #ifdef ID_SERCOM4 - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ + (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ #else - (void*) (0UL), /* Reserved*/ + (void*) (0UL), /* Reserved*/ #endif #ifdef ID_SERCOM5 - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ + (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ #else - (void*) (0UL), /* Reserved*/ + (void*) (0UL), /* Reserved*/ #endif - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ + (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ + (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ + (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ + (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ + (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ + (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ #ifdef ID_TC6 - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ + (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ #else - (void*) (0UL), /* Reserved*/ + (void*) (0UL), /* Reserved*/ #endif #ifdef ID_TC7 - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ + (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ #else - (void*) (0UL), /* Reserved*/ + (void*) (0UL), /* Reserved*/ #endif #ifdef ID_ADC - (void*) ADC_Handler, /* 23 Analog Digital Converter */ + (void*) ADC_Handler, /* 23 Analog Digital Converter */ #else - (void*) (0UL), /* Reserved*/ + (void*) (0UL), /* Reserved*/ #endif #ifdef ID_AC - (void*) AC_Handler, /* 24 Analog Comparators */ + (void*) AC_Handler, /* 24 Analog Comparators */ #else - (void*) (0UL), /* Reserved*/ + (void*) (0UL), /* Reserved*/ #endif #ifdef ID_DAC - (void*) DAC_Handler, /* 25 Digital Analog Converter */ + (void*) DAC_Handler, /* 25 Digital Analog Converter */ #else - (void*) (0UL), /* Reserved*/ + (void*) (0UL), /* Reserved*/ #endif #ifdef ID_PTC - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ + (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ #else - (void*) (0UL), /* Reserved*/ + (void*) (0UL), /* Reserved*/ #endif - (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */ - (void*) (0UL), /* Reserved */ + (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */ + (void*) (0UL), /* Reserved */ }; /**------------------------------------------------------------------------------ @@ -207,11 +210,11 @@ const DeviceVectors __vector_table[] = { *------------------------------------------------------------------------------*/ int __low_level_init(void) { - uint32_t *pSrc = __section_begin(".intvec"); + uint32_t *pSrc = __section_begin(".intvec"); - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - return 1; /* if return 0, the data sections will not be initialized */ + return 1; /* if return 0, the data sections will not be initialized */ } /**------------------------------------------------------------------------------ @@ -220,20 +223,20 @@ int __low_level_init(void) *------------------------------------------------------------------------------*/ void Reset_Handler(void) { - /* Change default QOS values to have the best performance and correct USB behaviour */ - SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; + /* Change default QOS values to have the best performance and correct USB behaviour */ + SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; #if defined(ID_USB) - USB->DEVICE.QOSCTRL.bit.CQOS = 2; - USB->DEVICE.QOSCTRL.bit.DQOS = 2; + USB->DEVICE.QOSCTRL.bit.CQOS = 2; + USB->DEVICE.QOSCTRL.bit.DQOS = 2; #endif - DMAC->QOSCTRL.bit.DQOS = 2; - DMAC->QOSCTRL.bit.FQOS = 2; - DMAC->QOSCTRL.bit.WRBQOS = 2; + DMAC->QOSCTRL.bit.DQOS = 2; + DMAC->QOSCTRL.bit.FQOS = 2; + DMAC->QOSCTRL.bit.WRBQOS = 2; - /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ - NVMCTRL->CTRLB.bit.MANW = 1; + /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ + NVMCTRL->CTRLB.bit.MANW = 1; - __iar_program_start(); + __iar_program_start(); } /** @@ -241,6 +244,6 @@ void Reset_Handler(void) */ void Dummy_Handler(void) { - while (1) { - } + while (1) { + } } diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/cmsis.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/cmsis.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/cmsis_nvic.c new file mode 100644 index 0000000000..c9e1799d28 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/cmsis_nvic.c @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2011 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +//extern uint32_t _sdvectors; +#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t*)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/cmsis_nvic.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis_nvic.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/cmsis_nvic.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h similarity index 67% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h index 7d133bfc64..55f0b63ce6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h @@ -59,14 +59,14 @@ /* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } AC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -87,16 +87,16 @@ typedef union { /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -115,25 +115,25 @@ typedef union { /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } AC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -164,20 +164,20 @@ typedef union { /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -201,20 +201,20 @@ typedef union { /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -238,20 +238,20 @@ typedef union { /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -275,18 +275,18 @@ typedef union { /* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_STATUSA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -314,17 +314,17 @@ typedef union { /* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_STATUSB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -345,18 +345,18 @@ typedef union { /* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_STATUSC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -384,12 +384,12 @@ typedef union { /* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } AC_WINCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -414,26 +414,26 @@ typedef union { /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ENABLE:1; /*!< bit: 0 Enable */ - uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ - uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 14 Reserved */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t OUT:2; /*!< bit: 16..17 Output */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ENABLE:1; /*!< bit: 0 Enable */ + uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ + uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ + uint32_t :1; /*!< bit: 4 Reserved */ + uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ + uint32_t :1; /*!< bit: 14 Reserved */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t OUT:2; /*!< bit: 16..17 Output */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } AC_COMPCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -519,11 +519,11 @@ typedef union { /* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } AC_SCALER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -538,22 +538,22 @@ typedef union { /** \brief AC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ - __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ - RoReg8 Reserved2[0x1]; - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ - RoReg8 Reserved3[0x3]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved4[0x8]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ + __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ + RoReg8 Reserved2[0x1]; + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ + RoReg8 Reserved3[0x3]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved4[0x8]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ } Ac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h similarity index 75% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h index fbd0bdba1b..65ea3e1ace 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h @@ -59,13 +59,13 @@ /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -83,12 +83,12 @@ typedef union { /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_REFCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -115,12 +115,12 @@ typedef union { /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_AVGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -160,11 +160,11 @@ typedef union { /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_SAMPCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -179,17 +179,17 @@ typedef union { /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -239,11 +239,11 @@ typedef union { /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_WINCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -268,12 +268,12 @@ typedef union { /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_SWTRIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -289,17 +289,17 @@ typedef union { /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ - uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ - uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ + uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ + uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } ADC_INPUTCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -408,15 +408,15 @@ typedef union { /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ - uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ + uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -436,14 +436,14 @@ typedef union { /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -463,14 +463,14 @@ typedef union { /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -490,14 +490,14 @@ typedef union { /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -517,11 +517,11 @@ typedef union { /* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -535,10 +535,10 @@ typedef union { /* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_RESULT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -553,10 +553,10 @@ typedef union { /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_WINLT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -571,10 +571,10 @@ typedef union { /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_WINUT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -589,11 +589,11 @@ typedef union { /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_GAINCORR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -608,11 +608,11 @@ typedef union { /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_OFFSETCORR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -627,12 +627,12 @@ typedef union { /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ - uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ + uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_CALIB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -650,11 +650,11 @@ typedef union { /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -668,32 +668,32 @@ typedef union { /** \brief ADC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ - RoReg8 Reserved1[0x2]; - __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ - RoReg8 Reserved2[0x3]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ - RoReg8 Reserved3[0x3]; - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ - RoReg8 Reserved4[0x1]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ - RoReg8 Reserved5[0x2]; - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ - RoReg8 Reserved6[0x2]; - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ + RoReg8 Reserved1[0x2]; + __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ + RoReg8 Reserved2[0x3]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ + RoReg8 Reserved3[0x3]; + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ + RoReg8 Reserved4[0x1]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ + RoReg8 Reserved5[0x2]; + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ + RoReg8 Reserved6[0x2]; + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ } Adc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h similarity index 69% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h index e1f6435411..968f00463e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h @@ -59,13 +59,13 @@ /* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -83,16 +83,16 @@ typedef union { /* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ - uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ - uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ - uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ - uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ + uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ + uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ + uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ + uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -123,12 +123,12 @@ typedef union { /* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ - uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ + uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -144,13 +144,13 @@ typedef union { /* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -168,13 +168,13 @@ typedef union { /* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -192,13 +192,13 @@ typedef union { /* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -216,11 +216,11 @@ typedef union { /* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DAC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -234,10 +234,10 @@ typedef union { /* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DAC_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -252,10 +252,10 @@ typedef union { /* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DAC_DATABUF_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -270,17 +270,17 @@ typedef union { /** \brief DAC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ - RoReg8 Reserved2[0x2]; - __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ + RoReg8 Reserved2[0x2]; + __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ } Dac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h similarity index 69% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h index 8ce0656b94..7f187915a0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h @@ -59,23 +59,23 @@ /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -104,14 +104,14 @@ typedef union { /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_CRCCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -146,10 +146,10 @@ typedef union { /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_CRCDATAIN_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -164,10 +164,10 @@ typedef union { /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_CRCCHKSUM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -182,12 +182,12 @@ typedef union { /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CRCSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -203,11 +203,11 @@ typedef union { /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -221,13 +221,13 @@ typedef union { /* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ + uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ + uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_QOSCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -272,26 +272,26 @@ typedef union { /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_SWTRIGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -330,21 +330,21 @@ typedef union { /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_PRICTRL0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -376,18 +376,18 @@ typedef union { /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_INTPEND_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -414,26 +414,26 @@ typedef union { /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_INTSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -472,26 +472,26 @@ typedef union { /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_BUSYCH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -530,26 +530,26 @@ typedef union { /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_PENDCH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -588,22 +588,22 @@ typedef union { /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_ACTIVE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -634,10 +634,10 @@ typedef union { /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_BASEADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -652,10 +652,10 @@ typedef union { /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_WRBADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -670,11 +670,11 @@ typedef union { /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHID_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -689,12 +689,12 @@ typedef union { /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -710,19 +710,19 @@ typedef union { /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_CHCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -789,13 +789,13 @@ typedef union { /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHINTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -813,13 +813,13 @@ typedef union { /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHINTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -837,13 +837,13 @@ typedef union { /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Transfer Error */ - uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TERR:1; /*!< bit: 0 Transfer Error */ + uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHINTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -861,13 +861,13 @@ typedef union { /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -885,18 +885,18 @@ typedef union { /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_BTCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -967,10 +967,10 @@ typedef union { /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_BTCNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -984,10 +984,10 @@ typedef union { /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_SRCADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1001,10 +1001,10 @@ typedef union { /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_DSTADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1018,10 +1018,10 @@ typedef union { /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_DESCADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1035,49 +1035,49 @@ typedef union { /** \brief DMAC APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ - __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ - __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ - __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ - __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ - __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ - __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ - RoReg8 Reserved1[0x1]; - __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ - __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ - RoReg8 Reserved2[0x8]; - __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ - RoReg8 Reserved3[0x2]; - __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ - __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ - __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ - __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ - __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ - __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ - RoReg8 Reserved4[0x3]; - __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ - __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ - RoReg8 Reserved5[0x3]; - __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ - RoReg8 Reserved6[0x4]; - __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ - __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ - __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ - __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ + __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ + __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ + __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ + __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ + __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ + __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ + __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ + RoReg8 Reserved1[0x1]; + __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ + __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ + RoReg8 Reserved2[0x8]; + __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ + RoReg8 Reserved3[0x2]; + __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ + __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ + __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ + __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ + __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ + __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ + RoReg8 Reserved4[0x3]; + __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ + __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ + RoReg8 Reserved5[0x3]; + __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ + RoReg8 Reserved6[0x4]; + __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ + __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ + __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ + __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ } Dmac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief DMAC Descriptor SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ - __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ - __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */ - __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */ - __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ + __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ + __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ + __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */ + __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */ + __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ } DmacDescriptor #ifdef __GNUC__ - __attribute__ ((aligned (8))) +__attribute__ ((aligned (8))) #endif ; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h similarity index 65% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h index fc7b5ec4f3..450f3444e5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h @@ -59,15 +59,15 @@ /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */ - uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */ - uint8_t CE:1; /*!< bit: 4 Chip Erase */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */ + uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */ + uint8_t CE:1; /*!< bit: 4 Chip Erase */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DSU_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -87,15 +87,15 @@ typedef union { /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DONE:1; /*!< bit: 0 Done */ - uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ - uint8_t BERR:1; /*!< bit: 2 Bus Error */ - uint8_t FAIL:1; /*!< bit: 3 Failure */ - uint8_t PERR:1; /*!< bit: 4 Protection Error */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DONE:1; /*!< bit: 0 Done */ + uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ + uint8_t BERR:1; /*!< bit: 2 Bus Error */ + uint8_t FAIL:1; /*!< bit: 3 Failure */ + uint8_t PERR:1; /*!< bit: 4 Protection Error */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DSU_STATUSA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -117,20 +117,20 @@ typedef union { /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PROT:1; /*!< bit: 0 Protected */ - uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ - uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ - uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ - uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PROT:1; /*!< bit: 0 Protected */ + uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ + uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ + uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ + uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } DSU_STATUSB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -155,11 +155,11 @@ typedef union { /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t ADDR:30; /*!< bit: 2..31 Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t ADDR:30; /*!< bit: 2..31 Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -174,11 +174,11 @@ typedef union { /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t LENGTH:30; /*!< bit: 2..31 Length */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t LENGTH:30; /*!< bit: 2..31 Length */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_LENGTH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -193,10 +193,10 @@ typedef union { /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -211,10 +211,10 @@ typedef union { /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_DCC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -229,16 +229,16 @@ typedef union { /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ - uint32_t REVISION:4; /*!< bit: 8..11 Revision */ - uint32_t DIE:4; /*!< bit: 12..15 Die Identification */ - uint32_t SERIES:6; /*!< bit: 16..21 Product Series */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */ - uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ + uint32_t REVISION:4; /*!< bit: 8..11 Revision */ + uint32_t DIE:4; /*!< bit: 12..15 Die Identification */ + uint32_t SERIES:6; /*!< bit: 16..21 Product Series */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */ + uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_DID_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -267,13 +267,13 @@ typedef union { /* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EPRES:1; /*!< bit: 0 Entry Present */ - uint32_t FMT:1; /*!< bit: 1 Format */ - uint32_t :10; /*!< bit: 2..11 Reserved */ - uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EPRES:1; /*!< bit: 0 Entry Present */ + uint32_t FMT:1; /*!< bit: 1 Format */ + uint32_t :10; /*!< bit: 2..11 Reserved */ + uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_ENTRY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -292,10 +292,10 @@ typedef union { /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t END:32; /*!< bit: 0..31 End Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t END:32; /*!< bit: 0..31 End Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_END_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -310,11 +310,11 @@ typedef union { /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_MEMTYPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -328,12 +328,12 @@ typedef union { /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ - uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ + uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID4_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -351,11 +351,11 @@ typedef union { /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -370,12 +370,12 @@ typedef union { /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ - uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ + uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -393,13 +393,13 @@ typedef union { /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ - uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ - uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ + uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ + uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -419,12 +419,12 @@ typedef union { /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ - uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ + uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -442,11 +442,11 @@ typedef union { /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -461,12 +461,12 @@ typedef union { /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ - uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ + uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -484,11 +484,11 @@ typedef union { /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -503,11 +503,11 @@ typedef union { /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -522,30 +522,30 @@ typedef union { /** \brief DSU hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ - __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ - __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ - RoReg8 Reserved1[0x1]; - __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ - __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ - __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ - __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ - __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ - RoReg8 Reserved2[0xFE4]; - __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ - __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ - RoReg8 Reserved3[0xFC0]; - __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ - __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ - RoReg8 Reserved4[0xC]; - __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ - __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ - __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ - __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ - __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ - __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ - __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ - __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ + __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ + __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ + __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ + RoReg8 Reserved1[0x1]; + __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ + __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ + __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ + __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ + __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ + RoReg8 Reserved2[0xFE4]; + __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ + __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ + RoReg8 Reserved3[0xFC0]; + __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ + __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ + RoReg8 Reserved4[0xC]; + __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ + __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ + __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ + __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ + __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ + __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ + __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ + __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ } Dsu; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h similarity index 72% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h index 8c324a4b6c..7ea6fe2833 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h @@ -59,12 +59,12 @@ /* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -80,11 +80,11 @@ typedef union { /* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -98,12 +98,12 @@ typedef union { /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ - uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ + uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_NMICTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -132,11 +132,11 @@ typedef union { /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_NMIFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -150,30 +150,30 @@ typedef union { /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ - uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ - uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ - uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ - uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ - uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ - uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ - uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ - uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ - uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ - uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ - uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ - uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ - uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ - uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ - uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ + uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ + uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ + uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ + uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ + uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ + uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ + uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ + uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ + uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ + uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ + uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ + uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ + uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ + uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ + uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -220,30 +220,30 @@ typedef union { /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ + uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ + uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ + uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ + uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ + uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ + uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ + uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ + uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ + uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ + uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ + uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ + uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ + uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ + uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ + uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -290,30 +290,30 @@ typedef union { /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ + uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ + uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ + uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ + uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ + uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ + uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ + uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ + uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ + uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ + uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ + uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ + uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ + uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ + uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ + uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -360,30 +360,30 @@ typedef union { /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ + uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ + uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ + uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ + uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ + uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ + uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ + uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ + uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ + uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ + uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ + uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ + uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ + uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ + uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ + uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -430,30 +430,30 @@ typedef union { /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ - uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ - uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ - uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ - uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ - uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ - uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ - uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ - uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ - uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ - uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ - uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ - uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ - uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ - uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ - uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ + uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ + uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ + uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ + uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ + uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ + uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ + uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ + uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ + uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ + uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ + uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ + uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ + uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ + uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ + uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_WAKEUP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -500,25 +500,25 @@ typedef union { /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ - uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ - uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ - uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ - uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ - uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ - uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ - uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ - uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ - uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ - uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ - uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ - uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ - uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ - uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ - uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ + uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ + uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ + uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ + uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ + uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ + uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ + uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ + uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ + uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ + uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ + uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ + uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ + uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ + uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ + uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } EIC_CONFIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -666,16 +666,16 @@ typedef union { /** \brief EIC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ - __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ - __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ - __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ - __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ - __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ - __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ - __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ - __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ + __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ + __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ + __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ + __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ + __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ + __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ + __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ + __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ + __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ + __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ } Eic; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h similarity index 66% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h index f4aa3ae09e..5f28cf416b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h @@ -59,13 +59,13 @@ /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :3; /*!< bit: 1.. 3 Reserved */ - uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :3; /*!< bit: 1.. 3 Reserved */ + uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EVSYS_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -81,18 +81,18 @@ typedef union { /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SWEVT:1; /*!< bit: 8 Software Event */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ - uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t SWEVT:1; /*!< bit: 8 Software Event */ + uint32_t :7; /*!< bit: 9..15 Reserved */ + uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ + uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_CHANNEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -132,13 +132,13 @@ typedef union { /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } EVSYS_USER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -158,43 +158,43 @@ typedef union { /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ - uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ - uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ - uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ - uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ - uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ - uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ - uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ - uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ - uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ - uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ - uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ - uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ - uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ - uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ - uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ - uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */ - uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */ - uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */ - uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ - uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ - uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ - uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ - uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ - uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ + uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ + uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ + uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ + uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ + uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ + uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ + uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ + uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ + uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ + uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ + uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ + uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ + uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ + uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ + uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ + uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */ + uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */ + uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */ + uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ + uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ + uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ + uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ + uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ + uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_CHSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -266,43 +266,43 @@ typedef union { /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ + uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ + uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ + uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ + uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ + uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ + uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ + uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ + uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ + uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ + uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ + uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ + uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ + uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ + uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -374,43 +374,43 @@ typedef union { /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ + uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ + uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ + uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ + uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ + uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ + uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ + uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ + uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ + uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ + uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ + uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ + uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ + uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ + uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -482,43 +482,43 @@ typedef union { /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ + uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ + uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ + uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ + uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ + uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ + uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ + uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ + uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ + uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */ + uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */ + uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */ + uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ + uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ + uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -590,15 +590,15 @@ typedef union { /** \brief EVSYS hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ - __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ - RoReg8 Reserved2[0x2]; - __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ - __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ - __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ - __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ + __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ + __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ + RoReg8 Reserved2[0x2]; + __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ + __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ + __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ + __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ } Evsys; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h similarity index 83% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h index 77f17fb677..2d2348f3c5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h @@ -59,11 +59,11 @@ /* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } GCLK_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -77,11 +77,11 @@ typedef union { /* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } GCLK_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -95,15 +95,15 @@ typedef union { /* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ - uint16_t :2; /*!< bit: 12..13 Reserved */ - uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ - uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ + uint16_t :2; /*!< bit: 12..13 Reserved */ + uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ + uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } GCLK_CLKCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -215,20 +215,20 @@ typedef union { /* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SRC:5; /*!< bit: 8..12 Source Select */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ - uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ - uint32_t OOV:1; /*!< bit: 18 Output Off Value */ - uint32_t OE:1; /*!< bit: 19 Output Enable */ - uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ - uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t SRC:5; /*!< bit: 8..12 Source Select */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ + uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ + uint32_t OOV:1; /*!< bit: 18 Output Off Value */ + uint32_t OE:1; /*!< bit: 19 Output Enable */ + uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ + uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } GCLK_GENCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -276,13 +276,13 @@ typedef union { /* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } GCLK_GENDIV_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -300,11 +300,11 @@ typedef union { /** \brief GCLK hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ - __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ - __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ - __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ + __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ + __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ + __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ + __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ } Gclk; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h similarity index 83% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h index 0b4c0100f2..21647a68bf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h @@ -59,7 +59,7 @@ /* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } HMATRIXB_PRAS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -71,7 +71,7 @@ typedef union { /* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } HMATRIXB_PRBS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -83,10 +83,10 @@ typedef union { /* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } HMATRIXB_SFR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -101,18 +101,18 @@ typedef union { /** \brief HmatrixbPrs hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ - __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ + __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ + __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ } HmatrixbPrs; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief HMATRIXB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - RoReg8 Reserved1[0x80]; - HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ - RoReg8 Reserved2[0x10]; - __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ + RoReg8 Reserved1[0x80]; + HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ + RoReg8 Reserved2[0x10]; + __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ } Hmatrixb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h similarity index 69% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h index d10f5d44a5..da7b7a0e3e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h @@ -59,22 +59,22 @@ /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */ - uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */ - uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */ - uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */ - uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */ + uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */ + uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */ + uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */ + uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } I2S_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -104,26 +104,26 @@ typedef union { /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */ - uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */ - uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */ - uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */ - uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */ - uint32_t :2; /*!< bit: 9..10 Reserved */ - uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */ - uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */ - uint32_t :1; /*!< bit: 17 Reserved */ - uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */ - uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */ - uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */ - uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */ - uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */ - uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */ + uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */ + uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */ + uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */ + uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */ + uint32_t :2; /*!< bit: 9..10 Reserved */ + uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */ + uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */ + uint32_t :1; /*!< bit: 17 Reserved */ + uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */ + uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */ + uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */ + uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */ + uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */ + uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } I2S_CLKCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -200,31 +200,31 @@ typedef union { /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ - uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ - uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ - uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ - uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ + uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ + uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ + uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ + uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } I2S_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -264,31 +264,31 @@ typedef union { /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ - uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ - uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ - uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ - uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ + uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ + uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ + uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ + uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } I2S_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -328,31 +328,31 @@ typedef union { /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */ - uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */ - uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */ - uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */ - uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */ + uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */ + uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */ + uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */ + uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } I2S_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -392,27 +392,27 @@ typedef union { /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */ - uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */ - uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */ - uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */ - uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */ - uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */ - uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */ - uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */ + uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */ + uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */ + uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */ + uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */ + uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */ + uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */ + uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } I2S_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -449,37 +449,37 @@ typedef union { /* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */ - uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */ - uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */ - uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */ - uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */ - uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */ - uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */ - uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */ - uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */ - uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */ - uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */ - uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */ - uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */ - uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */ - uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */ - uint32_t MONO:1; /*!< bit: 24 Mono Mode */ - uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */ - uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */ + uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */ + uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */ + uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */ + uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */ + uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */ + uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */ + uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */ + uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */ + uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */ + uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */ + uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */ + uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */ + uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */ + uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */ + uint32_t MONO:1; /*!< bit: 24 Mono Mode */ + uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */ + uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } I2S_SERCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -602,10 +602,10 @@ typedef union { /* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } I2S_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -620,20 +620,20 @@ typedef union { /** \brief I2S hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - RoReg8 Reserved1[0x3]; - __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */ - __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ - RoReg8 Reserved2[0x2]; - __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */ - RoReg8 Reserved3[0x2]; - __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x2]; - __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */ - RoReg8 Reserved5[0x6]; - __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */ - RoReg8 Reserved6[0x8]; - __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */ + __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + RoReg8 Reserved1[0x3]; + __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */ + __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ + RoReg8 Reserved2[0x2]; + __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */ + RoReg8 Reserved3[0x2]; + __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x2]; + __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */ + RoReg8 Reserved5[0x6]; + __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */ + RoReg8 Reserved6[0x8]; + __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */ } I2s; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h similarity index 70% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h index 579300a0ca..75c3511221 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h @@ -59,12 +59,12 @@ /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ - uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ + uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } MTB_POSITION_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -80,17 +80,17 @@ typedef union { /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ - uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ - uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ - uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ - uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ - uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ - uint32_t :21; /*!< bit: 10..30 Reserved */ - uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ + uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ + uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ + uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ + uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ + uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ + uint32_t :21; /*!< bit: 10..30 Reserved */ + uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } MTB_MASTER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -117,13 +117,13 @@ typedef union { /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ - uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ + uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } MTB_FLOW_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -142,7 +142,7 @@ typedef union { /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_BASE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -152,7 +152,7 @@ typedef union { /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_ITCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -162,7 +162,7 @@ typedef union { /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CLAIMSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -172,7 +172,7 @@ typedef union { /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CLAIMCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -182,7 +182,7 @@ typedef union { /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_LOCKACCESS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -192,7 +192,7 @@ typedef union { /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_LOCKSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -202,7 +202,7 @@ typedef union { /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_AUTHSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -212,7 +212,7 @@ typedef union { /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_DEVARCH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -222,7 +222,7 @@ typedef union { /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_DEVID_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -232,7 +232,7 @@ typedef union { /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_DEVTYPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -242,7 +242,7 @@ typedef union { /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID4_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -252,7 +252,7 @@ typedef union { /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID5_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -262,7 +262,7 @@ typedef union { /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID6_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -272,7 +272,7 @@ typedef union { /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID7_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -282,7 +282,7 @@ typedef union { /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -292,7 +292,7 @@ typedef union { /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -302,7 +302,7 @@ typedef union { /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -312,7 +312,7 @@ typedef union { /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -322,7 +322,7 @@ typedef union { /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -332,7 +332,7 @@ typedef union { /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -342,7 +342,7 @@ typedef union { /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -352,7 +352,7 @@ typedef union { /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -362,35 +362,35 @@ typedef union { /** \brief MTB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ - __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ - __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ - __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ - RoReg8 Reserved1[0xEF0]; - __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ - RoReg8 Reserved2[0x9C]; - __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ - __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ - RoReg8 Reserved3[0x8]; - __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ - __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ - __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ - __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ - RoReg8 Reserved4[0x8]; - __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ - __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ - __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */ - __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */ - __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */ - __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */ - __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */ - __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */ - __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */ - __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */ - __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */ - __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */ - __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */ - __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */ + __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ + __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ + __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ + __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ + RoReg8 Reserved1[0xEF0]; + __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ + RoReg8 Reserved2[0x9C]; + __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ + __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ + RoReg8 Reserved3[0x8]; + __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ + __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ + __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ + __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ + RoReg8 Reserved4[0x8]; + __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ + __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ + __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */ + __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */ + __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */ + __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */ + __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */ + __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */ + __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */ + __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */ + __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */ + __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */ + __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */ + __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */ } Mtb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h similarity index 86% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h index a9bfd4fd77..143af0a0ec 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h @@ -59,12 +59,12 @@ /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t CMD:7; /*!< bit: 0.. 6 Command */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t CMD:7; /*!< bit: 0.. 6 Command */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } NVMCTRL_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -114,18 +114,18 @@ typedef union { /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t MANW:1; /*!< bit: 7 Manual Write */ - uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ - uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t MANW:1; /*!< bit: 7 Manual Write */ + uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ + uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } NVMCTRL_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -168,13 +168,13 @@ typedef union { /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ - uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ - uint32_t :1; /*!< bit: 19 Reserved */ - uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ + uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } NVMCTRL_PARAM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -211,12 +211,12 @@ typedef union { /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ + uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } NVMCTRL_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -232,12 +232,12 @@ typedef union { /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ + uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } NVMCTRL_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -253,12 +253,12 @@ typedef union { /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready */ - uint8_t ERROR:1; /*!< bit: 1 Error */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready */ + uint8_t ERROR:1; /*!< bit: 1 Error */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } NVMCTRL_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -274,17 +274,17 @@ typedef union { /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ - uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ - uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ - uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ - uint16_t NVME:1; /*!< bit: 4 NVM Error */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t SB:1; /*!< bit: 8 Security Bit Status */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ + uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ + uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ + uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ + uint16_t NVME:1; /*!< bit: 4 NVM Error */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t SB:1; /*!< bit: 8 Security Bit Status */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } NVMCTRL_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -308,11 +308,11 @@ typedef union { /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } NVMCTRL_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -327,10 +327,10 @@ typedef union { /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } NVMCTRL_LOCK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -344,20 +344,20 @@ typedef union { /** \brief NVMCTRL APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - RoReg8 Reserved1[0x2]; - __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ - __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ - __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - RoReg8 Reserved2[0x3]; - __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ - RoReg8 Reserved3[0x3]; - __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x3]; - __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ - RoReg8 Reserved5[0x2]; - __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ - __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ + __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + RoReg8 Reserved1[0x2]; + __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ + __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ + __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + RoReg8 Reserved2[0x3]; + __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ + RoReg8 Reserved3[0x3]; + __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x3]; + __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ + RoReg8 Reserved5[0x2]; + __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ + __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ } Nvmctrl; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define SECTION_NVMCTRL_CAL diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h index 049fb2a3f2..43b8a4f792 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h @@ -59,11 +59,11 @@ /* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PAC_WPCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -78,11 +78,11 @@ typedef union { /* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PAC_WPSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -97,8 +97,8 @@ typedef union { /** \brief PAC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ - __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ + __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ + __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ } Pac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h similarity index 71% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h index 7e522dbe71..1dde1771ba 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h @@ -59,7 +59,7 @@ /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint8_t reg; /*!< Type used for register access */ + uint8_t reg; /*!< Type used for register access */ } PM_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -71,11 +71,11 @@ typedef union { /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_SLEEP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -96,11 +96,11 @@ typedef union { /* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W 8) External Reset Controller -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_EXTCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -114,11 +114,11 @@ typedef union { /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_CPUSEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -149,11 +149,11 @@ typedef union { /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_APBASEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -184,11 +184,11 @@ typedef union { /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_APBBSEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -219,11 +219,11 @@ typedef union { /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_APBCSEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -254,17 +254,17 @@ typedef union { /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ - uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ - uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ - uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ - uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ - uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ - uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ + uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ + uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ + uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ + uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ + uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ + uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_AHBMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -290,17 +290,17 @@ typedef union { /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ - uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ - uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ - uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ - uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ - uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ - uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ + uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ + uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ + uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ + uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ + uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ + uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_APBAMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -326,17 +326,17 @@ typedef union { /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ - uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ - uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ - uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ - uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ - uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ - uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ + uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ + uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ + uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ + uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ + uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ + uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_APBBMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -362,33 +362,33 @@ typedef union { /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ - uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ - uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ - uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ - uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ - uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ - uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ - uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ - uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ - uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ - uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ - uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ - uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ - uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ - uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */ - uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */ - uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ - uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ - uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */ - uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ - uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */ - uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */ - uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ + uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ + uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ + uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ + uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ + uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ + uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ + uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ + uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ + uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ + uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ + uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ + uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ + uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ + uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */ + uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */ + uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ + uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ + uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */ + uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ + uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */ + uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */ + uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_APBCMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -446,11 +446,11 @@ typedef union { /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -464,11 +464,11 @@ typedef union { /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -482,11 +482,11 @@ typedef union { /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -500,17 +500,17 @@ typedef union { /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t POR:1; /*!< bit: 0 Power On Reset */ - uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ - uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EXT:1; /*!< bit: 4 External Reset */ - uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ - uint8_t SYST:1; /*!< bit: 6 System Reset Request */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t POR:1; /*!< bit: 0 Power On Reset */ + uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ + uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EXT:1; /*!< bit: 4 External Reset */ + uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ + uint8_t SYST:1; /*!< bit: 6 System Reset Request */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_RCAUSE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -534,25 +534,25 @@ typedef union { /** \brief PM hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ - __IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */ - RoReg8 Reserved1[0x5]; - __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ - __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ - __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ - __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ - RoReg8 Reserved2[0x8]; - __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ - __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ - __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ - __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ - RoReg8 Reserved3[0x10]; - __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ - __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ - __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ + __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ + __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ + __IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */ + RoReg8 Reserved1[0x5]; + __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ + __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ + __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ + __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ + RoReg8 Reserved2[0x8]; + __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ + __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ + __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ + __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ + RoReg8 Reserved3[0x10]; + __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ + __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ + __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x1]; + __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ } Pm; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h similarity index 73% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h index a057f1824c..5d357d6e27 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h @@ -59,10 +59,10 @@ /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -77,10 +77,10 @@ typedef union { /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIRCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -95,10 +95,10 @@ typedef union { /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIRSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -113,10 +113,10 @@ typedef union { /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIRTGL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -131,10 +131,10 @@ typedef union { /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -149,10 +149,10 @@ typedef union { /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUTCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -167,10 +167,10 @@ typedef union { /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUTSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -185,10 +185,10 @@ typedef union { /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUTTGL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -203,10 +203,10 @@ typedef union { /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_IN_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -221,10 +221,10 @@ typedef union { /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -239,21 +239,21 @@ typedef union { /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ - uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ - uint32_t INEN:1; /*!< bit: 17 Input Enable */ - uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ - uint32_t :3; /*!< bit: 19..21 Reserved */ - uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ - uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ - uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ + uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ + uint32_t INEN:1; /*!< bit: 17 Input Enable */ + uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ + uint32_t :3; /*!< bit: 19..21 Reserved */ + uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ + uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ + uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_WRCONFIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -285,11 +285,11 @@ typedef union { /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */ - uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */ + uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PORT_PMUX_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -339,15 +339,15 @@ typedef union { /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ - uint8_t INEN:1; /*!< bit: 1 Input Enable */ - uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ + uint8_t INEN:1; /*!< bit: 1 Input Enable */ + uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PORT_PINCFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -367,28 +367,28 @@ typedef union { /** \brief PortGroup hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ - __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ - __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ - __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ - __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ - __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ - __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ - __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ - __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ - __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ - __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ - RoReg8 Reserved1[0x4]; - __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ - __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ - RoReg8 Reserved2[0x20]; + __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ + __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ + __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ + __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ + __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ + __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ + __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ + __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ + __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ + __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ + __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ + RoReg8 Reserved1[0x4]; + __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ + __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ + RoReg8 Reserved2[0x20]; } PortGroup; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief PORT hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ + PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ } Port; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define SECTION_PORT_IOBUS diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h similarity index 69% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h index a006274238..eff5738230 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h @@ -59,16 +59,16 @@ /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :3; /*!< bit: 4.. 6 Reserved */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :3; /*!< bit: 4.. 6 Reserved */ + uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE0_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -120,15 +120,15 @@ typedef union { /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -178,17 +178,17 @@ typedef union { /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :2; /*!< bit: 4.. 5 Reserved */ - uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :2; /*!< bit: 4.. 5 Reserved */ + uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ + uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE2_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -242,13 +242,13 @@ typedef union { /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ - uint16_t :8; /*!< bit: 6..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ + uint16_t :8; /*!< bit: 6..13 Reserved */ + uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ + uint16_t RREQ:1; /*!< bit: 15 Read Request */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_READREQ_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -267,25 +267,25 @@ typedef union { /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE0_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -323,26 +323,26 @@ typedef union { /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ - uint16_t :5; /*!< bit: 10..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ + uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ + uint16_t :5; /*!< bit: 10..14 Reserved */ + uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -382,25 +382,25 @@ typedef union { /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE2_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -438,17 +438,17 @@ typedef union { /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE0_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -469,18 +469,18 @@ typedef union { /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE1_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -503,17 +503,17 @@ typedef union { /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -534,17 +534,17 @@ typedef union { /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE0_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -565,18 +565,18 @@ typedef union { /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE1_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -599,17 +599,17 @@ typedef union { /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -630,17 +630,17 @@ typedef union { /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ + uint8_t OVF:1; /*!< bit: 7 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:1; /*!< bit: 0 Compare x */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE0_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -661,18 +661,18 @@ typedef union { /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ + uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ + uint8_t OVF:1; /*!< bit: 7 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE1_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -695,17 +695,17 @@ typedef union { /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ + uint8_t OVF:1; /*!< bit: 7 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t ALARM:1; /*!< bit: 0 Alarm x */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -726,11 +726,11 @@ typedef union { /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -744,11 +744,11 @@ typedef union { /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -762,11 +762,11 @@ typedef union { /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ - uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ + uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_FREQCORR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -783,10 +783,10 @@ typedef union { /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE0_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -801,10 +801,10 @@ typedef union { /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -819,15 +819,15 @@ typedef union { /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ + uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ + uint32_t HOUR:5; /*!< bit: 12..16 Hour */ + uint32_t DAY:5; /*!< bit: 17..21 Day */ + uint32_t MONTH:4; /*!< bit: 22..25 Month */ + uint32_t YEAR:6; /*!< bit: 26..31 Year */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE2_CLOCK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -859,10 +859,10 @@ typedef union { /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PER:16; /*!< bit: 0..15 Counter Period */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PER:16; /*!< bit: 0..15 Counter Period */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -877,10 +877,10 @@ typedef union { /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE0_COMP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -895,10 +895,10 @@ typedef union { /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_COMP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -913,15 +913,15 @@ typedef union { /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ + uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ + uint32_t HOUR:5; /*!< bit: 12..16 Hour */ + uint32_t DAY:5; /*!< bit: 17..21 Day */ + uint32_t MONTH:4; /*!< bit: 22..25 Month */ + uint32_t YEAR:6; /*!< bit: 26..31 Year */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE2_ALARM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -951,11 +951,11 @@ typedef union { /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_MASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -984,79 +984,79 @@ typedef union { /** \brief RtcMode2Alarm hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ - __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ - RoReg8 Reserved1[0x3]; + __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ + __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ + RoReg8 Reserved1[0x3]; } RtcMode2Alarm; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief RTC_MODE0 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 32-bit Counter with Single 32-bit Compare */ - __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ - __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ - __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ - __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ + __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ + __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ + __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ + __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ + __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ + RoReg8 Reserved2[0x3]; + __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ + RoReg8 Reserved3[0x4]; + __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ } RtcMode0; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief RTC_MODE1 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 16-bit Counter with Two 16-bit Compares */ - __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ - __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ - __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ - __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ - RoReg8 Reserved3[0x2]; - __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ - RoReg8 Reserved4[0x2]; - __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ + __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ + __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ + __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ + __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ + __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ + RoReg8 Reserved2[0x3]; + __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ + RoReg8 Reserved3[0x2]; + __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ + RoReg8 Reserved4[0x2]; + __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ } RtcMode1; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief RTC_MODE2 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* Clock/Calendar with Alarm */ - __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ - __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ - __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ - __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ - RoReg8 Reserved3[0x4]; - RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ + __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ + __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ + __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ + __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ + __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ + RoReg8 Reserved2[0x3]; + __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ + RoReg8 Reserved3[0x4]; + RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ } RtcMode2; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ - RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ - RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ + RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ + RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ + RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ } Rtc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h similarity index 66% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h index d26df24fc3..ee0733bea3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h @@ -59,26 +59,26 @@ /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -130,26 +130,26 @@ typedef union { /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t :2; /*!< bit: 28..29 Reserved */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -196,25 +196,25 @@ typedef union { /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :7; /*!< bit: 9..15 Reserved */ + uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -264,26 +264,26 @@ typedef union { /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :4; /*!< bit: 9..12 Reserved */ - uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ - uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ - uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :4; /*!< bit: 9..12 Reserved */ + uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ + uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ + uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_USART_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -339,16 +339,16 @@ typedef union { /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -369,18 +369,18 @@ typedef union { /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ - uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ - uint32_t :3; /*!< bit: 11..13 Reserved */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ + uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ + uint32_t :3; /*!< bit: 11..13 Reserved */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -406,20 +406,20 @@ typedef union { /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ - uint32_t :2; /*!< bit: 7.. 8 Reserved */ - uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ - uint32_t :3; /*!< bit: 10..12 Reserved */ - uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ + uint32_t :2; /*!< bit: 7.. 8 Reserved */ + uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ + uint32_t :3; /*!< bit: 10..12 Reserved */ + uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -445,22 +445,22 @@ typedef union { /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ - uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ - uint32_t ENC:1; /*!< bit: 10 Encoding Format */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ + uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ + uint32_t ENC:1; /*!< bit: 10 Encoding Format */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_USART_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -489,13 +489,13 @@ typedef union { /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ - uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ - uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ + uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ + uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_BAUD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -519,10 +519,10 @@ typedef union { /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_BAUD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -537,21 +537,21 @@ typedef union { /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - struct { // FRAC mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRAC; /*!< Structure used for FRAC */ - struct { // FRACFP mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRACFP; /*!< Structure used for FRACFP */ - struct { // USARTFP mode - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } USARTFP; /*!< Structure used for USARTFP */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + struct { // FRAC mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRAC; /*!< Structure used for FRAC */ + struct { // FRACFP mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRACFP; /*!< Structure used for FRACFP */ + struct { // USARTFP mode + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } USARTFP; /*!< Structure used for USARTFP */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_USART_BAUD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -590,10 +590,10 @@ typedef union { /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_RXPL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -608,13 +608,13 @@ typedef union { /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -632,14 +632,14 @@ typedef union { /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -659,15 +659,15 @@ typedef union { /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -689,17 +689,17 @@ typedef union { /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -725,13 +725,13 @@ typedef union { /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -749,14 +749,14 @@ typedef union { /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -776,15 +776,15 @@ typedef union { /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -806,17 +806,17 @@ typedef union { /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -842,13 +842,13 @@ typedef union { /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -866,14 +866,14 @@ typedef union { /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -893,15 +893,15 @@ typedef union { /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -923,17 +923,17 @@ typedef union { /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -959,20 +959,20 @@ typedef union { /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t LENERR:1; /*!< bit: 10 Length Error */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t LENERR:1; /*!< bit: 10 Length Error */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_I2CM_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1003,21 +1003,21 @@ typedef union { /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ - uint16_t SR:1; /*!< bit: 4 Repeated Start */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t :1; /*!< bit: 8 Reserved */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t HS:1; /*!< bit: 10 High Speed */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ + uint16_t SR:1; /*!< bit: 4 Repeated Start */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t :1; /*!< bit: 8 Reserved */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t HS:1; /*!< bit: 10 High Speed */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_I2CS_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1047,12 +1047,12 @@ typedef union { /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t :13; /*!< bit: 3..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t :13; /*!< bit: 3..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_SPI_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1066,16 +1066,16 @@ typedef union { /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PERR:1; /*!< bit: 0 Parity Error */ - uint16_t FERR:1; /*!< bit: 1 Frame Error */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t CTS:1; /*!< bit: 3 Clear To Send */ - uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ - uint16_t COLL:1; /*!< bit: 5 Collision Detected */ - uint16_t :10; /*!< bit: 6..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PERR:1; /*!< bit: 0 Parity Error */ + uint16_t FERR:1; /*!< bit: 1 Frame Error */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t CTS:1; /*!< bit: 3 Clear To Send */ + uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ + uint16_t COLL:1; /*!< bit: 5 Collision Detected */ + uint16_t :10; /*!< bit: 6..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_USART_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1099,13 +1099,13 @@ typedef union { /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1123,12 +1123,12 @@ typedef union { /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1144,13 +1144,13 @@ typedef union { /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1168,13 +1168,13 @@ typedef union { /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_USART_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1192,16 +1192,16 @@ typedef union { /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t LENEN:1; /*!< bit: 13 Length Enable */ - uint32_t HS:1; /*!< bit: 14 High Speed Mode */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t LEN:8; /*!< bit: 16..23 Length */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t LENEN:1; /*!< bit: 13 Length Enable */ + uint32_t HS:1; /*!< bit: 14 High Speed Mode */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t LEN:8; /*!< bit: 16..23 Length */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1225,16 +1225,16 @@ typedef union { /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ - uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ - uint32_t :4; /*!< bit: 11..14 Reserved */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ + uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ + uint32_t :4; /*!< bit: 11..14 Reserved */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1256,13 +1256,13 @@ typedef union { /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1280,10 +1280,10 @@ typedef union { /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1298,10 +1298,10 @@ typedef union { /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1316,11 +1316,11 @@ typedef union { /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint32_t :23; /*!< bit: 9..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint32_t :23; /*!< bit: 9..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1335,11 +1335,11 @@ typedef union { /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_USART_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1354,11 +1354,11 @@ typedef union { /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1372,11 +1372,11 @@ typedef union { /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1390,11 +1390,11 @@ typedef union { /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1408,101 +1408,101 @@ typedef union { /** \brief SERCOM_I2CM hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* I2C Master Mode */ - __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ - __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ - RoReg8 Reserved2[0x4]; - __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ - __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ - __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ - RoReg8 Reserved7[0x7]; - __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ + __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ + __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ + RoReg8 Reserved2[0x4]; + __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ + __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ + __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ + RoReg8 Reserved7[0x7]; + __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ } SercomI2cm; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief SERCOM_I2CS hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* I2C Slave Mode */ - __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ - __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ - RoReg8 Reserved1[0xC]; - __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ - RoReg8 Reserved2[0x1]; - __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ - __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ - RoReg8 Reserved5[0x4]; - __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ - __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ + __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ + __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ + RoReg8 Reserved1[0xC]; + __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ + RoReg8 Reserved2[0x1]; + __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ + __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ + RoReg8 Reserved5[0x4]; + __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ + __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ } SercomI2cs; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief SERCOM_SPI hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* SPI Mode */ - __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ - __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ - RoReg8 Reserved2[0x7]; - __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ - __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ - __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ - RoReg8 Reserved7[0x4]; - __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ + __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ + __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ + RoReg8 Reserved2[0x7]; + __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ + __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ + __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ + RoReg8 Reserved7[0x4]; + __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ } SercomSpi; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief SERCOM_USART hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USART Mode */ - __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ - __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ - __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ - RoReg8 Reserved2[0x5]; - __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ - __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ - RoReg8 Reserved6[0x8]; - __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ - RoReg8 Reserved7[0x6]; - __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ + __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ + __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ + __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ + RoReg8 Reserved2[0x5]; + __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ + __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ + RoReg8 Reserved6[0x8]; + __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ + RoReg8 Reserved7[0x6]; + __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ } SercomUsart; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ - SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ - SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ - SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ + SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ + SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ + SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ + SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ } Sercom; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h similarity index 68% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h index 1583d8893a..6cd64b6ea9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h @@ -59,26 +59,26 @@ /* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -120,26 +120,26 @@ typedef union { /* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -181,26 +181,26 @@ typedef union { /* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -242,26 +242,26 @@ typedef union { /* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_PCLKSR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -303,18 +303,18 @@ typedef union { /* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t :3; /*!< bit: 3.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ - uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ - uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint16_t :3; /*!< bit: 3.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ + uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ + uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_XOSC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -352,21 +352,21 @@ typedef union { /* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ - uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ - uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ + uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ + uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_XOSC32K_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -397,22 +397,22 @@ typedef union { /* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ - uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ - uint32_t :2; /*!< bit: 4.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ + uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ + uint32_t :2; /*!< bit: 4.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_OSC32K_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -442,12 +442,12 @@ typedef union { /* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_OSCULP32K_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -464,19 +464,19 @@ typedef union { /* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t :4; /*!< bit: 2.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t :4; /*!< bit: 2.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ + uint32_t :2; /*!< bit: 28..29 Reserved */ + uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_OSC8M_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -519,22 +519,22 @@ typedef union { /* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ - uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ - uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ - uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ - uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ - uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ - uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ - uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ + uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ + uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ + uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ + uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ + uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ + uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ + uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -568,12 +568,12 @@ typedef union { /* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ - uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ - uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ + uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ + uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLVAL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -594,12 +594,12 @@ typedef union { /* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ - uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ - uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ + uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ + uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLMUL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -620,11 +620,11 @@ typedef union { /* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t READREQ:1; /*!< bit: 7 Read Request */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t READREQ:1; /*!< bit: 7 Read Request */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLSYNC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -638,22 +638,22 @@ typedef union { /* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t HYST:1; /*!< bit: 2 Hysteresis */ - uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MODE:1; /*!< bit: 8 Operation Mode */ - uint32_t CEN:1; /*!< bit: 9 Clock Enable */ - uint32_t :2; /*!< bit: 10..11 Reserved */ - uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ - uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t HYST:1; /*!< bit: 2 Hysteresis */ + uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MODE:1; /*!< bit: 8 Operation Mode */ + uint32_t CEN:1; /*!< bit: 9 Clock Enable */ + uint32_t :2; /*!< bit: 10..11 Reserved */ + uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ + uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_BOD33_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -722,14 +722,14 @@ typedef union { /* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :6; /*!< bit: 0.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t :6; /*!< bit: 7..12 Reserved */ - uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :6; /*!< bit: 0.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t :6; /*!< bit: 7..12 Reserved */ + uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_VREG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -745,15 +745,15 @@ typedef union { /* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ - uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ - uint32_t :13; /*!< bit: 3..15 Reserved */ - uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ + uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ + uint32_t :13; /*!< bit: 3..15 Reserved */ + uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_VREF_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -772,14 +772,14 @@ typedef union { /* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -797,13 +797,13 @@ typedef union { /* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLRATIO_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -821,20 +821,20 @@ typedef union { /* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ - uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ - uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ - uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ + uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ + uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ + uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -888,14 +888,14 @@ typedef union { /* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ - uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ - uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ - uint8_t DIV:1; /*!< bit: 3 Divider Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ + uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ + uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ + uint8_t DIV:1; /*!< bit: 3 Divider Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -915,34 +915,34 @@ typedef union { /** \brief SYSCTRL hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ - __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ - __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ - __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ - __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ - RoReg8 Reserved1[0x2]; - __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ - RoReg8 Reserved2[0x2]; - __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ - __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ - RoReg8 Reserved3[0x3]; - __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ - __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ - RoReg8 Reserved4[0x2]; - __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ - __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ - __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ - RoReg8 Reserved5[0x3]; - __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ - RoReg8 Reserved6[0x4]; - __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ - RoReg8 Reserved7[0x2]; - __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ - __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ - RoReg8 Reserved8[0x3]; - __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ - __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ - __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ + __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ + __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ + __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ + __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ + __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ + RoReg8 Reserved1[0x2]; + __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ + RoReg8 Reserved2[0x2]; + __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ + __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ + RoReg8 Reserved3[0x3]; + __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ + __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ + RoReg8 Reserved4[0x2]; + __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ + __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ + __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ + RoReg8 Reserved5[0x3]; + __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ + RoReg8 Reserved6[0x4]; + __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ + RoReg8 Reserved7[0x2]; + __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ + __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ + RoReg8 Reserved8[0x3]; + __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ + __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ + __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ } Sysctrl; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h similarity index 64% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h index f631f961dd..5bf0b1f9f6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h @@ -59,19 +59,19 @@ /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -137,13 +137,13 @@ typedef union { /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ - uint16_t :9; /*!< bit: 5..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ + uint16_t :9; /*!< bit: 5..13 Reserved */ + uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ + uint16_t RREQ:1; /*!< bit: 15 Read Request */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_READREQ_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -162,14 +162,14 @@ typedef union { /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t CMD:2; /*!< bit: 6.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_CTRLBCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -194,14 +194,14 @@ typedef union { /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t CMD:2; /*!< bit: 6.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_CTRLBSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -226,21 +226,21 @@ typedef union { /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ - uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ - uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ + uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ + uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_CTRLC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -266,11 +266,11 @@ typedef union { /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -284,24 +284,24 @@ typedef union { /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ - uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ - uint16_t :3; /*!< bit: 9..11 Reserved */ - uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ - uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :12; /*!< bit: 0..11 Reserved */ - uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ + uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ + uint16_t :3; /*!< bit: 9..11 Reserved */ + uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ + uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :12; /*!< bit: 0..11 Reserved */ + uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -341,21 +341,21 @@ typedef union { /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -380,21 +380,21 @@ typedef union { /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -419,21 +419,21 @@ typedef union { /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow */ - uint8_t ERR:1; /*!< bit: 1 Error */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow */ + uint8_t ERR:1; /*!< bit: 1 Error */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -458,14 +458,14 @@ typedef union { /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :3; /*!< bit: 0.. 2 Reserved */ - uint8_t STOP:1; /*!< bit: 3 Stop */ - uint8_t SLAVE:1; /*!< bit: 4 Slave */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :3; /*!< bit: 0.. 2 Reserved */ + uint8_t STOP:1; /*!< bit: 3 Stop */ + uint8_t SLAVE:1; /*!< bit: 4 Slave */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -483,10 +483,10 @@ typedef union { /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_COUNT16_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -501,10 +501,10 @@ typedef union { /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TC_COUNT32_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -519,10 +519,10 @@ typedef union { /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_COUNT8_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -537,10 +537,10 @@ typedef union { /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_COUNT8_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -555,10 +555,10 @@ typedef union { /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_COUNT16_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -573,10 +573,10 @@ typedef union { /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TC_COUNT32_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -591,10 +591,10 @@ typedef union { /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_COUNT8_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -609,76 +609,76 @@ typedef union { /** \brief TC_COUNT8 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 8-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ - RoReg8 Reserved3[0x3]; - __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ - RoReg8 Reserved4[0x3]; - __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ + RoReg8 Reserved3[0x3]; + __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ + RoReg8 Reserved4[0x3]; + __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ } TcCount8; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief TC_COUNT16 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 16-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ - RoReg8 Reserved3[0x6]; - __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ + RoReg8 Reserved3[0x6]; + __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ } TcCount16; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief TC_COUNT32 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 32-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ + RoReg8 Reserved3[0x4]; + __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ } TcCount32; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ - TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ - TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ + TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ + TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ + TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ } Tc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h similarity index 68% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h index ddbf7bb6ae..fc23a16d11 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h @@ -59,29 +59,29 @@ /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t :3; /*!< bit: 2.. 4 Reserved */ - uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ - uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ - uint32_t :9; /*!< bit: 15..23 Reserved */ - uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ - uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ - uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ - uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :24; /*!< bit: 0..23 Reserved */ - uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t :3; /*!< bit: 2.. 4 Reserved */ + uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ + uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ + uint32_t :9; /*!< bit: 15..23 Reserved */ + uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ + uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ + uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ + uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :24; /*!< bit: 0..23 Reserved */ + uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -151,14 +151,14 @@ typedef union { /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_CTRLBCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -200,14 +200,14 @@ typedef union { /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_CTRLBSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -249,37 +249,37 @@ typedef union { /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ - uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ - uint32_t STATUS:1; /*!< bit: 3 Status Busy */ - uint32_t COUNT:1; /*!< bit: 4 Count Busy */ - uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ - uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ - uint32_t PER:1; /*!< bit: 7 Period busy */ - uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ - uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ - uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ - uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ - uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ - uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ - uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ - uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ - uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ - uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ - uint32_t :7; /*!< bit: 12..18 Reserved */ - uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ + uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ + uint32_t STATUS:1; /*!< bit: 3 Status Busy */ + uint32_t COUNT:1; /*!< bit: 4 Count Busy */ + uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ + uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ + uint32_t PER:1; /*!< bit: 7 Period busy */ + uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ + uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ + uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ + uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ + uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ + uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ + uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ + uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ + uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ + uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ + uint32_t :7; /*!< bit: 12..18 Reserved */ + uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -335,22 +335,22 @@ typedef union { /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_FCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -435,22 +435,22 @@ typedef union { /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_FCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -535,23 +535,23 @@ typedef union { /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ - uint32_t :6; /*!< bit: 2.. 7 Reserved */ - uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ - uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ - uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ - uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ - uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ + uint32_t :6; /*!< bit: 2.. 7 Reserved */ + uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ + uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ + uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ + uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ + uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WEXCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -583,41 +583,41 @@ typedef union { /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ - uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ - uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ - uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ - uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ - uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ - uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ - uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ - uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ - uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ - uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ - uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ - uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ - uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ - uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ - uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ - uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ - uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ - uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ - uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ - uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ - uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ - uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ - uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ - uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ - uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ - uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ - uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ + uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ + uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ + uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ + uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ + uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ + uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ + uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ + uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ + uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ + uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ + uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ + uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ + uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ + uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ + uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ + uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ + uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ + uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ + uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ + uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ + uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ + uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ + uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ + uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ + uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ + uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ + uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_DRVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -692,13 +692,13 @@ typedef union { /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -714,39 +714,39 @@ typedef union { /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ - uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ - uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ - uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ - uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ - uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ - uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ - uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ - uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ - uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ - uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ - uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ - uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ - uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ - uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ - uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :12; /*!< bit: 0..11 Reserved */ - uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ - uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ - uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ + uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ + uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ + uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ + uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ + uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ + uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ + uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ + uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ + uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ + uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ + uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ + uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ + uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ + uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ + uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :12; /*!< bit: 0..11 Reserved */ + uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ + uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ + uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -847,29 +847,29 @@ typedef union { /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -910,29 +910,29 @@ typedef union { /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -973,29 +973,29 @@ typedef union { /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow */ - uint32_t TRG:1; /*!< bit: 1 Retrigger */ - uint32_t CNT:1; /*!< bit: 2 Counter */ - uint32_t ERR:1; /*!< bit: 3 Error */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow */ + uint32_t TRG:1; /*!< bit: 1 Retrigger */ + uint32_t CNT:1; /*!< bit: 2 Counter */ + uint32_t ERR:1; /*!< bit: 3 Error */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1036,42 +1036,42 @@ typedef union { /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t STOP:1; /*!< bit: 0 Stop */ - uint32_t IDX:1; /*!< bit: 1 Ramp */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ - uint32_t SLAVE:1; /*!< bit: 4 Slave */ - uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ - uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ - uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ - uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ - uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ - uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ - uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ - uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ - uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ - uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ - uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ - uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ - uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ - uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t STOP:1; /*!< bit: 0 Stop */ + uint32_t IDX:1; /*!< bit: 1 Ramp */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ + uint32_t SLAVE:1; /*!< bit: 4 Slave */ + uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ + uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ + uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ + uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ + uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ + uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ + uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ + uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ + uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ + uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ + uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ + uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ + uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ + uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1135,26 +1135,26 @@ typedef union { /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t :6; /*!< bit: 0.. 5 Reserved */ - uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t :6; /*!< bit: 0.. 5 Reserved */ + uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1187,29 +1187,29 @@ typedef union { /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ - uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ - uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ - uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ - uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ - uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ - uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ - uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ - uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ - uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ - uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ - uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ - uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ - uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ - uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ - uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ - uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ + uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ + uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ + uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ + uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ + uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ + uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ + uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ + uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ + uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ + uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ + uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ + uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ + uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ + uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ + uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ + uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TCC_PATT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1259,38 +1259,38 @@ typedef union { /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ - uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ - uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ - uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ - uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ - uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ - uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ - uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ - uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ - uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ - uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ + uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ + uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ + uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ + uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ + uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ + uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ + uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ + uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ + uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ + uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WAVE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1363,26 +1363,26 @@ typedef union { /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t PER:20; /*!< bit: 4..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t PER:19; /*!< bit: 5..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t PER:18; /*!< bit: 6..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PER:24; /*!< bit: 0..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t PER:20; /*!< bit: 4..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t PER:19; /*!< bit: 5..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t PER:18; /*!< bit: 6..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PER:24; /*!< bit: 0..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1424,26 +1424,26 @@ typedef union { /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1485,29 +1485,29 @@ typedef union { /* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ - uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ - uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ - uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ - uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ - uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ - uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ - uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ - uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ - uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ - uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ - uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ - uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ - uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ - uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ - uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ - uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ + uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ + uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ + uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ + uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ + uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ + uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ + uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ + uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ + uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ + uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ + uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ + uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ + uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ + uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ + uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ + uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TCC_PATTB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1557,38 +1557,38 @@ typedef union { /* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ - uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ - uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ - uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ - uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ - uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ - uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ - uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ - uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ - uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ - uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ + uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ + uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ + uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ + uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ + uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ + uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ + uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ + uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ + uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ + uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WAVEB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1661,26 +1661,26 @@ typedef union { /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_PERB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1722,26 +1722,26 @@ typedef union { /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CCB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1783,35 +1783,35 @@ typedef union { /** \brief TCC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - RoReg8 Reserved1[0x2]; - __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ - __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ - __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ - __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ - RoReg8 Reserved2[0x2]; - __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ - RoReg8 Reserved3[0x1]; - __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ - __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ - __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ - __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ - __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ - __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ - __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ - RoReg8 Reserved4[0x2]; - __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ - __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ - __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ - RoReg8 Reserved5[0x10]; - __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ - RoReg8 Reserved6[0x2]; - __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ - __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ - __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ + __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + RoReg8 Reserved1[0x2]; + __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ + __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ + __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ + __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ + RoReg8 Reserved2[0x2]; + __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ + RoReg8 Reserved3[0x1]; + __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ + __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ + __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ + __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ + __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ + __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ + __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ + RoReg8 Reserved4[0x2]; + __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ + __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ + __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ + RoReg8 Reserved5[0x10]; + __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ + RoReg8 Reserved6[0x2]; + __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ + __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ + __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ } Tcc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h similarity index 69% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h index 41ae22acf4..9c1f64a7bd 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h @@ -56,29 +56,29 @@ /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t :3; /*!< bit: 2.. 4 Reserved */ - uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ - uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ - uint32_t :9; /*!< bit: 15..23 Reserved */ - uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ - uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ - uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ - uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :24; /*!< bit: 0..23 Reserved */ - uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t :3; /*!< bit: 2.. 4 Reserved */ + uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ + uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ + uint32_t :9; /*!< bit: 15..23 Reserved */ + uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ + uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ + uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ + uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :24; /*!< bit: 0..23 Reserved */ + uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -148,14 +148,14 @@ typedef union { /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_CTRLBCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -197,14 +197,14 @@ typedef union { /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_CTRLBSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -246,37 +246,37 @@ typedef union { /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ - uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ - uint32_t STATUS:1; /*!< bit: 3 Status Busy */ - uint32_t COUNT:1; /*!< bit: 4 Count Busy */ - uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ - uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ - uint32_t PER:1; /*!< bit: 7 Period busy */ - uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ - uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ - uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ - uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ - uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ - uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ - uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ - uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ - uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ - uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ - uint32_t :7; /*!< bit: 12..18 Reserved */ - uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ + uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ + uint32_t STATUS:1; /*!< bit: 3 Status Busy */ + uint32_t COUNT:1; /*!< bit: 4 Count Busy */ + uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ + uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ + uint32_t PER:1; /*!< bit: 7 Period busy */ + uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ + uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ + uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ + uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ + uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ + uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ + uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ + uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ + uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ + uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ + uint32_t :7; /*!< bit: 12..18 Reserved */ + uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -332,22 +332,22 @@ typedef union { /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_FCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -434,22 +434,22 @@ typedef union { /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_FCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -536,23 +536,23 @@ typedef union { /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ - uint32_t :6; /*!< bit: 2.. 7 Reserved */ - uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ - uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ - uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ - uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ - uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ + uint32_t :6; /*!< bit: 2.. 7 Reserved */ + uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ + uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ + uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ + uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ + uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WEXCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -584,41 +584,41 @@ typedef union { /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ - uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ - uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ - uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ - uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ - uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ - uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ - uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ - uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ - uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ - uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ - uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ - uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ - uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ - uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ - uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ - uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ - uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ - uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ - uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ - uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ - uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ - uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ - uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ - uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ - uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ - uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ - uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ + uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ + uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ + uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ + uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ + uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ + uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ + uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ + uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ + uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ + uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ + uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ + uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ + uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ + uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ + uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ + uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ + uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ + uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ + uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ + uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ + uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ + uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ + uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ + uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ + uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ + uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ + uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_DRVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -693,13 +693,13 @@ typedef union { /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -715,39 +715,39 @@ typedef union { /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ - uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ - uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ - uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ - uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ - uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ - uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ - uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ - uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ - uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ - uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ - uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ - uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ - uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ - uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ - uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :12; /*!< bit: 0..11 Reserved */ - uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ - uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ - uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ + uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ + uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ + uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ + uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ + uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ + uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ + uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ + uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ + uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ + uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ + uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ + uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ + uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ + uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ + uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :12; /*!< bit: 0..11 Reserved */ + uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ + uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ + uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -850,30 +850,30 @@ typedef union { /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :6; /*!< bit: 4.. 9 Reserved */ - uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -916,30 +916,30 @@ typedef union { /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :6; /*!< bit: 4.. 9 Reserved */ - uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -982,30 +982,30 @@ typedef union { /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow */ - uint32_t TRG:1; /*!< bit: 1 Retrigger */ - uint32_t CNT:1; /*!< bit: 2 Counter */ - uint32_t ERR:1; /*!< bit: 3 Error */ - uint32_t :6; /*!< bit: 4.. 9 Reserved */ - uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow */ + uint32_t TRG:1; /*!< bit: 1 Retrigger */ + uint32_t CNT:1; /*!< bit: 2 Counter */ + uint32_t ERR:1; /*!< bit: 3 Error */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1048,42 +1048,42 @@ typedef union { /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t STOP:1; /*!< bit: 0 Stop */ - uint32_t IDX:1; /*!< bit: 1 Ramp */ - uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */ - uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ - uint32_t SLAVE:1; /*!< bit: 4 Slave */ - uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ - uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ - uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ - uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ - uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ - uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ - uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ - uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ - uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ - uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ - uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ - uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ - uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ - uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t STOP:1; /*!< bit: 0 Stop */ + uint32_t IDX:1; /*!< bit: 1 Ramp */ + uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */ + uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ + uint32_t SLAVE:1; /*!< bit: 4 Slave */ + uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ + uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ + uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ + uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ + uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ + uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ + uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ + uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ + uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ + uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ + uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ + uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ + uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ + uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1149,26 +1149,26 @@ typedef union { /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t :6; /*!< bit: 0.. 5 Reserved */ - uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t :6; /*!< bit: 0.. 5 Reserved */ + uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1201,29 +1201,29 @@ typedef union { /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ - uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ - uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ - uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ - uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ - uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ - uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ - uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ - uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ - uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ - uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ - uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ - uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ - uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ - uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ - uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ - uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ + uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ + uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ + uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ + uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ + uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ + uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ + uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ + uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ + uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ + uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ + uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ + uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ + uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ + uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ + uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ + uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TCC_PATT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1273,38 +1273,38 @@ typedef union { /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ - uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ - uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ - uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ - uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ - uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ - uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ - uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ - uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ - uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ - uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ + uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ + uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ + uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ + uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ + uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ + uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ + uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ + uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ + uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ + uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WAVE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1379,26 +1379,26 @@ typedef union { /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t PER:20; /*!< bit: 4..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t PER:19; /*!< bit: 5..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t PER:18; /*!< bit: 6..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PER:24; /*!< bit: 0..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t PER:20; /*!< bit: 4..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t PER:19; /*!< bit: 5..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t PER:18; /*!< bit: 6..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PER:24; /*!< bit: 0..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1440,26 +1440,26 @@ typedef union { /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1501,29 +1501,29 @@ typedef union { /* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ - uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ - uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ - uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ - uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ - uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ - uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ - uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ - uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ - uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ - uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ - uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ - uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ - uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ - uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ - uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ - uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ + uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ + uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ + uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ + uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ + uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ + uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ + uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ + uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ + uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ + uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ + uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ + uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ + uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ + uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ + uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ + uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TCC_PATTB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1573,38 +1573,38 @@ typedef union { /* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ - uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ - uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ - uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ - uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ - uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ - uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ - uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ - uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ - uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ - uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ + uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ + uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ + uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ + uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ + uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ + uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ + uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ + uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ + uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ + uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WAVEB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1679,26 +1679,26 @@ typedef union { /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_PERB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1740,26 +1740,26 @@ typedef union { /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CCB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1801,35 +1801,35 @@ typedef union { /** \brief TCC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - RoReg8 Reserved1[0x2]; - __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ - __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ - __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ - __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ - RoReg8 Reserved2[0x2]; - __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ - RoReg8 Reserved3[0x1]; - __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ - __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ - __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ - __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ - __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ - __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ - __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ - RoReg8 Reserved4[0x2]; - __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ - __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ - __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ - RoReg8 Reserved5[0x10]; - __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ - RoReg8 Reserved6[0x2]; - __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ - __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ - __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ + __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + RoReg8 Reserved1[0x2]; + __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ + __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ + __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ + __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ + RoReg8 Reserved2[0x2]; + __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ + RoReg8 Reserved3[0x1]; + __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ + __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ + __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ + __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ + __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ + __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ + __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ + RoReg8 Reserved4[0x2]; + __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ + __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ + __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ + RoReg8 Reserved5[0x10]; + __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ + RoReg8 Reserved6[0x2]; + __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ + __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ + __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ } Tcc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h similarity index 66% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h index 7586ee5d9a..8a74359425 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h @@ -59,14 +59,14 @@ /* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t MODE:1; /*!< bit: 7 Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t MODE:1; /*!< bit: 7 Operating Mode */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -90,12 +90,12 @@ typedef union { /* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -111,12 +111,12 @@ typedef union { /* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ - uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ + uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_QOSCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -150,20 +150,20 @@ typedef union { /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DETACH:1; /*!< bit: 0 Detach */ - uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ - uint16_t NREPLY:1; /*!< bit: 4 No Reply */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ - uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ - uint16_t GNAK:1; /*!< bit: 9 Global NAK */ - uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DETACH:1; /*!< bit: 0 Detach */ + uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ + uint16_t NREPLY:1; /*!< bit: 4 No Reply */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ + uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ + uint16_t GNAK:1; /*!< bit: 9 Global NAK */ + uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -213,21 +213,21 @@ typedef union { /* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ - uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ - uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ - uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ + uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ + uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ + uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -260,11 +260,11 @@ typedef union { /* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ - uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ + uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_DADD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -281,12 +281,12 @@ typedef union { /* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_HSOFC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -303,13 +303,13 @@ typedef union { /* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -339,13 +339,13 @@ typedef union { /* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -363,11 +363,11 @@ typedef union { /* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_FSMSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -396,13 +396,13 @@ typedef union { /* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :1; /*!< bit: 14 Reserved */ - uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :1; /*!< bit: 14 Reserved */ + uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_FNUM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -422,12 +422,12 @@ typedef union { /* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_FNUM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -445,10 +445,10 @@ typedef union { /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_FLENHIGH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -463,20 +463,20 @@ typedef union { /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -508,19 +508,19 @@ typedef union { /* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ - uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ + uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ + uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -548,20 +548,20 @@ typedef union { /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -593,19 +593,19 @@ typedef union { /* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ - uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ + uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -633,20 +633,20 @@ typedef union { /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ - uint16_t EORST:1; /*!< bit: 3 End of Reset */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ + uint16_t EORST:1; /*!< bit: 3 End of Reset */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -678,19 +678,19 @@ typedef union { /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ - uint16_t RST:1; /*!< bit: 3 Bus Reset */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - uint16_t DNRSM:1; /*!< bit: 5 Downstream */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ + uint16_t RST:1; /*!< bit: 3 Bus Reset */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + uint16_t DNRSM:1; /*!< bit: 5 Downstream */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + uint16_t DCONN:1; /*!< bit: 8 Device Connection */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -718,22 +718,22 @@ typedef union { /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTSMRY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -764,22 +764,22 @@ typedef union { /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_PINTSMRY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -810,10 +810,10 @@ typedef union { /* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_DESCADD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -828,15 +828,15 @@ typedef union { /* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_PADCAL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -857,13 +857,13 @@ typedef union { /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ - uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ + uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPCFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -883,13 +883,13 @@ typedef union { /* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ - uint8_t BK:1; /*!< bit: 2 Pipe Bank */ - uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ + uint8_t BK:1; /*!< bit: 2 Pipe Bank */ + uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PCFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -909,10 +909,10 @@ typedef union { /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_BINTERVAL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -927,22 +927,22 @@ typedef union { /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ + uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPSTATUSCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -971,17 +971,17 @@ typedef union { /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PSTATUSCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1003,22 +1003,22 @@ typedef union { /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPSTATUSSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1047,17 +1047,17 @@ typedef union { /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PSTATUSSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1079,22 +1079,22 @@ typedef union { /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1123,17 +1123,17 @@ typedef union { /* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1155,24 +1155,24 @@ typedef union { /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1207,20 +1207,20 @@ typedef union { /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PINTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1247,24 +1247,24 @@ typedef union { /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1299,20 +1299,20 @@ typedef union { /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PINTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1339,24 +1339,24 @@ typedef union { /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1391,20 +1391,20 @@ typedef union { /* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PINTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1431,10 +1431,10 @@ typedef union { /* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_DEVICE_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1448,10 +1448,10 @@ typedef union { /* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_HOST_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1465,13 +1465,13 @@ typedef union { /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_DEVICE_PCKSIZE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1493,13 +1493,13 @@ typedef union { /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_HOST_PCKSIZE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1521,12 +1521,12 @@ typedef union { /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_EXTREG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1543,12 +1543,12 @@ typedef union { /* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_EXTREG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1565,12 +1565,12 @@ typedef union { /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_STATUS_BK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1585,12 +1585,12 @@ typedef union { /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_STATUS_BK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1605,13 +1605,13 @@ typedef union { /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ - uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ + uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_CTRL_PIPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1632,16 +1632,16 @@ typedef union { /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ - uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ - uint16_t PIDER:1; /*!< bit: 2 PID Error */ - uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ - uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ - uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ + uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ + uint16_t PIDER:1; /*!< bit: 2 PID Error */ + uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ + uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ + uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_STATUS_PIPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1665,140 +1665,140 @@ typedef union { /** \brief UsbDeviceDescBank SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ - __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ - __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ - __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ - RoReg8 Reserved1[0x5]; + __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ + __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ + __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ + __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ + RoReg8 Reserved1[0x5]; } UsbDeviceDescBank; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief UsbHostDescBank SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ - __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ - __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ - __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ - RoReg8 Reserved1[0x1]; - __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ - __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ + __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ + __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ + __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ + __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ + RoReg8 Reserved1[0x1]; + __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ + __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ } UsbHostDescBank; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief UsbDeviceEndpoint hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ - RoReg8 Reserved1[0x3]; - __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ - __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ - __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ - __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ - __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ - __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ - RoReg8 Reserved2[0x16]; + __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ + RoReg8 Reserved1[0x3]; + __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ + __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ + __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ + __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ + __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ + __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ + RoReg8 Reserved2[0x16]; } UsbDeviceEndpoint; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief UsbHostPipe hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ - RoReg8 Reserved1[0x2]; - __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ - __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ - __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ - __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ - __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ - __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ - __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ - RoReg8 Reserved2[0x16]; + __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ + RoReg8 Reserved1[0x2]; + __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ + __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ + __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ + __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ + __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ + __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ + __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ + RoReg8 Reserved2[0x16]; } UsbHostPipe; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_DEVICE APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Device */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ - __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ - RoReg8 Reserved3[0x1]; - __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ - RoReg8 Reserved5[0x2]; - __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ + RoReg8 Reserved2[0x4]; + __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ + __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ + RoReg8 Reserved3[0x1]; + __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ + RoReg8 Reserved5[0x2]; + __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ } UsbDevice; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_HOST hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Host */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ - __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ - RoReg8 Reserved3[0x1]; - __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ - __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ - RoReg8 Reserved5[0x1]; - __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ + RoReg8 Reserved2[0x4]; + __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ + __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ + RoReg8 Reserved3[0x1]; + __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ + __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ + RoReg8 Reserved5[0x1]; + __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ } UsbHost; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_DEVICE Descriptor SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Device */ - UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ + UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ } UsbDeviceDescriptor; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_HOST Descriptor SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Host */ - UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ + UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ } UsbHostDescriptor; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define SECTION_USB_DESCRIPTOR #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ - UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ + UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ + UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ } Usb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h similarity index 79% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h index 708398a712..05d0aaec6b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h @@ -59,14 +59,14 @@ /* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -84,11 +84,11 @@ typedef union { /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ - uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ + uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_CONFIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -154,11 +154,11 @@ typedef union { /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_EWCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -197,11 +197,11 @@ typedef union { /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -215,11 +215,11 @@ typedef union { /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -233,11 +233,11 @@ typedef union { /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -251,11 +251,11 @@ typedef union { /* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -269,10 +269,10 @@ typedef union { /* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_CLEAR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -289,15 +289,15 @@ typedef union { /** \brief WDT hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ - __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ - RoReg8 Reserved1[0x1]; - __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ + __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ + __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ + RoReg8 Reserved1[0x1]; + __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ } Wdt; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h index b2a6f5feb5..9555647475 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h @@ -84,7 +84,7 @@ #define AC_CMP_NUM 2 // Number of comparators #define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog #define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC_NUM_CMP 2 +#define AC_NUM_CMP 2 #define AC_PAIRS 1 // Number of pairs of comparators #endif /* _SAMD21_AC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h index 409ea40857..1cf4789d55 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h @@ -81,7 +81,7 @@ #define AC1_CMP_NUM 2 // Number of comparators #define AC1_GCLK_ID_ANA 32 // Index of Generic Clock for analog #define AC1_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC1_NUM_CMP 2 +#define AC1_NUM_CMP 2 #define AC1_PAIRS 1 // Number of pairs of comparators #endif /* _SAMD21_AC1_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_adc.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_adc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_adc.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_dac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dac.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_dac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dac.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_dmac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dmac.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_dmac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dmac.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dsu.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_dsu.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_dsu.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_eic.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_eic.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_eic.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_evsys.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_evsys.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_evsys.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h similarity index 98% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h index 318a89516f..6868a46fe0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h @@ -63,7 +63,7 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 +#define GCLK_GENDIV_BITS 16 #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_i2s.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_i2s.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_i2s.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_i2s.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_mtb.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_mtb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_mtb.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h similarity index 91% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h index 70811521f5..fc6350ac7f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h @@ -77,16 +77,16 @@ #define NVMCTRL_AUX3_ADDRESS 0x0080A000 #define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 65536 +#define NVMCTRL_FLASH_SIZE 65536 #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGES 1024 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_PAGES 1024 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 #define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac0.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac0.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac0.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac1.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac1.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac1.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac2.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac2.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pac2.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h similarity index 95% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h index ca35bf9422..5bd92cb87c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h @@ -83,10 +83,10 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for PM peripheral ========== */ -#define PM_CTRL_MCSEL_DFLL48M 3 -#define PM_CTRL_MCSEL_GCLK 0 -#define PM_CTRL_MCSEL_OSC8M 1 -#define PM_CTRL_MCSEL_XOSC 2 -#define PM_PM_CLK_APB_NUM 2 +#define PM_CTRL_MCSEL_DFLL48M 3 +#define PM_CTRL_MCSEL_GCLK 0 +#define PM_CTRL_MCSEL_OSC8M 1 +#define PM_CTRL_MCSEL_XOSC 2 +#define PM_PM_CLK_APB_NUM 2 #endif /* _SAMD21_PM_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_port.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_port.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_port.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_rtc.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_rtc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_rtc.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h index 870e14da5f..d352308091 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h @@ -149,7 +149,7 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SBMATRIX peripheral ========== */ -#define SBMATRIX_DEFINED +#define SBMATRIX_DEFINED /* ========== Instance parameters for SBMATRIX ========== */ #define SBMATRIX_SLAVE_FLASH 0 #define SBMATRIX_SLAVE_HPB0 1 diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h index 9f9c5f6108..cb294f27f8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h @@ -141,6 +141,6 @@ #define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger #define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core #define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM0_INT_MSB 6 +#define SERCOM0_INT_MSB 6 #endif /* _SAMD21_SERCOM0_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h index d0536328d5..aeeafcd139 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h @@ -141,6 +141,6 @@ #define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger #define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core #define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM1_INT_MSB 6 +#define SERCOM1_INT_MSB 6 #endif /* _SAMD21_SERCOM1_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h index 57cf5ad44c..d662b5d83d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h @@ -141,6 +141,6 @@ #define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger #define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core #define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM2_INT_MSB 6 +#define SERCOM2_INT_MSB 6 #endif /* _SAMD21_SERCOM2_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h index a6f2831ef2..1da53d6be0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h @@ -141,6 +141,6 @@ #define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger #define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core #define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM3_INT_MSB 6 +#define SERCOM3_INT_MSB 6 #endif /* _SAMD21_SERCOM3_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h index 36e9939eb0..b4d74044a0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h @@ -141,6 +141,6 @@ #define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger #define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core #define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM4_INT_MSB 6 +#define SERCOM4_INT_MSB 6 #endif /* _SAMD21_SERCOM4_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h index ea117a4b61..a468d17e85 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h @@ -141,6 +141,6 @@ #define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger #define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core #define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM5_INT_MSB 6 +#define SERCOM5_INT_MSB 6 #endif /* _SAMD21_SERCOM5_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h similarity index 86% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h index e2b181b78c..5b696479da 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h @@ -93,31 +93,31 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SYSCTRL peripheral ========== */ -#define SYSCTRL_BGAP_CALIB_MSB 11 -#define SYSCTRL_BOD33_CALIB_MSB 5 -#define SYSCTRL_DFLL48M_COARSE_MSB 5 -#define SYSCTRL_DFLL48M_FINE_MSB 9 +#define SYSCTRL_BGAP_CALIB_MSB 11 +#define SYSCTRL_BOD33_CALIB_MSB 5 +#define SYSCTRL_DFLL48M_COARSE_MSB 5 +#define SYSCTRL_DFLL48M_FINE_MSB 9 #define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 #define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL #define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 -#define SYSCTRL_POR33_ENTEST_MSB 1 -#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 -#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 -#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 -#define SYSCTRL_VREF_CONTROL_MSB 48 -#define SYSCTRL_VREF_STATUS_MSB 7 -#define SYSCTRL_VREG_LEVEL_MSB 2 -#define SYSCTRL_BOD12_VERSION 0x111 -#define SYSCTRL_BOD33_VERSION 0x111 -#define SYSCTRL_DFLL48M_VERSION 0x301 -#define SYSCTRL_FDPLL_VERSION 0x111 -#define SYSCTRL_OSCULP32K_VERSION 0x111 -#define SYSCTRL_OSC8M_VERSION 0x120 -#define SYSCTRL_OSC32K_VERSION 0x112 -#define SYSCTRL_VREF_VERSION 0x201 -#define SYSCTRL_VREG_VERSION 0x201 -#define SYSCTRL_XOSC_VERSION 0x114 -#define SYSCTRL_XOSC32K_VERSION 0x113 +#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define SYSCTRL_POR33_ENTEST_MSB 1 +#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 +#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 +#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 +#define SYSCTRL_VREF_CONTROL_MSB 48 +#define SYSCTRL_VREF_STATUS_MSB 7 +#define SYSCTRL_VREG_LEVEL_MSB 2 +#define SYSCTRL_BOD12_VERSION 0x111 +#define SYSCTRL_BOD33_VERSION 0x111 +#define SYSCTRL_DFLL48M_VERSION 0x301 +#define SYSCTRL_FDPLL_VERSION 0x111 +#define SYSCTRL_OSCULP32K_VERSION 0x111 +#define SYSCTRL_OSC8M_VERSION 0x120 +#define SYSCTRL_OSC32K_VERSION 0x112 +#define SYSCTRL_VREF_VERSION 0x201 +#define SYSCTRL_VREG_VERSION 0x201 +#define SYSCTRL_XOSC_VERSION 0x114 +#define SYSCTRL_XOSC32K_VERSION 0x113 #endif /* _SAMD21_SYSCTRL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h index 8eedead3bc..07ad9025d5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h @@ -106,7 +106,7 @@ #define TC3_DMAC_ID_MC_SIZE 2 #define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger #define TC3_GCLK_ID 27 // Index of Generic Clock -#define TC3_MASTER 0 +#define TC3_MASTER 0 #define TC3_OW_NUM 2 // Number of Output Waveforms #define TC3_PERIOD_EXT 0 // Period feature implemented #define TC3_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h index 68e2063740..8539bca755 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h @@ -106,7 +106,7 @@ #define TC4_DMAC_ID_MC_SIZE 2 #define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger #define TC4_GCLK_ID 28 // Index of Generic Clock -#define TC4_MASTER 1 +#define TC4_MASTER 1 #define TC4_OW_NUM 2 // Number of Output Waveforms #define TC4_PERIOD_EXT 0 // Period feature implemented #define TC4_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h index fd483f0f49..0dfecceeb5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h @@ -106,7 +106,7 @@ #define TC5_DMAC_ID_MC_SIZE 2 #define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger #define TC5_GCLK_ID 28 // Index of Generic Clock -#define TC5_MASTER 0 +#define TC5_MASTER 0 #define TC5_OW_NUM 2 // Number of Output Waveforms #define TC5_PERIOD_EXT 0 // Period feature implemented #define TC5_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h index 550bb40460..11cd7d2c10 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h @@ -106,7 +106,7 @@ #define TC6_DMAC_ID_MC_SIZE 2 #define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger #define TC6_GCLK_ID 29 // Index of Generic Clock -#define TC6_MASTER 1 +#define TC6_MASTER 1 #define TC6_OW_NUM 2 // Number of Output Waveforms #define TC6_PERIOD_EXT 0 // Period feature implemented #define TC6_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h index ebb32ce140..190990f773 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h @@ -106,7 +106,7 @@ #define TC7_DMAC_ID_MC_SIZE 2 #define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger #define TC7_GCLK_ID 29 // Index of Generic Clock -#define TC7_MASTER 0 +#define TC7_MASTER 0 #define TC7_OW_NUM 2 // Number of Output Waveforms #define TC7_PERIOD_EXT 0 // Period feature implemented #define TC7_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h index 711ef16ce0..dcc737a45d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h @@ -124,11 +124,11 @@ #define TCC0_DTI 1 // Dead-Time-Insertion feature implemented #define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1) #define TCC0_GCLK_ID 26 // Index of Generic Clock -#define TCC0_MASTER 0 +#define TCC0_MASTER 0 #define TCC0_OTMX 1 // Output Matrix feature implemented #define TCC0_OW_NUM 8 // Number of Output Waveforms #define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 +#define TCC0_SIZE 24 #define TCC0_SWAP 1 // DTI outputs swap feature implemented #define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h similarity index 98% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h index b4cc3bf2cf..bc4c1710e5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h @@ -112,11 +112,11 @@ #define TCC1_DTI 0 // Dead-Time-Insertion feature implemented #define TCC1_EXT 24 // Coding of implemented extended features #define TCC1_GCLK_ID 26 // Index of Generic Clock -#define TCC1_MASTER 1 +#define TCC1_MASTER 1 #define TCC1_OTMX 0 // Output Matrix feature implemented #define TCC1_OW_NUM 4 // Number of Output Waveforms #define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 +#define TCC1_SIZE 24 #define TCC1_SWAP 0 // DTI outputs swap feature implemented #define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h similarity index 98% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h index 3f295c097f..7b96139ca7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h @@ -108,11 +108,11 @@ #define TCC2_DTI 0 // Dead-Time-Insertion feature implemented #define TCC2_EXT 0 // Coding of implemented extended features #define TCC2_GCLK_ID 27 // Index of Generic Clock -#define TCC2_MASTER 0 +#define TCC2_MASTER 0 #define TCC2_OTMX 0 // Output Matrix feature implemented #define TCC2_OW_NUM 2 // Number of Output Waveforms #define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 +#define TCC2_SIZE 16 #define TCC2_SWAP 0 // DTI outputs swap feature implemented #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_usb.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_usb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_usb.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_wdt.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_wdt.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/instance/ins_wdt.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15b.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15b.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15bu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15bu.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15bu.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15bu.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15l.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15l.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15l.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e15l.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16b.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16b.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16bu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16bu.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16bu.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16bu.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16l.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16l.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16l.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e16l.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e17a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e17a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e18a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21e18a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15b.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g15b.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16b.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g16b.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h index 4515df0625..37dc08b552 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /* - * Support and FAQ: visit Atmel Support - */ +/* +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21G17AU_PIO_ #define _SAMD21G17AU_PIO_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h index f4ff76b1d9..e4c3f08e8e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /* - * Support and FAQ: visit Atmel Support - */ +/* +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21G18AU_PIO_ #define _SAMD21G18AU_PIO_ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15b.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j15b.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16b.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j16b.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j17a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j17a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j18a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21j18a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21.h similarity index 83% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21.h index 6c7b370e99..56cb09907d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21.h @@ -53,55 +53,55 @@ */ #if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__) - #include "samd21e15a.h" +#include "samd21e15a.h" #elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__) - #include "samd21e16a.h" +#include "samd21e16a.h" #elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__) - #include "samd21e17a.h" +#include "samd21e17a.h" #elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__) - #include "samd21e18a.h" +#include "samd21e18a.h" #elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__) - #include "samd21g15a.h" +#include "samd21g15a.h" #elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__) - #include "samd21g16a.h" +#include "samd21g16a.h" #elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__) - #include "samd21g17a.h" +#include "samd21g17a.h" #elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__) - #include "samd21g17au.h" +#include "samd21g17au.h" #elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__) - #include "samd21g18a.h" +#include "samd21g18a.h" #elif defined (__SAMD21G18AU__) || defined(__ATSAMD21G18AU__) - #include "samd21g18au.h" +#include "samd21g18au.h" #elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__) - #include "samd21j15a.h" +#include "samd21j15a.h" #elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__) - #include "samd21j16a.h" +#include "samd21j16a.h" #elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__) - #include "samd21j17a.h" +#include "samd21j17a.h" #elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__) - #include "samd21j18a.h" +#include "samd21j18a.h" #elif defined(__SAMD21E15B__) || defined(__ATSAMD21E15B__) - #include "samd21e15b.h" +#include "samd21e15b.h" #elif defined(__SAMD21E15BU__) || defined(__ATSAMD21E15BU__) - #include "samd21e15bu.h" +#include "samd21e15bu.h" #elif defined(__SAMD21E15L__) || defined(__ATSAMD21E15L__) - #include "samd21e15l.h" +#include "samd21e15l.h" #elif defined(__SAMD21E16B__) || defined(__ATSAMD21E16B__) - #include "samd21e16b.h" +#include "samd21e16b.h" #elif defined(__SAMD21E16BU__) || defined(__ATSAMD21E16BU__) - #include "samd21e16bu.h" +#include "samd21e16bu.h" #elif defined(__SAMD21E16L__) || defined(__ATSAMD21E16L__) - #include "samd21e16l.h" +#include "samd21e16l.h" #elif defined(__SAMD21G15B__) || defined(__ATSAMD21G15B__) - #include "samd21g15b.h" +#include "samd21g15b.h" #elif defined(__SAMD21G16B__) || defined(__ATSAMD21G16B__) - #include "samd21g16b.h" +#include "samd21g16b.h" #elif defined(__SAMD21J15B__) || defined(__ATSAMD21J15B__) - #include "samd21j15b.h" +#include "samd21j15b.h" #elif defined(__SAMD21J16B__) || defined(__ATSAMD21J16B__) - #include "samd21j16b.h" +#include "samd21j16b.h" #else - #error Library does not support the specified device. +#error Library does not support the specified device. #endif #endif /* _SAMD21_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h index 04bf30021d..ce18ac2b5c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E15A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -221,7 +219,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h index 1abc3e33de..383ebbc320 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E15B-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -219,7 +217,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h index 0cd86bbc87..4381001c3d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15BU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E15BU-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -219,7 +217,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h index ab7c70b6cf..fc4893f00e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,93 +90,91 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15L-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */ - AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E15L-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */ + AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */ - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnReserved7; - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnReserved26; - void* pfnReserved27; - void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnReserved7; + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnReserved26; + void* pfnReserved27; + void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -215,7 +213,7 @@ void AC1_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h index f708d078ec..e84da56403 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -221,7 +219,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h index 01a22eb86c..951d1f4889 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E16B-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -219,7 +217,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h index 5b40278a71..497b0d4fca 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16BU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E16BU-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -219,7 +217,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h index aa6cacb3b7..9ca3de0e88 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,93 +90,91 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16L-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */ - AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E16L-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */ + AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */ - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnReserved7; - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnReserved26; - void* pfnReserved27; - void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnReserved7; + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnReserved26; + void* pfnReserved27; + void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -215,7 +213,7 @@ void AC1_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h index 00912246bc..9e433c26e6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -221,7 +219,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h index 8e09efc5e9..6d51d95097 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnReserved13; - void* pfnReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnReserved13; + void* pfnReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -221,7 +219,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h index 880500e57d..65129029c0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G15A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -225,7 +223,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h index 0c883a40eb..005b09076c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,97 +90,95 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G15B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G15B-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -223,7 +221,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h index b30c493c29..707fbd3e89 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -225,7 +223,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h index 8e6e90aa40..1703045c4e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,97 +90,95 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G16B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G16B-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -223,7 +221,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h index 732d977e8f..ccf9f074f4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -225,7 +223,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h similarity index 80% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h index 2ca29801a0..01502c92ee 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /* - * Support and FAQ: visit Atmel Support - */ +/* +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21G17AU_ #define _SAMD21G17AU_ @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,99 +93,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G17AU-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -230,7 +228,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h index 68d362c0e5..83e232a224 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnReserved21; - void* pfnReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnReserved21; + void* pfnReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -225,7 +223,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h similarity index 80% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h index 3e4bff3dcd..dda17586c6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h @@ -40,9 +40,9 @@ * \asf_license_stop * */ - /* - * Support and FAQ: visit Atmel Support - */ +/* +* Support and FAQ: visit Atmel Support +*/ #ifndef _SAMD21G18AU_ #define _SAMD21G18AU_ @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G18AU-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -229,7 +227,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h index cb63e76a36..932efa3914 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J15A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -229,7 +227,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h index ab2e99b940..daaabc0794 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J15B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J15B-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -227,7 +225,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h index bdb84982fb..7862893987 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -229,7 +227,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h index 1d5f3c9590..471dc95ce2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J16B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J16B-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -227,7 +225,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h index 0f9c74ef49..c61c596149 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -229,7 +227,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h similarity index 81% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h index c6835110f7..c00fccdfca 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h @@ -59,7 +59,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -229,7 +227,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/source/system_samd21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/source/system_samd21.c rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.c diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/source/system_samd21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/source/system_samd21.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/source/system_samd21.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ac.h new file mode 100644 index 0000000000..482a111298 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ac.h @@ -0,0 +1,603 @@ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_AC_COMPONENT_ +#define _SAML21_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAML21_AC Analog Comparators */ +/*@{*/ + +#define AC_U2245 +#define REV_AC 0x100 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK 0x03ul /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))) +#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (1 << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (1 << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (0x3ul << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) ((AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))) +#define AC_EVCTRL_MASK 0x3313ul /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))) +#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))) +#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))) +#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))) +#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))) +#define AC_STATUSB_MASK 0x03ul /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (0x1ul << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK 0x01ul /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))) +#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (0x1ul << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))) +#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (0x7ul << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))) +#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val 0x4ul /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))) +#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_MEDLOW_Val 0x1ul /**< \brief (AC_COMPCTRL) Medium low speed */ +#define AC_COMPCTRL_SPEED_MEDHIGH_Val 0x2ul /**< \brief (AC_COMPCTRL) Medium high speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val 0x3ul /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (0x1ul << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (0x3ul << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) ((AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))) +#define AC_COMPCTRL_HYST_HYST50_Val 0x0ul /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST70_Val 0x1ul /**< \brief (AC_COMPCTRL) 70mV */ +#define AC_COMPCTRL_HYST_HYST90_Val 0x2ul /**< \brief (AC_COMPCTRL) 90mV */ +#define AC_COMPCTRL_HYST_HYST110_Val 0x3ul /**< \brief (AC_COMPCTRL) 110mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))) +#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))) +#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK 0x373BF75Eul /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (0x1ul << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (0x1ul << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (0x1ul << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (1 << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (1 << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (0x3ul << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) ((AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))) +#define AC_SYNCBUSY_MASK 0x0000001Ful /**< \brief (AC_SYNCBUSY) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_AC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_adc.h new file mode 100644 index 0000000000..3cba27bb15 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_adc.h @@ -0,0 +1,763 @@ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_ADC_COMPONENT_ +#define _SAML21_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAML21_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2247 +#define REV_ADC 0x100 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run during Standby */ +#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (0x1ul << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_MASK 0xC3ul /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE 0x00ul /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))) +#define ADC_CTRLB_PRESCALER_DIV2_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ +#define ADC_CTRLB_PRESCALER_DIV4_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK 0x07ul /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))) +#define ADC_REFCTRL_REFSEL_INTREF_Val 0x0ul /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC2_Val 0x5ul /**< \brief (ADC_REFCTRL) VCCANA */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (0x1ul << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (0x1ul << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (0x1ul << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK 0x3Ful /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK 0x07ul /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK 0x07ul /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK 0x07ul /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SEQSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ +#define ADC_SEQSTATUS_RESETVALUE 0x00ul /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ + +#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ +#define ADC_SEQSTATUS_SEQSTATE_Msk (0x1Ful << ADC_SEQSTATUS_SEQSTATE_Pos) +#define ADC_SEQSTATUS_SEQSTATE(value) ((ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos))) +#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ +#define ADC_SEQSTATUS_SEQBUSY (0x1ul << ADC_SEQSTATUS_SEQBUSY_Pos) +#define ADC_SEQSTATUS_MASK 0x9Ful /**< \brief (ADC_SEQSTATUS) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE 0x0000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN20_Val 0x14ul /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN21_Val 0x15ul /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN22_Val 0x16ul /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN23_Val 0x17ul /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ +#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val 0x1Dul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_OPAMP01_Val 0x1Eul /**< \brief (ADC_INPUTCTRL) OPAMP0 or OPAMP1 output */ +#define ADC_INPUTCTRL_MUXPOS_OPAMP2_Val 0x1Ful /**< \brief (ADC_INPUTCTRL) OPAMP2 output */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_OPAMP01 (ADC_INPUTCTRL_MUXPOS_OPAMP01_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_OPAMP2 (ADC_INPUTCTRL_MUXPOS_OPAMP2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MASK 0x1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ +#define ADC_CTRLC_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLC reset_value) Control C */ + +#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ +#define ADC_CTRLC_DIFFMODE (0x1ul << ADC_CTRLC_DIFFMODE_Pos) +#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ +#define ADC_CTRLC_LEFTADJ (0x1ul << ADC_CTRLC_LEFTADJ_Pos) +#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ +#define ADC_CTRLC_FREERUN (0x1ul << ADC_CTRLC_FREERUN_Pos) +#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ +#define ADC_CTRLC_CORREN (0x1ul << ADC_CTRLC_CORREN_Pos) +#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ +#define ADC_CTRLC_RESSEL_Msk (0x3ul << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL(value) ((ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos))) +#define ADC_CTRLC_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLC) 12-bit result */ +#define ADC_CTRLC_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLC) For averaging mode output */ +#define ADC_CTRLC_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLC) 10-bit result */ +#define ADC_CTRLC_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLC) 8-bit result */ +#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ +#define ADC_CTRLC_WINMODE_Msk (0x7ul << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE(value) ((ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos))) +#define ADC_CTRLC_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_CTRLC) No window mode (default) */ +#define ADC_CTRLC_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_CTRLC) RESULT > WINLT */ +#define ADC_CTRLC_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_CTRLC) RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_MASK 0x073Ful /**< \brief (ADC_CTRLC) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))) +#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))) +#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (0x1ul << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK 0xBFul /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))) +#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))) +#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))) +#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))) +#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ +#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */ + uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ + uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */ + uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */ + uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */ + uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */ + uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ + uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */ + uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (0x1ul << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (0x1ul << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (0x1ul << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLC (0x1ul << ADC_SYNCBUSY_CTRLC_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (0x1ul << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (0x1ul << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (0x1ul << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (0x1ul << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (0x1ul << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (0x1ul << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (0x1ul << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK 0x07FFul /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ +#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))) +#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ +#define ADC_SEQCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ + +#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ +#define ADC_SEQCTRL_SEQEN_Msk (0xFFFFFFFFul << ADC_SEQCTRL_SEQEN_Pos) +#define ADC_SEQCTRL_SEQEN(value) ((ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos))) +#define ADC_SEQCTRL_MASK 0xFFFFFFFFul /**< \brief (ADC_SEQCTRL) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (0x7ul << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) ((ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (0x7ul << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) ((ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))) +#define ADC_CALIB_MASK 0x0707ul /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ + __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ + RoReg8 Reserved1[0x2]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x3]; + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ + RoReg8 Reserved3[0x3]; + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ + RoReg8 Reserved4[0x2]; + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ + RoReg8 Reserved5[0x2]; + __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_ADC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_aes.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_aes.h new file mode 100644 index 0000000000..d4d262d42a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_aes.h @@ -0,0 +1,350 @@ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_AES_COMPONENT_ +#define _SAML21_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAML21_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x200 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ + uint32_t LOD:1; /*!< bit: 12 LOD Enable */ + uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ + uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE 0x00000000ul /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (0x1ul << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (0x1ul << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (0x7ul << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) ((AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ +#define AES_CTRLA_CFBS_Msk (0x7ul << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) ((AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ +#define AES_CTRLA_KEYSIZE_Msk (0x3ul << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) ((AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ +#define AES_CTRLA_CIPHER (0x1ul << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ +#define AES_CTRLA_STARTMODE (0x1ul << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ +#define AES_CTRLA_LOD (0x1ul << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ +#define AES_CTRLA_KEYGEN (0x1ul << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ +#define AES_CTRLA_XORKEY (0x1ul << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ +#define AES_CTRLA_CTYPE_Msk (0xFul << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) ((AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))) +#define AES_CTRLA_MASK 0x000F7FFFul /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Manual Start */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE 0x00ul /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ +#define AES_CTRLB_START (0x1ul << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (0x1ul << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (0x1ul << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (0x1ul << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK 0x0Ful /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE 0x00ul /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ +#define AES_INTENCLR_ENCCMP (0x1ul << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_ENCCMP_0_Val 0x0ul /**< \brief (AES_INTENCLR) 1 (no division) */ +#define AES_INTENCLR_ENCCMP_1_Val 0x1ul /**< \brief (AES_INTENCLR) 2 */ +#define AES_INTENCLR_ENCCMP_2_Val 0x2ul /**< \brief (AES_INTENCLR) 4 */ +#define AES_INTENCLR_ENCCMP_3_Val 0x3ul /**< \brief (AES_INTENCLR) 8 */ +#define AES_INTENCLR_ENCCMP_0 (AES_INTENCLR_ENCCMP_0_Val << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_ENCCMP_1 (AES_INTENCLR_ENCCMP_1_Val << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_ENCCMP_2 (AES_INTENCLR_ENCCMP_2_Val << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_ENCCMP_3 (AES_INTENCLR_ENCCMP_3_Val << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ +#define AES_INTENCLR_GFMCMP (0x1ul << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK 0x03ul /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE 0x00ul /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ +#define AES_INTENSET_ENCCMP (0x1ul << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ +#define AES_INTENSET_GFMCMP (0x1ul << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK 0x03ul /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE 0x00ul /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (0x1ul << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (0x1ul << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK 0x03ul /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE 0x00ul /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (0x3ul << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) ((AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))) +#define AES_DATABUFPTR_MASK 0x03ul /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (0x1ul << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK 0x01ul /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE 0x00000000ul /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK 0xFFFFFFFFul /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE 0x00000000ul /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK 0xFFFFFFFFul /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE 0x00000000ul /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK 0xFFFFFFFFul /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE 0x00000000ul /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK 0xFFFFFFFFul /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE 0x00000000ul /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK 0xFFFFFFFFul /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE 0x00000000ul /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK 0xFFFFFFFFul /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE 0x00000000ul /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK 0xFFFFFFFFul /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_AES_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ccl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ccl.h new file mode 100644 index 0000000000..0529623ec2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_ccl.h @@ -0,0 +1,205 @@ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_CCL_COMPONENT_ +#define _SAML21_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAML21_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x100 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE 0x00ul /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (0x1ul << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (0x1ul << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ +#define CCL_CTRL_RUNSTDBY (0x1ul << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK 0x43ul /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE 0x00ul /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (0xFul << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) ((CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val 0x0ul /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val 0x1ul /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val 0x2ul /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val 0x3ul /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val 0x4ul /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK 0x0Ful /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ + uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE 0x00000000ul /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (0x1ul << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (0x3ul << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) ((CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val 0x0ul /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val 0x1ul /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val 0x2ul /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (0x1ul << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (0xFul << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) ((CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))) +#define CCL_LUTCTRL_INSEL0_MASK_Val 0x0ul /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val 0x1ul /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val 0x2ul /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val 0x3ul /**< \brief (CCL_LUTCTRL) Event in put source */ +#define CCL_LUTCTRL_INSEL0_IO_Val 0x4ul /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val 0x5ul /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val 0x6ul /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val 0x7ul /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val 0x8ul /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val 0x9ul /**< \brief (CCL_LUTCTRL) SERCOM inout source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (0xFul << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) ((CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (0xFul << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) ((CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ +#define CCL_LUTCTRL_INVEI (0x1ul << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (0x1ul << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (0x1ul << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (0xFFul << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) ((CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))) +#define CCL_LUTCTRL_MASK 0xFF7FFFB2ul /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_CCL_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dac.h new file mode 100644 index 0000000000..eacec2df80 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dac.h @@ -0,0 +1,474 @@ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_DAC_COMPONENT_ +#define _SAML21_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAML21_DAC Digital-to-Analog Converter */ +/*@{*/ + +#define DAC_U2244 +#define REV_DAC 0x100 + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ +#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_MASK 0x03ul /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ + uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ +#define DAC_CTRLB_DIFF (0x1ul << DAC_CTRLB_DIFF_Pos) +#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ +#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))) +#define DAC_CTRLB_REFSEL_VREFPU_Val 0x0ul /**< \brief (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val 0x1ul /**< \brief (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val 0x2ul /**< \brief (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val 0x3ul /**< \brief (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK 0x07ul /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ + uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ + uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ + uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ + uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ + uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ + uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ + uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ +#define DAC_EVCTRL_STARTEI0 (1 << DAC_EVCTRL_STARTEI0_Pos) +#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ +#define DAC_EVCTRL_STARTEI1 (1 << DAC_EVCTRL_STARTEI1_Pos) +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (0x3ul << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_STARTEI(value) ((DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))) +#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ +#define DAC_EVCTRL_EMPTYEO0 (1 << DAC_EVCTRL_EMPTYEO0_Pos) +#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ +#define DAC_EVCTRL_EMPTYEO1 (1 << DAC_EVCTRL_EMPTYEO1_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (0x3ul << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_EMPTYEO(value) ((DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))) +#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ +#define DAC_EVCTRL_INVEI0 (1 << DAC_EVCTRL_INVEI0_Pos) +#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ +#define DAC_EVCTRL_INVEI1 (1 << DAC_EVCTRL_INVEI1_Pos) +#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (0x3ul << DAC_EVCTRL_INVEI_Pos) +#define DAC_EVCTRL_INVEI(value) ((DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))) +#define DAC_EVCTRL_MASK 0x3Ful /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 0 */ +#define DAC_INTENCLR_UNDERRUN0 (1 << DAC_INTENCLR_UNDERRUN0_Pos) +#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 1 */ +#define DAC_INTENCLR_UNDERRUN1 (1 << DAC_INTENCLR_UNDERRUN1_Pos) +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC x */ +#define DAC_INTENCLR_UNDERRUN_Msk (0x3ul << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_UNDERRUN(value) ((DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))) +#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY0 (1 << DAC_INTENCLR_EMPTY0_Pos) +#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY1 (1 << DAC_INTENCLR_EMPTY1_Pos) +#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (0x3ul << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_EMPTY(value) ((DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))) +#define DAC_INTENCLR_MASK 0x0Ful /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 0 */ +#define DAC_INTENSET_UNDERRUN0 (1 << DAC_INTENSET_UNDERRUN0_Pos) +#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 1 */ +#define DAC_INTENSET_UNDERRUN1 (1 << DAC_INTENSET_UNDERRUN1_Pos) +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC x */ +#define DAC_INTENSET_UNDERRUN_Msk (0x3ul << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_UNDERRUN(value) ((DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))) +#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY0 (1 << DAC_INTENSET_EMPTY0_Pos) +#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY1 (1 << DAC_INTENSET_EMPTY1_Pos) +#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (0x3ul << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_EMPTY(value) ((DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))) +#define DAC_INTENSET_MASK 0x0Ful /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 DAC 0 Underrun */ + uint8_t UNDERRUN1:1; /*!< bit: 1 DAC 1 Underrun */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 DAC x Underrun */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) DAC 0 Underrun */ +#define DAC_INTFLAG_UNDERRUN0 (1 << DAC_INTFLAG_UNDERRUN0_Pos) +#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) DAC 1 Underrun */ +#define DAC_INTFLAG_UNDERRUN1 (1 << DAC_INTFLAG_UNDERRUN1_Pos) +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) DAC x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (0x3ul << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_UNDERRUN(value) ((DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))) +#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ +#define DAC_INTFLAG_EMPTY0 (1 << DAC_INTFLAG_EMPTY0_Pos) +#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ +#define DAC_INTFLAG_EMPTY1 (1 << DAC_INTFLAG_EMPTY1_Pos) +#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (0x3ul << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_EMPTY(value) ((DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))) +#define DAC_INTFLAG_MASK 0x0Ful /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ + uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ + uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ + uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ + uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ +#define DAC_STATUS_READY0 (1 << DAC_STATUS_READY0_Pos) +#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ +#define DAC_STATUS_READY1 (1 << DAC_STATUS_READY1_Pos) +#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (0x3ul << DAC_STATUS_READY_Pos) +#define DAC_STATUS_READY(value) ((DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))) +#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ +#define DAC_STATUS_EOC0 (1 << DAC_STATUS_EOC0_Pos) +#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ +#define DAC_STATUS_EOC1 (1 << DAC_STATUS_EOC1_Pos) +#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (0x3ul << DAC_STATUS_EOC_Pos) +#define DAC_STATUS_EOC(value) ((DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))) +#define DAC_STATUS_MASK 0x0Ful /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ + uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ + uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ + uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ + uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ + uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DAC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ +#define DAC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ + +#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ +#define DAC_SYNCBUSY_SWRST (0x1ul << DAC_SYNCBUSY_SWRST_Pos) +#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ +#define DAC_SYNCBUSY_ENABLE (0x1ul << DAC_SYNCBUSY_ENABLE_Pos) +#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ +#define DAC_SYNCBUSY_DATA0 (1 << DAC_SYNCBUSY_DATA0_Pos) +#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ +#define DAC_SYNCBUSY_DATA1 (1 << DAC_SYNCBUSY_DATA1_Pos) +#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (0x3ul << DAC_SYNCBUSY_DATA_Pos) +#define DAC_SYNCBUSY_DATA(value) ((DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))) +#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ +#define DAC_SYNCBUSY_DATABUF0 (1 << DAC_SYNCBUSY_DATABUF0_Pos) +#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ +#define DAC_SYNCBUSY_DATABUF1 (1 << DAC_SYNCBUSY_DATABUF1_Pos) +#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (0x3ul << DAC_SYNCBUSY_DATABUF_Pos) +#define DAC_SYNCBUSY_DATABUF(value) ((DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))) +#define DAC_SYNCBUSY_MASK 0x0000003Ful /**< \brief (DAC_SYNCBUSY) MASK Register */ + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ + uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ + uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ + uint16_t :2; /*!< bit: 4.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ + uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DACCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ +#define DAC_DACCTRL_RESETVALUE 0x0000ul /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ + +#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ +#define DAC_DACCTRL_LEFTADJ (0x1ul << DAC_DACCTRL_LEFTADJ_Pos) +#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ +#define DAC_DACCTRL_ENABLE (0x1ul << DAC_DACCTRL_ENABLE_Pos) +#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ +#define DAC_DACCTRL_CCTRL_Msk (0x3ul << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL(value) ((DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))) +#define DAC_DACCTRL_CCTRL_CC12M_Val 0x0ul /**< \brief (DAC_DACCTRL) 1MHzAtmel Support + */ + +#ifndef _SAML21_DMAC_COMPONENT_ +#define _SAML21_DMAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DMAC */ +/* ========================================================================== */ +/** \addtogroup SAML21_DMAC Direct Memory Access Controller */ +/*@{*/ + +#define DMAC_U2223 +#define REV_DMAC 0x221 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ +#define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))) +#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))) +#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))) +#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))) +#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ + uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ + uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ + uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:16; /*!< bit: 0..15 Channel x Software Trigger */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG12 (1 << DMAC_SWTRIGCTRL_SWTRIG12_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG13 (1 << DMAC_SWTRIGCTRL_SWTRIG13_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG14 (1 << DMAC_SWTRIGCTRL_SWTRIG14_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG15 (1 << DMAC_SWTRIGCTRL_SWTRIG15_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))) +#define DMAC_SWTRIGCTRL_MASK 0x0000FFFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ + uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ + uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ + uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:16; /*!< bit: 0..15 Channel x Pending Interrupt */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT12 (1 << DMAC_INTSTATUS_CHINT12_Pos) +#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT13 (1 << DMAC_INTSTATUS_CHINT13_Pos) +#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT14 (1 << DMAC_INTSTATUS_CHINT14_Pos) +#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT15 (1 << DMAC_INTSTATUS_CHINT15_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (0xFFFFul << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))) +#define DMAC_INTSTATUS_MASK 0x0000FFFFul /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ + uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ + uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ + uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:16; /*!< bit: 0..15 Busy Channel x */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ +#define DMAC_BUSYCH_BUSYCH12 (1 << DMAC_BUSYCH_BUSYCH12_Pos) +#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ +#define DMAC_BUSYCH_BUSYCH13 (1 << DMAC_BUSYCH_BUSYCH13_Pos) +#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ +#define DMAC_BUSYCH_BUSYCH14 (1 << DMAC_BUSYCH_BUSYCH14_Pos) +#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ +#define DMAC_BUSYCH_BUSYCH15 (1 << DMAC_BUSYCH_BUSYCH15_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFFul << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))) +#define DMAC_BUSYCH_MASK 0x0000FFFFul /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ + uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ + uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ + uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:16; /*!< bit: 0..15 Pending Channel x */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ +#define DMAC_PENDCH_PENDCH12 (1 << DMAC_PENDCH_PENDCH12_Pos) +#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ +#define DMAC_PENDCH_PENDCH13 (1 << DMAC_PENDCH_PENDCH13_Pos) +#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ +#define DMAC_PENDCH_PENDCH14 (1 << DMAC_PENDCH_PENDCH14_Pos) +#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ +#define DMAC_PENDCH_PENDCH15 (1 << DMAC_PENDCH_PENDCH15_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (0xFFFFul << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))) +#define DMAC_PENDCH_MASK 0x0000FFFFul /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))) +#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))) +#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))) +#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ +#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */ + +#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ +#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos) +#define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))) +#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Channel run in standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ +#define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel run in standby */ +#define DMAC_CHCTRLA_RUNSTDBY (0x1ul << DMAC_CHCTRLA_RUNSTDBY_Pos) +#define DMAC_CHCTRLA_MASK 0x43ul /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ +#define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ + +#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ +#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))) +#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ +#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ +#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ +#define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos) +#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ +#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos) +#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ +#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))) +#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ +#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))) +#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ +#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ +#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))) +#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ +#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ +#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))) +#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ +#define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ +#define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ +#define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))) +#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1 */ +#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2 */ +#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4 */ +#define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8 */ +#define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16 */ +#define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32 */ +#define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64 */ +#define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128 */ +#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */ + +/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */ + +#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */ +#define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos) +#define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))) +#define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */ + +/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SRCADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */ + +#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */ +#define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos) +#define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))) +#define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */ + +/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_DSTADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */ + +#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */ +#define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos) +#define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))) +#define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */ + +/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_DESCADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */ + +#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */ +#define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos) +#define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))) +#define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */ + +/** \brief DMAC APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ + __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ + __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ + __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ + __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ + __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ + RoReg8 Reserved1[0x2]; + __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ + __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ + RoReg8 Reserved2[0x8]; + __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ + RoReg8 Reserved3[0x2]; + __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ + __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ + __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ + __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ + __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ + __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ + RoReg8 Reserved4[0x3]; + __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ + __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ + RoReg8 Reserved5[0x3]; + __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ + RoReg8 Reserved6[0x4]; + __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ + __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ + __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ + __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ +} Dmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief DMAC Descriptor SRAM registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ + __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ + __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ + __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ + __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ +} DmacDescriptor +#ifdef __GNUC__ +__attribute__ ((aligned (8))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#ifdef __GNUC__ +#define SECTION_DMAC_DESCRIPTOR __attribute__ ((section(".lpram"))) +#elif defined(__ICCARM__) +#define SECTION_DMAC_DESCRIPTOR @".lpram" +#endif + +/*@}*/ + +#endif /* _SAML21_DMAC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dsu.h new file mode 100644 index 0000000000..e936bf17e9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_dsu.h @@ -0,0 +1,630 @@ +/** + * \file + * + * \brief Component description for DSU + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_DSU_COMPONENT_ +#define _SAML21_DSU_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DSU */ +/* ========================================================================== */ +/** \addtogroup SAML21_DSU Device Service Unit */ +/*@{*/ + +#define DSU_U2209 +#define REV_DSU 0x250 + +/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */ + uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */ + uint8_t CE:1; /*!< bit: 4 Chip-Erase */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */ + uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DSU_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ +#define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */ + +#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ +#define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos) +#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */ +#define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos) +#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */ +#define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos) +#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */ +#define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos) +#define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */ +#define DSU_CTRL_ARR (0x1ul << DSU_CTRL_ARR_Pos) +#define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */ +#define DSU_CTRL_SMSA (0x1ul << DSU_CTRL_SMSA_Pos) +#define DSU_CTRL_MASK 0xDDul /**< \brief (DSU_CTRL) MASK Register */ + +/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DONE:1; /*!< bit: 0 Done */ + uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ + uint8_t BERR:1; /*!< bit: 2 Bus Error */ + uint8_t FAIL:1; /*!< bit: 3 Failure */ + uint8_t PERR:1; /*!< bit: 4 Protection Error */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DSU_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ +#define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */ + +#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ +#define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos) +#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ +#define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos) +#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ +#define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos) +#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ +#define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos) +#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ +#define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos) +#define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */ + +/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PROT:1; /*!< bit: 0 Protected */ + uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ + uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ + uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ + uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DSU_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ +#define DSU_STATUSB_RESETVALUE 0x00ul /**< \brief (DSU_STATUSB reset_value) Status B */ + +#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ +#define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos) +#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ +#define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos) +#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ +#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos) +#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ +#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos) +#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ +#define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos) +#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))) +#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ +#define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos) +#define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */ + +/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */ + uint32_t ADDR:30; /*!< bit: 2..31 Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ +#define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */ + +#define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */ +#define DSU_ADDR_AMOD_Msk (0x3ul << DSU_ADDR_AMOD_Pos) +#define DSU_ADDR_AMOD(value) ((DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))) +#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ +#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos) +#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))) +#define DSU_ADDR_MASK 0xFFFFFFFFul /**< \brief (DSU_ADDR) MASK Register */ + +/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t LENGTH:30; /*!< bit: 2..31 Length */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_LENGTH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ +#define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */ + +#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ +#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos) +#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))) +#define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */ + +/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ +#define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */ + +#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ +#define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos) +#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))) +#define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */ + +/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_DCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ +#define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ + +#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ +#define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos) +#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))) +#define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */ + +/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ + uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */ + uint32_t DIE:4; /*!< bit: 12..15 Die Number */ + uint32_t SERIES:6; /*!< bit: 16..21 Series */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t FAMILY:5; /*!< bit: 23..27 Family */ + uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_DID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ + +#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ +#define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos) +#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))) +#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */ +#define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos) +#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))) +#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */ +#define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos) +#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))) +#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */ +#define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos) +#define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))) +#define DSU_DID_SERIES_0_Val 0x0ul /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */ +#define DSU_DID_SERIES_1_Val 0x1ul /**< \brief (DSU_DID) Cortex-M0+ processor, USB */ +#define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos) +#define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos) +#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */ +#define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos) +#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))) +#define DSU_DID_FAMILY_0_Val 0x0ul /**< \brief (DSU_DID) General purpose microcontroller */ +#define DSU_DID_FAMILY_1_Val 0x1ul /**< \brief (DSU_DID) PicoPower */ +#define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos) +#define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos) +#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ +#define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))) +#define DSU_DID_PROCESSOR_0_Val 0x0ul /**< \brief (DSU_DID) Cortex-M0 */ +#define DSU_DID_PROCESSOR_1_Val 0x1ul /**< \brief (DSU_DID) Cortex-M0+ */ +#define DSU_DID_PROCESSOR_2_Val 0x2ul /**< \brief (DSU_DID) Cortex-M3 */ +#define DSU_DID_PROCESSOR_3_Val 0x3ul /**< \brief (DSU_DID) Cortex-M4 */ +#define DSU_DID_PROCESSOR_0 (DSU_DID_PROCESSOR_0_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR_1 (DSU_DID_PROCESSOR_1_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR_2 (DSU_DID_PROCESSOR_2_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR_3 (DSU_DID_PROCESSOR_3_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */ + +/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_DCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */ +#define DSU_DCFG_RESETVALUE 0x00000000ul /**< \brief (DSU_DCFG reset_value) Device Configuration */ + +#define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */ +#define DSU_DCFG_DCFG_Msk (0xFFFFFFFFul << DSU_DCFG_DCFG_Pos) +#define DSU_DCFG_DCFG(value) ((DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))) +#define DSU_DCFG_MASK 0xFFFFFFFFul /**< \brief (DSU_DCFG) MASK Register */ + +/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EPRES:1; /*!< bit: 0 Entry Present */ + uint32_t FMT:1; /*!< bit: 1 Format */ + uint32_t :10; /*!< bit: 2..11 Reserved */ + uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_ENTRY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */ + +#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */ +#define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos) +#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */ +#define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos) +#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */ +#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos) +#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))) +#define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */ + +/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t END:32; /*!< bit: 0..31 End Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_END_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */ +#define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */ + +#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */ +#define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos) +#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos))) +#define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */ + +/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MEMTYPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */ +#define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */ + +#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */ +#define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos) +#define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */ + +/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ + uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_PID4_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */ +#define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */ + +#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */ +#define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos) +#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))) +#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB count */ +#define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos) +#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))) +#define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */ + +/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} DSU_PID5_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */ +#define DSU_PID5_MASK 0x00000000ul /**< \brief (DSU_PID5) MASK Register */ + +/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} DSU_PID6_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */ +#define DSU_PID6_MASK 0x00000000ul /**< \brief (DSU_PID6) MASK Register */ + +/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} DSU_PID7_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */ +#define DSU_PID7_MASK 0x00000000ul /**< \brief (DSU_PID7) MASK Register */ + +/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_PID0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */ +#define DSU_PID0_RESETVALUE 0x00000000ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */ + +#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */ +#define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos) +#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))) +#define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */ + +/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ + uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_PID1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */ +#define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */ + +#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */ +#define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos) +#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))) +#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */ +#define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos) +#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))) +#define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */ + +/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ + uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ + uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_PID2_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */ +#define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */ + +#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */ +#define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos) +#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))) +#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */ +#define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos) +#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */ +#define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos) +#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))) +#define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */ + +/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ + uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_PID3_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */ +#define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */ + +#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */ +#define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos) +#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))) +#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */ +#define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos) +#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))) +#define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */ + +/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_CID0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */ +#define DSU_CID0_RESETVALUE 0x00000000ul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */ + +#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */ +#define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos) +#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))) +#define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */ + +/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ + uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_CID1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */ +#define DSU_CID1_RESETVALUE 0x00000000ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */ + +#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */ +#define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos) +#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))) +#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */ +#define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos) +#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))) +#define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */ + +/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_CID2_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */ +#define DSU_CID2_RESETVALUE 0x00000000ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */ + +#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */ +#define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos) +#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))) +#define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */ + +/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_CID3_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */ +#define DSU_CID3_RESETVALUE 0x00000000ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */ + +#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */ +#define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos) +#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))) +#define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */ + +/** \brief DSU hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ + __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ + __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ + RoReg8 Reserved1[0x1]; + __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ + __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ + __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ + __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ + __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ + RoReg8 Reserved2[0xD4]; + __IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */ + RoReg8 Reserved3[0xF08]; + __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ + __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ + RoReg8 Reserved4[0xFC0]; + __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ + __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ + __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */ + __I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */ + __I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */ + __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ + __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ + __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ + __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ + __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ + __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ + __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ + __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ +} Dsu; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_DSU_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_eic.h new file mode 100644 index 0000000000..930554bf92 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_eic.h @@ -0,0 +1,439 @@ +/** + * \file + * + * \brief Component description for EIC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_EIC_COMPONENT_ +#define _SAML21_EIC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR EIC */ +/* ========================================================================== */ +/** \addtogroup SAML21_EIC External Interrupt Controller */ +/*@{*/ + +#define EIC_U2254 +#define REV_EIC 0x200 + +/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} EIC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_CTRLA_OFFSET 0x00 /**< \brief (EIC_CTRLA offset) Control */ +#define EIC_CTRLA_RESETVALUE 0x00ul /**< \brief (EIC_CTRLA reset_value) Control */ + +#define EIC_CTRLA_SWRST_Pos 0 /**< \brief (EIC_CTRLA) Software Reset */ +#define EIC_CTRLA_SWRST (0x1ul << EIC_CTRLA_SWRST_Pos) +#define EIC_CTRLA_ENABLE_Pos 1 /**< \brief (EIC_CTRLA) Enable */ +#define EIC_CTRLA_ENABLE (0x1ul << EIC_CTRLA_ENABLE_Pos) +#define EIC_CTRLA_CKSEL_Pos 4 /**< \brief (EIC_CTRLA) Clock Selection */ +#define EIC_CTRLA_CKSEL (0x1ul << EIC_CTRLA_CKSEL_Pos) +#define EIC_CTRLA_MASK 0x13ul /**< \brief (EIC_CTRLA) MASK Register */ + +/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) NMI Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t NMISENSE:3; /*!< bit: 0.. 2 NMI Input Sense Configuration */ + uint8_t NMIFILTEN:1; /*!< bit: 3 NMI Filter Enable */ + uint8_t NMIASYNCH:1; /*!< bit: 4 NMI Asynchronous edge Detection Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} EIC_NMICTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_NMICTRL_OFFSET 0x01 /**< \brief (EIC_NMICTRL offset) NMI Control */ +#define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) NMI Control */ + +#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) NMI Input Sense Configuration */ +#define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos) +#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))) +#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */ +#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising edge detection */ +#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling edge detection */ +#define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both edges detection */ +#define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High level detection */ +#define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low level detection */ +#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) +#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) +#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) +#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) +#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) +#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) +#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) NMI Filter Enable */ +#define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos) +#define EIC_NMICTRL_NMIASYNCH_Pos 4 /**< \brief (EIC_NMICTRL) NMI Asynchronous edge Detection Enable */ +#define EIC_NMICTRL_NMIASYNCH (0x1ul << EIC_NMICTRL_NMIASYNCH_Pos) +#define EIC_NMICTRL_MASK 0x1Ful /**< \brief (EIC_NMICTRL) MASK Register */ + +/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) NMI Interrupt Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t NMI:1; /*!< bit: 0 NMI Interrupt Flag */ + uint16_t :15; /*!< bit: 1..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} EIC_NMIFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_NMIFLAG_OFFSET 0x02 /**< \brief (EIC_NMIFLAG offset) NMI Interrupt Flag */ +#define EIC_NMIFLAG_RESETVALUE 0x0000ul /**< \brief (EIC_NMIFLAG reset_value) NMI Interrupt Flag */ + +#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) NMI Interrupt Flag */ +#define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos) +#define EIC_NMIFLAG_MASK 0x0001ul /**< \brief (EIC_NMIFLAG) MASK Register */ + +/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/ 32) Syncbusy register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software reset synchronisation */ + uint32_t ENABLE:1; /*!< bit: 1 Enable synchronisation */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} EIC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_SYNCBUSY_OFFSET 0x04 /**< \brief (EIC_SYNCBUSY offset) Syncbusy register */ +#define EIC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (EIC_SYNCBUSY reset_value) Syncbusy register */ + +#define EIC_SYNCBUSY_SWRST_Pos 0 /**< \brief (EIC_SYNCBUSY) Software reset synchronisation */ +#define EIC_SYNCBUSY_SWRST (0x1ul << EIC_SYNCBUSY_SWRST_Pos) +#define EIC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (EIC_SYNCBUSY) Enable synchronisation */ +#define EIC_SYNCBUSY_ENABLE (0x1ul << EIC_SYNCBUSY_ENABLE_Pos) +#define EIC_SYNCBUSY_MASK 0x00000003ul /**< \brief (EIC_SYNCBUSY) MASK Register */ + +/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} EIC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_EVCTRL_OFFSET 0x08 /**< \brief (EIC_EVCTRL offset) Event Control */ +#define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */ + +#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */ +#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos) +#define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))) +#define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */ + +/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} EIC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_INTENCLR_OFFSET 0x0C /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */ +#define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Disable */ +#define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos) +#define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))) +#define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */ + +/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} EIC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_INTENSET_OFFSET 0x10 /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */ +#define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */ + +#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Disable */ +#define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos) +#define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))) +#define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */ + +/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Flag */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} EIC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_INTFLAG_OFFSET 0x14 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt Flag */ +#define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos) +#define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))) +#define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */ + +/* -------- EIC_EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) EIC Asynchronous edge Detection Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ASYNCH:16; /*!< bit: 0..15 EIC Asynchronous edge Detection Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} EIC_EIC_ASYNCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_EIC_ASYNCH_OFFSET 0x18 /**< \brief (EIC_EIC_ASYNCH offset) EIC Asynchronous edge Detection Enable */ +#define EIC_EIC_ASYNCH_RESETVALUE 0x00000000ul /**< \brief (EIC_EIC_ASYNCH reset_value) EIC Asynchronous edge Detection Enable */ + +#define EIC_EIC_ASYNCH_ASYNCH_Pos 0 /**< \brief (EIC_EIC_ASYNCH) EIC Asynchronous edge Detection Enable */ +#define EIC_EIC_ASYNCH_ASYNCH_Msk (0xFFFFul << EIC_EIC_ASYNCH_ASYNCH_Pos) +#define EIC_EIC_ASYNCH_ASYNCH(value) ((EIC_EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_EIC_ASYNCH_ASYNCH_Pos))) +#define EIC_EIC_ASYNCH_MASK 0x0000FFFFul /**< \brief (EIC_EIC_ASYNCH) MASK Register */ + +/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) Configuration n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */ + uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */ + uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */ + uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */ + uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */ + uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */ + uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */ + uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */ + uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */ + uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */ + uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */ + uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */ + uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */ + uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */ + uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */ + uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} EIC_CONFIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EIC_CONFIG_OFFSET 0x1C /**< \brief (EIC_CONFIG offset) Configuration n */ +#define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */ + +#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */ +#define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos) +#define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))) +#define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ +#define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ +#define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ +#define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ +#define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ +#define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ +#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) +#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) +#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) +#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) +#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) +#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) +#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */ +#define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos) +#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */ +#define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos) +#define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))) +#define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ +#define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ +#define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ +#define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ +#define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ +#define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ +#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) +#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) +#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) +#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) +#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) +#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) +#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */ +#define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos) +#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */ +#define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos) +#define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))) +#define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ +#define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ +#define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ +#define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ +#define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ +#define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ +#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) +#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) +#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) +#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) +#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) +#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) +#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */ +#define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos) +#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */ +#define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos) +#define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))) +#define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ +#define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ +#define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ +#define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ +#define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ +#define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ +#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) +#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) +#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) +#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) +#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) +#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) +#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */ +#define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos) +#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */ +#define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos) +#define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))) +#define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ +#define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ +#define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ +#define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ +#define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ +#define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ +#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) +#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) +#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) +#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) +#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) +#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) +#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */ +#define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos) +#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */ +#define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos) +#define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))) +#define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ +#define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ +#define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ +#define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ +#define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ +#define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ +#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) +#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) +#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) +#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) +#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) +#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) +#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */ +#define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos) +#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */ +#define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos) +#define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))) +#define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ +#define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ +#define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ +#define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ +#define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ +#define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ +#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) +#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) +#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) +#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) +#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) +#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) +#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */ +#define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos) +#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */ +#define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos) +#define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))) +#define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ +#define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ +#define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ +#define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ +#define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ +#define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ +#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) +#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) +#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) +#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) +#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) +#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) +#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */ +#define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos) +#define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */ + +/** \brief EIC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ + __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) NMI Control */ + __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) NMI Interrupt Flag */ + __I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Syncbusy register */ + __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */ + __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */ + __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */ + __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */ + __IO EIC_EIC_ASYNCH_Type EIC_ASYNCH; /**< \brief Offset: 0x18 (R/W 32) EIC Asynchronous edge Detection Enable */ + __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) Configuration n */ +} Eic; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_EIC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_evsys.h new file mode 100644 index 0000000000..56d5ed21f0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_evsys.h @@ -0,0 +1,621 @@ +/** + * \file + * + * \brief Component description for EVSYS + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_EVSYS_COMPONENT_ +#define _SAML21_EVSYS_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR EVSYS */ +/* ========================================================================== */ +/** \addtogroup SAML21_EVSYS Event System Interface */ +/*@{*/ + +#define EVSYS_U2256 +#define REV_EVSYS 0x100 + +/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x00) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} EVSYS_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EVSYS_CTRLA_OFFSET 0x00 /**< \brief (EVSYS_CTRLA offset) Control */ +#define EVSYS_CTRLA_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRLA reset_value) Control */ + +#define EVSYS_CTRLA_SWRST_Pos 0 /**< \brief (EVSYS_CTRLA) Software Reset */ +#define EVSYS_CTRLA_SWRST (0x1ul << EVSYS_CTRLA_SWRST_Pos) +#define EVSYS_CTRLA_MASK 0x01ul /**< \brief (EVSYS_CTRLA) MASK Register */ + +/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ + uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ + uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ + uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ + uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ + uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ + uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ + uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ + uint32_t USRRDY8:1; /*!< bit: 8 Channel 8 User Ready */ + uint32_t USRRDY9:1; /*!< bit: 9 Channel 9 User Ready */ + uint32_t USRRDY10:1; /*!< bit: 10 Channel 10 User Ready */ + uint32_t USRRDY11:1; /*!< bit: 11 Channel 11 User Ready */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t CHBUSY0:1; /*!< bit: 16 Channel 0 Busy */ + uint32_t CHBUSY1:1; /*!< bit: 17 Channel 1 Busy */ + uint32_t CHBUSY2:1; /*!< bit: 18 Channel 2 Busy */ + uint32_t CHBUSY3:1; /*!< bit: 19 Channel 3 Busy */ + uint32_t CHBUSY4:1; /*!< bit: 20 Channel 4 Busy */ + uint32_t CHBUSY5:1; /*!< bit: 21 Channel 5 Busy */ + uint32_t CHBUSY6:1; /*!< bit: 22 Channel 6 Busy */ + uint32_t CHBUSY7:1; /*!< bit: 23 Channel 7 Busy */ + uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ + uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ + uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ + uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t USRRDY:12; /*!< bit: 0..11 Channel x User Ready */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t CHBUSY:12; /*!< bit: 16..27 Channel x Busy */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} EVSYS_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */ +#define EVSYS_CHSTATUS_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */ + +#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */ +#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos) +#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */ +#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos) +#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */ +#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos) +#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */ +#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos) +#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */ +#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos) +#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */ +#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos) +#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */ +#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos) +#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */ +#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos) +#define EVSYS_CHSTATUS_USRRDY8_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */ +#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos) +#define EVSYS_CHSTATUS_USRRDY9_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */ +#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos) +#define EVSYS_CHSTATUS_USRRDY10_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */ +#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos) +#define EVSYS_CHSTATUS_USRRDY11_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */ +#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos) +#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */ +#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFFul << EVSYS_CHSTATUS_USRRDY_Pos) +#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))) +#define EVSYS_CHSTATUS_CHBUSY0_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */ +#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos) +#define EVSYS_CHSTATUS_CHBUSY1_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */ +#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos) +#define EVSYS_CHSTATUS_CHBUSY2_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */ +#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos) +#define EVSYS_CHSTATUS_CHBUSY3_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */ +#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos) +#define EVSYS_CHSTATUS_CHBUSY4_Pos 20 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */ +#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos) +#define EVSYS_CHSTATUS_CHBUSY5_Pos 21 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */ +#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos) +#define EVSYS_CHSTATUS_CHBUSY6_Pos 22 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */ +#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos) +#define EVSYS_CHSTATUS_CHBUSY7_Pos 23 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */ +#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos) +#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */ +#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos) +#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */ +#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos) +#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */ +#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos) +#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */ +#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos) +#define EVSYS_CHSTATUS_CHBUSY_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */ +#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFFul << EVSYS_CHSTATUS_CHBUSY_Pos) +#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))) +#define EVSYS_CHSTATUS_MASK 0x0FFF0FFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */ + +/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ + uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun Interrupt Enable */ + uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun Interrupt Enable */ + uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun Interrupt Enable */ + uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection Interrupt Enable */ + uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection Interrupt Enable */ + uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection Interrupt Enable */ + uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection Interrupt Enable */ + uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection Interrupt Enable */ + uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection Interrupt Enable */ + uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection Interrupt Enable */ + uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection Interrupt Enable */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} EVSYS_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */ +#define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */ + +#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos) +#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos) +#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos) +#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos) +#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos) +#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos) +#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos) +#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos) +#define EVSYS_INTENCLR_OVR8_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos) +#define EVSYS_INTENCLR_OVR9_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos) +#define EVSYS_INTENCLR_OVR10_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos) +#define EVSYS_INTENCLR_OVR11_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos) +#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */ +#define EVSYS_INTENCLR_OVR_Msk (0xFFFul << EVSYS_INTENCLR_OVR_Pos) +#define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))) +#define EVSYS_INTENCLR_EVD0_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos) +#define EVSYS_INTENCLR_EVD1_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos) +#define EVSYS_INTENCLR_EVD2_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos) +#define EVSYS_INTENCLR_EVD3_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos) +#define EVSYS_INTENCLR_EVD4_Pos 20 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos) +#define EVSYS_INTENCLR_EVD5_Pos 21 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos) +#define EVSYS_INTENCLR_EVD6_Pos 22 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos) +#define EVSYS_INTENCLR_EVD7_Pos 23 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos) +#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos) +#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos) +#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos) +#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos) +#define EVSYS_INTENCLR_EVD_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */ +#define EVSYS_INTENCLR_EVD_Msk (0xFFFul << EVSYS_INTENCLR_EVD_Pos) +#define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))) +#define EVSYS_INTENCLR_MASK 0x0FFF0FFFul /**< \brief (EVSYS_INTENCLR) MASK Register */ + +/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ + uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun Interrupt Enable */ + uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun Interrupt Enable */ + uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun Interrupt Enable */ + uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection Interrupt Enable */ + uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection Interrupt Enable */ + uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection Interrupt Enable */ + uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection Interrupt Enable */ + uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection Interrupt Enable */ + uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection Interrupt Enable */ + uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection Interrupt Enable */ + uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection Interrupt Enable */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} EVSYS_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */ +#define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */ + +#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos) +#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos) +#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos) +#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos) +#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos) +#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos) +#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos) +#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos) +#define EVSYS_INTENSET_OVR8_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos) +#define EVSYS_INTENSET_OVR9_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos) +#define EVSYS_INTENSET_OVR10_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos) +#define EVSYS_INTENSET_OVR11_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos) +#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */ +#define EVSYS_INTENSET_OVR_Msk (0xFFFul << EVSYS_INTENSET_OVR_Pos) +#define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))) +#define EVSYS_INTENSET_EVD0_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos) +#define EVSYS_INTENSET_EVD1_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos) +#define EVSYS_INTENSET_EVD2_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos) +#define EVSYS_INTENSET_EVD3_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos) +#define EVSYS_INTENSET_EVD4_Pos 20 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos) +#define EVSYS_INTENSET_EVD5_Pos 21 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos) +#define EVSYS_INTENSET_EVD6_Pos 22 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos) +#define EVSYS_INTENSET_EVD7_Pos 23 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos) +#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos) +#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos) +#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos) +#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos) +#define EVSYS_INTENSET_EVD_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */ +#define EVSYS_INTENSET_EVD_Msk (0xFFFul << EVSYS_INTENSET_EVD_Pos) +#define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))) +#define EVSYS_INTENSET_MASK 0x0FFF0FFFul /**< \brief (EVSYS_INTENSET) MASK Register */ + +/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ + uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun */ + uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun */ + uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun */ + uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection */ + uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection */ + uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection */ + uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection */ + uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection */ + uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection */ + uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection */ + uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} EVSYS_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */ +#define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */ +#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos) +#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */ +#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos) +#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */ +#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos) +#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */ +#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos) +#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */ +#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos) +#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */ +#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos) +#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */ +#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos) +#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */ +#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos) +#define EVSYS_INTFLAG_OVR8_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */ +#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos) +#define EVSYS_INTFLAG_OVR9_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */ +#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos) +#define EVSYS_INTFLAG_OVR10_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */ +#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos) +#define EVSYS_INTFLAG_OVR11_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */ +#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos) +#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */ +#define EVSYS_INTFLAG_OVR_Msk (0xFFFul << EVSYS_INTFLAG_OVR_Pos) +#define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))) +#define EVSYS_INTFLAG_EVD0_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */ +#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos) +#define EVSYS_INTFLAG_EVD1_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */ +#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos) +#define EVSYS_INTFLAG_EVD2_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */ +#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos) +#define EVSYS_INTFLAG_EVD3_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */ +#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos) +#define EVSYS_INTFLAG_EVD4_Pos 20 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */ +#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos) +#define EVSYS_INTFLAG_EVD5_Pos 21 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */ +#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos) +#define EVSYS_INTFLAG_EVD6_Pos 22 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */ +#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos) +#define EVSYS_INTFLAG_EVD7_Pos 23 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */ +#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos) +#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */ +#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos) +#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */ +#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos) +#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */ +#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos) +#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */ +#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos) +#define EVSYS_INTFLAG_EVD_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */ +#define EVSYS_INTFLAG_EVD_Msk (0xFFFul << EVSYS_INTFLAG_EVD_Pos) +#define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))) +#define EVSYS_INTFLAG_MASK 0x0FFF0FFFul /**< \brief (EVSYS_INTFLAG) MASK Register */ + +/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x1C) ( /W 32) Software Event -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */ + uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */ + uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */ + uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */ + uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */ + uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */ + uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */ + uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */ + uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */ + uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */ + uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */ + uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHANNEL:12; /*!< bit: 0..11 Channel x Software Selection */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} EVSYS_SWEVT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EVSYS_SWEVT_OFFSET 0x1C /**< \brief (EVSYS_SWEVT offset) Software Event */ +#define EVSYS_SWEVT_RESETVALUE 0x00000000ul /**< \brief (EVSYS_SWEVT reset_value) Software Event */ + +#define EVSYS_SWEVT_CHANNEL0_Pos 0 /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */ +#define EVSYS_SWEVT_CHANNEL0 (1 << EVSYS_SWEVT_CHANNEL0_Pos) +#define EVSYS_SWEVT_CHANNEL1_Pos 1 /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */ +#define EVSYS_SWEVT_CHANNEL1 (1 << EVSYS_SWEVT_CHANNEL1_Pos) +#define EVSYS_SWEVT_CHANNEL2_Pos 2 /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */ +#define EVSYS_SWEVT_CHANNEL2 (1 << EVSYS_SWEVT_CHANNEL2_Pos) +#define EVSYS_SWEVT_CHANNEL3_Pos 3 /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */ +#define EVSYS_SWEVT_CHANNEL3 (1 << EVSYS_SWEVT_CHANNEL3_Pos) +#define EVSYS_SWEVT_CHANNEL4_Pos 4 /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */ +#define EVSYS_SWEVT_CHANNEL4 (1 << EVSYS_SWEVT_CHANNEL4_Pos) +#define EVSYS_SWEVT_CHANNEL5_Pos 5 /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */ +#define EVSYS_SWEVT_CHANNEL5 (1 << EVSYS_SWEVT_CHANNEL5_Pos) +#define EVSYS_SWEVT_CHANNEL6_Pos 6 /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */ +#define EVSYS_SWEVT_CHANNEL6 (1 << EVSYS_SWEVT_CHANNEL6_Pos) +#define EVSYS_SWEVT_CHANNEL7_Pos 7 /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */ +#define EVSYS_SWEVT_CHANNEL7 (1 << EVSYS_SWEVT_CHANNEL7_Pos) +#define EVSYS_SWEVT_CHANNEL8_Pos 8 /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */ +#define EVSYS_SWEVT_CHANNEL8 (1 << EVSYS_SWEVT_CHANNEL8_Pos) +#define EVSYS_SWEVT_CHANNEL9_Pos 9 /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */ +#define EVSYS_SWEVT_CHANNEL9 (1 << EVSYS_SWEVT_CHANNEL9_Pos) +#define EVSYS_SWEVT_CHANNEL10_Pos 10 /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */ +#define EVSYS_SWEVT_CHANNEL10 (1 << EVSYS_SWEVT_CHANNEL10_Pos) +#define EVSYS_SWEVT_CHANNEL11_Pos 11 /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */ +#define EVSYS_SWEVT_CHANNEL11 (1 << EVSYS_SWEVT_CHANNEL11_Pos) +#define EVSYS_SWEVT_CHANNEL_Pos 0 /**< \brief (EVSYS_SWEVT) Channel x Software Selection */ +#define EVSYS_SWEVT_CHANNEL_Msk (0xFFFul << EVSYS_SWEVT_CHANNEL_Pos) +#define EVSYS_SWEVT_CHANNEL(value) ((EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))) +#define EVSYS_SWEVT_MASK 0x00000FFFul /**< \brief (EVSYS_SWEVT) MASK Register */ + +/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x20) (R/W 32) Channel n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */ + uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */ + uint32_t :2; /*!< bit: 12..13 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */ + uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} EVSYS_CHANNEL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EVSYS_CHANNEL_OFFSET 0x20 /**< \brief (EVSYS_CHANNEL offset) Channel n */ +#define EVSYS_CHANNEL_RESETVALUE 0x00008000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel n */ + +#define EVSYS_CHANNEL_EVGEN_Pos 0 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */ +#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos) +#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))) +#define EVSYS_CHANNEL_PATH_Pos 8 /**< \brief (EVSYS_CHANNEL) Path Selection */ +#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos) +#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))) +#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */ +#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */ +#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */ +#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) +#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) +#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) +#define EVSYS_CHANNEL_EDGSEL_Pos 10 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */ +#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos) +#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))) +#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */ +#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */ +#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */ +#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */ +#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) +#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) +#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) +#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) +#define EVSYS_CHANNEL_RUNSTDBY_Pos 14 /**< \brief (EVSYS_CHANNEL) Run in standby */ +#define EVSYS_CHANNEL_RUNSTDBY (0x1ul << EVSYS_CHANNEL_RUNSTDBY_Pos) +#define EVSYS_CHANNEL_ONDEMAND_Pos 15 /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */ +#define EVSYS_CHANNEL_ONDEMAND (0x1ul << EVSYS_CHANNEL_ONDEMAND_Pos) +#define EVSYS_CHANNEL_MASK 0x0000CF7Ful /**< \brief (EVSYS_CHANNEL) MASK Register */ + +/* -------- EVSYS_USER : (EVSYS Offset: 0x80) (R/W 32) User Multiplexer n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHANNEL:5; /*!< bit: 0.. 4 Channel Event Selection */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} EVSYS_USER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EVSYS_USER_OFFSET 0x80 /**< \brief (EVSYS_USER offset) User Multiplexer n */ +#define EVSYS_USER_RESETVALUE 0x00000000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer n */ + +#define EVSYS_USER_CHANNEL_Pos 0 /**< \brief (EVSYS_USER) Channel Event Selection */ +#define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos) +#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))) +#define EVSYS_USER_MASK 0x0000001Ful /**< \brief (EVSYS_USER) MASK Register */ + +/** \brief EVSYS hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ + RoReg8 Reserved1[0xB]; + __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ + __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ + __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ + __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ + __O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x1C ( /W 32) Software Event */ + __IO EVSYS_CHANNEL_Type CHANNEL[12]; /**< \brief Offset: 0x20 (R/W 32) Channel n */ + RoReg8 Reserved2[0x30]; + __IO EVSYS_USER_Type USER[45]; /**< \brief Offset: 0x80 (R/W 32) User Multiplexer n */ +} Evsys; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_EVSYS_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_gclk.h new file mode 100644 index 0000000000..743797da84 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_gclk.h @@ -0,0 +1,235 @@ +/** + * \file + * + * \brief Component description for GCLK + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_GCLK_COMPONENT_ +#define _SAML21_GCLK_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR GCLK */ +/* ========================================================================== */ +/** \addtogroup SAML21_GCLK Generic Clock Generator */ +/*@{*/ + +#define GCLK_U2122 +#define REV_GCLK 0x111 + +/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} GCLK_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */ +#define GCLK_CTRLA_RESETVALUE 0x00ul /**< \brief (GCLK_CTRLA reset_value) Control */ + +#define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */ +#define GCLK_CTRLA_SWRST (0x1ul << GCLK_CTRLA_SWRST_Pos) +#define GCLK_CTRLA_MASK 0x01ul /**< \brief (GCLK_CTRLA) MASK Register */ + +/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */ + uint32_t :1; /*!< bit: 1 Reserved */ + uint32_t GENCTRL:9; /*!< bit: 2..10 Generic Clock Generator Control Synchronization Busy bits */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} GCLK_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */ +#define GCLK_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */ + +#define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */ +#define GCLK_SYNCBUSY_SWRST (0x1ul << GCLK_SYNCBUSY_SWRST_Pos) +#define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control Synchronization Busy bits */ +#define GCLK_SYNCBUSY_GENCTRL_Msk (0x1FFul << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_GENCTRL(value) ((GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))) +#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val 0x0ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */ +#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val 0x1ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */ +#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val 0x2ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */ +#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val 0x3ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */ +#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val 0x4ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */ +#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val 0x5ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */ +#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val 0x6ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */ +#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val 0x7ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */ +#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val 0x8ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */ +#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos) +#define GCLK_SYNCBUSY_MASK 0x000007FDul /**< \brief (GCLK_SYNCBUSY) MASK Register */ + +/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */ + uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */ + uint32_t OOV:1; /*!< bit: 10 Output Off Value */ + uint32_t OE:1; /*!< bit: 11 Output Enable */ + uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */ + uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t DIV:16; /*!< bit: 16..31 Division Factor */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} GCLK_GENCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */ +#define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */ + +#define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */ +#define GCLK_GENCTRL_SRC_Msk (0xFul << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))) +#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */ +#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */ +#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */ +#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */ +#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */ +#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */ +#define GCLK_GENCTRL_SRC_OSC16M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC16M oscillator output */ +#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */ +#define GCLK_GENCTRL_SRC_DPLL96M_Val 0x8ul /**< \brief (GCLK_GENCTRL) DPLL96M output */ +#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_SRC_OSC16M (GCLK_GENCTRL_SRC_OSC16M_Val << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_SRC_DPLL96M (GCLK_GENCTRL_SRC_DPLL96M_Val << GCLK_GENCTRL_SRC_Pos) +#define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */ +#define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos) +#define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */ +#define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos) +#define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */ +#define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos) +#define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */ +#define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos) +#define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */ +#define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos) +#define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */ +#define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos) +#define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */ +#define GCLK_GENCTRL_DIV_Msk (0xFFFFul << GCLK_GENCTRL_DIV_Pos) +#define GCLK_GENCTRL_DIV(value) ((GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))) +#define GCLK_GENCTRL_MASK 0xFFFF3F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */ + +/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */ + uint32_t :2; /*!< bit: 4.. 5 Reserved */ + uint32_t CHEN:1; /*!< bit: 6 Channel Enable */ + uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} GCLK_PCHCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */ +#define GCLK_PCHCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */ + +#define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */ +#define GCLK_PCHCTRL_GEN_Msk (0xFul << GCLK_PCHCTRL_GEN_Pos) +#define GCLK_PCHCTRL_GEN(value) ((GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))) +#define GCLK_PCHCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */ +#define GCLK_PCHCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */ +#define GCLK_PCHCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */ +#define GCLK_PCHCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */ +#define GCLK_PCHCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */ +#define GCLK_PCHCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */ +#define GCLK_PCHCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */ +#define GCLK_PCHCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */ +#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos) +#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos) +#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos) +#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos) +#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos) +#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos) +#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos) +#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos) +#define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */ +#define GCLK_PCHCTRL_CHEN (0x1ul << GCLK_PCHCTRL_CHEN_Pos) +#define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */ +#define GCLK_PCHCTRL_WRTLOCK (0x1ul << GCLK_PCHCTRL_WRTLOCK_Pos) +#define GCLK_PCHCTRL_MASK 0x000000CFul /**< \brief (GCLK_PCHCTRL) MASK Register */ + +/** \brief GCLK hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */ + RoReg8 Reserved2[0x18]; + __IO GCLK_GENCTRL_Type GENCTRL[9]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */ + RoReg8 Reserved3[0x3C]; + __IO GCLK_PCHCTRL_Type PCHCTRL[36]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */ +} Gclk; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_GCLK_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mclk.h new file mode 100644 index 0000000000..5a3ecc098a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mclk.h @@ -0,0 +1,531 @@ +/** + * \file + * + * \brief Component description for MCLK + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_MCLK_COMPONENT_ +#define _SAML21_MCLK_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR MCLK */ +/* ========================================================================== */ +/** \addtogroup SAML21_MCLK Main Clock */ +/*@{*/ + +#define MCLK_U2234 +#define REV_MCLK 0x100 + +/* -------- MCLK_CTRLA : (MCLK Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t CFDEN:1; /*!< bit: 2 Clock Failure Detector Enable */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EMCLK:1; /*!< bit: 4 Emergency Clock Select */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} MCLK_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_CTRLA_OFFSET 0x00 /**< \brief (MCLK_CTRLA offset) Control A */ +#define MCLK_CTRLA_RESETVALUE 0x00ul /**< \brief (MCLK_CTRLA reset_value) Control A */ + +#define MCLK_CTRLA_CFDEN_Pos 2 /**< \brief (MCLK_CTRLA) Clock Failure Detector Enable */ +#define MCLK_CTRLA_CFDEN (0x1ul << MCLK_CTRLA_CFDEN_Pos) +#define MCLK_CTRLA_EMCLK_Pos 4 /**< \brief (MCLK_CTRLA) Emergency Clock Select */ +#define MCLK_CTRLA_EMCLK (0x1ul << MCLK_CTRLA_EMCLK_Pos) +#define MCLK_CTRLA_MASK 0x14ul /**< \brief (MCLK_CTRLA) MASK Register */ + +/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ + uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} MCLK_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */ +#define MCLK_INTENCLR_RESETVALUE 0x00ul /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */ + +#define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */ +#define MCLK_INTENCLR_CKRDY (0x1ul << MCLK_INTENCLR_CKRDY_Pos) +#define MCLK_INTENCLR_CFD_Pos 1 /**< \brief (MCLK_INTENCLR) Clock Failure Detector Interrupt Enable */ +#define MCLK_INTENCLR_CFD (0x1ul << MCLK_INTENCLR_CFD_Pos) +#define MCLK_INTENCLR_MASK 0x03ul /**< \brief (MCLK_INTENCLR) MASK Register */ + +/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ + uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} MCLK_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */ +#define MCLK_INTENSET_RESETVALUE 0x00ul /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */ + +#define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */ +#define MCLK_INTENSET_CKRDY (0x1ul << MCLK_INTENSET_CKRDY_Pos) +#define MCLK_INTENSET_CFD_Pos 1 /**< \brief (MCLK_INTENSET) Clock Failure Detector Interrupt Enable */ +#define MCLK_INTENSET_CFD (0x1ul << MCLK_INTENSET_CFD_Pos) +#define MCLK_INTENSET_MASK 0x03ul /**< \brief (MCLK_INTENSET) MASK Register */ + +/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ + uint8_t CFD:1; /*!< bit: 1 Clock Failure Detector */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} MCLK_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */ +#define MCLK_INTFLAG_RESETVALUE 0x01ul /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */ +#define MCLK_INTFLAG_CKRDY (0x1ul << MCLK_INTFLAG_CKRDY_Pos) +#define MCLK_INTFLAG_CFD_Pos 1 /**< \brief (MCLK_INTFLAG) Clock Failure Detector */ +#define MCLK_INTFLAG_CFD (0x1ul << MCLK_INTFLAG_CFD_Pos) +#define MCLK_INTFLAG_MASK 0x03ul /**< \brief (MCLK_INTFLAG) MASK Register */ + +/* -------- MCLK_CPUDIV : (MCLK Offset: 0x04) (R/W 8) CPU Clock Division -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CPUDIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} MCLK_CPUDIV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_CPUDIV_OFFSET 0x04 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */ +#define MCLK_CPUDIV_RESETVALUE 0x01ul /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */ + +#define MCLK_CPUDIV_CPUDIV_Pos 0 /**< \brief (MCLK_CPUDIV) CPU Clock Division Factor */ +#define MCLK_CPUDIV_CPUDIV_Msk (0xFFul << MCLK_CPUDIV_CPUDIV_Pos) +#define MCLK_CPUDIV_CPUDIV(value) ((MCLK_CPUDIV_CPUDIV_Msk & ((value) << MCLK_CPUDIV_CPUDIV_Pos))) +#define MCLK_CPUDIV_CPUDIV_DIV1_Val 0x1ul /**< \brief (MCLK_CPUDIV) Divide by 1 */ +#define MCLK_CPUDIV_CPUDIV_DIV2_Val 0x2ul /**< \brief (MCLK_CPUDIV) Divide by 2 */ +#define MCLK_CPUDIV_CPUDIV_DIV4_Val 0x4ul /**< \brief (MCLK_CPUDIV) Divide by 4 */ +#define MCLK_CPUDIV_CPUDIV_DIV8_Val 0x8ul /**< \brief (MCLK_CPUDIV) Divide by 8 */ +#define MCLK_CPUDIV_CPUDIV_DIV16_Val 0x10ul /**< \brief (MCLK_CPUDIV) Divide by 16 */ +#define MCLK_CPUDIV_CPUDIV_DIV32_Val 0x20ul /**< \brief (MCLK_CPUDIV) Divide by 32 */ +#define MCLK_CPUDIV_CPUDIV_DIV64_Val 0x40ul /**< \brief (MCLK_CPUDIV) Divide by 64 */ +#define MCLK_CPUDIV_CPUDIV_DIV128_Val 0x80ul /**< \brief (MCLK_CPUDIV) Divide by 128 */ +#define MCLK_CPUDIV_CPUDIV_DIV1 (MCLK_CPUDIV_CPUDIV_DIV1_Val << MCLK_CPUDIV_CPUDIV_Pos) +#define MCLK_CPUDIV_CPUDIV_DIV2 (MCLK_CPUDIV_CPUDIV_DIV2_Val << MCLK_CPUDIV_CPUDIV_Pos) +#define MCLK_CPUDIV_CPUDIV_DIV4 (MCLK_CPUDIV_CPUDIV_DIV4_Val << MCLK_CPUDIV_CPUDIV_Pos) +#define MCLK_CPUDIV_CPUDIV_DIV8 (MCLK_CPUDIV_CPUDIV_DIV8_Val << MCLK_CPUDIV_CPUDIV_Pos) +#define MCLK_CPUDIV_CPUDIV_DIV16 (MCLK_CPUDIV_CPUDIV_DIV16_Val << MCLK_CPUDIV_CPUDIV_Pos) +#define MCLK_CPUDIV_CPUDIV_DIV32 (MCLK_CPUDIV_CPUDIV_DIV32_Val << MCLK_CPUDIV_CPUDIV_Pos) +#define MCLK_CPUDIV_CPUDIV_DIV64 (MCLK_CPUDIV_CPUDIV_DIV64_Val << MCLK_CPUDIV_CPUDIV_Pos) +#define MCLK_CPUDIV_CPUDIV_DIV128 (MCLK_CPUDIV_CPUDIV_DIV128_Val << MCLK_CPUDIV_CPUDIV_Pos) +#define MCLK_CPUDIV_MASK 0xFFul /**< \brief (MCLK_CPUDIV) MASK Register */ + +/* -------- MCLK_LPDIV : (MCLK Offset: 0x05) (R/W 8) Low-Power Clock Division -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t LPDIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} MCLK_LPDIV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_LPDIV_OFFSET 0x05 /**< \brief (MCLK_LPDIV offset) Low-Power Clock Division */ +#define MCLK_LPDIV_RESETVALUE 0x01ul /**< \brief (MCLK_LPDIV reset_value) Low-Power Clock Division */ + +#define MCLK_LPDIV_LPDIV_Pos 0 /**< \brief (MCLK_LPDIV) Low-Power Clock Division Factor */ +#define MCLK_LPDIV_LPDIV_Msk (0xFFul << MCLK_LPDIV_LPDIV_Pos) +#define MCLK_LPDIV_LPDIV(value) ((MCLK_LPDIV_LPDIV_Msk & ((value) << MCLK_LPDIV_LPDIV_Pos))) +#define MCLK_LPDIV_LPDIV_DIV1_Val 0x1ul /**< \brief (MCLK_LPDIV) Divide by 1 */ +#define MCLK_LPDIV_LPDIV_DIV2_Val 0x2ul /**< \brief (MCLK_LPDIV) Divide by 2 */ +#define MCLK_LPDIV_LPDIV_DIV4_Val 0x4ul /**< \brief (MCLK_LPDIV) Divide by 4 */ +#define MCLK_LPDIV_LPDIV_DIV8_Val 0x8ul /**< \brief (MCLK_LPDIV) Divide by 8 */ +#define MCLK_LPDIV_LPDIV_DIV16_Val 0x10ul /**< \brief (MCLK_LPDIV) Divide by 16 */ +#define MCLK_LPDIV_LPDIV_DIV32_Val 0x20ul /**< \brief (MCLK_LPDIV) Divide by 32 */ +#define MCLK_LPDIV_LPDIV_DIV64_Val 0x40ul /**< \brief (MCLK_LPDIV) Divide by 64 */ +#define MCLK_LPDIV_LPDIV_DIV128_Val 0x80ul /**< \brief (MCLK_LPDIV) Divide by 128 */ +#define MCLK_LPDIV_LPDIV_DIV1 (MCLK_LPDIV_LPDIV_DIV1_Val << MCLK_LPDIV_LPDIV_Pos) +#define MCLK_LPDIV_LPDIV_DIV2 (MCLK_LPDIV_LPDIV_DIV2_Val << MCLK_LPDIV_LPDIV_Pos) +#define MCLK_LPDIV_LPDIV_DIV4 (MCLK_LPDIV_LPDIV_DIV4_Val << MCLK_LPDIV_LPDIV_Pos) +#define MCLK_LPDIV_LPDIV_DIV8 (MCLK_LPDIV_LPDIV_DIV8_Val << MCLK_LPDIV_LPDIV_Pos) +#define MCLK_LPDIV_LPDIV_DIV16 (MCLK_LPDIV_LPDIV_DIV16_Val << MCLK_LPDIV_LPDIV_Pos) +#define MCLK_LPDIV_LPDIV_DIV32 (MCLK_LPDIV_LPDIV_DIV32_Val << MCLK_LPDIV_LPDIV_Pos) +#define MCLK_LPDIV_LPDIV_DIV64 (MCLK_LPDIV_LPDIV_DIV64_Val << MCLK_LPDIV_LPDIV_Pos) +#define MCLK_LPDIV_LPDIV_DIV128 (MCLK_LPDIV_LPDIV_DIV128_Val << MCLK_LPDIV_LPDIV_Pos) +#define MCLK_LPDIV_MASK 0xFFul /**< \brief (MCLK_LPDIV) MASK Register */ + +/* -------- MCLK_BUPDIV : (MCLK Offset: 0x06) (R/W 8) Backup Clock Division -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BUPDIV:8; /*!< bit: 0.. 7 Backup Clock Division Factor */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} MCLK_BUPDIV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_BUPDIV_OFFSET 0x06 /**< \brief (MCLK_BUPDIV offset) Backup Clock Division */ +#define MCLK_BUPDIV_RESETVALUE 0x01ul /**< \brief (MCLK_BUPDIV reset_value) Backup Clock Division */ + +#define MCLK_BUPDIV_BUPDIV_Pos 0 /**< \brief (MCLK_BUPDIV) Backup Clock Division Factor */ +#define MCLK_BUPDIV_BUPDIV_Msk (0xFFul << MCLK_BUPDIV_BUPDIV_Pos) +#define MCLK_BUPDIV_BUPDIV(value) ((MCLK_BUPDIV_BUPDIV_Msk & ((value) << MCLK_BUPDIV_BUPDIV_Pos))) +#define MCLK_BUPDIV_BUPDIV_DIV1_Val 0x1ul /**< \brief (MCLK_BUPDIV) Divide by 1 */ +#define MCLK_BUPDIV_BUPDIV_DIV2_Val 0x2ul /**< \brief (MCLK_BUPDIV) Divide by 2 */ +#define MCLK_BUPDIV_BUPDIV_DIV4_Val 0x4ul /**< \brief (MCLK_BUPDIV) Divide by 4 */ +#define MCLK_BUPDIV_BUPDIV_DIV8_Val 0x8ul /**< \brief (MCLK_BUPDIV) Divide by 8 */ +#define MCLK_BUPDIV_BUPDIV_DIV16_Val 0x10ul /**< \brief (MCLK_BUPDIV) Divide by 16 */ +#define MCLK_BUPDIV_BUPDIV_DIV32_Val 0x20ul /**< \brief (MCLK_BUPDIV) Divide by 32 */ +#define MCLK_BUPDIV_BUPDIV_DIV64_Val 0x40ul /**< \brief (MCLK_BUPDIV) Divide by 64 */ +#define MCLK_BUPDIV_BUPDIV_DIV128_Val 0x80ul /**< \brief (MCLK_BUPDIV) Divide by 128 */ +#define MCLK_BUPDIV_BUPDIV_DIV1 (MCLK_BUPDIV_BUPDIV_DIV1_Val << MCLK_BUPDIV_BUPDIV_Pos) +#define MCLK_BUPDIV_BUPDIV_DIV2 (MCLK_BUPDIV_BUPDIV_DIV2_Val << MCLK_BUPDIV_BUPDIV_Pos) +#define MCLK_BUPDIV_BUPDIV_DIV4 (MCLK_BUPDIV_BUPDIV_DIV4_Val << MCLK_BUPDIV_BUPDIV_Pos) +#define MCLK_BUPDIV_BUPDIV_DIV8 (MCLK_BUPDIV_BUPDIV_DIV8_Val << MCLK_BUPDIV_BUPDIV_Pos) +#define MCLK_BUPDIV_BUPDIV_DIV16 (MCLK_BUPDIV_BUPDIV_DIV16_Val << MCLK_BUPDIV_BUPDIV_Pos) +#define MCLK_BUPDIV_BUPDIV_DIV32 (MCLK_BUPDIV_BUPDIV_DIV32_Val << MCLK_BUPDIV_BUPDIV_Pos) +#define MCLK_BUPDIV_BUPDIV_DIV64 (MCLK_BUPDIV_BUPDIV_DIV64_Val << MCLK_BUPDIV_BUPDIV_Pos) +#define MCLK_BUPDIV_BUPDIV_DIV128 (MCLK_BUPDIV_BUPDIV_DIV128_Val << MCLK_BUPDIV_BUPDIV_Pos) +#define MCLK_BUPDIV_MASK 0xFFul /**< \brief (MCLK_BUPDIV) MASK Register */ + +/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ + uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ + uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ + uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */ + uint32_t HPB4_:1; /*!< bit: 4 HPB4 AHB Clock Mask */ + uint32_t DSU_:1; /*!< bit: 5 DSU AHB Clock Mask */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t NVMCTRL_:1; /*!< bit: 8 NVMCTRL AHB Clock Mask */ + uint32_t HMCRAMCHS_:1; /*!< bit: 9 HMCRAMCHS AHB Clock Mask */ + uint32_t HMCRAMCLP_:1; /*!< bit: 10 HMCRAMCLP AHB Clock Mask */ + uint32_t DMAC_:1; /*!< bit: 11 DMAC AHB Clock Mask */ + uint32_t USB_:1; /*!< bit: 12 USB AHB Clock Mask */ + uint32_t PICOPRAM_:1; /*!< bit: 13 PICOPRAM AHB Clock Mask */ + uint32_t PAC_:1; /*!< bit: 14 PAC AHB Clock Mask */ + uint32_t NVMCTRL_PICACHU_:1; /*!< bit: 15 NVMCTRL_PICACHU AHB Clock Mask */ + uint32_t L2HBRIDGES_H_:1; /*!< bit: 16 L2HBRIDGES_H AHB Clock Mask */ + uint32_t H2LBRIDGES_H_:1; /*!< bit: 17 H2LBRIDGES_H AHB Clock Mask */ + uint32_t HMCRAMCHS_AHBSETUPKEEPER_:1; /*!< bit: 18 HMCRAMCHS_AHBSETUPKEEPER AHB Clock Mask */ + uint32_t HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_:1; /*!< bit: 19 HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} MCLK_AHBMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */ +#define MCLK_AHBMASK_RESETVALUE 0x000FFFFFul /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */ + +#define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */ +#define MCLK_AHBMASK_HPB0 (0x1ul << MCLK_AHBMASK_HPB0_Pos) +#define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */ +#define MCLK_AHBMASK_HPB1 (0x1ul << MCLK_AHBMASK_HPB1_Pos) +#define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */ +#define MCLK_AHBMASK_HPB2 (0x1ul << MCLK_AHBMASK_HPB2_Pos) +#define MCLK_AHBMASK_HPB3_Pos 3 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */ +#define MCLK_AHBMASK_HPB3 (0x1ul << MCLK_AHBMASK_HPB3_Pos) +#define MCLK_AHBMASK_HPB4_Pos 4 /**< \brief (MCLK_AHBMASK) HPB4 AHB Clock Mask */ +#define MCLK_AHBMASK_HPB4 (0x1ul << MCLK_AHBMASK_HPB4_Pos) +#define MCLK_AHBMASK_DSU_Pos 5 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */ +#define MCLK_AHBMASK_DSU (0x1ul << MCLK_AHBMASK_DSU_Pos) +#define MCLK_AHBMASK_NVMCTRL_Pos 8 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */ +#define MCLK_AHBMASK_NVMCTRL (0x1ul << MCLK_AHBMASK_NVMCTRL_Pos) +#define MCLK_AHBMASK_HMCRAMCHS_Pos 9 /**< \brief (MCLK_AHBMASK) HMCRAMCHS AHB Clock Mask */ +#define MCLK_AHBMASK_HMCRAMCHS (0x1ul << MCLK_AHBMASK_HMCRAMCHS_Pos) +#define MCLK_AHBMASK_HMCRAMCLP_Pos 10 /**< \brief (MCLK_AHBMASK) HMCRAMCLP AHB Clock Mask */ +#define MCLK_AHBMASK_HMCRAMCLP (0x1ul << MCLK_AHBMASK_HMCRAMCLP_Pos) +#define MCLK_AHBMASK_DMAC_Pos 11 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */ +#define MCLK_AHBMASK_DMAC (0x1ul << MCLK_AHBMASK_DMAC_Pos) +#define MCLK_AHBMASK_USB_Pos 12 /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */ +#define MCLK_AHBMASK_USB (0x1ul << MCLK_AHBMASK_USB_Pos) +#define MCLK_AHBMASK_PICOPRAM_Pos 13 /**< \brief (MCLK_AHBMASK) PICOPRAM AHB Clock Mask */ +#define MCLK_AHBMASK_PICOPRAM (0x1ul << MCLK_AHBMASK_PICOPRAM_Pos) +#define MCLK_AHBMASK_PAC_Pos 14 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */ +#define MCLK_AHBMASK_PAC (0x1ul << MCLK_AHBMASK_PAC_Pos) +#define MCLK_AHBMASK_NVMCTRL_PICACHU_Pos 15 /**< \brief (MCLK_AHBMASK) NVMCTRL_PICACHU AHB Clock Mask */ +#define MCLK_AHBMASK_NVMCTRL_PICACHU (0x1ul << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos) +#define MCLK_AHBMASK_L2HBRIDGES_H_Pos 16 /**< \brief (MCLK_AHBMASK) L2HBRIDGES_H AHB Clock Mask */ +#define MCLK_AHBMASK_L2HBRIDGES_H (0x1ul << MCLK_AHBMASK_L2HBRIDGES_H_Pos) +#define MCLK_AHBMASK_H2LBRIDGES_H_Pos 17 /**< \brief (MCLK_AHBMASK) H2LBRIDGES_H AHB Clock Mask */ +#define MCLK_AHBMASK_H2LBRIDGES_H (0x1ul << MCLK_AHBMASK_H2LBRIDGES_H_Pos) +#define MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_Pos 18 /**< \brief (MCLK_AHBMASK) HMCRAMCHS_AHBSETUPKEEPER AHB Clock Mask */ +#define MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER (0x1ul << MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_Pos) +#define MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_Pos 19 /**< \brief (MCLK_AHBMASK) HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask */ +#define MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE (0x1ul << MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_Pos) +#define MCLK_AHBMASK_MASK 0x000FFF3Ful /**< \brief (MCLK_AHBMASK) MASK Register */ + +/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PM_:1; /*!< bit: 0 PM APB Clock Enable */ + uint32_t MCLK_:1; /*!< bit: 1 MCLK APB Clock Enable */ + uint32_t RSTC_:1; /*!< bit: 2 RSTC APB Clock Enable */ + uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL APB Clock Enable */ + uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL APB Clock Enable */ + uint32_t SUPC_:1; /*!< bit: 5 SUPC APB Clock Enable */ + uint32_t GCLK_:1; /*!< bit: 6 GCLK APB Clock Enable */ + uint32_t WDT_:1; /*!< bit: 7 WDT APB Clock Enable */ + uint32_t RTC_:1; /*!< bit: 8 RTC APB Clock Enable */ + uint32_t EIC_:1; /*!< bit: 9 EIC APB Clock Enable */ + uint32_t PORT_:1; /*!< bit: 10 PORT APB Clock Enable */ + uint32_t TAL_:1; /*!< bit: 11 TAL APB Clock Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} MCLK_APBAMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */ +#define MCLK_APBAMASK_RESETVALUE 0x00001FFFul /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */ + +#define MCLK_APBAMASK_PM_Pos 0 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */ +#define MCLK_APBAMASK_PM (0x1ul << MCLK_APBAMASK_PM_Pos) +#define MCLK_APBAMASK_MCLK_Pos 1 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */ +#define MCLK_APBAMASK_MCLK (0x1ul << MCLK_APBAMASK_MCLK_Pos) +#define MCLK_APBAMASK_RSTC_Pos 2 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */ +#define MCLK_APBAMASK_RSTC (0x1ul << MCLK_APBAMASK_RSTC_Pos) +#define MCLK_APBAMASK_OSCCTRL_Pos 3 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */ +#define MCLK_APBAMASK_OSCCTRL (0x1ul << MCLK_APBAMASK_OSCCTRL_Pos) +#define MCLK_APBAMASK_OSC32KCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */ +#define MCLK_APBAMASK_OSC32KCTRL (0x1ul << MCLK_APBAMASK_OSC32KCTRL_Pos) +#define MCLK_APBAMASK_SUPC_Pos 5 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */ +#define MCLK_APBAMASK_SUPC (0x1ul << MCLK_APBAMASK_SUPC_Pos) +#define MCLK_APBAMASK_GCLK_Pos 6 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */ +#define MCLK_APBAMASK_GCLK (0x1ul << MCLK_APBAMASK_GCLK_Pos) +#define MCLK_APBAMASK_WDT_Pos 7 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */ +#define MCLK_APBAMASK_WDT (0x1ul << MCLK_APBAMASK_WDT_Pos) +#define MCLK_APBAMASK_RTC_Pos 8 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */ +#define MCLK_APBAMASK_RTC (0x1ul << MCLK_APBAMASK_RTC_Pos) +#define MCLK_APBAMASK_EIC_Pos 9 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */ +#define MCLK_APBAMASK_EIC (0x1ul << MCLK_APBAMASK_EIC_Pos) +#define MCLK_APBAMASK_PORT_Pos 10 /**< \brief (MCLK_APBAMASK) PORT APB Clock Enable */ +#define MCLK_APBAMASK_PORT (0x1ul << MCLK_APBAMASK_PORT_Pos) +#define MCLK_APBAMASK_TAL_Pos 11 /**< \brief (MCLK_APBAMASK) TAL APB Clock Enable */ +#define MCLK_APBAMASK_TAL (0x1ul << MCLK_APBAMASK_TAL_Pos) +#define MCLK_APBAMASK_MASK 0x00000FFFul /**< \brief (MCLK_APBAMASK) MASK Register */ + +/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t USB_:1; /*!< bit: 0 USB APB Clock Enable */ + uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ + uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} MCLK_APBBMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */ +#define MCLK_APBBMASK_RESETVALUE 0x00000017ul /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */ + +#define MCLK_APBBMASK_USB_Pos 0 /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */ +#define MCLK_APBBMASK_USB (0x1ul << MCLK_APBBMASK_USB_Pos) +#define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */ +#define MCLK_APBBMASK_DSU (0x1ul << MCLK_APBBMASK_DSU_Pos) +#define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */ +#define MCLK_APBBMASK_NVMCTRL (0x1ul << MCLK_APBBMASK_NVMCTRL_Pos) +#define MCLK_APBBMASK_MASK 0x00000007ul /**< \brief (MCLK_APBBMASK) MASK Register */ + +/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 APB Clock Enable */ + uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 APB Clock Enable */ + uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 APB Clock Enable */ + uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 APB Clock Enable */ + uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 APB Clock Enable */ + uint32_t TCC0_:1; /*!< bit: 5 TCC0 APB Clock Enable */ + uint32_t TCC1_:1; /*!< bit: 6 TCC1 APB Clock Enable */ + uint32_t TCC2_:1; /*!< bit: 7 TCC2 APB Clock Enable */ + uint32_t TC0_:1; /*!< bit: 8 TC0 APB Clock Enable */ + uint32_t TC1_:1; /*!< bit: 9 TC1 APB Clock Enable */ + uint32_t TC2_:1; /*!< bit: 10 TC2 APB Clock Enable */ + uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ + uint32_t DAC_:1; /*!< bit: 12 DAC APB Clock Enable */ + uint32_t AES_:1; /*!< bit: 13 AES APB Clock Enable */ + uint32_t TRNG_:1; /*!< bit: 14 TRNG APB Clock Enable */ + uint32_t :17; /*!< bit: 15..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} MCLK_APBCMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */ +#define MCLK_APBCMASK_RESETVALUE 0x00007FFFul /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */ + +#define MCLK_APBCMASK_SERCOM0_Pos 0 /**< \brief (MCLK_APBCMASK) SERCOM0 APB Clock Enable */ +#define MCLK_APBCMASK_SERCOM0 (0x1ul << MCLK_APBCMASK_SERCOM0_Pos) +#define MCLK_APBCMASK_SERCOM1_Pos 1 /**< \brief (MCLK_APBCMASK) SERCOM1 APB Clock Enable */ +#define MCLK_APBCMASK_SERCOM1 (0x1ul << MCLK_APBCMASK_SERCOM1_Pos) +#define MCLK_APBCMASK_SERCOM2_Pos 2 /**< \brief (MCLK_APBCMASK) SERCOM2 APB Clock Enable */ +#define MCLK_APBCMASK_SERCOM2 (0x1ul << MCLK_APBCMASK_SERCOM2_Pos) +#define MCLK_APBCMASK_SERCOM3_Pos 3 /**< \brief (MCLK_APBCMASK) SERCOM3 APB Clock Enable */ +#define MCLK_APBCMASK_SERCOM3 (0x1ul << MCLK_APBCMASK_SERCOM3_Pos) +#define MCLK_APBCMASK_SERCOM4_Pos 4 /**< \brief (MCLK_APBCMASK) SERCOM4 APB Clock Enable */ +#define MCLK_APBCMASK_SERCOM4 (0x1ul << MCLK_APBCMASK_SERCOM4_Pos) +#define MCLK_APBCMASK_TCC0_Pos 5 /**< \brief (MCLK_APBCMASK) TCC0 APB Clock Enable */ +#define MCLK_APBCMASK_TCC0 (0x1ul << MCLK_APBCMASK_TCC0_Pos) +#define MCLK_APBCMASK_TCC1_Pos 6 /**< \brief (MCLK_APBCMASK) TCC1 APB Clock Enable */ +#define MCLK_APBCMASK_TCC1 (0x1ul << MCLK_APBCMASK_TCC1_Pos) +#define MCLK_APBCMASK_TCC2_Pos 7 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */ +#define MCLK_APBCMASK_TCC2 (0x1ul << MCLK_APBCMASK_TCC2_Pos) +#define MCLK_APBCMASK_TC0_Pos 8 /**< \brief (MCLK_APBCMASK) TC0 APB Clock Enable */ +#define MCLK_APBCMASK_TC0 (0x1ul << MCLK_APBCMASK_TC0_Pos) +#define MCLK_APBCMASK_TC1_Pos 9 /**< \brief (MCLK_APBCMASK) TC1 APB Clock Enable */ +#define MCLK_APBCMASK_TC1 (0x1ul << MCLK_APBCMASK_TC1_Pos) +#define MCLK_APBCMASK_TC2_Pos 10 /**< \brief (MCLK_APBCMASK) TC2 APB Clock Enable */ +#define MCLK_APBCMASK_TC2 (0x1ul << MCLK_APBCMASK_TC2_Pos) +#define MCLK_APBCMASK_TC3_Pos 11 /**< \brief (MCLK_APBCMASK) TC3 APB Clock Enable */ +#define MCLK_APBCMASK_TC3 (0x1ul << MCLK_APBCMASK_TC3_Pos) +#define MCLK_APBCMASK_DAC_Pos 12 /**< \brief (MCLK_APBCMASK) DAC APB Clock Enable */ +#define MCLK_APBCMASK_DAC (0x1ul << MCLK_APBCMASK_DAC_Pos) +#define MCLK_APBCMASK_AES_Pos 13 /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */ +#define MCLK_APBCMASK_AES (0x1ul << MCLK_APBCMASK_AES_Pos) +#define MCLK_APBCMASK_TRNG_Pos 14 /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */ +#define MCLK_APBCMASK_TRNG (0x1ul << MCLK_APBCMASK_TRNG_Pos) +#define MCLK_APBCMASK_MASK 0x00007FFFul /**< \brief (MCLK_APBCMASK) MASK Register */ + +/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Clock Enable */ + uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */ + uint32_t TC4_:1; /*!< bit: 2 TC4 APB Clock Enable */ + uint32_t ADC_:1; /*!< bit: 3 ADC APB Clock Enable */ + uint32_t AC_:1; /*!< bit: 4 AC APB Clock Enable */ + uint32_t PTC_:1; /*!< bit: 5 PTC APB Clock Enable */ + uint32_t OPAMP_:1; /*!< bit: 6 OPAMP APB Clock Enable */ + uint32_t CCL_:1; /*!< bit: 7 CCL APB Clock Enable */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} MCLK_APBDMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */ +#define MCLK_APBDMASK_RESETVALUE 0x000000FFul /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */ + +#define MCLK_APBDMASK_EVSYS_Pos 0 /**< \brief (MCLK_APBDMASK) EVSYS APB Clock Enable */ +#define MCLK_APBDMASK_EVSYS (0x1ul << MCLK_APBDMASK_EVSYS_Pos) +#define MCLK_APBDMASK_SERCOM5_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */ +#define MCLK_APBDMASK_SERCOM5 (0x1ul << MCLK_APBDMASK_SERCOM5_Pos) +#define MCLK_APBDMASK_TC4_Pos 2 /**< \brief (MCLK_APBDMASK) TC4 APB Clock Enable */ +#define MCLK_APBDMASK_TC4 (0x1ul << MCLK_APBDMASK_TC4_Pos) +#define MCLK_APBDMASK_ADC_Pos 3 /**< \brief (MCLK_APBDMASK) ADC APB Clock Enable */ +#define MCLK_APBDMASK_ADC (0x1ul << MCLK_APBDMASK_ADC_Pos) +#define MCLK_APBDMASK_AC_Pos 4 /**< \brief (MCLK_APBDMASK) AC APB Clock Enable */ +#define MCLK_APBDMASK_AC (0x1ul << MCLK_APBDMASK_AC_Pos) +#define MCLK_APBDMASK_PTC_Pos 5 /**< \brief (MCLK_APBDMASK) PTC APB Clock Enable */ +#define MCLK_APBDMASK_PTC (0x1ul << MCLK_APBDMASK_PTC_Pos) +#define MCLK_APBDMASK_OPAMP_Pos 6 /**< \brief (MCLK_APBDMASK) OPAMP APB Clock Enable */ +#define MCLK_APBDMASK_OPAMP (0x1ul << MCLK_APBDMASK_OPAMP_Pos) +#define MCLK_APBDMASK_CCL_Pos 7 /**< \brief (MCLK_APBDMASK) CCL APB Clock Enable */ +#define MCLK_APBDMASK_CCL (0x1ul << MCLK_APBDMASK_CCL_Pos) +#define MCLK_APBDMASK_MASK 0x000000FFul /**< \brief (MCLK_APBDMASK) MASK Register */ + +/* -------- MCLK_APBEMASK : (MCLK Offset: 0x24) (R/W 32) APBE Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} MCLK_APBEMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCLK_APBEMASK_OFFSET 0x24 /**< \brief (MCLK_APBEMASK offset) APBE Mask */ +#define MCLK_APBEMASK_RESETVALUE 0x0000000Dul /**< \brief (MCLK_APBEMASK reset_value) APBE Mask */ + +#define MCLK_APBEMASK_PAC_Pos 0 /**< \brief (MCLK_APBEMASK) PAC APB Clock Enable */ +#define MCLK_APBEMASK_PAC (0x1ul << MCLK_APBEMASK_PAC_Pos) +#define MCLK_APBEMASK_MASK 0x00000001ul /**< \brief (MCLK_APBEMASK) MASK Register */ + +/** \brief MCLK hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO MCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */ + __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */ + __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */ + __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x04 (R/W 8) CPU Clock Division */ + __IO MCLK_LPDIV_Type LPDIV; /**< \brief Offset: 0x05 (R/W 8) Low-Power Clock Division */ + __IO MCLK_BUPDIV_Type BUPDIV; /**< \brief Offset: 0x06 (R/W 8) Backup Clock Division */ + RoReg8 Reserved1[0x9]; + __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */ + __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */ + __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */ + __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */ + __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */ + __IO MCLK_APBEMASK_Type APBEMASK; /**< \brief Offset: 0x24 (R/W 32) APBE Mask */ +} Mclk; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_MCLK_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mtb.h new file mode 100644 index 0000000000..28fc408e77 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_mtb.h @@ -0,0 +1,399 @@ +/** + * \file + * + * \brief Component description for MTB + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_MTB_COMPONENT_ +#define _SAML21_MTB_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR MTB */ +/* ========================================================================== */ +/** \addtogroup SAML21_MTB Cortex-M0+ Micro-Trace Buffer */ +/*@{*/ + +#define MTB_U2002 +#define REV_MTB 0x100 + +/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ + uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} MTB_POSITION_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */ + +#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */ +#define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos) +#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */ +#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos) +#define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))) +#define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */ + +/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ + uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ + uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ + uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ + uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ + uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ + uint32_t :21; /*!< bit: 10..30 Reserved */ + uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} MTB_MASTER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */ +#define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */ + +#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */ +#define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos) +#define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))) +#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */ +#define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos) +#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */ +#define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos) +#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */ +#define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos) +#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */ +#define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos) +#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */ +#define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos) +#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */ +#define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos) +#define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */ + +/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ + uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} MTB_FLOW_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */ +#define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */ + +#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */ +#define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos) +#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */ +#define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos) +#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */ +#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos) +#define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))) +#define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */ + +/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_BASE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */ +#define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */ + +/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_ITCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */ +#define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */ + +/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_CLAIMSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */ +#define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */ + +/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_CLAIMCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */ +#define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */ + +/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_LOCKACCESS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */ +#define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */ + +/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_LOCKSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */ +#define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */ + +/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_AUTHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */ +#define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */ + +/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_DEVARCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */ +#define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */ + +/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_DEVID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */ +#define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */ + +/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_DEVTYPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */ +#define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */ + +/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) Peripheral Identification 4 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_PID4_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) Peripheral Identification 4 */ +#define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */ + +/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) Peripheral Identification 5 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_PID5_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) Peripheral Identification 5 */ +#define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */ + +/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) Peripheral Identification 6 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_PID6_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) Peripheral Identification 6 */ +#define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */ + +/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) Peripheral Identification 7 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_PID7_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) Peripheral Identification 7 */ +#define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */ + +/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) Peripheral Identification 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_PID0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) Peripheral Identification 0 */ +#define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */ + +/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) Peripheral Identification 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_PID1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) Peripheral Identification 1 */ +#define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */ + +/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) Peripheral Identification 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_PID2_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) Peripheral Identification 2 */ +#define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */ + +/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) Peripheral Identification 3 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_PID3_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) Peripheral Identification 3 */ +#define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */ + +/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) Component Identification 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_CID0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) Component Identification 0 */ +#define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */ + +/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) Component Identification 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_CID1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) Component Identification 1 */ +#define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */ + +/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) Component Identification 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_CID2_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) Component Identification 2 */ +#define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */ + +/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) Component Identification 3 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} MTB_CID3_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) Component Identification 3 */ +#define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */ + +/** \brief MTB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ + __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ + __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ + __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ + RoReg8 Reserved1[0xEF0]; + __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ + RoReg8 Reserved2[0x9C]; + __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ + __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ + RoReg8 Reserved3[0x8]; + __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ + __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ + __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ + __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ + RoReg8 Reserved4[0x8]; + __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ + __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ + __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) Peripheral Identification 4 */ + __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) Peripheral Identification 5 */ + __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) Peripheral Identification 6 */ + __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) Peripheral Identification 7 */ + __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) Peripheral Identification 0 */ + __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) Peripheral Identification 1 */ + __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) Peripheral Identification 2 */ + __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) Peripheral Identification 3 */ + __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) Component Identification 0 */ + __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) Component Identification 1 */ + __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) Component Identification 2 */ + __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) Component Identification 3 */ +} Mtb; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_MTB_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_nvmctrl.h new file mode 100644 index 0000000000..a37a2f1fd8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_nvmctrl.h @@ -0,0 +1,582 @@ +/** + * \file + * + * \brief Component description for NVMCTRL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_NVMCTRL_COMPONENT_ +#define _SAML21_NVMCTRL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR NVMCTRL */ +/* ========================================================================== */ +/** \addtogroup SAML21_NVMCTRL Non-Volatile Memory Controller */ +/*@{*/ + +#define NVMCTRL_U2207 +#define REV_NVMCTRL 0x302 + +/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CMD:7; /*!< bit: 0.. 6 Command */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} NVMCTRL_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */ +#define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */ + +#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */ +#define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))) +#define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */ +#define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ +#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ +#define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ +#define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */ +#define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */ +#define NVMCTRL_CTRLA_CMD_RWWEEER_Val 0x1Aul /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */ +#define NVMCTRL_CTRLA_CMD_RWWEEWP_Val 0x1Cul /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ +#define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */ +#define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ +#define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */ +#define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */ +#define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */ +#define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */ +#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */ +#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_RWWEEER (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_RWWEEWP (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos) +#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */ +#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos) +#define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))) +#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */ +#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos) +#define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */ + +/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t MANW:1; /*!< bit: 7 Manual Write */ + uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ + uint32_t :1; /*!< bit: 10 Reserved */ + uint32_t FWUP:1; /*!< bit: 11 fast wake-up */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ + uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} NVMCTRL_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */ +#define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */ + +#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */ +#define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos) +#define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))) +#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */ +#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */ +#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */ +#define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos) +#define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos) +#define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos) +#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */ +#define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos) +#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */ +#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos) +#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))) +#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */ +#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */ +#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */ +#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) +#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) +#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) +#define NVMCTRL_CTRLB_FWUP_Pos 11 /**< \brief (NVMCTRL_CTRLB) fast wake-up */ +#define NVMCTRL_CTRLB_FWUP (0x1ul << NVMCTRL_CTRLB_FWUP_Pos) +#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */ +#define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos) +#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))) +#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */ +#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */ +#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */ +#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos) +#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos) +#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos) +#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */ +#define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos) +#define NVMCTRL_CTRLB_MASK 0x00070B9Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */ + +/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ + uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} NVMCTRL_PARAM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */ +#define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */ + +#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */ +#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos) +#define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))) +#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */ +#define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos) +#define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))) +#define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */ +#define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */ +#define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */ +#define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */ +#define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */ +#define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */ +#define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */ +#define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */ +#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) +#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) +#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) +#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) +#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) +#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) +#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) +#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) +#define NVMCTRL_PARAM_RWWEEP_Pos 20 /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */ +#define NVMCTRL_PARAM_RWWEEP_Msk (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos) +#define NVMCTRL_PARAM_RWWEEP(value) ((NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))) +#define NVMCTRL_PARAM_MASK 0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */ + +/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ + uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} NVMCTRL_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */ +#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */ + +#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */ +#define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos) +#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */ +#define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos) +#define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */ + +/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ + uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} NVMCTRL_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */ +#define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */ + +#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */ +#define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos) +#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */ +#define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos) +#define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */ + +/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready */ + uint8_t ERROR:1; /*!< bit: 1 Error */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} NVMCTRL_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ +#define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */ +#define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos) +#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */ +#define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos) +#define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */ + +/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ + uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ + uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ + uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ + uint16_t NVME:1; /*!< bit: 4 NVM Error */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t SB:1; /*!< bit: 8 Security Bit Status */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} NVMCTRL_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */ +#define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */ + +#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */ +#define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos) +#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */ +#define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos) +#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */ +#define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos) +#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */ +#define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos) +#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */ +#define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos) +#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */ +#define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos) +#define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */ + +/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} NVMCTRL_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */ +#define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */ + +#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */ +#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos) +#define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))) +#define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */ + +/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} NVMCTRL_LOCK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */ + +#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */ +#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos) +#define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))) +#define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */ + +/** \brief NVMCTRL APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + RoReg8 Reserved1[0x2]; + __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ + __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ + __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + RoReg8 Reserved2[0x3]; + __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ + RoReg8 Reserved3[0x3]; + __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x3]; + __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ + RoReg8 Reserved5[0x2]; + __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ + __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ +} Nvmctrl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#ifdef __GNUC__ +#define SECTION_NVMCTRL_CAL __attribute__ ((section(".flash"))) +#elif defined(__ICCARM__) +#define SECTION_NVMCTRL_CAL @".flash" +#endif + +#ifdef __GNUC__ +#define SECTION_NVMCTRL_LOCKBIT __attribute__ ((section(".flash"))) +#elif defined(__ICCARM__) +#define SECTION_NVMCTRL_LOCKBIT @".flash" +#endif + +#ifdef __GNUC__ +#define SECTION_NVMCTRL_OTP1 __attribute__ ((section(".flash"))) +#elif defined(__ICCARM__) +#define SECTION_NVMCTRL_OTP1 @".flash" +#endif + +#ifdef __GNUC__ +#define SECTION_NVMCTRL_OTP2 __attribute__ ((section(".flash"))) +#elif defined(__ICCARM__) +#define SECTION_NVMCTRL_OTP2 @".flash" +#endif + +#ifdef __GNUC__ +#define SECTION_NVMCTRL_OTP3 __attribute__ ((section(".flash"))) +#elif defined(__ICCARM__) +#define SECTION_NVMCTRL_OTP3 @".flash" +#endif + +#ifdef __GNUC__ +#define SECTION_NVMCTRL_OTP4 __attribute__ ((section(".flash"))) +#elif defined(__ICCARM__) +#define SECTION_NVMCTRL_OTP4 @".flash" +#endif + +#ifdef __GNUC__ +#define SECTION_NVMCTRL_OTP5 __attribute__ ((section(".flash"))) +#elif defined(__ICCARM__) +#define SECTION_NVMCTRL_OTP5 @".flash" +#endif + +#ifdef __GNUC__ +#define SECTION_NVMCTRL_TEMP_LOG __attribute__ ((section(".flash"))) +#elif defined(__ICCARM__) +#define SECTION_NVMCTRL_TEMP_LOG @".flash" +#endif + +#ifdef __GNUC__ +#define SECTION_NVMCTRL_USER __attribute__ ((section(".flash"))) +#elif defined(__ICCARM__) +#define SECTION_NVMCTRL_USER @".flash" +#endif + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ +/* ************************************************************************** */ +/** \addtogroup fuses_api Peripheral Software API */ +/*@{*/ + + +#define ADC_FUSES_BIASCOMP_ADDR NVMCTRL_OTP5 +#define ADC_FUSES_BIASCOMP_Pos 3 /**< \brief (NVMCTRL_OTP5) ADC Comparator Scaling */ +#define ADC_FUSES_BIASCOMP_Msk (0x7ul << ADC_FUSES_BIASCOMP_Pos) +#define ADC_FUSES_BIASCOMP(value) ((ADC_FUSES_BIASCOMP_Msk & ((value) << ADC_FUSES_BIASCOMP_Pos))) + +#define ADC_FUSES_BIASREFBUF_ADDR NVMCTRL_OTP5 +#define ADC_FUSES_BIASREFBUF_Pos 0 /**< \brief (NVMCTRL_OTP5) ADC Bias Reference Buffer Scaling */ +#define ADC_FUSES_BIASREFBUF_Msk (0x7ul << ADC_FUSES_BIASREFBUF_Pos) +#define ADC_FUSES_BIASREFBUF(value) ((ADC_FUSES_BIASREFBUF_Msk & ((value) << ADC_FUSES_BIASREFBUF_Pos))) + +#define FUSES_BOD12_HYST_ADDR (NVMCTRL_USER + 4) +#define FUSES_BOD12_HYST_Pos 10 /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */ +#define FUSES_BOD12_HYST_Msk (0x1ul << FUSES_BOD12_HYST_Pos) + +#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER +#define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */ +#define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos) +#define FUSES_BOD33USERLEVEL(value) ((FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))) + +#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER +#define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */ +#define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos) +#define FUSES_BOD33_ACTION(value) ((FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))) + +#define FUSES_BOD33_DIS_ADDR NVMCTRL_USER +#define FUSES_BOD33_DIS_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Disable */ +#define FUSES_BOD33_DIS_Msk (0x1ul << FUSES_BOD33_DIS_Pos) + +#define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4) +#define FUSES_BOD33_HYST_Pos 9 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */ +#define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos) + +#define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) +#define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */ +#define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos) +#define FUSES_HOT_ADC_VAL(value) ((FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))) + +#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) +#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */ +#define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos) +#define FUSES_HOT_INT1V_VAL(value) ((FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))) + +#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG +#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */ +#define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos) +#define FUSES_HOT_TEMP_VAL_DEC(value) ((FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))) + +#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG +#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */ +#define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos) +#define FUSES_HOT_TEMP_VAL_INT(value) ((FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))) + +#define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) +#define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */ +#define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos) +#define FUSES_ROOM_ADC_VAL(value) ((FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))) + +#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG +#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */ +#define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos) +#define FUSES_ROOM_INT1V_VAL(value) ((FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))) + +#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG +#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */ +#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos) +#define FUSES_ROOM_TEMP_VAL_DEC(value) ((FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))) + +#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG +#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */ +#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos) +#define FUSES_ROOM_TEMP_VAL_INT(value) ((FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))) + +#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER +#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */ +#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos) +#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))) + +#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER +#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */ +#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos) +#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))) + +#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1 +#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */ +#define NVMCTRL_FUSES_NVMP_Msk (0x1FFFul << NVMCTRL_FUSES_NVMP_Pos) +#define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos))) + +#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1 +#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */ +#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos) +#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos))) + +#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1 +#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */ +#define NVMCTRL_FUSES_PSZ_Msk (0x3ul << NVMCTRL_FUSES_PSZ_Pos) +#define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos))) + +#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4) +#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */ +#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos) +#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))) + +#define NVMCTRL_FUSES_RWWEEP_ADDR (NVMCTRL_OTP1 + 4) +#define NVMCTRL_FUSES_RWWEEP_Pos 0 /**< \brief (NVMCTRL_OTP1) Number of RWW EEPROM Pages */ +#define NVMCTRL_FUSES_RWWEEP_Msk (0xFFul << NVMCTRL_FUSES_RWWEEP_Pos) +#define NVMCTRL_FUSES_RWWEEP(value) ((NVMCTRL_FUSES_RWWEEP_Msk & ((value) << NVMCTRL_FUSES_RWWEEP_Pos))) + +#define USB_FUSES_TRANSN_ADDR NVMCTRL_OTP5 +#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP5) USB pad Transn calibration */ +#define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos) +#define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))) + +#define USB_FUSES_TRANSP_ADDR NVMCTRL_OTP5 +#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP5) USB pad Transp calibration */ +#define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos) +#define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))) + +#define USB_FUSES_TRIM_ADDR NVMCTRL_OTP5 +#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP5) USB pad Trim calibration */ +#define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos) +#define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))) + +#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER +#define WDT_FUSES_ALWAYSON_Pos 27 /**< \brief (NVMCTRL_USER) WDT Always On */ +#define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos) + +#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER +#define WDT_FUSES_ENABLE_Pos 26 /**< \brief (NVMCTRL_USER) WDT Enable */ +#define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos) + +#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4) +#define WDT_FUSES_EWOFFSET_Pos 4 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */ +#define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos) +#define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))) + +#define WDT_FUSES_PER_ADDR NVMCTRL_USER +#define WDT_FUSES_PER_Pos 28 /**< \brief (NVMCTRL_USER) WDT Period */ +#define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos) +#define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))) + +#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4) +#define WDT_FUSES_WEN_Pos 8 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */ +#define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos) + +#define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4) +#define WDT_FUSES_WINDOW_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window */ +#define WDT_FUSES_WINDOW_Msk (0xFul << WDT_FUSES_WINDOW_Pos) +#define WDT_FUSES_WINDOW(value) ((WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))) + +/*@}*/ + +#endif /* _SAML21_NVMCTRL_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_opamp.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_opamp.h new file mode 100644 index 0000000000..974eb52f93 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_opamp.h @@ -0,0 +1,186 @@ +/** + * \file + * + * \brief Component description for OPAMP + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_OPAMP_COMPONENT_ +#define _SAML21_OPAMP_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR OPAMP */ +/* ========================================================================== */ +/** \addtogroup SAML21_OPAMP Operational Amplifier */ +/*@{*/ + +#define OPAMP_U2237 +#define REV_OPAMP 0x100 + +/* -------- OPAMP_CTRLA : (OPAMP Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} OPAMP_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OPAMP_CTRLA_OFFSET 0x00 /**< \brief (OPAMP_CTRLA offset) Control A */ +#define OPAMP_CTRLA_RESETVALUE 0x00ul /**< \brief (OPAMP_CTRLA reset_value) Control A */ + +#define OPAMP_CTRLA_SWRST_Pos 0 /**< \brief (OPAMP_CTRLA) Software Reset */ +#define OPAMP_CTRLA_SWRST (0x1ul << OPAMP_CTRLA_SWRST_Pos) +#define OPAMP_CTRLA_ENABLE_Pos 1 /**< \brief (OPAMP_CTRLA) Enable */ +#define OPAMP_CTRLA_ENABLE (0x1ul << OPAMP_CTRLA_ENABLE_Pos) +#define OPAMP_CTRLA_LPMUX_Pos 7 /**< \brief (OPAMP_CTRLA) Low-Power Mux */ +#define OPAMP_CTRLA_LPMUX (0x1ul << OPAMP_CTRLA_LPMUX_Pos) +#define OPAMP_CTRLA_MASK 0x83ul /**< \brief (OPAMP_CTRLA) MASK Register */ + +/* -------- OPAMP_STATUS : (OPAMP Offset: 0x02) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 OPAMP 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 OPAMP 1 Ready */ + uint8_t READY2:1; /*!< bit: 2 OPAMP 2 Ready */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:3; /*!< bit: 0.. 2 OPAMP x Ready */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} OPAMP_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OPAMP_STATUS_OFFSET 0x02 /**< \brief (OPAMP_STATUS offset) Status */ +#define OPAMP_STATUS_RESETVALUE 0x00ul /**< \brief (OPAMP_STATUS reset_value) Status */ + +#define OPAMP_STATUS_READY0_Pos 0 /**< \brief (OPAMP_STATUS) OPAMP 0 Ready */ +#define OPAMP_STATUS_READY0 (1 << OPAMP_STATUS_READY0_Pos) +#define OPAMP_STATUS_READY1_Pos 1 /**< \brief (OPAMP_STATUS) OPAMP 1 Ready */ +#define OPAMP_STATUS_READY1 (1 << OPAMP_STATUS_READY1_Pos) +#define OPAMP_STATUS_READY2_Pos 2 /**< \brief (OPAMP_STATUS) OPAMP 2 Ready */ +#define OPAMP_STATUS_READY2 (1 << OPAMP_STATUS_READY2_Pos) +#define OPAMP_STATUS_READY_Pos 0 /**< \brief (OPAMP_STATUS) OPAMP x Ready */ +#define OPAMP_STATUS_READY_Msk (0x7ul << OPAMP_STATUS_READY_Pos) +#define OPAMP_STATUS_READY(value) ((OPAMP_STATUS_READY_Msk & ((value) << OPAMP_STATUS_READY_Pos))) +#define OPAMP_STATUS_MASK 0x07ul /**< \brief (OPAMP_STATUS) MASK Register */ + +/* -------- OPAMP_OPAMPCTRL : (OPAMP Offset: 0x04) (R/W 32) OPAMP n Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Operational Amplifier Enable */ + uint32_t ANAOUT:1; /*!< bit: 2 Analog Output */ + uint32_t BIAS:2; /*!< bit: 3.. 4 Bias Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t RES2OUT:1; /*!< bit: 8 Resistor ladder To Output */ + uint32_t RES2VCC:1; /*!< bit: 9 Resistor ladder To VCC */ + uint32_t RES1EN:1; /*!< bit: 10 Resistor 1 Enable */ + uint32_t RES1MUX:2; /*!< bit: 11..12 Resistor 1 Mux */ + uint32_t POTMUX:3; /*!< bit: 13..15 Potentiometer Selection */ + uint32_t MUXPOS:3; /*!< bit: 16..18 Positive Input Mux Selection */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 20..22 Negative Input Mux Selection */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OPAMP_OPAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OPAMP_OPAMPCTRL_OFFSET 0x04 /**< \brief (OPAMP_OPAMPCTRL offset) OPAMP n Control */ +#define OPAMP_OPAMPCTRL_RESETVALUE 0x00000000ul /**< \brief (OPAMP_OPAMPCTRL reset_value) OPAMP n Control */ + +#define OPAMP_OPAMPCTRL_ENABLE_Pos 1 /**< \brief (OPAMP_OPAMPCTRL) Operational Amplifier Enable */ +#define OPAMP_OPAMPCTRL_ENABLE (0x1ul << OPAMP_OPAMPCTRL_ENABLE_Pos) +#define OPAMP_OPAMPCTRL_ANAOUT_Pos 2 /**< \brief (OPAMP_OPAMPCTRL) Analog Output */ +#define OPAMP_OPAMPCTRL_ANAOUT (0x1ul << OPAMP_OPAMPCTRL_ANAOUT_Pos) +#define OPAMP_OPAMPCTRL_BIAS_Pos 3 /**< \brief (OPAMP_OPAMPCTRL) Bias Selection */ +#define OPAMP_OPAMPCTRL_BIAS_Msk (0x3ul << OPAMP_OPAMPCTRL_BIAS_Pos) +#define OPAMP_OPAMPCTRL_BIAS(value) ((OPAMP_OPAMPCTRL_BIAS_Msk & ((value) << OPAMP_OPAMPCTRL_BIAS_Pos))) +#define OPAMP_OPAMPCTRL_RUNSTDBY_Pos 6 /**< \brief (OPAMP_OPAMPCTRL) Run in Standby */ +#define OPAMP_OPAMPCTRL_RUNSTDBY (0x1ul << OPAMP_OPAMPCTRL_RUNSTDBY_Pos) +#define OPAMP_OPAMPCTRL_ONDEMAND_Pos 7 /**< \brief (OPAMP_OPAMPCTRL) On Demand Control */ +#define OPAMP_OPAMPCTRL_ONDEMAND (0x1ul << OPAMP_OPAMPCTRL_ONDEMAND_Pos) +#define OPAMP_OPAMPCTRL_RES2OUT_Pos 8 /**< \brief (OPAMP_OPAMPCTRL) Resistor ladder To Output */ +#define OPAMP_OPAMPCTRL_RES2OUT (0x1ul << OPAMP_OPAMPCTRL_RES2OUT_Pos) +#define OPAMP_OPAMPCTRL_RES2VCC_Pos 9 /**< \brief (OPAMP_OPAMPCTRL) Resistor ladder To VCC */ +#define OPAMP_OPAMPCTRL_RES2VCC (0x1ul << OPAMP_OPAMPCTRL_RES2VCC_Pos) +#define OPAMP_OPAMPCTRL_RES1EN_Pos 10 /**< \brief (OPAMP_OPAMPCTRL) Resistor 1 Enable */ +#define OPAMP_OPAMPCTRL_RES1EN (0x1ul << OPAMP_OPAMPCTRL_RES1EN_Pos) +#define OPAMP_OPAMPCTRL_RES1MUX_Pos 11 /**< \brief (OPAMP_OPAMPCTRL) Resistor 1 Mux */ +#define OPAMP_OPAMPCTRL_RES1MUX_Msk (0x3ul << OPAMP_OPAMPCTRL_RES1MUX_Pos) +#define OPAMP_OPAMPCTRL_RES1MUX(value) ((OPAMP_OPAMPCTRL_RES1MUX_Msk & ((value) << OPAMP_OPAMPCTRL_RES1MUX_Pos))) +#define OPAMP_OPAMPCTRL_POTMUX_Pos 13 /**< \brief (OPAMP_OPAMPCTRL) Potentiometer Selection */ +#define OPAMP_OPAMPCTRL_POTMUX_Msk (0x7ul << OPAMP_OPAMPCTRL_POTMUX_Pos) +#define OPAMP_OPAMPCTRL_POTMUX(value) ((OPAMP_OPAMPCTRL_POTMUX_Msk & ((value) << OPAMP_OPAMPCTRL_POTMUX_Pos))) +#define OPAMP_OPAMPCTRL_MUXPOS_Pos 16 /**< \brief (OPAMP_OPAMPCTRL) Positive Input Mux Selection */ +#define OPAMP_OPAMPCTRL_MUXPOS_Msk (0x7ul << OPAMP_OPAMPCTRL_MUXPOS_Pos) +#define OPAMP_OPAMPCTRL_MUXPOS(value) ((OPAMP_OPAMPCTRL_MUXPOS_Msk & ((value) << OPAMP_OPAMPCTRL_MUXPOS_Pos))) +#define OPAMP_OPAMPCTRL_MUXNEG_Pos 20 /**< \brief (OPAMP_OPAMPCTRL) Negative Input Mux Selection */ +#define OPAMP_OPAMPCTRL_MUXNEG_Msk (0x7ul << OPAMP_OPAMPCTRL_MUXNEG_Pos) +#define OPAMP_OPAMPCTRL_MUXNEG(value) ((OPAMP_OPAMPCTRL_MUXNEG_Msk & ((value) << OPAMP_OPAMPCTRL_MUXNEG_Pos))) +#define OPAMP_OPAMPCTRL_MASK 0x0077FFDEul /**< \brief (OPAMP_OPAMPCTRL) MASK Register */ + +/** \brief OPAMP hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO OPAMP_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I OPAMP_STATUS_Type STATUS; /**< \brief Offset: 0x02 (R/ 8) Status */ + RoReg8 Reserved2[0x1]; + __IO OPAMP_OPAMPCTRL_Type OPAMPCTRL[3]; /**< \brief Offset: 0x04 (R/W 32) OPAMP n Control */ +} Opamp; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_OPAMP_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_osc32kctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_osc32kctrl.h new file mode 100644 index 0000000000..7d3a1afb67 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_osc32kctrl.h @@ -0,0 +1,301 @@ +/** + * \file + * + * \brief Component description for OSC32KCTRL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_OSC32KCTRL_COMPONENT_ +#define _SAML21_OSC32KCTRL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR OSC32KCTRL */ +/* ========================================================================== */ +/** \addtogroup SAML21_OSC32KCTRL 32k Oscillators Control */ +/*@{*/ + +#define OSC32KCTRL_U2246 +#define REV_OSC32KCTRL 0x110 + +/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSC32KCTRL_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */ +#define OSC32KCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */ + +#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ +#define OSC32KCTRL_INTENCLR_XOSC32KRDY (0x1ul << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) +#define OSC32KCTRL_INTENCLR_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ +#define OSC32KCTRL_INTENCLR_OSC32KRDY (0x1ul << OSC32KCTRL_INTENCLR_OSC32KRDY_Pos) +#define OSC32KCTRL_INTENCLR_MASK 0x00000003ul /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */ + +/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSC32KCTRL_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */ +#define OSC32KCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */ + +#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ +#define OSC32KCTRL_INTENSET_XOSC32KRDY (0x1ul << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) +#define OSC32KCTRL_INTENSET_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENSET) OSC32K Ready Interrupt Enable */ +#define OSC32KCTRL_INTENSET_OSC32KRDY (0x1ul << OSC32KCTRL_INTENSET_OSC32KRDY_Pos) +#define OSC32KCTRL_INTENSET_MASK 0x00000003ul /**< \brief (OSC32KCTRL_INTENSET) MASK Register */ + +/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ + uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSC32KCTRL_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ +#define OSC32KCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */ +#define OSC32KCTRL_INTFLAG_XOSC32KRDY (0x1ul << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) +#define OSC32KCTRL_INTFLAG_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTFLAG) OSC32K Ready */ +#define OSC32KCTRL_INTFLAG_OSC32KRDY (0x1ul << OSC32KCTRL_INTFLAG_OSC32KRDY_Pos) +#define OSC32KCTRL_INTFLAG_MASK 0x00000003ul /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */ + +/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ + uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSC32KCTRL_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */ +#define OSC32KCTRL_STATUS_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */ + +#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */ +#define OSC32KCTRL_STATUS_XOSC32KRDY (0x1ul << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) +#define OSC32KCTRL_STATUS_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_STATUS) OSC32K Ready */ +#define OSC32KCTRL_STATUS_OSC32KRDY (0x1ul << OSC32KCTRL_STATUS_OSC32KRDY_Pos) +#define OSC32KCTRL_STATUS_MASK 0x00000003ul /**< \brief (OSC32KCTRL_STATUS) MASK Register */ + +/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 32) Clock selection -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSC32KCTRL_RTCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) Clock selection */ +#define OSC32KCTRL_RTCCTRL_RESETVALUE 0x00000000ul /**< \brief (OSC32KCTRL_RTCCTRL reset_value) Clock selection */ + +#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */ +#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (0x7ul << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) +#define OSC32KCTRL_RTCCTRL_RTCSEL(value) ((OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))) +#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val 0x0ul /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */ +#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val 0x1ul /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */ +#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val 0x2ul /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ +#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val 0x3ul /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator */ +#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val 0x4ul /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ +#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val 0x5ul /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */ +#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) +#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) +#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) +#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) +#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) +#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) +#define OSC32KCTRL_RTCCTRL_MASK 0x00000007ul /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */ + +/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint32_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ + uint32_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint32_t :19; /*!< bit: 13..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSC32KCTRL_XOSC32K_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define OSC32KCTRL_XOSC32K_RESETVALUE 0x00000080ul /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ + +#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */ +#define OSC32KCTRL_XOSC32K_ENABLE (0x1ul << OSC32KCTRL_XOSC32K_ENABLE_Pos) +#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */ +#define OSC32KCTRL_XOSC32K_XTALEN (0x1ul << OSC32KCTRL_XOSC32K_XTALEN_Pos) +#define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */ +#define OSC32KCTRL_XOSC32K_EN32K (0x1ul << OSC32KCTRL_XOSC32K_EN32K_Pos) +#define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */ +#define OSC32KCTRL_XOSC32K_EN1K (0x1ul << OSC32KCTRL_XOSC32K_EN1K_Pos) +#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */ +#define OSC32KCTRL_XOSC32K_RUNSTDBY (0x1ul << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) +#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */ +#define OSC32KCTRL_XOSC32K_ONDEMAND (0x1ul << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) +#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */ +#define OSC32KCTRL_XOSC32K_STARTUP_Msk (0x7ul << OSC32KCTRL_XOSC32K_STARTUP_Pos) +#define OSC32KCTRL_XOSC32K_STARTUP(value) ((OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))) +#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */ +#define OSC32KCTRL_XOSC32K_WRTLOCK (0x1ul << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) +#define OSC32KCTRL_XOSC32K_MASK 0x000017DEul /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */ + +/* -------- OSC32KCTRL_OSC32K : (OSC32KCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ + uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ + uint32_t :2; /*!< bit: 4.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSC32KCTRL_OSC32K_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSC32KCTRL_OSC32K_OFFSET 0x18 /**< \brief (OSC32KCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ +#define OSC32KCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (OSC32KCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ + +#define OSC32KCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Enable */ +#define OSC32KCTRL_OSC32K_ENABLE (0x1ul << OSC32KCTRL_OSC32K_ENABLE_Pos) +#define OSC32KCTRL_OSC32K_EN32K_Pos 2 /**< \brief (OSC32KCTRL_OSC32K) 32kHz Output Enable */ +#define OSC32KCTRL_OSC32K_EN32K (0x1ul << OSC32KCTRL_OSC32K_EN32K_Pos) +#define OSC32KCTRL_OSC32K_EN1K_Pos 3 /**< \brief (OSC32KCTRL_OSC32K) 1kHz Output Enable */ +#define OSC32KCTRL_OSC32K_EN1K (0x1ul << OSC32KCTRL_OSC32K_EN1K_Pos) +#define OSC32KCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_OSC32K) Run in Standby */ +#define OSC32KCTRL_OSC32K_RUNSTDBY (0x1ul << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) +#define OSC32KCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_OSC32K) On Demand Control */ +#define OSC32KCTRL_OSC32K_ONDEMAND (0x1ul << OSC32KCTRL_OSC32K_ONDEMAND_Pos) +#define OSC32KCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Start-Up Time */ +#define OSC32KCTRL_OSC32K_STARTUP_Msk (0x7ul << OSC32KCTRL_OSC32K_STARTUP_Pos) +#define OSC32KCTRL_OSC32K_STARTUP(value) ((OSC32KCTRL_OSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_OSC32K_STARTUP_Pos))) +#define OSC32KCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_OSC32K) Write Lock */ +#define OSC32KCTRL_OSC32K_WRTLOCK (0x1ul << OSC32KCTRL_OSC32K_WRTLOCK_Pos) +#define OSC32KCTRL_OSC32K_CALIB_Pos 16 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Calibration */ +#define OSC32KCTRL_OSC32K_CALIB_Msk (0x7Ful << OSC32KCTRL_OSC32K_CALIB_Pos) +#define OSC32KCTRL_OSC32K_CALIB(value) ((OSC32KCTRL_OSC32K_CALIB_Msk & ((value) << OSC32KCTRL_OSC32K_CALIB_Pos))) +#define OSC32KCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (OSC32KCTRL_OSC32K) MASK Register */ + +/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CALIB:5; /*!< bit: 8..12 Oscillator Calibration */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSC32KCTRL_OSCULP32K_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ + +#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */ +#define OSC32KCTRL_OSCULP32K_CALIB_Msk (0x1Ful << OSC32KCTRL_OSCULP32K_CALIB_Pos) +#define OSC32KCTRL_OSCULP32K_CALIB(value) ((OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))) +#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */ +#define OSC32KCTRL_OSCULP32K_WRTLOCK (0x1ul << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) +#define OSC32KCTRL_OSCULP32K_MASK 0x00009F00ul /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */ + +/** \brief OSC32KCTRL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ + __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ + __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ + __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ + __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 32) Clock selection */ + __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control */ + __IO OSC32KCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ + __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +} Osc32kctrl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_OSC32KCTRL_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_oscctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_oscctrl.h new file mode 100644 index 0000000000..253a3d2cc9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_oscctrl.h @@ -0,0 +1,652 @@ +/** + * \file + * + * \brief Component description for OSCCTRL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_OSCCTRL_COMPONENT_ +#define _SAML21_OSCCTRL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR OSCCTRL */ +/* ========================================================================== */ +/** \addtogroup SAML21_OSCCTRL Oscillators Control */ +/*@{*/ + +#define OSCCTRL_U2119 +#define REV_OSCCTRL 0x100 + +/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 1.. 3 Reserved */ + uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Time Out Interrupt Enable */ + uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSCCTRL_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */ +#define OSCCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */ + +#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC Ready Interrupt Enable */ +#define OSCCTRL_INTENCLR_XOSCRDY (0x1ul << OSCCTRL_INTENCLR_XOSCRDY_Pos) +#define OSCCTRL_INTENCLR_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTENCLR) OSC16M Ready Interrupt Enable */ +#define OSCCTRL_INTENCLR_OSC16MRDY (0x1ul << OSCCTRL_INTENCLR_OSC16MRDY_Pos) +#define OSCCTRL_INTENCLR_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */ +#define OSCCTRL_INTENCLR_DFLLRDY (0x1ul << OSCCTRL_INTENCLR_DFLLRDY_Pos) +#define OSCCTRL_INTENCLR_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */ +#define OSCCTRL_INTENCLR_DFLLOOB (0x1ul << OSCCTRL_INTENCLR_DFLLOOB_Pos) +#define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */ +#define OSCCTRL_INTENCLR_DFLLLCKF (0x1ul << OSCCTRL_INTENCLR_DFLLLCKF_Pos) +#define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */ +#define OSCCTRL_INTENCLR_DFLLLCKC (0x1ul << OSCCTRL_INTENCLR_DFLLLCKC_Pos) +#define OSCCTRL_INTENCLR_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */ +#define OSCCTRL_INTENCLR_DFLLRCS (0x1ul << OSCCTRL_INTENCLR_DFLLRCS_Pos) +#define OSCCTRL_INTENCLR_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */ +#define OSCCTRL_INTENCLR_DPLLLCKR (0x1ul << OSCCTRL_INTENCLR_DPLLLCKR_Pos) +#define OSCCTRL_INTENCLR_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */ +#define OSCCTRL_INTENCLR_DPLLLCKF (0x1ul << OSCCTRL_INTENCLR_DPLLLCKF_Pos) +#define OSCCTRL_INTENCLR_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTENCLR) DPLL Time Out Interrupt Enable */ +#define OSCCTRL_INTENCLR_DPLLLTO (0x1ul << OSCCTRL_INTENCLR_DPLLLTO_Pos) +#define OSCCTRL_INTENCLR_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTENCLR) DPLL Ratio Ready Interrupt Enable */ +#define OSCCTRL_INTENCLR_DPLLLDRTO (0x1ul << OSCCTRL_INTENCLR_DPLLLDRTO_Pos) +#define OSCCTRL_INTENCLR_MASK 0x000F1F11ul /**< \brief (OSCCTRL_INTENCLR) MASK Register */ + +/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 1.. 3 Reserved */ + uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Time Out Interrupt Enable */ + uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSCCTRL_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */ +#define OSCCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */ + +#define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC Ready Interrupt Enable */ +#define OSCCTRL_INTENSET_XOSCRDY (0x1ul << OSCCTRL_INTENSET_XOSCRDY_Pos) +#define OSCCTRL_INTENSET_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTENSET) OSC16M Ready Interrupt Enable */ +#define OSCCTRL_INTENSET_OSC16MRDY (0x1ul << OSCCTRL_INTENSET_OSC16MRDY_Pos) +#define OSCCTRL_INTENSET_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */ +#define OSCCTRL_INTENSET_DFLLRDY (0x1ul << OSCCTRL_INTENSET_DFLLRDY_Pos) +#define OSCCTRL_INTENSET_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */ +#define OSCCTRL_INTENSET_DFLLOOB (0x1ul << OSCCTRL_INTENSET_DFLLOOB_Pos) +#define OSCCTRL_INTENSET_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */ +#define OSCCTRL_INTENSET_DFLLLCKF (0x1ul << OSCCTRL_INTENSET_DFLLLCKF_Pos) +#define OSCCTRL_INTENSET_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */ +#define OSCCTRL_INTENSET_DFLLLCKC (0x1ul << OSCCTRL_INTENSET_DFLLLCKC_Pos) +#define OSCCTRL_INTENSET_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */ +#define OSCCTRL_INTENSET_DFLLRCS (0x1ul << OSCCTRL_INTENSET_DFLLRCS_Pos) +#define OSCCTRL_INTENSET_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */ +#define OSCCTRL_INTENSET_DPLLLCKR (0x1ul << OSCCTRL_INTENSET_DPLLLCKR_Pos) +#define OSCCTRL_INTENSET_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */ +#define OSCCTRL_INTENSET_DPLLLCKF (0x1ul << OSCCTRL_INTENSET_DPLLLCKF_Pos) +#define OSCCTRL_INTENSET_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTENSET) DPLL Time Out Interrupt Enable */ +#define OSCCTRL_INTENSET_DPLLLTO (0x1ul << OSCCTRL_INTENSET_DPLLLTO_Pos) +#define OSCCTRL_INTENSET_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTENSET) DPLL Ratio Ready Interrupt Enable */ +#define OSCCTRL_INTENSET_DPLLLDRTO (0x1ul << OSCCTRL_INTENSET_DPLLLDRTO_Pos) +#define OSCCTRL_INTENSET_MASK 0x000F1F11ul /**< \brief (OSCCTRL_INTENSET) MASK Register */ + +/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + uint32_t :3; /*!< bit: 1.. 3 Reserved */ + uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ + uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ + uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ + uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ + uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise */ + uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall */ + uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Timeout */ + uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSCCTRL_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ +#define OSCCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC Ready */ +#define OSCCTRL_INTFLAG_XOSCRDY (0x1ul << OSCCTRL_INTFLAG_XOSCRDY_Pos) +#define OSCCTRL_INTFLAG_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTFLAG) OSC16M Ready */ +#define OSCCTRL_INTFLAG_OSC16MRDY (0x1ul << OSCCTRL_INTFLAG_OSC16MRDY_Pos) +#define OSCCTRL_INTFLAG_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */ +#define OSCCTRL_INTFLAG_DFLLRDY (0x1ul << OSCCTRL_INTFLAG_DFLLRDY_Pos) +#define OSCCTRL_INTFLAG_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */ +#define OSCCTRL_INTFLAG_DFLLOOB (0x1ul << OSCCTRL_INTFLAG_DFLLOOB_Pos) +#define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */ +#define OSCCTRL_INTFLAG_DFLLLCKF (0x1ul << OSCCTRL_INTFLAG_DFLLLCKF_Pos) +#define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */ +#define OSCCTRL_INTFLAG_DFLLLCKC (0x1ul << OSCCTRL_INTFLAG_DFLLLCKC_Pos) +#define OSCCTRL_INTFLAG_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */ +#define OSCCTRL_INTFLAG_DFLLRCS (0x1ul << OSCCTRL_INTFLAG_DFLLRCS_Pos) +#define OSCCTRL_INTFLAG_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Rise */ +#define OSCCTRL_INTFLAG_DPLLLCKR (0x1ul << OSCCTRL_INTFLAG_DPLLLCKR_Pos) +#define OSCCTRL_INTFLAG_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Fall */ +#define OSCCTRL_INTFLAG_DPLLLCKF (0x1ul << OSCCTRL_INTFLAG_DPLLLCKF_Pos) +#define OSCCTRL_INTFLAG_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTFLAG) DPLL Timeout */ +#define OSCCTRL_INTFLAG_DPLLLTO (0x1ul << OSCCTRL_INTFLAG_DPLLLTO_Pos) +#define OSCCTRL_INTFLAG_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTFLAG) DPLL Ratio Ready */ +#define OSCCTRL_INTFLAG_DPLLLDRTO (0x1ul << OSCCTRL_INTFLAG_DPLLLDRTO_Pos) +#define OSCCTRL_INTFLAG_MASK 0x000F1F11ul /**< \brief (OSCCTRL_INTFLAG) MASK Register */ + +/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + uint32_t :3; /*!< bit: 1.. 3 Reserved */ + uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ + uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ + uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ + uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ + uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise */ + uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall */ + uint32_t DPLLTO:1; /*!< bit: 18 DPLL Timeout */ + uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSCCTRL_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_STATUS_OFFSET 0x0C /**< \brief (OSCCTRL_STATUS offset) Power and Clocks Status */ +#define OSCCTRL_STATUS_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_STATUS reset_value) Power and Clocks Status */ + +#define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC Ready */ +#define OSCCTRL_STATUS_XOSCRDY (0x1ul << OSCCTRL_STATUS_XOSCRDY_Pos) +#define OSCCTRL_STATUS_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_STATUS) OSC16M Ready */ +#define OSCCTRL_STATUS_OSC16MRDY (0x1ul << OSCCTRL_STATUS_OSC16MRDY_Pos) +#define OSCCTRL_STATUS_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_STATUS) DFLL Ready */ +#define OSCCTRL_STATUS_DFLLRDY (0x1ul << OSCCTRL_STATUS_DFLLRDY_Pos) +#define OSCCTRL_STATUS_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */ +#define OSCCTRL_STATUS_DFLLOOB (0x1ul << OSCCTRL_STATUS_DFLLOOB_Pos) +#define OSCCTRL_STATUS_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */ +#define OSCCTRL_STATUS_DFLLLCKF (0x1ul << OSCCTRL_STATUS_DFLLLCKF_Pos) +#define OSCCTRL_STATUS_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */ +#define OSCCTRL_STATUS_DFLLLCKC (0x1ul << OSCCTRL_STATUS_DFLLLCKC_Pos) +#define OSCCTRL_STATUS_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */ +#define OSCCTRL_STATUS_DFLLRCS (0x1ul << OSCCTRL_STATUS_DFLLRCS_Pos) +#define OSCCTRL_STATUS_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_STATUS) DPLL Lock Rise */ +#define OSCCTRL_STATUS_DPLLLCKR (0x1ul << OSCCTRL_STATUS_DPLLLCKR_Pos) +#define OSCCTRL_STATUS_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_STATUS) DPLL Lock Fall */ +#define OSCCTRL_STATUS_DPLLLCKF (0x1ul << OSCCTRL_STATUS_DPLLLCKF_Pos) +#define OSCCTRL_STATUS_DPLLTO_Pos 18 /**< \brief (OSCCTRL_STATUS) DPLL Timeout */ +#define OSCCTRL_STATUS_DPLLTO (0x1ul << OSCCTRL_STATUS_DPLLTO_Pos) +#define OSCCTRL_STATUS_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_STATUS) DPLL Ratio Ready */ +#define OSCCTRL_STATUS_DPLLLDRTO (0x1ul << OSCCTRL_STATUS_DPLLLDRTO_Pos) +#define OSCCTRL_STATUS_MASK 0x000F1F11ul /**< \brief (OSCCTRL_STATUS) MASK Register */ + +/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint16_t :3; /*!< bit: 3.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ + uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ + uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} OSCCTRL_XOSCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_XOSCCTRL_OFFSET 0x10 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define OSCCTRL_XOSCCTRL_RESETVALUE 0x0080ul /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */ + +#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */ +#define OSCCTRL_XOSCCTRL_ENABLE (0x1ul << OSCCTRL_XOSCCTRL_ENABLE_Pos) +#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */ +#define OSCCTRL_XOSCCTRL_XTALEN (0x1ul << OSCCTRL_XOSCCTRL_XTALEN_Pos) +#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */ +#define OSCCTRL_XOSCCTRL_RUNSTDBY (0x1ul << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) +#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */ +#define OSCCTRL_XOSCCTRL_ONDEMAND (0x1ul << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) +#define OSCCTRL_XOSCCTRL_GAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Gain */ +#define OSCCTRL_XOSCCTRL_GAIN_Msk (0x7ul << OSCCTRL_XOSCCTRL_GAIN_Pos) +#define OSCCTRL_XOSCCTRL_GAIN(value) ((OSCCTRL_XOSCCTRL_GAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_GAIN_Pos))) +#define OSCCTRL_XOSCCTRL_AMPGC_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Amplitude Gain Control */ +#define OSCCTRL_XOSCCTRL_AMPGC (0x1ul << OSCCTRL_XOSCCTRL_AMPGC_Pos) +#define OSCCTRL_XOSCCTRL_STARTUP_Pos 12 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */ +#define OSCCTRL_XOSCCTRL_STARTUP_Msk (0xFul << OSCCTRL_XOSCCTRL_STARTUP_Pos) +#define OSCCTRL_XOSCCTRL_STARTUP(value) ((OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))) +#define OSCCTRL_XOSCCTRL_MASK 0xFFC6ul /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */ + +/* -------- OSCCTRL_OSC16MCTRL : (OSCCTRL Offset: 0x14) (R/W 8) 16MHz Internal Oscillator (OSC16M) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint8_t FSEL:2; /*!< bit: 2.. 3 Oscillator Frequency Select */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} OSCCTRL_OSC16MCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_OSC16MCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_OSC16MCTRL offset) 16MHz Internal Oscillator (OSC16M) Control */ +#define OSCCTRL_OSC16MCTRL_RESETVALUE 0x82ul /**< \brief (OSCCTRL_OSC16MCTRL reset_value) 16MHz Internal Oscillator (OSC16M) Control */ + +#define OSCCTRL_OSC16MCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Enable */ +#define OSCCTRL_OSC16MCTRL_ENABLE (0x1ul << OSCCTRL_OSC16MCTRL_ENABLE_Pos) +#define OSCCTRL_OSC16MCTRL_FSEL_Pos 2 /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Frequency Select */ +#define OSCCTRL_OSC16MCTRL_FSEL_Msk (0x3ul << OSCCTRL_OSC16MCTRL_FSEL_Pos) +#define OSCCTRL_OSC16MCTRL_FSEL(value) ((OSCCTRL_OSC16MCTRL_FSEL_Msk & ((value) << OSCCTRL_OSC16MCTRL_FSEL_Pos))) +#define OSCCTRL_OSC16MCTRL_FSEL_4_Val 0x0ul /**< \brief (OSCCTRL_OSC16MCTRL) 4MHz */ +#define OSCCTRL_OSC16MCTRL_FSEL_8_Val 0x1ul /**< \brief (OSCCTRL_OSC16MCTRL) 8MHz */ +#define OSCCTRL_OSC16MCTRL_FSEL_12_Val 0x2ul /**< \brief (OSCCTRL_OSC16MCTRL) 12MHz */ +#define OSCCTRL_OSC16MCTRL_FSEL_16_Val 0x3ul /**< \brief (OSCCTRL_OSC16MCTRL) 16MHz */ +#define OSCCTRL_OSC16MCTRL_FSEL_4 (OSCCTRL_OSC16MCTRL_FSEL_4_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) +#define OSCCTRL_OSC16MCTRL_FSEL_8 (OSCCTRL_OSC16MCTRL_FSEL_8_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) +#define OSCCTRL_OSC16MCTRL_FSEL_12 (OSCCTRL_OSC16MCTRL_FSEL_12_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) +#define OSCCTRL_OSC16MCTRL_FSEL_16 (OSCCTRL_OSC16MCTRL_FSEL_16_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) +#define OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_OSC16MCTRL) Run in Standby */ +#define OSCCTRL_OSC16MCTRL_RUNSTDBY (0x1ul << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos) +#define OSCCTRL_OSC16MCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_OSC16MCTRL) On Demand Control */ +#define OSCCTRL_OSC16MCTRL_ONDEMAND (0x1ul << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos) +#define OSCCTRL_OSC16MCTRL_MASK 0xCEul /**< \brief (OSCCTRL_OSC16MCTRL) MASK Register */ + +/* -------- OSCCTRL_DFLLCTRL : (OSCCTRL Offset: 0x18) (R/W 16) DFLL48M Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ + uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ + uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ + uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ + uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ + uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ + uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ + uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} OSCCTRL_DFLLCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DFLLCTRL_OFFSET 0x18 /**< \brief (OSCCTRL_DFLLCTRL offset) DFLL48M Control */ +#define OSCCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (OSCCTRL_DFLLCTRL reset_value) DFLL48M Control */ + +#define OSCCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRL) DFLL Enable */ +#define OSCCTRL_DFLLCTRL_ENABLE (0x1ul << OSCCTRL_DFLLCTRL_ENABLE_Pos) +#define OSCCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (OSCCTRL_DFLLCTRL) Operating Mode Selection */ +#define OSCCTRL_DFLLCTRL_MODE (0x1ul << OSCCTRL_DFLLCTRL_MODE_Pos) +#define OSCCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (OSCCTRL_DFLLCTRL) Stable DFLL Frequency */ +#define OSCCTRL_DFLLCTRL_STABLE (0x1ul << OSCCTRL_DFLLCTRL_STABLE_Pos) +#define OSCCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (OSCCTRL_DFLLCTRL) Lose Lock After Wake */ +#define OSCCTRL_DFLLCTRL_LLAW (0x1ul << OSCCTRL_DFLLCTRL_LLAW_Pos) +#define OSCCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (OSCCTRL_DFLLCTRL) USB Clock Recovery Mode */ +#define OSCCTRL_DFLLCTRL_USBCRM (0x1ul << OSCCTRL_DFLLCTRL_USBCRM_Pos) +#define OSCCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DFLLCTRL) Run in Standby */ +#define OSCCTRL_DFLLCTRL_RUNSTDBY (0x1ul << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos) +#define OSCCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DFLLCTRL) On Demand Control */ +#define OSCCTRL_DFLLCTRL_ONDEMAND (0x1ul << OSCCTRL_DFLLCTRL_ONDEMAND_Pos) +#define OSCCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (OSCCTRL_DFLLCTRL) Chill Cycle Disable */ +#define OSCCTRL_DFLLCTRL_CCDIS (0x1ul << OSCCTRL_DFLLCTRL_CCDIS_Pos) +#define OSCCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (OSCCTRL_DFLLCTRL) Quick Lock Disable */ +#define OSCCTRL_DFLLCTRL_QLDIS (0x1ul << OSCCTRL_DFLLCTRL_QLDIS_Pos) +#define OSCCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (OSCCTRL_DFLLCTRL) Bypass Coarse Lock */ +#define OSCCTRL_DFLLCTRL_BPLCKC (0x1ul << OSCCTRL_DFLLCTRL_BPLCKC_Pos) +#define OSCCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (OSCCTRL_DFLLCTRL) Wait Lock */ +#define OSCCTRL_DFLLCTRL_WAITLOCK (0x1ul << OSCCTRL_DFLLCTRL_WAITLOCK_Pos) +#define OSCCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (OSCCTRL_DFLLCTRL) MASK Register */ + +/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x1C) (R/W 32) DFLL48M Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ + uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ + uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSCCTRL_DFLLVAL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DFLLVAL_OFFSET 0x1C /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */ +#define OSCCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */ + +#define OSCCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (OSCCTRL_DFLLVAL) Fine Value */ +#define OSCCTRL_DFLLVAL_FINE_Msk (0x3FFul << OSCCTRL_DFLLVAL_FINE_Pos) +#define OSCCTRL_DFLLVAL_FINE(value) ((OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))) +#define OSCCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */ +#define OSCCTRL_DFLLVAL_COARSE_Msk (0x3Ful << OSCCTRL_DFLLVAL_COARSE_Pos) +#define OSCCTRL_DFLLVAL_COARSE(value) ((OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))) +#define OSCCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */ +#define OSCCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << OSCCTRL_DFLLVAL_DIFF_Pos) +#define OSCCTRL_DFLLVAL_DIFF(value) ((OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))) +#define OSCCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (OSCCTRL_DFLLVAL) MASK Register */ + +/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x20) (R/W 32) DFLL48M Multiplier -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ + uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ + uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSCCTRL_DFLLMUL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DFLLMUL_OFFSET 0x20 /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */ +#define OSCCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */ + +#define OSCCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */ +#define OSCCTRL_DFLLMUL_MUL_Msk (0xFFFFul << OSCCTRL_DFLLMUL_MUL_Pos) +#define OSCCTRL_DFLLMUL_MUL(value) ((OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))) +#define OSCCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */ +#define OSCCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << OSCCTRL_DFLLMUL_FSTEP_Pos) +#define OSCCTRL_DFLLMUL_FSTEP(value) ((OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))) +#define OSCCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */ +#define OSCCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << OSCCTRL_DFLLMUL_CSTEP_Pos) +#define OSCCTRL_DFLLMUL_CSTEP(value) ((OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))) +#define OSCCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (OSCCTRL_DFLLMUL) MASK Register */ + +/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x24) (R/W 8) DFLL48M Synchronization -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t READREQ:1; /*!< bit: 7 Read Request */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} OSCCTRL_DFLLSYNC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DFLLSYNC_OFFSET 0x24 /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */ +#define OSCCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */ + +#define OSCCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (OSCCTRL_DFLLSYNC) Read Request */ +#define OSCCTRL_DFLLSYNC_READREQ (0x1ul << OSCCTRL_DFLLSYNC_READREQ_Pos) +#define OSCCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */ + +/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x28) (R/W 8) DPLL Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} OSCCTRL_DPLLCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DPLLCTRLA_OFFSET 0x28 /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control */ +#define OSCCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control */ + +#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) Enable */ +#define OSCCTRL_DPLLCTRLA_ENABLE (0x1ul << OSCCTRL_DPLLCTRLA_ENABLE_Pos) +#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */ +#define OSCCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) +#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand */ +#define OSCCTRL_DPLLCTRLA_ONDEMAND (0x1ul << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) +#define OSCCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */ + +/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x2C) (R/W 32) DPLL Ratio Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSCCTRL_DPLLRATIO_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DPLLRATIO_OFFSET 0x2C /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */ +#define OSCCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ + +#define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */ +#define OSCCTRL_DPLLRATIO_LDR_Msk (0xFFFul << OSCCTRL_DPLLRATIO_LDR_Pos) +#define OSCCTRL_DPLLRATIO_LDR(value) ((OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))) +#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ +#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << OSCCTRL_DPLLRATIO_LDRFRAC_Pos) +#define OSCCTRL_DPLLRATIO_LDRFRAC(value) ((OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))) +#define OSCCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */ + +/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x30) (R/W 32) Digital Core Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ + uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ + uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ + uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} OSCCTRL_DPLLCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DPLLCTRLB_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLCTRLB offset) Digital Core Configuration */ +#define OSCCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (OSCCTRL_DPLLCTRLB reset_value) Digital Core Configuration */ + +#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ +#define OSCCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << OSCCTRL_DPLLCTRLB_FILTER_Pos) +#define OSCCTRL_DPLLCTRLB_FILTER(value) ((OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))) +#define OSCCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (OSCCTRL_DPLLCTRLB) Low-Power Enable */ +#define OSCCTRL_DPLLCTRLB_LPEN (0x1ul << OSCCTRL_DPLLCTRLB_LPEN_Pos) +#define OSCCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */ +#define OSCCTRL_DPLLCTRLB_WUF (0x1ul << OSCCTRL_DPLLCTRLB_WUF_Pos) +#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */ +#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << OSCCTRL_DPLLCTRLB_REFCLK_Pos) +#define OSCCTRL_DPLLCTRLB_REFCLK(value) ((OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))) +#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */ +#define OSCCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << OSCCTRL_DPLLCTRLB_LTIME_Pos) +#define OSCCTRL_DPLLCTRLB_LTIME(value) ((OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))) +#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */ +#define OSCCTRL_DPLLCTRLB_LBYPASS (0x1ul << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) +#define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */ +#define OSCCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << OSCCTRL_DPLLCTRLB_DIV_Pos) +#define OSCCTRL_DPLLCTRLB_DIV(value) ((OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))) +#define OSCCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */ + +/* -------- OSCCTRL_DPLLPRESC : (OSCCTRL Offset: 0x34) (R/W 8) DPLL Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRESC:2; /*!< bit: 0.. 1 Output Clock Prescaler */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} OSCCTRL_DPLLPRESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DPLLPRESC_OFFSET 0x34 /**< \brief (OSCCTRL_DPLLPRESC offset) DPLL Prescaler */ +#define OSCCTRL_DPLLPRESC_RESETVALUE 0x00ul /**< \brief (OSCCTRL_DPLLPRESC reset_value) DPLL Prescaler */ + +#define OSCCTRL_DPLLPRESC_PRESC_Pos 0 /**< \brief (OSCCTRL_DPLLPRESC) Output Clock Prescaler */ +#define OSCCTRL_DPLLPRESC_PRESC_Msk (0x3ul << OSCCTRL_DPLLPRESC_PRESC_Pos) +#define OSCCTRL_DPLLPRESC_PRESC(value) ((OSCCTRL_DPLLPRESC_PRESC_Msk & ((value) << OSCCTRL_DPLLPRESC_PRESC_Pos))) +#define OSCCTRL_DPLLPRESC_PRESC_DIV1_Val 0x0ul /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 1 */ +#define OSCCTRL_DPLLPRESC_PRESC_DIV2_Val 0x1ul /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 2 */ +#define OSCCTRL_DPLLPRESC_PRESC_DIV4_Val 0x2ul /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 4 */ +#define OSCCTRL_DPLLPRESC_PRESC_DIV1 (OSCCTRL_DPLLPRESC_PRESC_DIV1_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) +#define OSCCTRL_DPLLPRESC_PRESC_DIV2 (OSCCTRL_DPLLPRESC_PRESC_DIV2_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) +#define OSCCTRL_DPLLPRESC_PRESC_DIV4 (OSCCTRL_DPLLPRESC_PRESC_DIV4_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) +#define OSCCTRL_DPLLPRESC_MASK 0x03ul /**< \brief (OSCCTRL_DPLLPRESC) MASK Register */ + +/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x38) (R/ 8) DPLL Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */ + uint8_t DPLLRATIO:1; /*!< bit: 2 DPLL Ratio Synchronization Status */ + uint8_t DPLLPRESC:1; /*!< bit: 3 DPLL Prescaler Synchronization Status */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} OSCCTRL_DPLLSYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x38 /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */ +#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE 0x00ul /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */ + +#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */ +#define OSCCTRL_DPLLSYNCBUSY_ENABLE (0x1ul << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos) +#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Ratio Synchronization Status */ +#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (0x1ul << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos) +#define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos 3 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Prescaler Synchronization Status */ +#define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC (0x1ul << OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos) +#define OSCCTRL_DPLLSYNCBUSY_MASK 0x0Eul /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */ + +/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x3C) (R/ 8) DPLL Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ + uint8_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} OSCCTRL_DPLLSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define OSCCTRL_DPLLSTATUS_OFFSET 0x3C /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */ +#define OSCCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */ + +#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */ +#define OSCCTRL_DPLLSTATUS_LOCK (0x1ul << OSCCTRL_DPLLSTATUS_LOCK_Pos) +#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */ +#define OSCCTRL_DPLLSTATUS_CLKRDY (0x1ul << OSCCTRL_DPLLSTATUS_CLKRDY_Pos) +#define OSCCTRL_DPLLSTATUS_MASK 0x03ul /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */ + +/** \brief OSCCTRL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ + __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ + __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ + __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ + __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ + RoReg8 Reserved1[0x2]; + __IO OSCCTRL_OSC16MCTRL_Type OSC16MCTRL; /**< \brief Offset: 0x14 (R/W 8) 16MHz Internal Oscillator (OSC16M) Control */ + RoReg8 Reserved2[0x3]; + __IO OSCCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x18 (R/W 16) DFLL48M Control */ + RoReg8 Reserved3[0x2]; + __IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x1C (R/W 32) DFLL48M Value */ + __IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x20 (R/W 32) DFLL48M Multiplier */ + __IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x24 (R/W 8) DFLL48M Synchronization */ + RoReg8 Reserved4[0x3]; + __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x28 (R/W 8) DPLL Control */ + RoReg8 Reserved5[0x3]; + __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x2C (R/W 32) DPLL Ratio Control */ + __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x30 (R/W 32) Digital Core Configuration */ + __IO OSCCTRL_DPLLPRESC_Type DPLLPRESC; /**< \brief Offset: 0x34 (R/W 8) DPLL Prescaler */ + RoReg8 Reserved6[0x3]; + __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x38 (R/ 8) DPLL Synchronization Busy */ + RoReg8 Reserved7[0x3]; + __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x3C (R/ 8) DPLL Status */ +} Oscctrl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_OSCCTRL_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pac.h new file mode 100644 index 0000000000..221758132c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pac.h @@ -0,0 +1,627 @@ +/** + * \file + * + * \brief Component description for PAC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_PAC_COMPONENT_ +#define _SAML21_PAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR PAC */ +/* ========================================================================== */ +/** \addtogroup SAML21_PAC Peripheral Access Controller */ +/*@{*/ + +#define PAC_U2120 +#define REV_PAC 0x110 + +/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */ + uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_WRCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */ +#define PAC_WRCTRL_RESETVALUE 0x00000000ul /**< \brief (PAC_WRCTRL reset_value) Write control */ + +#define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */ +#define PAC_WRCTRL_PERID_Msk (0xFFFFul << PAC_WRCTRL_PERID_Pos) +#define PAC_WRCTRL_PERID(value) ((PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))) +#define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */ +#define PAC_WRCTRL_KEY_Msk (0xFFul << PAC_WRCTRL_KEY_Pos) +#define PAC_WRCTRL_KEY(value) ((PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))) +#define PAC_WRCTRL_KEY_OFF_Val 0x0ul /**< \brief (PAC_WRCTRL) No action */ +#define PAC_WRCTRL_KEY_CLR_Val 0x1ul /**< \brief (PAC_WRCTRL) Clear protection */ +#define PAC_WRCTRL_KEY_SET_Val 0x2ul /**< \brief (PAC_WRCTRL) Set protection */ +#define PAC_WRCTRL_KEY_SETLCK_Val 0x3ul /**< \brief (PAC_WRCTRL) Set and lock protection */ +#define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos) +#define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos) +#define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos) +#define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos) +#define PAC_WRCTRL_MASK 0x00FFFFFFul /**< \brief (PAC_WRCTRL) MASK Register */ + +/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */ +#define PAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (PAC_EVCTRL reset_value) Event control */ + +#define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */ +#define PAC_EVCTRL_ERREO (0x1ul << PAC_EVCTRL_ERREO_Pos) +#define PAC_EVCTRL_MASK 0x01ul /**< \brief (PAC_EVCTRL) MASK Register */ + +/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */ +#define PAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */ + +#define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */ +#define PAC_INTENCLR_ERR (0x1ul << PAC_INTENCLR_ERR_Pos) +#define PAC_INTENCLR_MASK 0x01ul /**< \brief (PAC_INTENCLR) MASK Register */ + +/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */ +#define PAC_INTENSET_RESETVALUE 0x00ul /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */ + +#define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */ +#define PAC_INTENSET_ERR (0x1ul << PAC_INTENSET_ERR_Pos) +#define PAC_INTENSET_MASK 0x01ul /**< \brief (PAC_INTENSET) MASK Register */ + +/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLASH_:1; /*!< bit: 0 FLASH */ + uint32_t HSRAMCM0P_:1; /*!< bit: 1 HSRAMCM0P */ + uint32_t HSRAMDSU_:1; /*!< bit: 2 HSRAMDSU */ + uint32_t HPB1_:1; /*!< bit: 3 HPB1 */ + uint32_t H2LBRIDGES_:1; /*!< bit: 4 H2LBRIDGES */ + uint32_t :11; /*!< bit: 5..15 Reserved */ + uint32_t HPB0_:1; /*!< bit: 16 HPB0 */ + uint32_t HPB2_:1; /*!< bit: 17 HPB2 */ + uint32_t HPB3_:1; /*!< bit: 18 HPB3 */ + uint32_t HPB4_:1; /*!< bit: 19 HPB4 */ + uint32_t PICOPRAM_:1; /*!< bit: 20 PICOPRAM */ + uint32_t LPRAMHS_:1; /*!< bit: 21 LPRAMHS */ + uint32_t LPRAMPICOP_:1; /*!< bit: 22 LPRAMPICOP */ + uint32_t LPRAMDMAC_:1; /*!< bit: 23 LPRAMDMAC */ + uint32_t L2HBRIDGES_:1; /*!< bit: 24 L2HBRIDGES */ + uint32_t HSRAMLP_:1; /*!< bit: 25 HSRAMLP */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_INTFLAGAHB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */ +#define PAC_INTFLAGAHB_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */ + +#define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */ +#define PAC_INTFLAGAHB_FLASH (0x1ul << PAC_INTFLAGAHB_FLASH_Pos) +#define PAC_INTFLAGAHB_HSRAMCM0P_Pos 1 /**< \brief (PAC_INTFLAGAHB) HSRAMCM0P */ +#define PAC_INTFLAGAHB_HSRAMCM0P (0x1ul << PAC_INTFLAGAHB_HSRAMCM0P_Pos) +#define PAC_INTFLAGAHB_HSRAMDSU_Pos 2 /**< \brief (PAC_INTFLAGAHB) HSRAMDSU */ +#define PAC_INTFLAGAHB_HSRAMDSU (0x1ul << PAC_INTFLAGAHB_HSRAMDSU_Pos) +#define PAC_INTFLAGAHB_HPB1_Pos 3 /**< \brief (PAC_INTFLAGAHB) HPB1 */ +#define PAC_INTFLAGAHB_HPB1 (0x1ul << PAC_INTFLAGAHB_HPB1_Pos) +#define PAC_INTFLAGAHB_H2LBRIDGES_Pos 4 /**< \brief (PAC_INTFLAGAHB) H2LBRIDGES */ +#define PAC_INTFLAGAHB_H2LBRIDGES (0x1ul << PAC_INTFLAGAHB_H2LBRIDGES_Pos) +#define PAC_INTFLAGAHB_HPB0_Pos 16 /**< \brief (PAC_INTFLAGAHB) HPB0 */ +#define PAC_INTFLAGAHB_HPB0 (0x1ul << PAC_INTFLAGAHB_HPB0_Pos) +#define PAC_INTFLAGAHB_HPB2_Pos 17 /**< \brief (PAC_INTFLAGAHB) HPB2 */ +#define PAC_INTFLAGAHB_HPB2 (0x1ul << PAC_INTFLAGAHB_HPB2_Pos) +#define PAC_INTFLAGAHB_HPB3_Pos 18 /**< \brief (PAC_INTFLAGAHB) HPB3 */ +#define PAC_INTFLAGAHB_HPB3 (0x1ul << PAC_INTFLAGAHB_HPB3_Pos) +#define PAC_INTFLAGAHB_HPB4_Pos 19 /**< \brief (PAC_INTFLAGAHB) HPB4 */ +#define PAC_INTFLAGAHB_HPB4 (0x1ul << PAC_INTFLAGAHB_HPB4_Pos) +#define PAC_INTFLAGAHB_PICOPRAM_Pos 20 /**< \brief (PAC_INTFLAGAHB) PICOPRAM */ +#define PAC_INTFLAGAHB_PICOPRAM (0x1ul << PAC_INTFLAGAHB_PICOPRAM_Pos) +#define PAC_INTFLAGAHB_LPRAMHS_Pos 21 /**< \brief (PAC_INTFLAGAHB) LPRAMHS */ +#define PAC_INTFLAGAHB_LPRAMHS (0x1ul << PAC_INTFLAGAHB_LPRAMHS_Pos) +#define PAC_INTFLAGAHB_LPRAMPICOP_Pos 22 /**< \brief (PAC_INTFLAGAHB) LPRAMPICOP */ +#define PAC_INTFLAGAHB_LPRAMPICOP (0x1ul << PAC_INTFLAGAHB_LPRAMPICOP_Pos) +#define PAC_INTFLAGAHB_LPRAMDMAC_Pos 23 /**< \brief (PAC_INTFLAGAHB) LPRAMDMAC */ +#define PAC_INTFLAGAHB_LPRAMDMAC (0x1ul << PAC_INTFLAGAHB_LPRAMDMAC_Pos) +#define PAC_INTFLAGAHB_L2HBRIDGES_Pos 24 /**< \brief (PAC_INTFLAGAHB) L2HBRIDGES */ +#define PAC_INTFLAGAHB_L2HBRIDGES (0x1ul << PAC_INTFLAGAHB_L2HBRIDGES_Pos) +#define PAC_INTFLAGAHB_HSRAMLP_Pos 25 /**< \brief (PAC_INTFLAGAHB) HSRAMLP */ +#define PAC_INTFLAGAHB_HSRAMLP (0x1ul << PAC_INTFLAGAHB_HSRAMLP_Pos) +#define PAC_INTFLAGAHB_MASK 0x03FF001Ful /**< \brief (PAC_INTFLAGAHB) MASK Register */ + +/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PM_:1; /*!< bit: 0 PM */ + uint32_t MCLK_:1; /*!< bit: 1 MCLK */ + uint32_t RSTC_:1; /*!< bit: 2 RSTC */ + uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL */ + uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL */ + uint32_t SUPC_:1; /*!< bit: 5 SUPC */ + uint32_t GCLK_:1; /*!< bit: 6 GCLK */ + uint32_t WDT_:1; /*!< bit: 7 WDT */ + uint32_t RTC_:1; /*!< bit: 8 RTC */ + uint32_t EIC_:1; /*!< bit: 9 EIC */ + uint32_t PORT_:1; /*!< bit: 10 PORT */ + uint32_t TAL_:1; /*!< bit: 11 TAL */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_INTFLAGA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */ +#define PAC_INTFLAGA_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */ + +#define PAC_INTFLAGA_PM_Pos 0 /**< \brief (PAC_INTFLAGA) PM */ +#define PAC_INTFLAGA_PM (0x1ul << PAC_INTFLAGA_PM_Pos) +#define PAC_INTFLAGA_MCLK_Pos 1 /**< \brief (PAC_INTFLAGA) MCLK */ +#define PAC_INTFLAGA_MCLK (0x1ul << PAC_INTFLAGA_MCLK_Pos) +#define PAC_INTFLAGA_RSTC_Pos 2 /**< \brief (PAC_INTFLAGA) RSTC */ +#define PAC_INTFLAGA_RSTC (0x1ul << PAC_INTFLAGA_RSTC_Pos) +#define PAC_INTFLAGA_OSCCTRL_Pos 3 /**< \brief (PAC_INTFLAGA) OSCCTRL */ +#define PAC_INTFLAGA_OSCCTRL (0x1ul << PAC_INTFLAGA_OSCCTRL_Pos) +#define PAC_INTFLAGA_OSC32KCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */ +#define PAC_INTFLAGA_OSC32KCTRL (0x1ul << PAC_INTFLAGA_OSC32KCTRL_Pos) +#define PAC_INTFLAGA_SUPC_Pos 5 /**< \brief (PAC_INTFLAGA) SUPC */ +#define PAC_INTFLAGA_SUPC (0x1ul << PAC_INTFLAGA_SUPC_Pos) +#define PAC_INTFLAGA_GCLK_Pos 6 /**< \brief (PAC_INTFLAGA) GCLK */ +#define PAC_INTFLAGA_GCLK (0x1ul << PAC_INTFLAGA_GCLK_Pos) +#define PAC_INTFLAGA_WDT_Pos 7 /**< \brief (PAC_INTFLAGA) WDT */ +#define PAC_INTFLAGA_WDT (0x1ul << PAC_INTFLAGA_WDT_Pos) +#define PAC_INTFLAGA_RTC_Pos 8 /**< \brief (PAC_INTFLAGA) RTC */ +#define PAC_INTFLAGA_RTC (0x1ul << PAC_INTFLAGA_RTC_Pos) +#define PAC_INTFLAGA_EIC_Pos 9 /**< \brief (PAC_INTFLAGA) EIC */ +#define PAC_INTFLAGA_EIC (0x1ul << PAC_INTFLAGA_EIC_Pos) +#define PAC_INTFLAGA_PORT_Pos 10 /**< \brief (PAC_INTFLAGA) PORT */ +#define PAC_INTFLAGA_PORT (0x1ul << PAC_INTFLAGA_PORT_Pos) +#define PAC_INTFLAGA_TAL_Pos 11 /**< \brief (PAC_INTFLAGA) TAL */ +#define PAC_INTFLAGA_TAL (0x1ul << PAC_INTFLAGA_TAL_Pos) +#define PAC_INTFLAGA_MASK 0x00000FFFul /**< \brief (PAC_INTFLAGA) MASK Register */ + +/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t USB_:1; /*!< bit: 0 USB */ + uint32_t DSU_:1; /*!< bit: 1 DSU */ + uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */ + uint32_t MTB_:1; /*!< bit: 3 MTB */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_INTFLAGB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */ +#define PAC_INTFLAGB_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */ + +#define PAC_INTFLAGB_USB_Pos 0 /**< \brief (PAC_INTFLAGB) USB */ +#define PAC_INTFLAGB_USB (0x1ul << PAC_INTFLAGB_USB_Pos) +#define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */ +#define PAC_INTFLAGB_DSU (0x1ul << PAC_INTFLAGB_DSU_Pos) +#define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */ +#define PAC_INTFLAGB_NVMCTRL (0x1ul << PAC_INTFLAGB_NVMCTRL_Pos) +#define PAC_INTFLAGB_MTB_Pos 3 /**< \brief (PAC_INTFLAGB) MTB */ +#define PAC_INTFLAGB_MTB (0x1ul << PAC_INTFLAGB_MTB_Pos) +#define PAC_INTFLAGB_MASK 0x0000000Ful /**< \brief (PAC_INTFLAGB) MASK Register */ + +/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 */ + uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 */ + uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 */ + uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 */ + uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 */ + uint32_t TCC0_:1; /*!< bit: 5 TCC0 */ + uint32_t TCC1_:1; /*!< bit: 6 TCC1 */ + uint32_t TCC2_:1; /*!< bit: 7 TCC2 */ + uint32_t TC0_:1; /*!< bit: 8 TC0 */ + uint32_t TC1_:1; /*!< bit: 9 TC1 */ + uint32_t TC2_:1; /*!< bit: 10 TC2 */ + uint32_t TC3_:1; /*!< bit: 11 TC3 */ + uint32_t DAC_:1; /*!< bit: 12 DAC */ + uint32_t AES_:1; /*!< bit: 13 AES */ + uint32_t TRNG_:1; /*!< bit: 14 TRNG */ + uint32_t :17; /*!< bit: 15..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_INTFLAGC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */ +#define PAC_INTFLAGC_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */ + +#define PAC_INTFLAGC_SERCOM0_Pos 0 /**< \brief (PAC_INTFLAGC) SERCOM0 */ +#define PAC_INTFLAGC_SERCOM0 (0x1ul << PAC_INTFLAGC_SERCOM0_Pos) +#define PAC_INTFLAGC_SERCOM1_Pos 1 /**< \brief (PAC_INTFLAGC) SERCOM1 */ +#define PAC_INTFLAGC_SERCOM1 (0x1ul << PAC_INTFLAGC_SERCOM1_Pos) +#define PAC_INTFLAGC_SERCOM2_Pos 2 /**< \brief (PAC_INTFLAGC) SERCOM2 */ +#define PAC_INTFLAGC_SERCOM2 (0x1ul << PAC_INTFLAGC_SERCOM2_Pos) +#define PAC_INTFLAGC_SERCOM3_Pos 3 /**< \brief (PAC_INTFLAGC) SERCOM3 */ +#define PAC_INTFLAGC_SERCOM3 (0x1ul << PAC_INTFLAGC_SERCOM3_Pos) +#define PAC_INTFLAGC_SERCOM4_Pos 4 /**< \brief (PAC_INTFLAGC) SERCOM4 */ +#define PAC_INTFLAGC_SERCOM4 (0x1ul << PAC_INTFLAGC_SERCOM4_Pos) +#define PAC_INTFLAGC_TCC0_Pos 5 /**< \brief (PAC_INTFLAGC) TCC0 */ +#define PAC_INTFLAGC_TCC0 (0x1ul << PAC_INTFLAGC_TCC0_Pos) +#define PAC_INTFLAGC_TCC1_Pos 6 /**< \brief (PAC_INTFLAGC) TCC1 */ +#define PAC_INTFLAGC_TCC1 (0x1ul << PAC_INTFLAGC_TCC1_Pos) +#define PAC_INTFLAGC_TCC2_Pos 7 /**< \brief (PAC_INTFLAGC) TCC2 */ +#define PAC_INTFLAGC_TCC2 (0x1ul << PAC_INTFLAGC_TCC2_Pos) +#define PAC_INTFLAGC_TC0_Pos 8 /**< \brief (PAC_INTFLAGC) TC0 */ +#define PAC_INTFLAGC_TC0 (0x1ul << PAC_INTFLAGC_TC0_Pos) +#define PAC_INTFLAGC_TC1_Pos 9 /**< \brief (PAC_INTFLAGC) TC1 */ +#define PAC_INTFLAGC_TC1 (0x1ul << PAC_INTFLAGC_TC1_Pos) +#define PAC_INTFLAGC_TC2_Pos 10 /**< \brief (PAC_INTFLAGC) TC2 */ +#define PAC_INTFLAGC_TC2 (0x1ul << PAC_INTFLAGC_TC2_Pos) +#define PAC_INTFLAGC_TC3_Pos 11 /**< \brief (PAC_INTFLAGC) TC3 */ +#define PAC_INTFLAGC_TC3 (0x1ul << PAC_INTFLAGC_TC3_Pos) +#define PAC_INTFLAGC_DAC_Pos 12 /**< \brief (PAC_INTFLAGC) DAC */ +#define PAC_INTFLAGC_DAC (0x1ul << PAC_INTFLAGC_DAC_Pos) +#define PAC_INTFLAGC_AES_Pos 13 /**< \brief (PAC_INTFLAGC) AES */ +#define PAC_INTFLAGC_AES (0x1ul << PAC_INTFLAGC_AES_Pos) +#define PAC_INTFLAGC_TRNG_Pos 14 /**< \brief (PAC_INTFLAGC) TRNG */ +#define PAC_INTFLAGC_TRNG (0x1ul << PAC_INTFLAGC_TRNG_Pos) +#define PAC_INTFLAGC_MASK 0x00007FFFul /**< \brief (PAC_INTFLAGC) MASK Register */ + +/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVSYS_:1; /*!< bit: 0 EVSYS */ + uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */ + uint32_t TC4_:1; /*!< bit: 2 TC4 */ + uint32_t ADC_:1; /*!< bit: 3 ADC */ + uint32_t AC_:1; /*!< bit: 4 AC */ + uint32_t PTC_:1; /*!< bit: 5 PTC */ + uint32_t OPAMP_:1; /*!< bit: 6 OPAMP */ + uint32_t CCL_:1; /*!< bit: 7 CCL */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_INTFLAGD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_INTFLAGD_OFFSET 0x20 /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */ +#define PAC_INTFLAGD_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */ + +#define PAC_INTFLAGD_EVSYS_Pos 0 /**< \brief (PAC_INTFLAGD) EVSYS */ +#define PAC_INTFLAGD_EVSYS (0x1ul << PAC_INTFLAGD_EVSYS_Pos) +#define PAC_INTFLAGD_SERCOM5_Pos 1 /**< \brief (PAC_INTFLAGD) SERCOM5 */ +#define PAC_INTFLAGD_SERCOM5 (0x1ul << PAC_INTFLAGD_SERCOM5_Pos) +#define PAC_INTFLAGD_TC4_Pos 2 /**< \brief (PAC_INTFLAGD) TC4 */ +#define PAC_INTFLAGD_TC4 (0x1ul << PAC_INTFLAGD_TC4_Pos) +#define PAC_INTFLAGD_ADC_Pos 3 /**< \brief (PAC_INTFLAGD) ADC */ +#define PAC_INTFLAGD_ADC (0x1ul << PAC_INTFLAGD_ADC_Pos) +#define PAC_INTFLAGD_AC_Pos 4 /**< \brief (PAC_INTFLAGD) AC */ +#define PAC_INTFLAGD_AC (0x1ul << PAC_INTFLAGD_AC_Pos) +#define PAC_INTFLAGD_PTC_Pos 5 /**< \brief (PAC_INTFLAGD) PTC */ +#define PAC_INTFLAGD_PTC (0x1ul << PAC_INTFLAGD_PTC_Pos) +#define PAC_INTFLAGD_OPAMP_Pos 6 /**< \brief (PAC_INTFLAGD) OPAMP */ +#define PAC_INTFLAGD_OPAMP (0x1ul << PAC_INTFLAGD_OPAMP_Pos) +#define PAC_INTFLAGD_CCL_Pos 7 /**< \brief (PAC_INTFLAGD) CCL */ +#define PAC_INTFLAGD_CCL (0x1ul << PAC_INTFLAGD_CCL_Pos) +#define PAC_INTFLAGD_MASK 0x000000FFul /**< \brief (PAC_INTFLAGD) MASK Register */ + +/* -------- PAC_INTFLAGE : (PAC Offset: 0x24) (R/W 32) Peripheral interrupt flag status - Bridge E -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PAC_:1; /*!< bit: 0 PAC */ + uint32_t DMAC_:1; /*!< bit: 1 DMAC */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_INTFLAGE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_INTFLAGE_OFFSET 0x24 /**< \brief (PAC_INTFLAGE offset) Peripheral interrupt flag status - Bridge E */ +#define PAC_INTFLAGE_RESETVALUE 0x00000000ul /**< \brief (PAC_INTFLAGE reset_value) Peripheral interrupt flag status - Bridge E */ + +#define PAC_INTFLAGE_PAC_Pos 0 /**< \brief (PAC_INTFLAGE) PAC */ +#define PAC_INTFLAGE_PAC (0x1ul << PAC_INTFLAGE_PAC_Pos) +#define PAC_INTFLAGE_DMAC_Pos 1 /**< \brief (PAC_INTFLAGE) DMAC */ +#define PAC_INTFLAGE_DMAC (0x1ul << PAC_INTFLAGE_DMAC_Pos) +#define PAC_INTFLAGE_MASK 0x00000003ul /**< \brief (PAC_INTFLAGE) MASK Register */ + +/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PM_:1; /*!< bit: 0 PM APB Protect Enable */ + uint32_t MCLK_:1; /*!< bit: 1 MCLK APB Protect Enable */ + uint32_t RSTC_:1; /*!< bit: 2 RSTC APB Protect Enable */ + uint32_t OSCCTRL_:1; /*!< bit: 3 OSCCTRL APB Protect Enable */ + uint32_t OSC32KCTRL_:1; /*!< bit: 4 OSC32KCTRL APB Protect Enable */ + uint32_t SUPC_:1; /*!< bit: 5 SUPC APB Protect Enable */ + uint32_t GCLK_:1; /*!< bit: 6 GCLK APB Protect Enable */ + uint32_t WDT_:1; /*!< bit: 7 WDT APB Protect Enable */ + uint32_t RTC_:1; /*!< bit: 8 RTC APB Protect Enable */ + uint32_t EIC_:1; /*!< bit: 9 EIC APB Protect Enable */ + uint32_t PORT_:1; /*!< bit: 10 PORT APB Protect Enable */ + uint32_t TAL_:1; /*!< bit: 11 TAL APB Protect Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */ +#define PAC_STATUSA_RESETVALUE 0x00003000ul /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */ + +#define PAC_STATUSA_PM_Pos 0 /**< \brief (PAC_STATUSA) PM APB Protect Enable */ +#define PAC_STATUSA_PM (0x1ul << PAC_STATUSA_PM_Pos) +#define PAC_STATUSA_MCLK_Pos 1 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */ +#define PAC_STATUSA_MCLK (0x1ul << PAC_STATUSA_MCLK_Pos) +#define PAC_STATUSA_RSTC_Pos 2 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */ +#define PAC_STATUSA_RSTC (0x1ul << PAC_STATUSA_RSTC_Pos) +#define PAC_STATUSA_OSCCTRL_Pos 3 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */ +#define PAC_STATUSA_OSCCTRL (0x1ul << PAC_STATUSA_OSCCTRL_Pos) +#define PAC_STATUSA_OSC32KCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */ +#define PAC_STATUSA_OSC32KCTRL (0x1ul << PAC_STATUSA_OSC32KCTRL_Pos) +#define PAC_STATUSA_SUPC_Pos 5 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */ +#define PAC_STATUSA_SUPC (0x1ul << PAC_STATUSA_SUPC_Pos) +#define PAC_STATUSA_GCLK_Pos 6 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */ +#define PAC_STATUSA_GCLK (0x1ul << PAC_STATUSA_GCLK_Pos) +#define PAC_STATUSA_WDT_Pos 7 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */ +#define PAC_STATUSA_WDT (0x1ul << PAC_STATUSA_WDT_Pos) +#define PAC_STATUSA_RTC_Pos 8 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */ +#define PAC_STATUSA_RTC (0x1ul << PAC_STATUSA_RTC_Pos) +#define PAC_STATUSA_EIC_Pos 9 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */ +#define PAC_STATUSA_EIC (0x1ul << PAC_STATUSA_EIC_Pos) +#define PAC_STATUSA_PORT_Pos 10 /**< \brief (PAC_STATUSA) PORT APB Protect Enable */ +#define PAC_STATUSA_PORT (0x1ul << PAC_STATUSA_PORT_Pos) +#define PAC_STATUSA_TAL_Pos 11 /**< \brief (PAC_STATUSA) TAL APB Protect Enable */ +#define PAC_STATUSA_TAL (0x1ul << PAC_STATUSA_TAL_Pos) +#define PAC_STATUSA_MASK 0x00000FFFul /**< \brief (PAC_STATUSA) MASK Register */ + +/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */ + uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */ + uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */ + uint32_t MTB_:1; /*!< bit: 3 MTB APB Protect Enable */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */ +#define PAC_STATUSB_RESETVALUE 0x00000002ul /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */ + +#define PAC_STATUSB_USB_Pos 0 /**< \brief (PAC_STATUSB) USB APB Protect Enable */ +#define PAC_STATUSB_USB (0x1ul << PAC_STATUSB_USB_Pos) +#define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */ +#define PAC_STATUSB_DSU (0x1ul << PAC_STATUSB_DSU_Pos) +#define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */ +#define PAC_STATUSB_NVMCTRL (0x1ul << PAC_STATUSB_NVMCTRL_Pos) +#define PAC_STATUSB_MTB_Pos 3 /**< \brief (PAC_STATUSB) MTB APB Protect Enable */ +#define PAC_STATUSB_MTB (0x1ul << PAC_STATUSB_MTB_Pos) +#define PAC_STATUSB_MASK 0x0000000Ful /**< \brief (PAC_STATUSB) MASK Register */ + +/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SERCOM0_:1; /*!< bit: 0 SERCOM0 APB Protect Enable */ + uint32_t SERCOM1_:1; /*!< bit: 1 SERCOM1 APB Protect Enable */ + uint32_t SERCOM2_:1; /*!< bit: 2 SERCOM2 APB Protect Enable */ + uint32_t SERCOM3_:1; /*!< bit: 3 SERCOM3 APB Protect Enable */ + uint32_t SERCOM4_:1; /*!< bit: 4 SERCOM4 APB Protect Enable */ + uint32_t TCC0_:1; /*!< bit: 5 TCC0 APB Protect Enable */ + uint32_t TCC1_:1; /*!< bit: 6 TCC1 APB Protect Enable */ + uint32_t TCC2_:1; /*!< bit: 7 TCC2 APB Protect Enable */ + uint32_t TC0_:1; /*!< bit: 8 TC0 APB Protect Enable */ + uint32_t TC1_:1; /*!< bit: 9 TC1 APB Protect Enable */ + uint32_t TC2_:1; /*!< bit: 10 TC2 APB Protect Enable */ + uint32_t TC3_:1; /*!< bit: 11 TC3 APB Protect Enable */ + uint32_t DAC_:1; /*!< bit: 12 DAC APB Protect Enable */ + uint32_t AES_:1; /*!< bit: 13 AES APB Protect Enable */ + uint32_t TRNG_:1; /*!< bit: 14 TRNG APB Protect Enable */ + uint32_t :17; /*!< bit: 15..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_STATUSC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */ +#define PAC_STATUSC_RESETVALUE 0x00000000ul /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */ + +#define PAC_STATUSC_SERCOM0_Pos 0 /**< \brief (PAC_STATUSC) SERCOM0 APB Protect Enable */ +#define PAC_STATUSC_SERCOM0 (0x1ul << PAC_STATUSC_SERCOM0_Pos) +#define PAC_STATUSC_SERCOM1_Pos 1 /**< \brief (PAC_STATUSC) SERCOM1 APB Protect Enable */ +#define PAC_STATUSC_SERCOM1 (0x1ul << PAC_STATUSC_SERCOM1_Pos) +#define PAC_STATUSC_SERCOM2_Pos 2 /**< \brief (PAC_STATUSC) SERCOM2 APB Protect Enable */ +#define PAC_STATUSC_SERCOM2 (0x1ul << PAC_STATUSC_SERCOM2_Pos) +#define PAC_STATUSC_SERCOM3_Pos 3 /**< \brief (PAC_STATUSC) SERCOM3 APB Protect Enable */ +#define PAC_STATUSC_SERCOM3 (0x1ul << PAC_STATUSC_SERCOM3_Pos) +#define PAC_STATUSC_SERCOM4_Pos 4 /**< \brief (PAC_STATUSC) SERCOM4 APB Protect Enable */ +#define PAC_STATUSC_SERCOM4 (0x1ul << PAC_STATUSC_SERCOM4_Pos) +#define PAC_STATUSC_TCC0_Pos 5 /**< \brief (PAC_STATUSC) TCC0 APB Protect Enable */ +#define PAC_STATUSC_TCC0 (0x1ul << PAC_STATUSC_TCC0_Pos) +#define PAC_STATUSC_TCC1_Pos 6 /**< \brief (PAC_STATUSC) TCC1 APB Protect Enable */ +#define PAC_STATUSC_TCC1 (0x1ul << PAC_STATUSC_TCC1_Pos) +#define PAC_STATUSC_TCC2_Pos 7 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */ +#define PAC_STATUSC_TCC2 (0x1ul << PAC_STATUSC_TCC2_Pos) +#define PAC_STATUSC_TC0_Pos 8 /**< \brief (PAC_STATUSC) TC0 APB Protect Enable */ +#define PAC_STATUSC_TC0 (0x1ul << PAC_STATUSC_TC0_Pos) +#define PAC_STATUSC_TC1_Pos 9 /**< \brief (PAC_STATUSC) TC1 APB Protect Enable */ +#define PAC_STATUSC_TC1 (0x1ul << PAC_STATUSC_TC1_Pos) +#define PAC_STATUSC_TC2_Pos 10 /**< \brief (PAC_STATUSC) TC2 APB Protect Enable */ +#define PAC_STATUSC_TC2 (0x1ul << PAC_STATUSC_TC2_Pos) +#define PAC_STATUSC_TC3_Pos 11 /**< \brief (PAC_STATUSC) TC3 APB Protect Enable */ +#define PAC_STATUSC_TC3 (0x1ul << PAC_STATUSC_TC3_Pos) +#define PAC_STATUSC_DAC_Pos 12 /**< \brief (PAC_STATUSC) DAC APB Protect Enable */ +#define PAC_STATUSC_DAC (0x1ul << PAC_STATUSC_DAC_Pos) +#define PAC_STATUSC_AES_Pos 13 /**< \brief (PAC_STATUSC) AES APB Protect Enable */ +#define PAC_STATUSC_AES (0x1ul << PAC_STATUSC_AES_Pos) +#define PAC_STATUSC_TRNG_Pos 14 /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */ +#define PAC_STATUSC_TRNG (0x1ul << PAC_STATUSC_TRNG_Pos) +#define PAC_STATUSC_MASK 0x00007FFFul /**< \brief (PAC_STATUSC) MASK Register */ + +/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Protect Enable */ + uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */ + uint32_t TC4_:1; /*!< bit: 2 TC4 APB Protect Enable */ + uint32_t ADC_:1; /*!< bit: 3 ADC APB Protect Enable */ + uint32_t AC_:1; /*!< bit: 4 AC APB Protect Enable */ + uint32_t PTC_:1; /*!< bit: 5 PTC APB Protect Enable */ + uint32_t OPAMP_:1; /*!< bit: 6 OPAMP APB Protect Enable */ + uint32_t CCL_:1; /*!< bit: 7 CCL APB Protect Enable */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_STATUSD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_STATUSD_OFFSET 0x40 /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */ +#define PAC_STATUSD_RESETVALUE 0x00000000ul /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */ + +#define PAC_STATUSD_EVSYS_Pos 0 /**< \brief (PAC_STATUSD) EVSYS APB Protect Enable */ +#define PAC_STATUSD_EVSYS (0x1ul << PAC_STATUSD_EVSYS_Pos) +#define PAC_STATUSD_SERCOM5_Pos 1 /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */ +#define PAC_STATUSD_SERCOM5 (0x1ul << PAC_STATUSD_SERCOM5_Pos) +#define PAC_STATUSD_TC4_Pos 2 /**< \brief (PAC_STATUSD) TC4 APB Protect Enable */ +#define PAC_STATUSD_TC4 (0x1ul << PAC_STATUSD_TC4_Pos) +#define PAC_STATUSD_ADC_Pos 3 /**< \brief (PAC_STATUSD) ADC APB Protect Enable */ +#define PAC_STATUSD_ADC (0x1ul << PAC_STATUSD_ADC_Pos) +#define PAC_STATUSD_AC_Pos 4 /**< \brief (PAC_STATUSD) AC APB Protect Enable */ +#define PAC_STATUSD_AC (0x1ul << PAC_STATUSD_AC_Pos) +#define PAC_STATUSD_PTC_Pos 5 /**< \brief (PAC_STATUSD) PTC APB Protect Enable */ +#define PAC_STATUSD_PTC (0x1ul << PAC_STATUSD_PTC_Pos) +#define PAC_STATUSD_OPAMP_Pos 6 /**< \brief (PAC_STATUSD) OPAMP APB Protect Enable */ +#define PAC_STATUSD_OPAMP (0x1ul << PAC_STATUSD_OPAMP_Pos) +#define PAC_STATUSD_CCL_Pos 7 /**< \brief (PAC_STATUSD) CCL APB Protect Enable */ +#define PAC_STATUSD_CCL (0x1ul << PAC_STATUSD_CCL_Pos) +#define PAC_STATUSD_MASK 0x000000FFul /**< \brief (PAC_STATUSD) MASK Register */ + +/* -------- PAC_STATUSE : (PAC Offset: 0x44) (R/ 32) Peripheral write protection status - Bridge E -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */ + uint32_t DMAC_:1; /*!< bit: 1 DMAC APB Protect Enable */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PAC_STATUSE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PAC_STATUSE_OFFSET 0x44 /**< \brief (PAC_STATUSE offset) Peripheral write protection status - Bridge E */ +#define PAC_STATUSE_RESETVALUE 0x00000000ul /**< \brief (PAC_STATUSE reset_value) Peripheral write protection status - Bridge E */ + +#define PAC_STATUSE_PAC_Pos 0 /**< \brief (PAC_STATUSE) PAC APB Protect Enable */ +#define PAC_STATUSE_PAC (0x1ul << PAC_STATUSE_PAC_Pos) +#define PAC_STATUSE_DMAC_Pos 1 /**< \brief (PAC_STATUSE) DMAC APB Protect Enable */ +#define PAC_STATUSE_DMAC (0x1ul << PAC_STATUSE_DMAC_Pos) +#define PAC_STATUSE_MASK 0x00000003ul /**< \brief (PAC_STATUSE) MASK Register */ + +/** \brief PAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */ + __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */ + RoReg8 Reserved1[0x3]; + __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */ + __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */ + RoReg8 Reserved2[0x6]; + __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */ + __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */ + __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */ + __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */ + __IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */ + __IO PAC_INTFLAGE_Type INTFLAGE; /**< \brief Offset: 0x24 (R/W 32) Peripheral interrupt flag status - Bridge E */ + RoReg8 Reserved3[0xC]; + __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */ + __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */ + __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */ + __I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */ + __I PAC_STATUSE_Type STATUSE; /**< \brief Offset: 0x44 (R/ 32) Peripheral write protection status - Bridge E */ +} Pac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_PAC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pm.h new file mode 100644 index 0000000000..52de099441 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_pm.h @@ -0,0 +1,289 @@ +/** + * \file + * + * \brief Component description for PM + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_PM_COMPONENT_ +#define _SAML21_PM_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR PM */ +/* ========================================================================== */ +/** \addtogroup SAML21_PM Power Manager */ +/*@{*/ + +#define PM_U2240 +#define REV_PM 0x101 + +/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t IORET:1; /*!< bit: 2 I/O Retention */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PM_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */ +#define PM_CTRLA_RESETVALUE 0x00ul /**< \brief (PM_CTRLA reset_value) Control A */ + +#define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */ +#define PM_CTRLA_IORET (0x1ul << PM_CTRLA_IORET_Pos) +#define PM_CTRLA_MASK 0x04ul /**< \brief (PM_CTRLA) MASK Register */ + +/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PM_SLEEPCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */ +#define PM_SLEEPCFG_RESETVALUE 0x02ul /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */ + +#define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */ +#define PM_SLEEPCFG_SLEEPMODE_Msk (0x7ul << PM_SLEEPCFG_SLEEPMODE_Pos) +#define PM_SLEEPCFG_SLEEPMODE(value) ((PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))) +#define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val 0x0ul /**< \brief (PM_SLEEPCFG) CPU clock is OFF */ +#define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val 0x1ul /**< \brief (PM_SLEEPCFG) AHB clock is OFF */ +#define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val 0x2ul /**< \brief (PM_SLEEPCFG) APB clock are OFF */ +#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val 0x4ul /**< \brief (PM_SLEEPCFG) All Clocks are OFF */ +#define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val 0x5ul /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */ +#define PM_SLEEPCFG_SLEEPMODE_OFF_Val 0x6ul /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */ +#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos) +#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos) +#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos) +#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos) +#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos) +#define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos) +#define PM_SLEEPCFG_MASK 0x07ul /**< \brief (PM_SLEEPCFG) MASK Register */ + +/* -------- PM_PLCFG : (PM Offset: 0x02) (R/W 8) Performance Level Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PLSEL:2; /*!< bit: 0.. 1 Performance Level Select */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PM_PLCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PM_PLCFG_OFFSET 0x02 /**< \brief (PM_PLCFG offset) Performance Level Configuration */ +#define PM_PLCFG_RESETVALUE 0x00ul /**< \brief (PM_PLCFG reset_value) Performance Level Configuration */ + +#define PM_PLCFG_PLSEL_Pos 0 /**< \brief (PM_PLCFG) Performance Level Select */ +#define PM_PLCFG_PLSEL_Msk (0x3ul << PM_PLCFG_PLSEL_Pos) +#define PM_PLCFG_PLSEL(value) ((PM_PLCFG_PLSEL_Msk & ((value) << PM_PLCFG_PLSEL_Pos))) +#define PM_PLCFG_PLSEL_PL0_Val 0x0ul /**< \brief (PM_PLCFG) Performance Level 0 */ +#define PM_PLCFG_PLSEL_PL1_Val 0x1ul /**< \brief (PM_PLCFG) Performance Level 1 */ +#define PM_PLCFG_PLSEL_PL2_Val 0x2ul /**< \brief (PM_PLCFG) Performance Level 2 */ +#define PM_PLCFG_PLSEL_PL0 (PM_PLCFG_PLSEL_PL0_Val << PM_PLCFG_PLSEL_Pos) +#define PM_PLCFG_PLSEL_PL1 (PM_PLCFG_PLSEL_PL1_Val << PM_PLCFG_PLSEL_Pos) +#define PM_PLCFG_PLSEL_PL2 (PM_PLCFG_PLSEL_PL2_Val << PM_PLCFG_PLSEL_Pos) +#define PM_PLCFG_MASK 0x03ul /**< \brief (PM_PLCFG) MASK Register */ + +/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PLRDY:1; /*!< bit: 0 Performance Level Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PM_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */ +#define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */ + +#define PM_INTENCLR_PLRDY_Pos 0 /**< \brief (PM_INTENCLR) Performance Level Interrupt Enable */ +#define PM_INTENCLR_PLRDY (0x1ul << PM_INTENCLR_PLRDY_Pos) +#define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */ + +/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PLRDY:1; /*!< bit: 0 Performance Level Ready interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PM_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */ +#define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */ + +#define PM_INTENSET_PLRDY_Pos 0 /**< \brief (PM_INTENSET) Performance Level Ready interrupt Enable */ +#define PM_INTENSET_PLRDY (0x1ul << PM_INTENSET_PLRDY_Pos) +#define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */ + +/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PLRDY:1; /*!< bit: 0 Performance Level Ready */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PM_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */ +#define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define PM_INTFLAG_PLRDY_Pos 0 /**< \brief (PM_INTFLAG) Performance Level Ready */ +#define PM_INTFLAG_PLRDY (0x1ul << PM_INTFLAG_PLRDY_Pos) +#define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */ + +/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 16) Standby Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PDCFG:2; /*!< bit: 0.. 1 Power Domain Configuration */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t DPGPD0:1; /*!< bit: 4 Dynamic Power Gating for PD0 */ + uint16_t DPGPD1:1; /*!< bit: 5 Dynamic Power Gating for PD1 */ + uint16_t :1; /*!< bit: 6 Reserved */ + uint16_t AVREGSD:1; /*!< bit: 7 Automatic VREG Switching Disable */ + uint16_t LINKPD:2; /*!< bit: 8.. 9 Linked Power Domain */ + uint16_t BBIASHS:2; /*!< bit: 10..11 Back Bias for HMCRAMCHS */ + uint16_t BBIASLP:2; /*!< bit: 12..13 Back Bias for HMCRAMCLP */ + uint16_t BBIASPP:2; /*!< bit: 14..15 Back Bias for PicoPram */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} PM_STDBYCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */ +#define PM_STDBYCFG_RESETVALUE 0x0000ul /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */ + +#define PM_STDBYCFG_PDCFG_Pos 0 /**< \brief (PM_STDBYCFG) Power Domain Configuration */ +#define PM_STDBYCFG_PDCFG_Msk (0x3ul << PM_STDBYCFG_PDCFG_Pos) +#define PM_STDBYCFG_PDCFG(value) ((PM_STDBYCFG_PDCFG_Msk & ((value) << PM_STDBYCFG_PDCFG_Pos))) +#define PM_STDBYCFG_PDCFG_DEFAULT_Val 0x0ul /**< \brief (PM_STDBYCFG) All power domains switching is handled by hardware. */ +#define PM_STDBYCFG_PDCFG_PD0_Val 0x1ul /**< \brief (PM_STDBYCFG) PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware. */ +#define PM_STDBYCFG_PDCFG_PD01_Val 0x2ul /**< \brief (PM_STDBYCFG) PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware. */ +#define PM_STDBYCFG_PDCFG_PD012_Val 0x3ul /**< \brief (PM_STDBYCFG) All power domains are forced ACTIVE. */ +#define PM_STDBYCFG_PDCFG_DEFAULT (PM_STDBYCFG_PDCFG_DEFAULT_Val << PM_STDBYCFG_PDCFG_Pos) +#define PM_STDBYCFG_PDCFG_PD0 (PM_STDBYCFG_PDCFG_PD0_Val << PM_STDBYCFG_PDCFG_Pos) +#define PM_STDBYCFG_PDCFG_PD01 (PM_STDBYCFG_PDCFG_PD01_Val << PM_STDBYCFG_PDCFG_Pos) +#define PM_STDBYCFG_PDCFG_PD012 (PM_STDBYCFG_PDCFG_PD012_Val << PM_STDBYCFG_PDCFG_Pos) +#define PM_STDBYCFG_DPGPD0_Pos 4 /**< \brief (PM_STDBYCFG) Dynamic Power Gating for PD0 */ +#define PM_STDBYCFG_DPGPD0 (0x1ul << PM_STDBYCFG_DPGPD0_Pos) +#define PM_STDBYCFG_DPGPD1_Pos 5 /**< \brief (PM_STDBYCFG) Dynamic Power Gating for PD1 */ +#define PM_STDBYCFG_DPGPD1 (0x1ul << PM_STDBYCFG_DPGPD1_Pos) +#define PM_STDBYCFG_AVREGSD_Pos 7 /**< \brief (PM_STDBYCFG) Automatic VREG Switching Disable */ +#define PM_STDBYCFG_AVREGSD (0x1ul << PM_STDBYCFG_AVREGSD_Pos) +#define PM_STDBYCFG_LINKPD_Pos 8 /**< \brief (PM_STDBYCFG) Linked Power Domain */ +#define PM_STDBYCFG_LINKPD_Msk (0x3ul << PM_STDBYCFG_LINKPD_Pos) +#define PM_STDBYCFG_LINKPD(value) ((PM_STDBYCFG_LINKPD_Msk & ((value) << PM_STDBYCFG_LINKPD_Pos))) +#define PM_STDBYCFG_LINKPD_DEFAULT_Val 0x0ul /**< \brief (PM_STDBYCFG) Power domains are not linked */ +#define PM_STDBYCFG_LINKPD_PD01_Val 0x1ul /**< \brief (PM_STDBYCFG) PD0 and PD1 power domains are linked */ +#define PM_STDBYCFG_LINKPD_PD12_Val 0x2ul /**< \brief (PM_STDBYCFG) PD1 and PD2 power domains are linked */ +#define PM_STDBYCFG_LINKPD_PD012_Val 0x3ul /**< \brief (PM_STDBYCFG) All power domains are linked */ +#define PM_STDBYCFG_LINKPD_DEFAULT (PM_STDBYCFG_LINKPD_DEFAULT_Val << PM_STDBYCFG_LINKPD_Pos) +#define PM_STDBYCFG_LINKPD_PD01 (PM_STDBYCFG_LINKPD_PD01_Val << PM_STDBYCFG_LINKPD_Pos) +#define PM_STDBYCFG_LINKPD_PD12 (PM_STDBYCFG_LINKPD_PD12_Val << PM_STDBYCFG_LINKPD_Pos) +#define PM_STDBYCFG_LINKPD_PD012 (PM_STDBYCFG_LINKPD_PD012_Val << PM_STDBYCFG_LINKPD_Pos) +#define PM_STDBYCFG_BBIASHS_Pos 10 /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCHS */ +#define PM_STDBYCFG_BBIASHS_Msk (0x3ul << PM_STDBYCFG_BBIASHS_Pos) +#define PM_STDBYCFG_BBIASHS(value) ((PM_STDBYCFG_BBIASHS_Msk & ((value) << PM_STDBYCFG_BBIASHS_Pos))) +#define PM_STDBYCFG_BBIASLP_Pos 12 /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCLP */ +#define PM_STDBYCFG_BBIASLP_Msk (0x3ul << PM_STDBYCFG_BBIASLP_Pos) +#define PM_STDBYCFG_BBIASLP(value) ((PM_STDBYCFG_BBIASLP_Msk & ((value) << PM_STDBYCFG_BBIASLP_Pos))) +#define PM_STDBYCFG_BBIASPP_Pos 14 /**< \brief (PM_STDBYCFG) Back Bias for PicoPram */ +#define PM_STDBYCFG_BBIASPP_Msk (0x3ul << PM_STDBYCFG_BBIASPP_Pos) +#define PM_STDBYCFG_BBIASPP(value) ((PM_STDBYCFG_BBIASPP_Msk & ((value) << PM_STDBYCFG_BBIASPP_Pos))) +#define PM_STDBYCFG_MASK 0xFFB3ul /**< \brief (PM_STDBYCFG) MASK Register */ + +/* -------- PM_PWSAKDLY : (PM Offset: 0x0C) (R/W 8) Power Switch Acknowledge Delay -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */ + uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PM_PWSAKDLY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PM_PWSAKDLY_OFFSET 0x0C /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */ +#define PM_PWSAKDLY_RESETVALUE 0x00ul /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */ + +#define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */ +#define PM_PWSAKDLY_DLYVAL_Msk (0x7Ful << PM_PWSAKDLY_DLYVAL_Pos) +#define PM_PWSAKDLY_DLYVAL(value) ((PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))) +#define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */ +#define PM_PWSAKDLY_IGNACK (0x1ul << PM_PWSAKDLY_IGNACK_Pos) +#define PM_PWSAKDLY_MASK 0xFFul /**< \brief (PM_PWSAKDLY) MASK Register */ + +/** \brief PM hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */ + __IO PM_PLCFG_Type PLCFG; /**< \brief Offset: 0x02 (R/W 8) Performance Level Configuration */ + RoReg8 Reserved1[0x1]; + __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved2[0x1]; + __IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 16) Standby Configuration */ + RoReg8 Reserved3[0x2]; + __IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x0C (R/W 8) Power Switch Acknowledge Delay */ +} Pm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_PM_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_port.h new file mode 100644 index 0000000000..73a8f8bd28 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_port.h @@ -0,0 +1,361 @@ +/** + * \file + * + * \brief Component description for PORT + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_PORT_COMPONENT_ +#define _SAML21_PORT_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR PORT */ +/* ========================================================================== */ +/** \addtogroup SAML21_PORT Port Module */ +/*@{*/ + +#define PORT_U2210 +#define REV_PORT 0x201 + +/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} PORT_DIR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */ +#define PORT_DIR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */ +#define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */ + +/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} PORT_DIRCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */ +#define PORT_DIRCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */ +#define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */ + +/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} PORT_DIRSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */ +#define PORT_DIRSET_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */ +#define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */ + +/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} PORT_DIRTGL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */ +#define PORT_DIRTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */ +#define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */ + +/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} PORT_OUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */ +#define PORT_OUT_RESETVALUE 0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */ +#define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */ + +/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} PORT_OUTCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */ +#define PORT_OUTCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */ +#define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */ + +/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} PORT_OUTSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */ +#define PORT_OUTSET_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */ +#define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */ + +/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} PORT_OUTTGL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */ +#define PORT_OUTTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */ +#define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */ + +/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} PORT_IN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */ +#define PORT_IN_RESETVALUE 0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */ +#define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */ + +/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PORT_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */ +#define PORT_CTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */ + +#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */ +#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos) +#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))) +#define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */ + +/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ + uint32_t PMUXEN:1; /*!< bit: 16 Select Peripheral Multiplexer */ + uint32_t INEN:1; /*!< bit: 17 Input Enable */ + uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ + uint32_t :3; /*!< bit: 19..21 Reserved */ + uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing Template */ + uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX Registers */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG Registers */ + uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PORT_WRCONFIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */ +#define PORT_WRCONFIG_RESETVALUE 0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */ + +#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */ +#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos) +#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))) +#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Select Peripheral Multiplexer */ +#define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos) +#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */ +#define PORT_WRCONFIG_INEN (0x1ul << PORT_WRCONFIG_INEN_Pos) +#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */ +#define PORT_WRCONFIG_PULLEN (0x1ul << PORT_WRCONFIG_PULLEN_Pos) +#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */ +#define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos) +#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing Template */ +#define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos) +#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))) +#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX Registers */ +#define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos) +#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG Registers */ +#define PORT_WRCONFIG_WRPINCFG (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos) +#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */ +#define PORT_WRCONFIG_HWSEL (0x1ul << PORT_WRCONFIG_HWSEL_Pos) +#define PORT_WRCONFIG_MASK 0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */ + +/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PID0:5; /*!< bit: 0.. 4 Port Event Pin Identifier 0 */ + uint32_t EVACT0:2; /*!< bit: 5.. 6 Port Event Action 0 */ + uint32_t PORTEI0:1; /*!< bit: 7 Port Event Enable Input 0 */ + uint32_t PID1:5; /*!< bit: 8..12 Port Event Pin Identifier 1 */ + uint32_t EVACT1:2; /*!< bit: 13..14 Port Event Action 1 */ + uint32_t PORTEI1:1; /*!< bit: 15 Port Event Enable Input 1 */ + uint32_t PID2:5; /*!< bit: 16..20 Port Event Pin Identifier 2 */ + uint32_t EVACT2:2; /*!< bit: 21..22 Port Event Action 2 */ + uint32_t PORTEI2:1; /*!< bit: 23 Port Event Enable Input 2 */ + uint32_t PID3:5; /*!< bit: 24..28 Port Event Pin Identifier 3 */ + uint32_t EVACT3:2; /*!< bit: 29..30 Port Event Action 3 */ + uint32_t PORTEI3:1; /*!< bit: 31 Port Event Enable Input 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} PORT_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */ +#define PORT_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_EVCTRL reset_value) Event Input Control */ + +#define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 0 */ +#define PORT_EVCTRL_PID0_Msk (0x1Ful << PORT_EVCTRL_PID0_Pos) +#define PORT_EVCTRL_PID0(value) ((PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))) +#define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) Port Event Action 0 */ +#define PORT_EVCTRL_EVACT0_Msk (0x3ul << PORT_EVCTRL_EVACT0_Pos) +#define PORT_EVCTRL_EVACT0(value) ((PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))) +#define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) Port Event Enable Input 0 */ +#define PORT_EVCTRL_PORTEI0 (0x1ul << PORT_EVCTRL_PORTEI0_Pos) +#define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 1 */ +#define PORT_EVCTRL_PID1_Msk (0x1Ful << PORT_EVCTRL_PID1_Pos) +#define PORT_EVCTRL_PID1(value) ((PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))) +#define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) Port Event Action 1 */ +#define PORT_EVCTRL_EVACT1_Msk (0x3ul << PORT_EVCTRL_EVACT1_Pos) +#define PORT_EVCTRL_EVACT1(value) ((PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))) +#define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) Port Event Enable Input 1 */ +#define PORT_EVCTRL_PORTEI1 (0x1ul << PORT_EVCTRL_PORTEI1_Pos) +#define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 2 */ +#define PORT_EVCTRL_PID2_Msk (0x1Ful << PORT_EVCTRL_PID2_Pos) +#define PORT_EVCTRL_PID2(value) ((PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))) +#define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) Port Event Action 2 */ +#define PORT_EVCTRL_EVACT2_Msk (0x3ul << PORT_EVCTRL_EVACT2_Pos) +#define PORT_EVCTRL_EVACT2(value) ((PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))) +#define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) Port Event Enable Input 2 */ +#define PORT_EVCTRL_PORTEI2 (0x1ul << PORT_EVCTRL_PORTEI2_Pos) +#define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 3 */ +#define PORT_EVCTRL_PID3_Msk (0x1Ful << PORT_EVCTRL_PID3_Pos) +#define PORT_EVCTRL_PID3(value) ((PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))) +#define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) Port Event Action 3 */ +#define PORT_EVCTRL_EVACT3_Msk (0x3ul << PORT_EVCTRL_EVACT3_Pos) +#define PORT_EVCTRL_EVACT3(value) ((PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))) +#define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) Port Event Enable Input 3 */ +#define PORT_EVCTRL_PORTEI3 (0x1ul << PORT_EVCTRL_PORTEI3_Pos) +#define PORT_EVCTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_EVCTRL) MASK Register */ + +/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */ + uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PORT_PMUX_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */ +#define PORT_PMUX_RESETVALUE 0x00ul /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */ + +#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */ +#define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos) +#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))) +#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */ +#define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos) +#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))) +#define PORT_PMUX_MASK 0xFFul /**< \brief (PORT_PMUX) MASK Register */ + +/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PMUXEN:1; /*!< bit: 0 Select Peripheral Multiplexer */ + uint8_t INEN:1; /*!< bit: 1 Input Enable */ + uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} PORT_PINCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */ +#define PORT_PINCFG_RESETVALUE 0x00ul /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */ + +#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Select Peripheral Multiplexer */ +#define PORT_PINCFG_PMUXEN (0x1ul << PORT_PINCFG_PMUXEN_Pos) +#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */ +#define PORT_PINCFG_INEN (0x1ul << PORT_PINCFG_INEN_Pos) +#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */ +#define PORT_PINCFG_PULLEN (0x1ul << PORT_PINCFG_PULLEN_Pos) +#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */ +#define PORT_PINCFG_DRVSTR (0x1ul << PORT_PINCFG_DRVSTR_Pos) +#define PORT_PINCFG_MASK 0x47ul /**< \brief (PORT_PINCFG) MASK Register */ + +/** \brief PortGroup hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ + __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ + __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ + __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ + __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ + __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ + __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ + __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ + __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ + __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ + __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ + __IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */ + __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ + __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ + RoReg8 Reserved1[0x20]; +} PortGroup; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief PORT hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ +} Port; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#define SECTION_PORT_IOBUS + +/*@}*/ + +#endif /* _SAML21_PORT_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rstc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rstc.h new file mode 100644 index 0000000000..b8affb96bf --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rstc.h @@ -0,0 +1,225 @@ +/** + * \file + * + * \brief Component description for RSTC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_RSTC_COMPONENT_ +#define _SAML21_RSTC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR RSTC */ +/* ========================================================================== */ +/** \addtogroup SAML21_RSTC Reset Controller */ +/*@{*/ + +#define RSTC_U2239 +#define REV_RSTC 0x110 + +/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t POR:1; /*!< bit: 0 Power On Reset */ + uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ + uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EXT:1; /*!< bit: 4 External Reset */ + uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ + uint8_t SYST:1; /*!< bit: 6 System Reset Request */ + uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} RSTC_RCAUSE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */ + +#define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */ +#define RSTC_RCAUSE_POR (0x1ul << RSTC_RCAUSE_POR_Pos) +#define RSTC_RCAUSE_BOD12_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out 12 Detector Reset */ +#define RSTC_RCAUSE_BOD12 (0x1ul << RSTC_RCAUSE_BOD12_Pos) +#define RSTC_RCAUSE_BOD33_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out 33 Detector Reset */ +#define RSTC_RCAUSE_BOD33 (0x1ul << RSTC_RCAUSE_BOD33_Pos) +#define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */ +#define RSTC_RCAUSE_EXT (0x1ul << RSTC_RCAUSE_EXT_Pos) +#define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */ +#define RSTC_RCAUSE_WDT (0x1ul << RSTC_RCAUSE_WDT_Pos) +#define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */ +#define RSTC_RCAUSE_SYST (0x1ul << RSTC_RCAUSE_SYST_Pos) +#define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */ +#define RSTC_RCAUSE_BACKUP (0x1ul << RSTC_RCAUSE_BACKUP_Pos) +#define RSTC_RCAUSE_MASK 0xF7ul /**< \brief (RSTC_RCAUSE) MASK Register */ + +/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EXTWAKE:1; /*!< bit: 0 External Wakeup */ + uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */ + uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} RSTC_BKUPEXIT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */ + +#define RSTC_BKUPEXIT_EXTWAKE_Pos 0 /**< \brief (RSTC_BKUPEXIT) External Wakeup */ +#define RSTC_BKUPEXIT_EXTWAKE (0x1ul << RSTC_BKUPEXIT_EXTWAKE_Pos) +#define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */ +#define RSTC_BKUPEXIT_RTC (0x1ul << RSTC_BKUPEXIT_RTC_Pos) +#define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */ +#define RSTC_BKUPEXIT_BBPS (0x1ul << RSTC_BKUPEXIT_BBPS_Pos) +#define RSTC_BKUPEXIT_MASK 0x07ul /**< \brief (RSTC_BKUPEXIT) MASK Register */ + +/* -------- RSTC_WKDBCONF : (RSTC Offset: 0x04) (R/W 8) Wakeup Debounce Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WKDBCNT:5; /*!< bit: 0.. 4 Wakeup Debounce Counter */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} RSTC_WKDBCONF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSTC_WKDBCONF_OFFSET 0x04 /**< \brief (RSTC_WKDBCONF offset) Wakeup Debounce Configuration */ +#define RSTC_WKDBCONF_RESETVALUE 0x00ul /**< \brief (RSTC_WKDBCONF reset_value) Wakeup Debounce Configuration */ + +#define RSTC_WKDBCONF_WKDBCNT_Pos 0 /**< \brief (RSTC_WKDBCONF) Wakeup Debounce Counter */ +#define RSTC_WKDBCONF_WKDBCNT_Msk (0x1Ful << RSTC_WKDBCONF_WKDBCNT_Pos) +#define RSTC_WKDBCONF_WKDBCNT(value) ((RSTC_WKDBCONF_WKDBCNT_Msk & ((value) << RSTC_WKDBCONF_WKDBCNT_Pos))) +#define RSTC_WKDBCONF_WKDBCNT_OFF_Val 0x0ul /**< \brief (RSTC_WKDBCONF) No debouncing.Input pin is low or high level sensitive depending on its WKPOLx bit. */ +#define RSTC_WKDBCONF_WKDBCNT_2K32_Val 0x1ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least two 32kHz clock period. */ +#define RSTC_WKDBCONF_WKDBCNT_3CK32_Val 0x2ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least three 32kHz clock period. */ +#define RSTC_WKDBCONF_WKDBCNT_32CK32_Val 0x3ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 32 32kHz clock period. */ +#define RSTC_WKDBCONF_WKDBCNT_512CK32_Val 0x4ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 512 32kHz clock period. */ +#define RSTC_WKDBCONF_WKDBCNT_4096CK32_Val 0x5ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 4096 32kHz clock period. */ +#define RSTC_WKDBCONF_WKDBCNT_32768CK32_Val 0x6ul /**< \brief (RSTC_WKDBCONF) Input pin shall be active for at least 32768 32kHz clock period. */ +#define RSTC_WKDBCONF_WKDBCNT_OFF (RSTC_WKDBCONF_WKDBCNT_OFF_Val << RSTC_WKDBCONF_WKDBCNT_Pos) +#define RSTC_WKDBCONF_WKDBCNT_2K32 (RSTC_WKDBCONF_WKDBCNT_2K32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) +#define RSTC_WKDBCONF_WKDBCNT_3CK32 (RSTC_WKDBCONF_WKDBCNT_3CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) +#define RSTC_WKDBCONF_WKDBCNT_32CK32 (RSTC_WKDBCONF_WKDBCNT_32CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) +#define RSTC_WKDBCONF_WKDBCNT_512CK32 (RSTC_WKDBCONF_WKDBCNT_512CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) +#define RSTC_WKDBCONF_WKDBCNT_4096CK32 (RSTC_WKDBCONF_WKDBCNT_4096CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) +#define RSTC_WKDBCONF_WKDBCNT_32768CK32 (RSTC_WKDBCONF_WKDBCNT_32768CK32_Val << RSTC_WKDBCONF_WKDBCNT_Pos) +#define RSTC_WKDBCONF_MASK 0x1Ful /**< \brief (RSTC_WKDBCONF) MASK Register */ + +/* -------- RSTC_WKPOL : (RSTC Offset: 0x08) (R/W 16) Wakeup Polarity -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WKPOL:8; /*!< bit: 0.. 7 Wakeup Polarity */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} RSTC_WKPOL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSTC_WKPOL_OFFSET 0x08 /**< \brief (RSTC_WKPOL offset) Wakeup Polarity */ +#define RSTC_WKPOL_RESETVALUE 0x0000ul /**< \brief (RSTC_WKPOL reset_value) Wakeup Polarity */ + +#define RSTC_WKPOL_WKPOL_Pos 0 /**< \brief (RSTC_WKPOL) Wakeup Polarity */ +#define RSTC_WKPOL_WKPOL_Msk (0xFFul << RSTC_WKPOL_WKPOL_Pos) +#define RSTC_WKPOL_WKPOL(value) ((RSTC_WKPOL_WKPOL_Msk & ((value) << RSTC_WKPOL_WKPOL_Pos))) +#define RSTC_WKPOL_MASK 0x00FFul /**< \brief (RSTC_WKPOL) MASK Register */ + +/* -------- RSTC_WKEN : (RSTC Offset: 0x0C) (R/W 16) Wakeup Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WKEN:8; /*!< bit: 0.. 7 Wakeup Enable */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} RSTC_WKEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSTC_WKEN_OFFSET 0x0C /**< \brief (RSTC_WKEN offset) Wakeup Enable */ +#define RSTC_WKEN_RESETVALUE 0x0000ul /**< \brief (RSTC_WKEN reset_value) Wakeup Enable */ + +#define RSTC_WKEN_WKEN_Pos 0 /**< \brief (RSTC_WKEN) Wakeup Enable */ +#define RSTC_WKEN_WKEN_Msk (0xFFul << RSTC_WKEN_WKEN_Pos) +#define RSTC_WKEN_WKEN(value) ((RSTC_WKEN_WKEN_Msk & ((value) << RSTC_WKEN_WKEN_Pos))) +#define RSTC_WKEN_MASK 0x00FFul /**< \brief (RSTC_WKEN) MASK Register */ + +/* -------- RSTC_WKCAUSE : (RSTC Offset: 0x10) (R/W 16) Wakeup Cause -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WKCAUSE:16; /*!< bit: 0..15 Wakeup Cause */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} RSTC_WKCAUSE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSTC_WKCAUSE_OFFSET 0x10 /**< \brief (RSTC_WKCAUSE offset) Wakeup Cause */ +#define RSTC_WKCAUSE_RESETVALUE 0x0000ul /**< \brief (RSTC_WKCAUSE reset_value) Wakeup Cause */ + +#define RSTC_WKCAUSE_WKCAUSE_Pos 0 /**< \brief (RSTC_WKCAUSE) Wakeup Cause */ +#define RSTC_WKCAUSE_WKCAUSE_Msk (0xFFFFul << RSTC_WKCAUSE_WKCAUSE_Pos) +#define RSTC_WKCAUSE_WKCAUSE(value) ((RSTC_WKCAUSE_WKCAUSE_Msk & ((value) << RSTC_WKCAUSE_WKCAUSE_Pos))) +#define RSTC_WKCAUSE_MASK 0xFFFFul /**< \brief (RSTC_WKCAUSE) MASK Register */ + +/** \brief RSTC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */ + RoReg8 Reserved1[0x1]; + __I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */ + RoReg8 Reserved2[0x1]; + __IO RSTC_WKDBCONF_Type WKDBCONF; /**< \brief Offset: 0x04 (R/W 8) Wakeup Debounce Configuration */ + RoReg8 Reserved3[0x3]; + __IO RSTC_WKPOL_Type WKPOL; /**< \brief Offset: 0x08 (R/W 16) Wakeup Polarity */ + RoReg8 Reserved4[0x2]; + __IO RSTC_WKEN_Type WKEN; /**< \brief Offset: 0x0C (R/W 16) Wakeup Enable */ + RoReg8 Reserved5[0x2]; + __IO RSTC_WKCAUSE_Type WKCAUSE; /**< \brief Offset: 0x10 (R/W 16) Wakeup Cause */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_RSTC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rtc.h new file mode 100644 index 0000000000..08008e2073 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_rtc.h @@ -0,0 +1,1423 @@ +/** + * \file + * + * \brief Component description for RTC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_RTC_COMPONENT_ +#define _SAML21_RTC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR RTC */ +/* ========================================================================== */ +/** \addtogroup SAML21_RTC Real-Time Counter */ +/*@{*/ + +#define RTC_U2250 +#define REV_RTC 0x110 + +/* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :3; /*!< bit: 4.. 6 Reserved */ + uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :3; /*!< bit: 12..14 Reserved */ + uint16_t SYNCDIS:1; /*!< bit: 15 Count Read Synchronization Disable */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE0_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE0_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRLA offset) MODE0 Control A */ +#define RTC_MODE0_CTRLA_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Control A */ + +#define RTC_MODE0_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRLA) Software Reset */ +#define RTC_MODE0_CTRLA_SWRST (0x1ul << RTC_MODE0_CTRLA_SWRST_Pos) +#define RTC_MODE0_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRLA) Enable */ +#define RTC_MODE0_CTRLA_ENABLE (0x1ul << RTC_MODE0_CTRLA_ENABLE_Pos) +#define RTC_MODE0_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRLA) Operating Mode */ +#define RTC_MODE0_CTRLA_MODE_Msk (0x3ul << RTC_MODE0_CTRLA_MODE_Pos) +#define RTC_MODE0_CTRLA_MODE(value) ((RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))) +#define RTC_MODE0_CTRLA_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */ +#define RTC_MODE0_CTRLA_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */ +#define RTC_MODE0_CTRLA_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */ +#define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos) +#define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos) +#define RTC_MODE0_CTRLA_MODE_CLOCK (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos) +#define RTC_MODE0_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRLA) Clear on Match */ +#define RTC_MODE0_CTRLA_MATCHCLR (0x1ul << RTC_MODE0_CTRLA_MATCHCLR_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRLA) Prescaler */ +#define RTC_MODE0_CTRLA_PRESCALER_Msk (0xFul << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER(value) ((RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))) +#define RTC_MODE0_CTRLA_PRESCALER_OFF_Val 0x0ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV1_Val 0x1ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV2_Val 0x2ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV4_Val 0x3ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV8_Val 0x4ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV16_Val 0x5ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV32_Val 0x6ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV64_Val 0x7ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV128_Val 0x8ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV256_Val 0x9ul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV512_Val 0xAul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ +#define RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val 0xBul /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ +#define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) +#define RTC_MODE0_CTRLA_SYNCDIS_Pos 15 /**< \brief (RTC_MODE0_CTRLA) Count Read Synchronization Disable */ +#define RTC_MODE0_CTRLA_SYNCDIS (0x1ul << RTC_MODE0_CTRLA_SYNCDIS_Pos) +#define RTC_MODE0_CTRLA_MASK 0x8F8Ful /**< \brief (RTC_MODE0_CTRLA) MASK Register */ + +/* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :3; /*!< bit: 12..14 Reserved */ + uint16_t SYNCDIS:1; /*!< bit: 15 Count Read Synchronization Disable */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE1_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE1_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRLA offset) MODE1 Control A */ +#define RTC_MODE1_CTRLA_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRLA reset_value) MODE1 Control A */ + +#define RTC_MODE1_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRLA) Software Reset */ +#define RTC_MODE1_CTRLA_SWRST (0x1ul << RTC_MODE1_CTRLA_SWRST_Pos) +#define RTC_MODE1_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRLA) Enable */ +#define RTC_MODE1_CTRLA_ENABLE (0x1ul << RTC_MODE1_CTRLA_ENABLE_Pos) +#define RTC_MODE1_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRLA) Operating Mode */ +#define RTC_MODE1_CTRLA_MODE_Msk (0x3ul << RTC_MODE1_CTRLA_MODE_Pos) +#define RTC_MODE1_CTRLA_MODE(value) ((RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))) +#define RTC_MODE1_CTRLA_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */ +#define RTC_MODE1_CTRLA_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */ +#define RTC_MODE1_CTRLA_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */ +#define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos) +#define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos) +#define RTC_MODE1_CTRLA_MODE_CLOCK (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRLA) Prescaler */ +#define RTC_MODE1_CTRLA_PRESCALER_Msk (0xFul << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER(value) ((RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))) +#define RTC_MODE1_CTRLA_PRESCALER_OFF_Val 0x0ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV1_Val 0x1ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV2_Val 0x2ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV4_Val 0x3ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV8_Val 0x4ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV16_Val 0x5ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV32_Val 0x6ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV64_Val 0x7ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV128_Val 0x8ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV256_Val 0x9ul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV512_Val 0xAul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ +#define RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val 0xBul /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ +#define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) +#define RTC_MODE1_CTRLA_SYNCDIS_Pos 15 /**< \brief (RTC_MODE1_CTRLA) Count Read Synchronization Disable */ +#define RTC_MODE1_CTRLA_SYNCDIS (0x1ul << RTC_MODE1_CTRLA_SYNCDIS_Pos) +#define RTC_MODE1_CTRLA_MASK 0x8F0Ful /**< \brief (RTC_MODE1_CTRLA) MASK Register */ + +/* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :2; /*!< bit: 4.. 5 Reserved */ + uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ + uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :3; /*!< bit: 12..14 Reserved */ + uint16_t SYNCDIS:1; /*!< bit: 15 Clock Read Synchronization Disable */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE2_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE2_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRLA offset) MODE2 Control A */ +#define RTC_MODE2_CTRLA_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRLA reset_value) MODE2 Control A */ + +#define RTC_MODE2_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRLA) Software Reset */ +#define RTC_MODE2_CTRLA_SWRST (0x1ul << RTC_MODE2_CTRLA_SWRST_Pos) +#define RTC_MODE2_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRLA) Enable */ +#define RTC_MODE2_CTRLA_ENABLE (0x1ul << RTC_MODE2_CTRLA_ENABLE_Pos) +#define RTC_MODE2_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRLA) Operating Mode */ +#define RTC_MODE2_CTRLA_MODE_Msk (0x3ul << RTC_MODE2_CTRLA_MODE_Pos) +#define RTC_MODE2_CTRLA_MODE(value) ((RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))) +#define RTC_MODE2_CTRLA_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */ +#define RTC_MODE2_CTRLA_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */ +#define RTC_MODE2_CTRLA_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */ +#define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos) +#define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos) +#define RTC_MODE2_CTRLA_MODE_CLOCK (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos) +#define RTC_MODE2_CTRLA_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRLA) Clock Representation */ +#define RTC_MODE2_CTRLA_CLKREP (0x1ul << RTC_MODE2_CTRLA_CLKREP_Pos) +#define RTC_MODE2_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRLA) Clear on Match */ +#define RTC_MODE2_CTRLA_MATCHCLR (0x1ul << RTC_MODE2_CTRLA_MATCHCLR_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRLA) Prescaler */ +#define RTC_MODE2_CTRLA_PRESCALER_Msk (0xFul << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER(value) ((RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))) +#define RTC_MODE2_CTRLA_PRESCALER_OFF_Val 0x0ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV1_Val 0x1ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV2_Val 0x2ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV4_Val 0x3ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV8_Val 0x4ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV16_Val 0x5ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV32_Val 0x6ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV64_Val 0x7ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV128_Val 0x8ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV256_Val 0x9ul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV512_Val 0xAul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ +#define RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val 0xBul /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ +#define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) +#define RTC_MODE2_CTRLA_SYNCDIS_Pos 15 /**< \brief (RTC_MODE2_CTRLA) Clock Read Synchronization Disable */ +#define RTC_MODE2_CTRLA_SYNCDIS (0x1ul << RTC_MODE2_CTRLA_SYNCDIS_Pos) +#define RTC_MODE2_CTRLA_MASK 0x8FCFul /**< \brief (RTC_MODE2_CTRLA) MASK Register */ + +/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ + uint32_t :6; /*!< bit: 9..14 Reserved */ + uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint32_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ + uint32_t :23; /*!< bit: 9..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE0_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */ +#define RTC_MODE0_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */ + +#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */ +#define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos) +#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */ +#define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos) +#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */ +#define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos) +#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */ +#define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos) +#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */ +#define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos) +#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */ +#define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos) +#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */ +#define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos) +#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */ +#define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos) +#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */ +#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos) +#define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))) +#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */ +#define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos) +#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */ +#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos) +#define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))) +#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */ +#define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos) +#define RTC_MODE0_EVCTRL_MASK 0x000081FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */ + +/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ + uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ + uint32_t :5; /*!< bit: 10..14 Reserved */ + uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint32_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ + uint32_t :22; /*!< bit: 10..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE1_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */ +#define RTC_MODE1_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */ + +#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */ +#define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos) +#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */ +#define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos) +#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */ +#define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos) +#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */ +#define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos) +#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */ +#define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos) +#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */ +#define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos) +#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */ +#define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos) +#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */ +#define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos) +#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */ +#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos) +#define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))) +#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */ +#define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos) +#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */ +#define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos) +#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */ +#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos) +#define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))) +#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */ +#define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos) +#define RTC_MODE1_EVCTRL_MASK 0x000083FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */ + +/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint32_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ + uint32_t :6; /*!< bit: 9..14 Reserved */ + uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint32_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ + uint32_t :23; /*!< bit: 9..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE2_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */ +#define RTC_MODE2_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */ + +#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */ +#define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos) +#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */ +#define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos) +#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */ +#define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos) +#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */ +#define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos) +#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */ +#define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos) +#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */ +#define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos) +#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */ +#define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos) +#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */ +#define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos) +#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */ +#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos) +#define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))) +#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */ +#define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos) +#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */ +#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos) +#define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))) +#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */ +#define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos) +#define RTC_MODE2_EVCTRL_MASK 0x000081FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */ + +/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ + uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ + uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ + uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ + uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ + uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ + uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ + uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ + uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ + uint16_t CMP:1; /*!< bit: 8 Compare x Interrupt Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE0_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE0_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */ +#define RTC_MODE0_INTENCLR_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */ + +#define RTC_MODE0_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable */ +#define RTC_MODE0_INTENCLR_PER0 (1 << RTC_MODE0_INTENCLR_PER0_Pos) +#define RTC_MODE0_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable */ +#define RTC_MODE0_INTENCLR_PER1 (1 << RTC_MODE0_INTENCLR_PER1_Pos) +#define RTC_MODE0_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable */ +#define RTC_MODE0_INTENCLR_PER2 (1 << RTC_MODE0_INTENCLR_PER2_Pos) +#define RTC_MODE0_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable */ +#define RTC_MODE0_INTENCLR_PER3 (1 << RTC_MODE0_INTENCLR_PER3_Pos) +#define RTC_MODE0_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable */ +#define RTC_MODE0_INTENCLR_PER4 (1 << RTC_MODE0_INTENCLR_PER4_Pos) +#define RTC_MODE0_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable */ +#define RTC_MODE0_INTENCLR_PER5 (1 << RTC_MODE0_INTENCLR_PER5_Pos) +#define RTC_MODE0_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable */ +#define RTC_MODE0_INTENCLR_PER6 (1 << RTC_MODE0_INTENCLR_PER6_Pos) +#define RTC_MODE0_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable */ +#define RTC_MODE0_INTENCLR_PER7 (1 << RTC_MODE0_INTENCLR_PER7_Pos) +#define RTC_MODE0_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable */ +#define RTC_MODE0_INTENCLR_PER_Msk (0xFFul << RTC_MODE0_INTENCLR_PER_Pos) +#define RTC_MODE0_INTENCLR_PER(value) ((RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))) +#define RTC_MODE0_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */ +#define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos) +#define RTC_MODE0_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */ +#define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos) +#define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))) +#define RTC_MODE0_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */ +#define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos) +#define RTC_MODE0_INTENCLR_MASK 0x81FFul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */ + +/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ + uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ + uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ + uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ + uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ + uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ + uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ + uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ + uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ + uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ + uint16_t :5; /*!< bit: 10..14 Reserved */ + uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ + uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE1_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE1_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */ +#define RTC_MODE1_INTENCLR_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */ + +#define RTC_MODE1_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_PER0 (1 << RTC_MODE1_INTENCLR_PER0_Pos) +#define RTC_MODE1_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_PER1 (1 << RTC_MODE1_INTENCLR_PER1_Pos) +#define RTC_MODE1_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_PER2 (1 << RTC_MODE1_INTENCLR_PER2_Pos) +#define RTC_MODE1_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_PER3 (1 << RTC_MODE1_INTENCLR_PER3_Pos) +#define RTC_MODE1_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_PER4 (1 << RTC_MODE1_INTENCLR_PER4_Pos) +#define RTC_MODE1_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_PER5 (1 << RTC_MODE1_INTENCLR_PER5_Pos) +#define RTC_MODE1_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_PER6 (1 << RTC_MODE1_INTENCLR_PER6_Pos) +#define RTC_MODE1_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_PER7 (1 << RTC_MODE1_INTENCLR_PER7_Pos) +#define RTC_MODE1_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable */ +#define RTC_MODE1_INTENCLR_PER_Msk (0xFFul << RTC_MODE1_INTENCLR_PER_Pos) +#define RTC_MODE1_INTENCLR_PER(value) ((RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))) +#define RTC_MODE1_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos) +#define RTC_MODE1_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */ +#define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos) +#define RTC_MODE1_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */ +#define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos) +#define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))) +#define RTC_MODE1_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */ +#define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos) +#define RTC_MODE1_INTENCLR_MASK 0x83FFul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */ + +/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ + uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ + uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ + uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ + uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ + uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ + uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ + uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ + uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ + uint16_t ALARM:1; /*!< bit: 8 Alarm x Interrupt Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE2_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE2_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */ +#define RTC_MODE2_INTENCLR_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */ + +#define RTC_MODE2_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable */ +#define RTC_MODE2_INTENCLR_PER0 (1 << RTC_MODE2_INTENCLR_PER0_Pos) +#define RTC_MODE2_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable */ +#define RTC_MODE2_INTENCLR_PER1 (1 << RTC_MODE2_INTENCLR_PER1_Pos) +#define RTC_MODE2_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable */ +#define RTC_MODE2_INTENCLR_PER2 (1 << RTC_MODE2_INTENCLR_PER2_Pos) +#define RTC_MODE2_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable */ +#define RTC_MODE2_INTENCLR_PER3 (1 << RTC_MODE2_INTENCLR_PER3_Pos) +#define RTC_MODE2_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable */ +#define RTC_MODE2_INTENCLR_PER4 (1 << RTC_MODE2_INTENCLR_PER4_Pos) +#define RTC_MODE2_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable */ +#define RTC_MODE2_INTENCLR_PER5 (1 << RTC_MODE2_INTENCLR_PER5_Pos) +#define RTC_MODE2_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable */ +#define RTC_MODE2_INTENCLR_PER6 (1 << RTC_MODE2_INTENCLR_PER6_Pos) +#define RTC_MODE2_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable */ +#define RTC_MODE2_INTENCLR_PER7 (1 << RTC_MODE2_INTENCLR_PER7_Pos) +#define RTC_MODE2_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable */ +#define RTC_MODE2_INTENCLR_PER_Msk (0xFFul << RTC_MODE2_INTENCLR_PER_Pos) +#define RTC_MODE2_INTENCLR_PER(value) ((RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))) +#define RTC_MODE2_INTENCLR_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */ +#define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos) +#define RTC_MODE2_INTENCLR_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */ +#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos) +#define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))) +#define RTC_MODE2_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */ +#define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos) +#define RTC_MODE2_INTENCLR_MASK 0x81FFul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */ + +/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ + uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ + uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ + uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ + uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ + uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ + uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ + uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ + uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ + uint16_t CMP:1; /*!< bit: 8 Compare x Interrupt Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE0_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE0_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */ +#define RTC_MODE0_INTENSET_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */ + +#define RTC_MODE0_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable */ +#define RTC_MODE0_INTENSET_PER0 (1 << RTC_MODE0_INTENSET_PER0_Pos) +#define RTC_MODE0_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable */ +#define RTC_MODE0_INTENSET_PER1 (1 << RTC_MODE0_INTENSET_PER1_Pos) +#define RTC_MODE0_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable */ +#define RTC_MODE0_INTENSET_PER2 (1 << RTC_MODE0_INTENSET_PER2_Pos) +#define RTC_MODE0_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable */ +#define RTC_MODE0_INTENSET_PER3 (1 << RTC_MODE0_INTENSET_PER3_Pos) +#define RTC_MODE0_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable */ +#define RTC_MODE0_INTENSET_PER4 (1 << RTC_MODE0_INTENSET_PER4_Pos) +#define RTC_MODE0_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable */ +#define RTC_MODE0_INTENSET_PER5 (1 << RTC_MODE0_INTENSET_PER5_Pos) +#define RTC_MODE0_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable */ +#define RTC_MODE0_INTENSET_PER6 (1 << RTC_MODE0_INTENSET_PER6_Pos) +#define RTC_MODE0_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable */ +#define RTC_MODE0_INTENSET_PER7 (1 << RTC_MODE0_INTENSET_PER7_Pos) +#define RTC_MODE0_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable */ +#define RTC_MODE0_INTENSET_PER_Msk (0xFFul << RTC_MODE0_INTENSET_PER_Pos) +#define RTC_MODE0_INTENSET_PER(value) ((RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))) +#define RTC_MODE0_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */ +#define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos) +#define RTC_MODE0_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */ +#define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos) +#define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))) +#define RTC_MODE0_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */ +#define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos) +#define RTC_MODE0_INTENSET_MASK 0x81FFul /**< \brief (RTC_MODE0_INTENSET) MASK Register */ + +/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ + uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ + uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ + uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ + uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ + uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ + uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ + uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ + uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ + uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ + uint16_t :5; /*!< bit: 10..14 Reserved */ + uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ + uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE1_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE1_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */ +#define RTC_MODE1_INTENSET_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */ + +#define RTC_MODE1_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable */ +#define RTC_MODE1_INTENSET_PER0 (1 << RTC_MODE1_INTENSET_PER0_Pos) +#define RTC_MODE1_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable */ +#define RTC_MODE1_INTENSET_PER1 (1 << RTC_MODE1_INTENSET_PER1_Pos) +#define RTC_MODE1_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable */ +#define RTC_MODE1_INTENSET_PER2 (1 << RTC_MODE1_INTENSET_PER2_Pos) +#define RTC_MODE1_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable */ +#define RTC_MODE1_INTENSET_PER3 (1 << RTC_MODE1_INTENSET_PER3_Pos) +#define RTC_MODE1_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable */ +#define RTC_MODE1_INTENSET_PER4 (1 << RTC_MODE1_INTENSET_PER4_Pos) +#define RTC_MODE1_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable */ +#define RTC_MODE1_INTENSET_PER5 (1 << RTC_MODE1_INTENSET_PER5_Pos) +#define RTC_MODE1_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable */ +#define RTC_MODE1_INTENSET_PER6 (1 << RTC_MODE1_INTENSET_PER6_Pos) +#define RTC_MODE1_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable */ +#define RTC_MODE1_INTENSET_PER7 (1 << RTC_MODE1_INTENSET_PER7_Pos) +#define RTC_MODE1_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable */ +#define RTC_MODE1_INTENSET_PER_Msk (0xFFul << RTC_MODE1_INTENSET_PER_Pos) +#define RTC_MODE1_INTENSET_PER(value) ((RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))) +#define RTC_MODE1_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */ +#define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos) +#define RTC_MODE1_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */ +#define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos) +#define RTC_MODE1_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */ +#define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos) +#define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))) +#define RTC_MODE1_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */ +#define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos) +#define RTC_MODE1_INTENSET_MASK 0x83FFul /**< \brief (RTC_MODE1_INTENSET) MASK Register */ + +/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Enable */ + uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Enable */ + uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Enable */ + uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Enable */ + uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Enable */ + uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Enable */ + uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Enable */ + uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Enable */ + uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Enable */ + uint16_t ALARM:1; /*!< bit: 8 Alarm x Interrupt Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE2_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE2_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */ +#define RTC_MODE2_INTENSET_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */ + +#define RTC_MODE2_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 0 Enable */ +#define RTC_MODE2_INTENSET_PER0 (1 << RTC_MODE2_INTENSET_PER0_Pos) +#define RTC_MODE2_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 1 Enable */ +#define RTC_MODE2_INTENSET_PER1 (1 << RTC_MODE2_INTENSET_PER1_Pos) +#define RTC_MODE2_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 2 Enable */ +#define RTC_MODE2_INTENSET_PER2 (1 << RTC_MODE2_INTENSET_PER2_Pos) +#define RTC_MODE2_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 3 Enable */ +#define RTC_MODE2_INTENSET_PER3 (1 << RTC_MODE2_INTENSET_PER3_Pos) +#define RTC_MODE2_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 4 Enable */ +#define RTC_MODE2_INTENSET_PER4 (1 << RTC_MODE2_INTENSET_PER4_Pos) +#define RTC_MODE2_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 5 Enable */ +#define RTC_MODE2_INTENSET_PER5 (1 << RTC_MODE2_INTENSET_PER5_Pos) +#define RTC_MODE2_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 6 Enable */ +#define RTC_MODE2_INTENSET_PER6 (1 << RTC_MODE2_INTENSET_PER6_Pos) +#define RTC_MODE2_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 7 Enable */ +#define RTC_MODE2_INTENSET_PER7 (1 << RTC_MODE2_INTENSET_PER7_Pos) +#define RTC_MODE2_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval x Enable */ +#define RTC_MODE2_INTENSET_PER_Msk (0xFFul << RTC_MODE2_INTENSET_PER_Pos) +#define RTC_MODE2_INTENSET_PER(value) ((RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))) +#define RTC_MODE2_INTENSET_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */ +#define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos) +#define RTC_MODE2_INTENSET_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */ +#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos) +#define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))) +#define RTC_MODE2_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */ +#define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos) +#define RTC_MODE2_INTENSET_MASK 0x81FFul /**< \brief (RTC_MODE2_INTENSET) MASK Register */ + +/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ + uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ + uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ + uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ + uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ + uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ + uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ + uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ + uint16_t CMP0:1; /*!< bit: 8 Compare 0 */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVF:1; /*!< bit: 15 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ + uint16_t CMP:1; /*!< bit: 8 Compare x */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE0_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE0_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */ +#define RTC_MODE0_INTFLAG_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */ + +#define RTC_MODE0_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 0 */ +#define RTC_MODE0_INTFLAG_PER0 (1 << RTC_MODE0_INTFLAG_PER0_Pos) +#define RTC_MODE0_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 1 */ +#define RTC_MODE0_INTFLAG_PER1 (1 << RTC_MODE0_INTFLAG_PER1_Pos) +#define RTC_MODE0_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 2 */ +#define RTC_MODE0_INTFLAG_PER2 (1 << RTC_MODE0_INTFLAG_PER2_Pos) +#define RTC_MODE0_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 3 */ +#define RTC_MODE0_INTFLAG_PER3 (1 << RTC_MODE0_INTFLAG_PER3_Pos) +#define RTC_MODE0_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 4 */ +#define RTC_MODE0_INTFLAG_PER4 (1 << RTC_MODE0_INTFLAG_PER4_Pos) +#define RTC_MODE0_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 5 */ +#define RTC_MODE0_INTFLAG_PER5 (1 << RTC_MODE0_INTFLAG_PER5_Pos) +#define RTC_MODE0_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 6 */ +#define RTC_MODE0_INTFLAG_PER6 (1 << RTC_MODE0_INTFLAG_PER6_Pos) +#define RTC_MODE0_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 7 */ +#define RTC_MODE0_INTFLAG_PER7 (1 << RTC_MODE0_INTFLAG_PER7_Pos) +#define RTC_MODE0_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval x */ +#define RTC_MODE0_INTFLAG_PER_Msk (0xFFul << RTC_MODE0_INTFLAG_PER_Pos) +#define RTC_MODE0_INTFLAG_PER(value) ((RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))) +#define RTC_MODE0_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */ +#define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos) +#define RTC_MODE0_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare x */ +#define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos) +#define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))) +#define RTC_MODE0_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE0_INTFLAG) Overflow */ +#define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos) +#define RTC_MODE0_INTFLAG_MASK 0x81FFul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */ + +/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ + uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ + uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ + uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ + uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ + uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ + uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ + uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ + uint16_t CMP0:1; /*!< bit: 8 Compare 0 */ + uint16_t CMP1:1; /*!< bit: 9 Compare 1 */ + uint16_t :5; /*!< bit: 10..14 Reserved */ + uint16_t OVF:1; /*!< bit: 15 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ + uint16_t CMP:2; /*!< bit: 8.. 9 Compare x */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE1_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE1_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */ +#define RTC_MODE1_INTFLAG_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */ + +#define RTC_MODE1_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 0 */ +#define RTC_MODE1_INTFLAG_PER0 (1 << RTC_MODE1_INTFLAG_PER0_Pos) +#define RTC_MODE1_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 1 */ +#define RTC_MODE1_INTFLAG_PER1 (1 << RTC_MODE1_INTFLAG_PER1_Pos) +#define RTC_MODE1_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 2 */ +#define RTC_MODE1_INTFLAG_PER2 (1 << RTC_MODE1_INTFLAG_PER2_Pos) +#define RTC_MODE1_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 3 */ +#define RTC_MODE1_INTFLAG_PER3 (1 << RTC_MODE1_INTFLAG_PER3_Pos) +#define RTC_MODE1_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 4 */ +#define RTC_MODE1_INTFLAG_PER4 (1 << RTC_MODE1_INTFLAG_PER4_Pos) +#define RTC_MODE1_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 5 */ +#define RTC_MODE1_INTFLAG_PER5 (1 << RTC_MODE1_INTFLAG_PER5_Pos) +#define RTC_MODE1_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 6 */ +#define RTC_MODE1_INTFLAG_PER6 (1 << RTC_MODE1_INTFLAG_PER6_Pos) +#define RTC_MODE1_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 7 */ +#define RTC_MODE1_INTFLAG_PER7 (1 << RTC_MODE1_INTFLAG_PER7_Pos) +#define RTC_MODE1_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval x */ +#define RTC_MODE1_INTFLAG_PER_Msk (0xFFul << RTC_MODE1_INTFLAG_PER_Pos) +#define RTC_MODE1_INTFLAG_PER(value) ((RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))) +#define RTC_MODE1_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */ +#define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos) +#define RTC_MODE1_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */ +#define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos) +#define RTC_MODE1_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare x */ +#define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos) +#define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))) +#define RTC_MODE1_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE1_INTFLAG) Overflow */ +#define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos) +#define RTC_MODE1_INTFLAG_MASK 0x83FFul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */ + +/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ + uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ + uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ + uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ + uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ + uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ + uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ + uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ + uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVF:1; /*!< bit: 15 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ + uint16_t ALARM:1; /*!< bit: 8 Alarm x */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE2_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE2_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */ +#define RTC_MODE2_INTFLAG_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */ + +#define RTC_MODE2_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 0 */ +#define RTC_MODE2_INTFLAG_PER0 (1 << RTC_MODE2_INTFLAG_PER0_Pos) +#define RTC_MODE2_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 1 */ +#define RTC_MODE2_INTFLAG_PER1 (1 << RTC_MODE2_INTFLAG_PER1_Pos) +#define RTC_MODE2_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 2 */ +#define RTC_MODE2_INTFLAG_PER2 (1 << RTC_MODE2_INTFLAG_PER2_Pos) +#define RTC_MODE2_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 3 */ +#define RTC_MODE2_INTFLAG_PER3 (1 << RTC_MODE2_INTFLAG_PER3_Pos) +#define RTC_MODE2_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 4 */ +#define RTC_MODE2_INTFLAG_PER4 (1 << RTC_MODE2_INTFLAG_PER4_Pos) +#define RTC_MODE2_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 5 */ +#define RTC_MODE2_INTFLAG_PER5 (1 << RTC_MODE2_INTFLAG_PER5_Pos) +#define RTC_MODE2_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 6 */ +#define RTC_MODE2_INTFLAG_PER6 (1 << RTC_MODE2_INTFLAG_PER6_Pos) +#define RTC_MODE2_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 7 */ +#define RTC_MODE2_INTFLAG_PER7 (1 << RTC_MODE2_INTFLAG_PER7_Pos) +#define RTC_MODE2_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval x */ +#define RTC_MODE2_INTFLAG_PER_Msk (0xFFul << RTC_MODE2_INTFLAG_PER_Pos) +#define RTC_MODE2_INTFLAG_PER(value) ((RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))) +#define RTC_MODE2_INTFLAG_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */ +#define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos) +#define RTC_MODE2_INTFLAG_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */ +#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos) +#define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))) +#define RTC_MODE2_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE2_INTFLAG) Overflow */ +#define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos) +#define RTC_MODE2_INTFLAG_MASK 0x81FFul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */ + +/* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} RTC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_DBGCTRL_OFFSET 0x0E /**< \brief (RTC_DBGCTRL offset) Debug Control */ +#define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */ + +#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */ +#define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos) +#define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */ + +/* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE0 MODE0 Synchronization Busy Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ + uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ + uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */ + uint32_t :1; /*!< bit: 4 Reserved */ + uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */ + uint32_t :9; /*!< bit: 6..14 Reserved */ + uint32_t SYNCDIS:1; /*!< bit: 15 Count Read Synchronization Disable Bit Busy */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COMP:1; /*!< bit: 5 COMP x Register Busy */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE0_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE0_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status */ +#define RTC_MODE0_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status */ + +#define RTC_MODE0_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE0_SYNCBUSY) Software Reset Busy */ +#define RTC_MODE0_SYNCBUSY_SWRST (0x1ul << RTC_MODE0_SYNCBUSY_SWRST_Pos) +#define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE0_SYNCBUSY) Enable Bit Busy */ +#define RTC_MODE0_SYNCBUSY_ENABLE (0x1ul << RTC_MODE0_SYNCBUSY_ENABLE_Pos) +#define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy */ +#define RTC_MODE0_SYNCBUSY_FREQCORR (0x1ul << RTC_MODE0_SYNCBUSY_FREQCORR_Pos) +#define RTC_MODE0_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE0_SYNCBUSY) COUNT Register Busy */ +#define RTC_MODE0_SYNCBUSY_COUNT (0x1ul << RTC_MODE0_SYNCBUSY_COUNT_Pos) +#define RTC_MODE0_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy */ +#define RTC_MODE0_SYNCBUSY_COMP0 (1 << RTC_MODE0_SYNCBUSY_COMP0_Pos) +#define RTC_MODE0_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP x Register Busy */ +#define RTC_MODE0_SYNCBUSY_COMP_Msk (0x1ul << RTC_MODE0_SYNCBUSY_COMP_Pos) +#define RTC_MODE0_SYNCBUSY_COMP(value) ((RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))) +#define RTC_MODE0_SYNCBUSY_SYNCDIS_Pos 15 /**< \brief (RTC_MODE0_SYNCBUSY) Count Read Synchronization Disable Bit Busy */ +#define RTC_MODE0_SYNCBUSY_SYNCDIS (0x1ul << RTC_MODE0_SYNCBUSY_SYNCDIS_Pos) +#define RTC_MODE0_SYNCBUSY_MASK 0x0000802Ful /**< \brief (RTC_MODE0_SYNCBUSY) MASK Register */ + +/* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE1 MODE1 Synchronization Busy Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ + uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ + uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */ + uint32_t PER:1; /*!< bit: 4 PER Register Busy */ + uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */ + uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */ + uint32_t :8; /*!< bit: 7..14 Reserved */ + uint32_t SYNCDIS:1; /*!< bit: 15 Count Read Synchronization Disable Bit Busy */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COMP:2; /*!< bit: 5.. 6 COMP x Register Busy */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE1_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE1_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status */ +#define RTC_MODE1_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status */ + +#define RTC_MODE1_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy */ +#define RTC_MODE1_SYNCBUSY_SWRST (0x1ul << RTC_MODE1_SYNCBUSY_SWRST_Pos) +#define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE1_SYNCBUSY) Enable Bit Busy */ +#define RTC_MODE1_SYNCBUSY_ENABLE (0x1ul << RTC_MODE1_SYNCBUSY_ENABLE_Pos) +#define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy */ +#define RTC_MODE1_SYNCBUSY_FREQCORR (0x1ul << RTC_MODE1_SYNCBUSY_FREQCORR_Pos) +#define RTC_MODE1_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE1_SYNCBUSY) COUNT Register Busy */ +#define RTC_MODE1_SYNCBUSY_COUNT (0x1ul << RTC_MODE1_SYNCBUSY_COUNT_Pos) +#define RTC_MODE1_SYNCBUSY_PER_Pos 4 /**< \brief (RTC_MODE1_SYNCBUSY) PER Register Busy */ +#define RTC_MODE1_SYNCBUSY_PER (0x1ul << RTC_MODE1_SYNCBUSY_PER_Pos) +#define RTC_MODE1_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy */ +#define RTC_MODE1_SYNCBUSY_COMP0 (1 << RTC_MODE1_SYNCBUSY_COMP0_Pos) +#define RTC_MODE1_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy */ +#define RTC_MODE1_SYNCBUSY_COMP1 (1 << RTC_MODE1_SYNCBUSY_COMP1_Pos) +#define RTC_MODE1_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP x Register Busy */ +#define RTC_MODE1_SYNCBUSY_COMP_Msk (0x3ul << RTC_MODE1_SYNCBUSY_COMP_Pos) +#define RTC_MODE1_SYNCBUSY_COMP(value) ((RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))) +#define RTC_MODE1_SYNCBUSY_SYNCDIS_Pos 15 /**< \brief (RTC_MODE1_SYNCBUSY) Count Read Synchronization Disable Bit Busy */ +#define RTC_MODE1_SYNCBUSY_SYNCDIS (0x1ul << RTC_MODE1_SYNCBUSY_SYNCDIS_Pos) +#define RTC_MODE1_SYNCBUSY_MASK 0x0000807Ful /**< \brief (RTC_MODE1_SYNCBUSY) MASK Register */ + +/* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE2 MODE2 Synchronization Busy Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ + uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ + uint32_t CLOCK:1; /*!< bit: 3 CLOCK Register Busy */ + uint32_t :1; /*!< bit: 4 Reserved */ + uint32_t ALARM0:1; /*!< bit: 5 ALARM 0 Register Busy */ + uint32_t :5; /*!< bit: 6..10 Reserved */ + uint32_t MASK0:1; /*!< bit: 11 MASK 0 Register Busy */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t SYNCDIS:1; /*!< bit: 15 Clock Read Synchronization Disable Bit Busy */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t ALARM:1; /*!< bit: 5 ALARM x Register Busy */ + uint32_t :5; /*!< bit: 6..10 Reserved */ + uint32_t MASK:1; /*!< bit: 11 MASK x Register Busy */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE2_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE2_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status */ +#define RTC_MODE2_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status */ + +#define RTC_MODE2_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy */ +#define RTC_MODE2_SYNCBUSY_SWRST (0x1ul << RTC_MODE2_SYNCBUSY_SWRST_Pos) +#define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE2_SYNCBUSY) Enable Bit Busy */ +#define RTC_MODE2_SYNCBUSY_ENABLE (0x1ul << RTC_MODE2_SYNCBUSY_ENABLE_Pos) +#define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy */ +#define RTC_MODE2_SYNCBUSY_FREQCORR (0x1ul << RTC_MODE2_SYNCBUSY_FREQCORR_Pos) +#define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3 /**< \brief (RTC_MODE2_SYNCBUSY) CLOCK Register Busy */ +#define RTC_MODE2_SYNCBUSY_CLOCK (0x1ul << RTC_MODE2_SYNCBUSY_CLOCK_Pos) +#define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy */ +#define RTC_MODE2_SYNCBUSY_ALARM0 (1 << RTC_MODE2_SYNCBUSY_ALARM0_Pos) +#define RTC_MODE2_SYNCBUSY_ALARM_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM x Register Busy */ +#define RTC_MODE2_SYNCBUSY_ALARM_Msk (0x1ul << RTC_MODE2_SYNCBUSY_ALARM_Pos) +#define RTC_MODE2_SYNCBUSY_ALARM(value) ((RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))) +#define RTC_MODE2_SYNCBUSY_MASK0_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy */ +#define RTC_MODE2_SYNCBUSY_MASK0 (1 << RTC_MODE2_SYNCBUSY_MASK0_Pos) +#define RTC_MODE2_SYNCBUSY_MASK_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK x Register Busy */ +#define RTC_MODE2_SYNCBUSY_MASK_Msk (0x1ul << RTC_MODE2_SYNCBUSY_MASK_Pos) +#define RTC_MODE2_SYNCBUSY_MASK(value) ((RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))) +#define RTC_MODE2_SYNCBUSY_SYNCDIS_Pos 15 /**< \brief (RTC_MODE2_SYNCBUSY) Clock Read Synchronization Disable Bit Busy */ +#define RTC_MODE2_SYNCBUSY_SYNCDIS (0x1ul << RTC_MODE2_SYNCBUSY_SYNCDIS_Pos) +#define RTC_MODE2_SYNCBUSY_MASK_ 0x0000882Ful /**< \brief (RTC_MODE2_SYNCBUSY) MASK Register */ + +/* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ + uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} RTC_FREQCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_FREQCORR_OFFSET 0x14 /**< \brief (RTC_FREQCORR offset) Frequency Correction */ +#define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */ + +#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */ +#define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos) +#define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))) +#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */ +#define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos) +#define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */ + +/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE0_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE0_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */ +#define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */ + +#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */ +#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos) +#define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))) +#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */ + +/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE1_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE1_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */ +#define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */ + +#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */ +#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos) +#define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))) +#define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */ + +/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ + uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ + uint32_t HOUR:5; /*!< bit: 12..16 Hour */ + uint32_t DAY:5; /*!< bit: 17..21 Day */ + uint32_t MONTH:4; /*!< bit: 22..25 Month */ + uint32_t YEAR:6; /*!< bit: 26..31 Year */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE2_CLOCK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE2_CLOCK_OFFSET 0x18 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */ +#define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */ + +#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */ +#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos) +#define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))) +#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */ +#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos) +#define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))) +#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */ +#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos) +#define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))) +#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */ +#define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos) +#define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))) +#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */ +#define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos) +#define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))) +#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */ +#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos) +#define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))) +#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */ + +/* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PER:16; /*!< bit: 0..15 Counter Period */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE1_PER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE1_PER_OFFSET 0x1C /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */ +#define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */ + +#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */ +#define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos) +#define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))) +#define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */ + +/* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE0_COMP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE0_COMP_OFFSET 0x20 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */ +#define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */ + +#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */ +#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos) +#define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))) +#define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */ + +/* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} RTC_MODE1_COMP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE1_COMP_OFFSET 0x20 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */ +#define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */ + +#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */ +#define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos) +#define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))) +#define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */ + +/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ + uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ + uint32_t HOUR:5; /*!< bit: 12..16 Hour */ + uint32_t DAY:5; /*!< bit: 17..21 Day */ + uint32_t MONTH:4; /*!< bit: 22..25 Month */ + uint32_t YEAR:6; /*!< bit: 26..31 Year */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} RTC_MODE2_ALARM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE2_ALARM_OFFSET 0x20 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */ +#define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */ + +#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */ +#define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos) +#define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))) +#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */ +#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos) +#define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))) +#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */ +#define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos) +#define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))) +#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */ +#define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos) +#define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))) +#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */ +#define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos) +#define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))) +#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */ +#define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos) +#define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))) +#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */ + +/* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} RTC_MODE2_MASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MODE2_MASK_OFFSET 0x24 /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */ +#define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */ + +#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */ +#define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos) +#define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))) +#define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */ +#define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */ +#define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */ +#define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */ +#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */ +#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */ +#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */ +#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) +#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) +#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) +#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) +#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) +#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) +#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) +#define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */ + +/* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} RTC_GP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_GP_OFFSET 0x40 /**< \brief (RTC_GP offset) General Purpose */ +#define RTC_GP_RESETVALUE 0x00000000ul /**< \brief (RTC_GP reset_value) General Purpose */ +#define RTC_GP_MASK 0xFFFFFFFFul /**< \brief (RTC_GP) MASK Register */ + +/** \brief RtcMode2Alarm hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ + __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ + RoReg8 Reserved1[0x3]; +} RtcMode2Alarm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief RTC_MODE0 hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* 32-bit Counter with Single 32-bit Compare */ + __IO RTC_MODE0_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */ + RoReg8 Reserved1[0x2]; + __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */ + __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */ + __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */ + __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __I RTC_MODE0_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE0 Synchronization Busy Status */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ + RoReg8 Reserved3[0x3]; + __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */ + RoReg8 Reserved4[0x4]; + __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */ + RoReg8 Reserved5[0x1C]; + __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ +} RtcMode0; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief RTC_MODE1 hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* 16-bit Counter with Two 16-bit Compares */ + __IO RTC_MODE1_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */ + RoReg8 Reserved1[0x2]; + __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */ + __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */ + __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */ + __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __I RTC_MODE1_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ + RoReg8 Reserved3[0x3]; + __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */ + RoReg8 Reserved4[0x2]; + __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */ + RoReg8 Reserved5[0x2]; + __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */ + RoReg8 Reserved6[0x1C]; + __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ +} RtcMode1; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief RTC_MODE2 hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* Clock/Calendar with Alarm */ + __IO RTC_MODE2_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */ + RoReg8 Reserved1[0x2]; + __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */ + __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */ + __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */ + __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __I RTC_MODE2_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE2 Synchronization Busy Status */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ + RoReg8 Reserved3[0x3]; + __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */ + RoReg8 Reserved4[0x4]; + RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [ALARM_NUM] */ + RoReg8 Reserved5[0x18]; + __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ +} RtcMode2; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ + RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ + RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_RTC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_sercom.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_sercom.h new file mode 100644 index 0000000000..07d03daf14 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_sercom.h @@ -0,0 +1,1463 @@ +/** + * \file + * + * \brief Component description for SERCOM + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_SERCOM_COMPONENT_ +#define _SAML21_SERCOM_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR SERCOM */ +/* ========================================================================== */ +/** \addtogroup SAML21_SERCOM Serial Communication Interface */ +/*@{*/ + +#define SERCOM_U2201 +#define REV_SERCOM 0x220 + +/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ +#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ + +#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ +#define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos) +#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ +#define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos) +#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ +#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos) +#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))) +#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ +#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) +#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ +#define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos) +#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ +#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) +#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))) +#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */ +#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) +#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */ +#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) +#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */ +#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos) +#define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))) +#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */ +#define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos) +#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */ +#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos) +#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))) +#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */ +#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) +#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ + +/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t :2; /*!< bit: 28..29 Reserved */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ +#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ + +#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ +#define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos) +#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ +#define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos) +#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ +#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos) +#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))) +#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */ +#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) +#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ +#define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos) +#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ +#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) +#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))) +#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */ +#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) +#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */ +#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos) +#define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))) +#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */ +#define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos) +#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */ +#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) +#define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ + +/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :7; /*!< bit: 9..15 Reserved */ + uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ +#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ + +#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ +#define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos) +#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ +#define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos) +#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ +#define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos) +#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))) +#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */ +#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) +#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ +#define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos) +#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ +#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos) +#define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))) +#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ +#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos) +#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))) +#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ +#define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos) +#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))) +#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ +#define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos) +#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ +#define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos) +#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ +#define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos) +#define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ + +/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :4; /*!< bit: 9..12 Reserved */ + uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ + uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ + uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_USART_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ +#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ + +#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ +#define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos) +#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ +#define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos) +#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ +#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos) +#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))) +#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */ +#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos) +#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ +#define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos) +#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */ +#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos) +#define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))) +#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ +#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos) +#define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))) +#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ +#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos) +#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))) +#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */ +#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos) +#define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))) +#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ +#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos) +#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))) +#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ +#define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos) +#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ +#define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos) +#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ +#define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos) +#define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */ + +/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ +#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ + +#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ +#define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos) +#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ +#define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos) +#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ +#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos) +#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))) +#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ +#define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos) +#define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ + +/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ + uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ + uint32_t :3; /*!< bit: 11..13 Reserved */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ +#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ + +#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ +#define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos) +#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */ +#define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos) +#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */ +#define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos) +#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ +#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos) +#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))) +#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ +#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos) +#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))) +#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ +#define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos) +#define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ + +/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ + uint32_t :2; /*!< bit: 7.. 8 Reserved */ + uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ + uint32_t :3; /*!< bit: 10..12 Reserved */ + uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ +#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ + +#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ +#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos) +#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))) +#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */ +#define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos) +#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */ +#define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos) +#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */ +#define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos) +#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ +#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos) +#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))) +#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ +#define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos) +#define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ + +/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ + uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ + uint32_t ENC:1; /*!< bit: 10 Encoding Format */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_USART_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ +#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ + +#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ +#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos) +#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))) +#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ +#define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos) +#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */ +#define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos) +#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ +#define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos) +#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */ +#define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos) +#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ +#define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos) +#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ +#define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos) +#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ +#define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos) +#define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */ + +/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ + uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ + uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_BAUD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ +#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ + +#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */ +#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos) +#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))) +#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */ +#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos) +#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))) +#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */ +#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos) +#define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))) +#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */ +#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos) +#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))) +#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ + +/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_BAUD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ +#define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ + +#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */ +#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos) +#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))) +#define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */ + +/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + struct { // FRAC mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRAC; /*!< Structure used for FRAC */ + struct { // FRACFP mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRACFP; /*!< Structure used for FRACFP */ + struct { // USARTFP mode + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } USARTFP; /*!< Structure used for USARTFP */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_USART_BAUD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */ +#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */ + +#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */ +#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos) +#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))) +#define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */ + +// FRAC mode +#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */ +#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos) +#define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))) +#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */ +#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos) +#define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))) +#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */ + +// FRACFP mode +#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */ +#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) +#define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))) +#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */ +#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos) +#define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))) +#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */ + +// USARTFP mode +#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */ +#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) +#define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))) +#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */ + +/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_RXPL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */ +#define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */ + +#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */ +#define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos) +#define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))) +#define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */ + +/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ +#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ + +#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */ +#define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos) +#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */ +#define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos) +#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */ +#define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos) +#define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ + +/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ +#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ + +#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */ +#define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos) +#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */ +#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos) +#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */ +#define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos) +#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */ +#define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos) +#define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ + +/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ +#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ + +#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos) +#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos) +#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos) +#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos) +#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos) +#define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ + +/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ +#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ + +#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */ +#define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos) +#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */ +#define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos) +#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */ +#define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos) +#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ +#define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos) +#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */ +#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos) +#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */ +#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos) +#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */ +#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos) +#define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ + +/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ +#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ + +#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */ +#define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos) +#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */ +#define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos) +#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */ +#define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos) +#define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ + +/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ +#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ + +#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ +#define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos) +#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ +#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos) +#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */ +#define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos) +#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */ +#define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos) +#define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ + +/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ +#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ + +#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ +#define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos) +#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ +#define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos) +#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ +#define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos) +#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */ +#define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos) +#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */ +#define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos) +#define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ + +/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ +#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ + +#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ +#define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos) +#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ +#define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos) +#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ +#define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos) +#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ +#define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos) +#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */ +#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos) +#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */ +#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos) +#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */ +#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos) +#define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */ + +/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ +#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ + +#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */ +#define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos) +#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */ +#define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos) +#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */ +#define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos) +#define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ + +/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ +#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ + +#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */ +#define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos) +#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */ +#define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos) +#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */ +#define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos) +#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */ +#define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos) +#define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ + +/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ +#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ + +#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */ +#define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos) +#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */ +#define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos) +#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */ +#define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos) +#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */ +#define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos) +#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */ +#define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos) +#define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ + +/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ +#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ + +#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */ +#define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos) +#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */ +#define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos) +#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */ +#define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos) +#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ +#define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos) +#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */ +#define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos) +#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */ +#define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos) +#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */ +#define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos) +#define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ + +/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t LENERR:1; /*!< bit: 10 Length Error */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ +#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ + +#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ +#define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos) +#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ +#define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos) +#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ +#define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos) +#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ +#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos) +#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))) +#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */ +#define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos) +#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ +#define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos) +#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */ +#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos) +#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */ +#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos) +#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */ +#define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos) +#define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ + +/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ + uint16_t SR:1; /*!< bit: 4 Repeated Start */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t :1; /*!< bit: 8 Reserved */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t HS:1; /*!< bit: 10 High Speed */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ +#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ + +#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ +#define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos) +#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ +#define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos) +#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ +#define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos) +#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */ +#define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos) +#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ +#define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos) +#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */ +#define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos) +#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ +#define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos) +#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */ +#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos) +#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */ +#define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos) +#define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ + +/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t :13; /*!< bit: 3..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_SPI_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ +#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ + +#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ +#define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos) +#define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */ + +/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PERR:1; /*!< bit: 0 Parity Error */ + uint16_t FERR:1; /*!< bit: 1 Frame Error */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t CTS:1; /*!< bit: 3 Clear To Send */ + uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ + uint16_t COLL:1; /*!< bit: 5 Collision Detected */ + uint16_t :10; /*!< bit: 6..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_USART_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */ +#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ + +#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ +#define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos) +#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ +#define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos) +#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ +#define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos) +#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */ +#define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos) +#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */ +#define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos) +#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */ +#define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos) +#define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */ + +/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */ +#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */ + +#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */ +#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos) +#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */ +#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos) +#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */ +#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos) +#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */ + +/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */ +#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */ + +#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */ +#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos) +#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */ +#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos) +#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */ + +/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */ +#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */ + +#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */ +#define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos) +#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */ +#define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos) +#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */ +#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos) +#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */ + +/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_USART_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */ +#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */ + +#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */ +#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos) +#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */ +#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos) +#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */ +#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos) +#define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */ + +/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t LENEN:1; /*!< bit: 13 Length Enable */ + uint32_t HS:1; /*!< bit: 14 High Speed Mode */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t LEN:8; /*!< bit: 16..23 Length */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ +#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ + +#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */ +#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos) +#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))) +#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */ +#define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos) +#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */ +#define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos) +#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */ +#define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos) +#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */ +#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos) +#define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))) +#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ + +/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ + uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ + uint32_t :4; /*!< bit: 11..14 Reserved */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ +#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ + +#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ +#define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos) +#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */ +#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos) +#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))) +#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */ +#define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos) +#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ +#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos) +#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))) +#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ + +/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ +#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ + +#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */ +#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos) +#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))) +#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ +#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos) +#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))) +#define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */ + +/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ +#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ + +#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */ +#define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos) +#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))) +#define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */ + +/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ +#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ + +#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */ +#define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos) +#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))) +#define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */ + +/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint32_t :23; /*!< bit: 9..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ +#define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ + +#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */ +#define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos) +#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))) +#define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */ + +/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_USART_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */ +#define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ + +#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */ +#define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos) +#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))) +#define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */ + +/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ +#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ + +#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */ +#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) +#define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ + +/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ +#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ + +#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */ +#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) +#define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ + +/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ +#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ + +#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */ +#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) +#define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ + +/** \brief SERCOM_I2CM hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* I2C Master Mode */ + __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ + __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ + RoReg8 Reserved2[0x4]; + __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ + __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ + __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ + RoReg8 Reserved7[0x7]; + __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ +} SercomI2cm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief SERCOM_I2CS hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* I2C Slave Mode */ + __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ + __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ + RoReg8 Reserved1[0xC]; + __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ + RoReg8 Reserved2[0x1]; + __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ + __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */ + RoReg8 Reserved5[0x4]; + __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ + __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ +} SercomI2cs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief SERCOM_SPI hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* SPI Mode */ + __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ + __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ + RoReg8 Reserved2[0x7]; + __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ + __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ + __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ + RoReg8 Reserved7[0x4]; + __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ +} SercomSpi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief SERCOM_USART hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USART Mode */ + __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ + __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ + __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ + RoReg8 Reserved2[0x5]; + __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ + __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */ + RoReg8 Reserved6[0x8]; + __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ + RoReg8 Reserved7[0x6]; + __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ +} SercomUsart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ + SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ + SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ + SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ +} Sercom; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_SERCOM_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_supc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_supc.h new file mode 100644 index 0000000000..f19e209e6c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_supc.h @@ -0,0 +1,614 @@ +/** + * \file + * + * \brief Component description for SUPC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_SUPC_COMPONENT_ +#define _SAML21_SUPC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR SUPC */ +/* ========================================================================== */ +/** \addtogroup SAML21_SUPC Supply Controller */ +/*@{*/ + +#define SUPC_U2117 +#define REV_SUPC 0x110 + +/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ + uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ + uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ + uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ + uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ + uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */ +#define SUPC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define SUPC_INTENCLR_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENCLR) BOD33 Ready */ +#define SUPC_INTENCLR_BOD33RDY (0x1ul << SUPC_INTENCLR_BOD33RDY_Pos) +#define SUPC_INTENCLR_BOD33DET_Pos 1 /**< \brief (SUPC_INTENCLR) BOD33 Detection */ +#define SUPC_INTENCLR_BOD33DET (0x1ul << SUPC_INTENCLR_BOD33DET_Pos) +#define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */ +#define SUPC_INTENCLR_B33SRDY (0x1ul << SUPC_INTENCLR_B33SRDY_Pos) +#define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */ +#define SUPC_INTENCLR_BOD12RDY (0x1ul << SUPC_INTENCLR_BOD12RDY_Pos) +#define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */ +#define SUPC_INTENCLR_BOD12DET (0x1ul << SUPC_INTENCLR_BOD12DET_Pos) +#define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */ +#define SUPC_INTENCLR_B12SRDY (0x1ul << SUPC_INTENCLR_B12SRDY_Pos) +#define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */ +#define SUPC_INTENCLR_VREGRDY (0x1ul << SUPC_INTENCLR_VREGRDY_Pos) +#define SUPC_INTENCLR_APWSRDY_Pos 9 /**< \brief (SUPC_INTENCLR) Automatic Power Switch Ready */ +#define SUPC_INTENCLR_APWSRDY (0x1ul << SUPC_INTENCLR_APWSRDY_Pos) +#define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */ +#define SUPC_INTENCLR_VCORERDY (0x1ul << SUPC_INTENCLR_VCORERDY_Pos) +#define SUPC_INTENCLR_MASK 0x0000073Ful /**< \brief (SUPC_INTENCLR) MASK Register */ + +/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ + uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ + uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ + uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ + uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ + uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */ +#define SUPC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */ + +#define SUPC_INTENSET_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENSET) BOD33 Ready */ +#define SUPC_INTENSET_BOD33RDY (0x1ul << SUPC_INTENSET_BOD33RDY_Pos) +#define SUPC_INTENSET_BOD33DET_Pos 1 /**< \brief (SUPC_INTENSET) BOD33 Detection */ +#define SUPC_INTENSET_BOD33DET (0x1ul << SUPC_INTENSET_BOD33DET_Pos) +#define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */ +#define SUPC_INTENSET_B33SRDY (0x1ul << SUPC_INTENSET_B33SRDY_Pos) +#define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */ +#define SUPC_INTENSET_BOD12RDY (0x1ul << SUPC_INTENSET_BOD12RDY_Pos) +#define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */ +#define SUPC_INTENSET_BOD12DET (0x1ul << SUPC_INTENSET_BOD12DET_Pos) +#define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */ +#define SUPC_INTENSET_B12SRDY (0x1ul << SUPC_INTENSET_B12SRDY_Pos) +#define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */ +#define SUPC_INTENSET_VREGRDY (0x1ul << SUPC_INTENSET_VREGRDY_Pos) +#define SUPC_INTENSET_APWSRDY_Pos 9 /**< \brief (SUPC_INTENSET) Automatic Power Switch Ready */ +#define SUPC_INTENSET_APWSRDY (0x1ul << SUPC_INTENSET_APWSRDY_Pos) +#define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */ +#define SUPC_INTENSET_VCORERDY (0x1ul << SUPC_INTENSET_VCORERDY_Pos) +#define SUPC_INTENSET_MASK 0x0000073Ful /**< \brief (SUPC_INTENSET) MASK Register */ + +/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ + uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ + uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ + uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ + uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ + uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define SUPC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define SUPC_INTFLAG_BOD33RDY_Pos 0 /**< \brief (SUPC_INTFLAG) BOD33 Ready */ +#define SUPC_INTFLAG_BOD33RDY (0x1ul << SUPC_INTFLAG_BOD33RDY_Pos) +#define SUPC_INTFLAG_BOD33DET_Pos 1 /**< \brief (SUPC_INTFLAG) BOD33 Detection */ +#define SUPC_INTFLAG_BOD33DET (0x1ul << SUPC_INTFLAG_BOD33DET_Pos) +#define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */ +#define SUPC_INTFLAG_B33SRDY (0x1ul << SUPC_INTFLAG_B33SRDY_Pos) +#define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */ +#define SUPC_INTFLAG_BOD12RDY (0x1ul << SUPC_INTFLAG_BOD12RDY_Pos) +#define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */ +#define SUPC_INTFLAG_BOD12DET (0x1ul << SUPC_INTFLAG_BOD12DET_Pos) +#define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */ +#define SUPC_INTFLAG_B12SRDY (0x1ul << SUPC_INTFLAG_B12SRDY_Pos) +#define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */ +#define SUPC_INTFLAG_VREGRDY (0x1ul << SUPC_INTFLAG_VREGRDY_Pos) +#define SUPC_INTFLAG_APWSRDY_Pos 9 /**< \brief (SUPC_INTFLAG) Automatic Power Switch Ready */ +#define SUPC_INTFLAG_APWSRDY (0x1ul << SUPC_INTFLAG_APWSRDY_Pos) +#define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */ +#define SUPC_INTFLAG_VCORERDY (0x1ul << SUPC_INTFLAG_VCORERDY_Pos) +#define SUPC_INTFLAG_MASK 0x0000073Ful /**< \brief (SUPC_INTFLAG) MASK Register */ + +/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ + uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ + uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ + uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ + uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ + uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ + uint32_t BBPS:1; /*!< bit: 11 Battery Backup Power Switch */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */ +#define SUPC_STATUS_RESETVALUE 0x00000000ul /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */ + +#define SUPC_STATUS_BOD33RDY_Pos 0 /**< \brief (SUPC_STATUS) BOD33 Ready */ +#define SUPC_STATUS_BOD33RDY (0x1ul << SUPC_STATUS_BOD33RDY_Pos) +#define SUPC_STATUS_BOD33DET_Pos 1 /**< \brief (SUPC_STATUS) BOD33 Detection */ +#define SUPC_STATUS_BOD33DET (0x1ul << SUPC_STATUS_BOD33DET_Pos) +#define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */ +#define SUPC_STATUS_B33SRDY (0x1ul << SUPC_STATUS_B33SRDY_Pos) +#define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */ +#define SUPC_STATUS_BOD12RDY (0x1ul << SUPC_STATUS_BOD12RDY_Pos) +#define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */ +#define SUPC_STATUS_BOD12DET (0x1ul << SUPC_STATUS_BOD12DET_Pos) +#define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */ +#define SUPC_STATUS_B12SRDY (0x1ul << SUPC_STATUS_B12SRDY_Pos) +#define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */ +#define SUPC_STATUS_VREGRDY (0x1ul << SUPC_STATUS_VREGRDY_Pos) +#define SUPC_STATUS_APWSRDY_Pos 9 /**< \brief (SUPC_STATUS) Automatic Power Switch Ready */ +#define SUPC_STATUS_APWSRDY (0x1ul << SUPC_STATUS_APWSRDY_Pos) +#define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */ +#define SUPC_STATUS_VCORERDY (0x1ul << SUPC_STATUS_VCORERDY_Pos) +#define SUPC_STATUS_BBPS_Pos 11 /**< \brief (SUPC_STATUS) Battery Backup Power Switch */ +#define SUPC_STATUS_BBPS (0x1ul << SUPC_STATUS_BBPS_Pos) +#define SUPC_STATUS_MASK 0x00000F3Ful /**< \brief (SUPC_STATUS) MASK Register */ + +/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ + uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ + uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint32_t RUNBKUP:1; /*!< bit: 7 Configuration in Backup mode */ + uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ + uint32_t :1; /*!< bit: 9 Reserved */ + uint32_t VMON:1; /*!< bit: 10 Voltage Monitored in active and standby mode */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ + uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level for VDD */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t BKUPLEVEL:6; /*!< bit: 24..29 Threshold Level in backup sleep mode or for VBAT */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_BOD33_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_BOD33_OFFSET 0x10 /**< \brief (SUPC_BOD33 offset) BOD33 Control */ +#define SUPC_BOD33_RESETVALUE 0x00000000ul /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */ + +#define SUPC_BOD33_ENABLE_Pos 1 /**< \brief (SUPC_BOD33) Enable */ +#define SUPC_BOD33_ENABLE (0x1ul << SUPC_BOD33_ENABLE_Pos) +#define SUPC_BOD33_HYST_Pos 2 /**< \brief (SUPC_BOD33) Hysteresis Enable */ +#define SUPC_BOD33_HYST (0x1ul << SUPC_BOD33_HYST_Pos) +#define SUPC_BOD33_ACTION_Pos 3 /**< \brief (SUPC_BOD33) Action when Threshold Crossed */ +#define SUPC_BOD33_ACTION_Msk (0x3ul << SUPC_BOD33_ACTION_Pos) +#define SUPC_BOD33_ACTION(value) ((SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))) +#define SUPC_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SUPC_BOD33) No action */ +#define SUPC_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SUPC_BOD33) The BOD33 generates a reset */ +#define SUPC_BOD33_ACTION_INT_Val 0x2ul /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */ +#define SUPC_BOD33_ACTION_BKUP_Val 0x3ul /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode if VMON=0 */ +#define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos) +#define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos) +#define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos) +#define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos) +#define SUPC_BOD33_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD33) Configuration in Standby mode */ +#define SUPC_BOD33_STDBYCFG (0x1ul << SUPC_BOD33_STDBYCFG_Pos) +#define SUPC_BOD33_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD33) Run during Standby */ +#define SUPC_BOD33_RUNSTDBY (0x1ul << SUPC_BOD33_RUNSTDBY_Pos) +#define SUPC_BOD33_RUNBKUP_Pos 7 /**< \brief (SUPC_BOD33) Configuration in Backup mode */ +#define SUPC_BOD33_RUNBKUP (0x1ul << SUPC_BOD33_RUNBKUP_Pos) +#define SUPC_BOD33_ACTCFG_Pos 8 /**< \brief (SUPC_BOD33) Configuration in Active mode */ +#define SUPC_BOD33_ACTCFG (0x1ul << SUPC_BOD33_ACTCFG_Pos) +#define SUPC_BOD33_VMON_Pos 10 /**< \brief (SUPC_BOD33) Voltage Monitored in active and standby mode */ +#define SUPC_BOD33_VMON (0x1ul << SUPC_BOD33_VMON_Pos) +#define SUPC_BOD33_PSEL_Pos 12 /**< \brief (SUPC_BOD33) Prescaler Select */ +#define SUPC_BOD33_PSEL_Msk (0xFul << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL(value) ((SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))) +#define SUPC_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SUPC_BOD33) Divide clock by 2 */ +#define SUPC_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SUPC_BOD33) Divide clock by 4 */ +#define SUPC_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SUPC_BOD33) Divide clock by 8 */ +#define SUPC_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SUPC_BOD33) Divide clock by 16 */ +#define SUPC_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SUPC_BOD33) Divide clock by 32 */ +#define SUPC_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SUPC_BOD33) Divide clock by 64 */ +#define SUPC_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SUPC_BOD33) Divide clock by 128 */ +#define SUPC_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SUPC_BOD33) Divide clock by 256 */ +#define SUPC_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SUPC_BOD33) Divide clock by 512 */ +#define SUPC_BOD33_PSEL_DIV1024_Val 0x9ul /**< \brief (SUPC_BOD33) Divide clock by 1024 */ +#define SUPC_BOD33_PSEL_DIV2048_Val 0xAul /**< \brief (SUPC_BOD33) Divide clock by 2048 */ +#define SUPC_BOD33_PSEL_DIV4096_Val 0xBul /**< \brief (SUPC_BOD33) Divide clock by 4096 */ +#define SUPC_BOD33_PSEL_DIV8192_Val 0xCul /**< \brief (SUPC_BOD33) Divide clock by 8192 */ +#define SUPC_BOD33_PSEL_DIV16384_Val 0xDul /**< \brief (SUPC_BOD33) Divide clock by 16384 */ +#define SUPC_BOD33_PSEL_DIV32768_Val 0xEul /**< \brief (SUPC_BOD33) Divide clock by 32768 */ +#define SUPC_BOD33_PSEL_DIV65536_Val 0xFul /**< \brief (SUPC_BOD33) Divide clock by 65536 */ +#define SUPC_BOD33_PSEL_DIV2 (SUPC_BOD33_PSEL_DIV2_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV512 (SUPC_BOD33_PSEL_DIV512_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV1024 (SUPC_BOD33_PSEL_DIV1024_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV2048 (SUPC_BOD33_PSEL_DIV2048_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV4096 (SUPC_BOD33_PSEL_DIV4096_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV8192 (SUPC_BOD33_PSEL_DIV8192_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV16384 (SUPC_BOD33_PSEL_DIV16384_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV32768 (SUPC_BOD33_PSEL_DIV32768_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_PSEL_DIV65536 (SUPC_BOD33_PSEL_DIV65536_Val << SUPC_BOD33_PSEL_Pos) +#define SUPC_BOD33_LEVEL_Pos 16 /**< \brief (SUPC_BOD33) Threshold Level for VDD */ +#define SUPC_BOD33_LEVEL_Msk (0x3Ful << SUPC_BOD33_LEVEL_Pos) +#define SUPC_BOD33_LEVEL(value) ((SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))) +#define SUPC_BOD33_BKUPLEVEL_Pos 24 /**< \brief (SUPC_BOD33) Threshold Level in backup sleep mode or for VBAT */ +#define SUPC_BOD33_BKUPLEVEL_Msk (0x3Ful << SUPC_BOD33_BKUPLEVEL_Pos) +#define SUPC_BOD33_BKUPLEVEL(value) ((SUPC_BOD33_BKUPLEVEL_Msk & ((value) << SUPC_BOD33_BKUPLEVEL_Pos))) +#define SUPC_BOD33_MASK 0x3F3FF5FEul /**< \brief (SUPC_BOD33) MASK Register */ + +/* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ + uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ + uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ + uint32_t :3; /*!< bit: 9..11 Reserved */ + uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ + uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_BOD12_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */ +#define SUPC_BOD12_RESETVALUE 0x00000000ul /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */ + +#define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */ +#define SUPC_BOD12_ENABLE (0x1ul << SUPC_BOD12_ENABLE_Pos) +#define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */ +#define SUPC_BOD12_HYST (0x1ul << SUPC_BOD12_HYST_Pos) +#define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */ +#define SUPC_BOD12_ACTION_Msk (0x3ul << SUPC_BOD12_ACTION_Pos) +#define SUPC_BOD12_ACTION(value) ((SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos))) +#define SUPC_BOD12_ACTION_NONE_Val 0x0ul /**< \brief (SUPC_BOD12) No action */ +#define SUPC_BOD12_ACTION_RESET_Val 0x1ul /**< \brief (SUPC_BOD12) The BOD12 generates a reset */ +#define SUPC_BOD12_ACTION_INT_Val 0x2ul /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */ +#define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos) +#define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos) +#define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos) +#define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */ +#define SUPC_BOD12_STDBYCFG (0x1ul << SUPC_BOD12_STDBYCFG_Pos) +#define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */ +#define SUPC_BOD12_RUNSTDBY (0x1ul << SUPC_BOD12_RUNSTDBY_Pos) +#define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */ +#define SUPC_BOD12_ACTCFG (0x1ul << SUPC_BOD12_ACTCFG_Pos) +#define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */ +#define SUPC_BOD12_PSEL_Msk (0xFul << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL(value) ((SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos))) +#define SUPC_BOD12_PSEL_DIV2_Val 0x0ul /**< \brief (SUPC_BOD12) Divide clock by 2 */ +#define SUPC_BOD12_PSEL_DIV4_Val 0x1ul /**< \brief (SUPC_BOD12) Divide clock by 4 */ +#define SUPC_BOD12_PSEL_DIV8_Val 0x2ul /**< \brief (SUPC_BOD12) Divide clock by 8 */ +#define SUPC_BOD12_PSEL_DIV16_Val 0x3ul /**< \brief (SUPC_BOD12) Divide clock by 16 */ +#define SUPC_BOD12_PSEL_DIV32_Val 0x4ul /**< \brief (SUPC_BOD12) Divide clock by 32 */ +#define SUPC_BOD12_PSEL_DIV64_Val 0x5ul /**< \brief (SUPC_BOD12) Divide clock by 64 */ +#define SUPC_BOD12_PSEL_DIV128_Val 0x6ul /**< \brief (SUPC_BOD12) Divide clock by 128 */ +#define SUPC_BOD12_PSEL_DIV256_Val 0x7ul /**< \brief (SUPC_BOD12) Divide clock by 256 */ +#define SUPC_BOD12_PSEL_DIV512_Val 0x8ul /**< \brief (SUPC_BOD12) Divide clock by 512 */ +#define SUPC_BOD12_PSEL_DIV1024_Val 0x9ul /**< \brief (SUPC_BOD12) Divide clock by 1024 */ +#define SUPC_BOD12_PSEL_DIV2048_Val 0xAul /**< \brief (SUPC_BOD12) Divide clock by 2048 */ +#define SUPC_BOD12_PSEL_DIV4096_Val 0xBul /**< \brief (SUPC_BOD12) Divide clock by 4096 */ +#define SUPC_BOD12_PSEL_DIV8192_Val 0xCul /**< \brief (SUPC_BOD12) Divide clock by 8192 */ +#define SUPC_BOD12_PSEL_DIV16384_Val 0xDul /**< \brief (SUPC_BOD12) Divide clock by 16384 */ +#define SUPC_BOD12_PSEL_DIV32768_Val 0xEul /**< \brief (SUPC_BOD12) Divide clock by 32768 */ +#define SUPC_BOD12_PSEL_DIV65536_Val 0xFul /**< \brief (SUPC_BOD12) Divide clock by 65536 */ +#define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos) +#define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */ +#define SUPC_BOD12_LEVEL_Msk (0x3Ful << SUPC_BOD12_LEVEL_Pos) +#define SUPC_BOD12_LEVEL(value) ((SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos))) +#define SUPC_BOD12_MASK 0x003FF17Eul /**< \brief (SUPC_BOD12) MASK Register */ + +/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SEL:2; /*!< bit: 2.. 3 Voltage Regulator Selection in active mode */ + uint32_t :2; /*!< bit: 4.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t LPEFF:1; /*!< bit: 8 Low Power Efficiency */ + uint32_t :7; /*!< bit: 9..15 Reserved */ + uint32_t VSVSTEP:4; /*!< bit: 16..19 Voltage Scaling Voltage Step */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t VSPER:8; /*!< bit: 24..31 Voltage Scaling Period */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_VREG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */ +#define SUPC_VREG_RESETVALUE 0x00000000ul /**< \brief (SUPC_VREG reset_value) VREG Control */ + +#define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */ +#define SUPC_VREG_ENABLE (0x1ul << SUPC_VREG_ENABLE_Pos) +#define SUPC_VREG_SEL_Pos 2 /**< \brief (SUPC_VREG) Voltage Regulator Selection in active mode */ +#define SUPC_VREG_SEL_Msk (0x3ul << SUPC_VREG_SEL_Pos) +#define SUPC_VREG_SEL(value) ((SUPC_VREG_SEL_Msk & ((value) << SUPC_VREG_SEL_Pos))) +#define SUPC_VREG_SEL_LDO_Val 0x0ul /**< \brief (SUPC_VREG) LDO selection */ +#define SUPC_VREG_SEL_BUCK_Val 0x1ul /**< \brief (SUPC_VREG) Buck selection */ +#define SUPC_VREG_SEL_SCVREG_Val 0x2ul /**< \brief (SUPC_VREG) Switched Cap selection */ +#define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos) +#define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos) +#define SUPC_VREG_SEL_SCVREG (SUPC_VREG_SEL_SCVREG_Val << SUPC_VREG_SEL_Pos) +#define SUPC_VREG_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREG) Run during Standby */ +#define SUPC_VREG_RUNSTDBY (0x1ul << SUPC_VREG_RUNSTDBY_Pos) +#define SUPC_VREG_LPEFF_Pos 8 /**< \brief (SUPC_VREG) Low Power Efficiency */ +#define SUPC_VREG_LPEFF (0x1ul << SUPC_VREG_LPEFF_Pos) +#define SUPC_VREG_VSVSTEP_Pos 16 /**< \brief (SUPC_VREG) Voltage Scaling Voltage Step */ +#define SUPC_VREG_VSVSTEP_Msk (0xFul << SUPC_VREG_VSVSTEP_Pos) +#define SUPC_VREG_VSVSTEP(value) ((SUPC_VREG_VSVSTEP_Msk & ((value) << SUPC_VREG_VSVSTEP_Pos))) +#define SUPC_VREG_VSPER_Pos 24 /**< \brief (SUPC_VREG) Voltage Scaling Period */ +#define SUPC_VREG_VSPER_Msk (0xFFul << SUPC_VREG_VSPER_Pos) +#define SUPC_VREG_VSPER(value) ((SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))) +#define SUPC_VREG_MASK 0xFF0F014Eul /**< \brief (SUPC_VREG) MASK Register */ + +/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */ + uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_VREF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */ +#define SUPC_VREF_RESETVALUE 0x00000000ul /**< \brief (SUPC_VREF reset_value) VREF Control */ + +#define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */ +#define SUPC_VREF_TSEN (0x1ul << SUPC_VREF_TSEN_Pos) +#define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */ +#define SUPC_VREF_VREFOE (0x1ul << SUPC_VREF_VREFOE_Pos) +#define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */ +#define SUPC_VREF_RUNSTDBY (0x1ul << SUPC_VREF_RUNSTDBY_Pos) +#define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */ +#define SUPC_VREF_ONDEMAND (0x1ul << SUPC_VREF_ONDEMAND_Pos) +#define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */ +#define SUPC_VREF_SEL_Msk (0xFul << SUPC_VREF_SEL_Pos) +#define SUPC_VREF_SEL(value) ((SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))) +#define SUPC_VREF_SEL_1V0_Val 0x0ul /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */ +#define SUPC_VREF_SEL_1V1_Val 0x1ul /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */ +#define SUPC_VREF_SEL_1V2_Val 0x2ul /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */ +#define SUPC_VREF_SEL_1V25_Val 0x3ul /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */ +#define SUPC_VREF_SEL_2V0_Val 0x4ul /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */ +#define SUPC_VREF_SEL_2V2_Val 0x5ul /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */ +#define SUPC_VREF_SEL_2V4_Val 0x6ul /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */ +#define SUPC_VREF_SEL_2V5_Val 0x7ul /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */ +#define SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos) +#define SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos) +#define SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos) +#define SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos) +#define SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos) +#define SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos) +#define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos) +#define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos) +#define SUPC_VREF_MASK 0x000F00C6ul /**< \brief (SUPC_VREF) MASK Register */ + +/* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CONF:2; /*!< bit: 0.. 1 Battery Backup Configuration */ + uint32_t WAKEEN:1; /*!< bit: 2 Wake Enable */ + uint32_t PSOKEN:1; /*!< bit: 3 Power Supply OK Enable */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_BBPS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_BBPS_OFFSET 0x20 /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */ +#define SUPC_BBPS_RESETVALUE 0x00000000ul /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */ + +#define SUPC_BBPS_CONF_Pos 0 /**< \brief (SUPC_BBPS) Battery Backup Configuration */ +#define SUPC_BBPS_CONF_Msk (0x3ul << SUPC_BBPS_CONF_Pos) +#define SUPC_BBPS_CONF(value) ((SUPC_BBPS_CONF_Msk & ((value) << SUPC_BBPS_CONF_Pos))) +#define SUPC_BBPS_CONF_NONE_Val 0x0ul /**< \brief (SUPC_BBPS) The backup domain is always supplied by main power */ +#define SUPC_BBPS_CONF_APWS_Val 0x1ul /**< \brief (SUPC_BBPS) The power switch is handled by the automatic power switch */ +#define SUPC_BBPS_CONF_FORCED_Val 0x2ul /**< \brief (SUPC_BBPS) The backup domain is always supplied by battery backup power */ +#define SUPC_BBPS_CONF_BOD33_Val 0x3ul /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */ +#define SUPC_BBPS_CONF_NONE (SUPC_BBPS_CONF_NONE_Val << SUPC_BBPS_CONF_Pos) +#define SUPC_BBPS_CONF_APWS (SUPC_BBPS_CONF_APWS_Val << SUPC_BBPS_CONF_Pos) +#define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos) +#define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos) +#define SUPC_BBPS_WAKEEN_Pos 2 /**< \brief (SUPC_BBPS) Wake Enable */ +#define SUPC_BBPS_WAKEEN (0x1ul << SUPC_BBPS_WAKEEN_Pos) +#define SUPC_BBPS_PSOKEN_Pos 3 /**< \brief (SUPC_BBPS) Power Supply OK Enable */ +#define SUPC_BBPS_PSOKEN (0x1ul << SUPC_BBPS_PSOKEN_Pos) +#define SUPC_BBPS_MASK 0x0000000Ful /**< \brief (SUPC_BBPS) MASK Register */ + +/* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EN:2; /*!< bit: 0.. 1 Enable Output */ + uint32_t :6; /*!< bit: 2.. 7 Reserved */ + uint32_t CLR:2; /*!< bit: 8.. 9 Clear Output */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t SET:2; /*!< bit: 16..17 Set Output */ + uint32_t :6; /*!< bit: 18..23 Reserved */ + uint32_t RTCTGL:2; /*!< bit: 24..25 RTC Toggle Output */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_BKOUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_BKOUT_OFFSET 0x24 /**< \brief (SUPC_BKOUT offset) Backup Output Control */ +#define SUPC_BKOUT_RESETVALUE 0x00000000ul /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */ + +#define SUPC_BKOUT_EN_Pos 0 /**< \brief (SUPC_BKOUT) Enable Output */ +#define SUPC_BKOUT_EN_Msk (0x3ul << SUPC_BKOUT_EN_Pos) +#define SUPC_BKOUT_EN(value) ((SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))) +#define SUPC_BKOUT_CLR_Pos 8 /**< \brief (SUPC_BKOUT) Clear Output */ +#define SUPC_BKOUT_CLR_Msk (0x3ul << SUPC_BKOUT_CLR_Pos) +#define SUPC_BKOUT_CLR(value) ((SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))) +#define SUPC_BKOUT_SET_Pos 16 /**< \brief (SUPC_BKOUT) Set Output */ +#define SUPC_BKOUT_SET_Msk (0x3ul << SUPC_BKOUT_SET_Pos) +#define SUPC_BKOUT_SET(value) ((SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))) +#define SUPC_BKOUT_RTCTGL_Pos 24 /**< \brief (SUPC_BKOUT) RTC Toggle Output */ +#define SUPC_BKOUT_RTCTGL_Msk (0x3ul << SUPC_BKOUT_RTCTGL_Pos) +#define SUPC_BKOUT_RTCTGL(value) ((SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))) +#define SUPC_BKOUT_MASK 0x03030303ul /**< \brief (SUPC_BKOUT) MASK Register */ + +/* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/ 32) Backup Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BKIN:8; /*!< bit: 0.. 7 Backup Input Value */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SUPC_BKIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_BKIN_OFFSET 0x28 /**< \brief (SUPC_BKIN offset) Backup Input Control */ +#define SUPC_BKIN_RESETVALUE 0x00000000ul /**< \brief (SUPC_BKIN reset_value) Backup Input Control */ + +#define SUPC_BKIN_BKIN_Pos 0 /**< \brief (SUPC_BKIN) Backup Input Value */ +#define SUPC_BKIN_BKIN_Msk (0xFFul << SUPC_BKIN_BKIN_Pos) +#define SUPC_BKIN_BKIN(value) ((SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))) +#define SUPC_BKIN_MASK 0x000000FFul /**< \brief (SUPC_BKIN) MASK Register */ + +/** \brief SUPC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ + __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ + __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ + __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ + __IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */ + __IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */ + __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */ + __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */ + __IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */ + __IO SUPC_BKOUT_Type BKOUT; /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */ + __I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_SUPC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tal.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tal.h new file mode 100644 index 0000000000..c6e7610305 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tal.h @@ -0,0 +1,883 @@ +/** + * \file + * + * \brief Component description for TAL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TAL_COMPONENT_ +#define _SAML21_TAL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR TAL */ +/* ========================================================================== */ +/** \addtogroup SAML21_TAL Trigger Allocator */ +/*@{*/ + +#define TAL_U2253 +#define REV_TAL 0x102 + +/* -------- TAL_CTRLA : (TAL Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_CTRLA_OFFSET 0x00 /**< \brief (TAL_CTRLA offset) Control A */ +#define TAL_CTRLA_RESETVALUE 0x00ul /**< \brief (TAL_CTRLA reset_value) Control A */ + +#define TAL_CTRLA_SWRST_Pos 0 /**< \brief (TAL_CTRLA) Software Reset */ +#define TAL_CTRLA_SWRST (0x1ul << TAL_CTRLA_SWRST_Pos) +#define TAL_CTRLA_ENABLE_Pos 1 /**< \brief (TAL_CTRLA) Enable */ +#define TAL_CTRLA_ENABLE (0x1ul << TAL_CTRLA_ENABLE_Pos) +#define TAL_CTRLA_MASK 0x03ul /**< \brief (TAL_CTRLA) MASK Register */ + +/* -------- TAL_RSTCTRL : (TAL Offset: 0x04) (R/W 8) Reset Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint8_t reg; /*!< Type used for register access */ +} TAL_RSTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_RSTCTRL_OFFSET 0x04 /**< \brief (TAL_RSTCTRL offset) Reset Control */ +#define TAL_RSTCTRL_RESETVALUE 0x00ul /**< \brief (TAL_RSTCTRL reset_value) Reset Control */ +#define TAL_RSTCTRL_MASK 0x00ul /**< \brief (TAL_RSTCTRL) MASK Register */ + +/* -------- TAL_EXTCTRL : (TAL Offset: 0x05) (R/W 8) External Break Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENABLE:1; /*!< bit: 0 Enable BRK Pin */ + uint8_t INV:1; /*!< bit: 1 Invert BRK Pin */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_EXTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_EXTCTRL_OFFSET 0x05 /**< \brief (TAL_EXTCTRL offset) External Break Control */ +#define TAL_EXTCTRL_RESETVALUE 0x00ul /**< \brief (TAL_EXTCTRL reset_value) External Break Control */ + +#define TAL_EXTCTRL_ENABLE_Pos 0 /**< \brief (TAL_EXTCTRL) Enable BRK Pin */ +#define TAL_EXTCTRL_ENABLE (0x1ul << TAL_EXTCTRL_ENABLE_Pos) +#define TAL_EXTCTRL_INV_Pos 1 /**< \brief (TAL_EXTCTRL) Invert BRK Pin */ +#define TAL_EXTCTRL_INV (0x1ul << TAL_EXTCTRL_INV_Pos) +#define TAL_EXTCTRL_MASK 0x03ul /**< \brief (TAL_EXTCTRL) MASK Register */ + +/* -------- TAL_EVCTRL : (TAL Offset: 0x06) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BRKEI:1; /*!< bit: 0 Break Input Event Enable */ + uint8_t BRKEO:1; /*!< bit: 1 Break Output Event Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_EVCTRL_OFFSET 0x06 /**< \brief (TAL_EVCTRL offset) Event Control */ +#define TAL_EVCTRL_RESETVALUE 0x00ul /**< \brief (TAL_EVCTRL reset_value) Event Control */ + +#define TAL_EVCTRL_BRKEI_Pos 0 /**< \brief (TAL_EVCTRL) Break Input Event Enable */ +#define TAL_EVCTRL_BRKEI (0x1ul << TAL_EVCTRL_BRKEI_Pos) +#define TAL_EVCTRL_BRKEO_Pos 1 /**< \brief (TAL_EVCTRL) Break Output Event Enable */ +#define TAL_EVCTRL_BRKEO (0x1ul << TAL_EVCTRL_BRKEO_Pos) +#define TAL_EVCTRL_MASK 0x03ul /**< \brief (TAL_EVCTRL) MASK Register */ + +/* -------- TAL_INTENCLR : (TAL Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTENCLR_OFFSET 0x08 /**< \brief (TAL_INTENCLR offset) Interrupt Enable Clear */ +#define TAL_INTENCLR_RESETVALUE 0x00ul /**< \brief (TAL_INTENCLR reset_value) Interrupt Enable Clear */ + +#define TAL_INTENCLR_BRK_Pos 0 /**< \brief (TAL_INTENCLR) Break Interrupt Enable */ +#define TAL_INTENCLR_BRK (0x1ul << TAL_INTENCLR_BRK_Pos) +#define TAL_INTENCLR_MASK 0x01ul /**< \brief (TAL_INTENCLR) MASK Register */ + +/* -------- TAL_INTENSET : (TAL Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTENSET_OFFSET 0x09 /**< \brief (TAL_INTENSET offset) Interrupt Enable Set */ +#define TAL_INTENSET_RESETVALUE 0x00ul /**< \brief (TAL_INTENSET reset_value) Interrupt Enable Set */ + +#define TAL_INTENSET_BRK_Pos 0 /**< \brief (TAL_INTENSET) Break Interrupt Enable */ +#define TAL_INTENSET_BRK (0x1ul << TAL_INTENSET_BRK_Pos) +#define TAL_INTENSET_MASK 0x01ul /**< \brief (TAL_INTENSET) MASK Register */ + +/* -------- TAL_INTFLAG : (TAL Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BRK:1; /*!< bit: 0 Break */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTFLAG_OFFSET 0x0A /**< \brief (TAL_INTFLAG offset) Interrupt Flag Status and Clear */ +#define TAL_INTFLAG_RESETVALUE 0x00ul /**< \brief (TAL_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define TAL_INTFLAG_BRK_Pos 0 /**< \brief (TAL_INTFLAG) Break */ +#define TAL_INTFLAG_BRK (0x1ul << TAL_INTFLAG_BRK_Pos) +#define TAL_INTFLAG_MASK 0x01ul /**< \brief (TAL_INTFLAG) MASK Register */ + +/* -------- TAL_GLOBMASK : (TAL Offset: 0x0B) (R/W 8) Global Break Requests Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ + uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ + uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_GLOBMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_GLOBMASK_OFFSET 0x0B /**< \brief (TAL_GLOBMASK offset) Global Break Requests Mask */ +#define TAL_GLOBMASK_RESETVALUE 0x00ul /**< \brief (TAL_GLOBMASK reset_value) Global Break Requests Mask */ + +#define TAL_GLOBMASK_CM0P_Pos 0 /**< \brief (TAL_GLOBMASK) CM0P Break Master */ +#define TAL_GLOBMASK_CM0P (0x1ul << TAL_GLOBMASK_CM0P_Pos) +#define TAL_GLOBMASK_PPP_Pos 1 /**< \brief (TAL_GLOBMASK) PPP Break Master */ +#define TAL_GLOBMASK_PPP (0x1ul << TAL_GLOBMASK_PPP_Pos) +#define TAL_GLOBMASK_EVBRK_Pos 6 /**< \brief (TAL_GLOBMASK) Event Break Master */ +#define TAL_GLOBMASK_EVBRK (0x1ul << TAL_GLOBMASK_EVBRK_Pos) +#define TAL_GLOBMASK_EXTBRK_Pos 7 /**< \brief (TAL_GLOBMASK) External Break Master */ +#define TAL_GLOBMASK_EXTBRK (0x1ul << TAL_GLOBMASK_EXTBRK_Pos) +#define TAL_GLOBMASK_MASK 0xC3ul /**< \brief (TAL_GLOBMASK) MASK Register */ + +/* -------- TAL_HALT : (TAL Offset: 0x0C) ( /W 8) Debug Halt Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ + uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ + uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_HALT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_HALT_OFFSET 0x0C /**< \brief (TAL_HALT offset) Debug Halt Request */ +#define TAL_HALT_RESETVALUE 0x00ul /**< \brief (TAL_HALT reset_value) Debug Halt Request */ + +#define TAL_HALT_CM0P_Pos 0 /**< \brief (TAL_HALT) CM0P Break Master */ +#define TAL_HALT_CM0P (0x1ul << TAL_HALT_CM0P_Pos) +#define TAL_HALT_PPP_Pos 1 /**< \brief (TAL_HALT) PPP Break Master */ +#define TAL_HALT_PPP (0x1ul << TAL_HALT_PPP_Pos) +#define TAL_HALT_EVBRK_Pos 6 /**< \brief (TAL_HALT) Event Break Master */ +#define TAL_HALT_EVBRK (0x1ul << TAL_HALT_EVBRK_Pos) +#define TAL_HALT_EXTBRK_Pos 7 /**< \brief (TAL_HALT) External Break Master */ +#define TAL_HALT_EXTBRK (0x1ul << TAL_HALT_EXTBRK_Pos) +#define TAL_HALT_MASK 0xC3ul /**< \brief (TAL_HALT) MASK Register */ + +/* -------- TAL_RESTART : (TAL Offset: 0x0D) ( /W 8) Debug Restart Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ + uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_RESTART_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_RESTART_OFFSET 0x0D /**< \brief (TAL_RESTART offset) Debug Restart Request */ +#define TAL_RESTART_RESETVALUE 0x00ul /**< \brief (TAL_RESTART reset_value) Debug Restart Request */ + +#define TAL_RESTART_CM0P_Pos 0 /**< \brief (TAL_RESTART) CM0P Break Master */ +#define TAL_RESTART_CM0P (0x1ul << TAL_RESTART_CM0P_Pos) +#define TAL_RESTART_PPP_Pos 1 /**< \brief (TAL_RESTART) PPP Break Master */ +#define TAL_RESTART_PPP (0x1ul << TAL_RESTART_PPP_Pos) +#define TAL_RESTART_EXTBRK_Pos 7 /**< \brief (TAL_RESTART) External Break Master */ +#define TAL_RESTART_EXTBRK (0x1ul << TAL_RESTART_EXTBRK_Pos) +#define TAL_RESTART_MASK 0x83ul /**< \brief (TAL_RESTART) MASK Register */ + +/* -------- TAL_BRKSTATUS : (TAL Offset: 0x0E) (R/ 16) Break Request Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CM0P:2; /*!< bit: 0.. 1 CM0P Break Request */ + uint16_t PPP:2; /*!< bit: 2.. 3 PPP Break Request */ + uint16_t :8; /*!< bit: 4..11 Reserved */ + uint16_t EVBRK:2; /*!< bit: 12..13 Event Break Request */ + uint16_t EXTBRK:2; /*!< bit: 14..15 External Break Request */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TAL_BRKSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_BRKSTATUS_OFFSET 0x0E /**< \brief (TAL_BRKSTATUS offset) Break Request Status */ +#define TAL_BRKSTATUS_RESETVALUE 0x0000ul /**< \brief (TAL_BRKSTATUS reset_value) Break Request Status */ + +#define TAL_BRKSTATUS_CM0P_Pos 0 /**< \brief (TAL_BRKSTATUS) CM0P Break Request */ +#define TAL_BRKSTATUS_CM0P_Msk (0x3ul << TAL_BRKSTATUS_CM0P_Pos) +#define TAL_BRKSTATUS_CM0P(value) ((TAL_BRKSTATUS_CM0P_Msk & ((value) << TAL_BRKSTATUS_CM0P_Pos))) +#define TAL_BRKSTATUS_PPP_Pos 2 /**< \brief (TAL_BRKSTATUS) PPP Break Request */ +#define TAL_BRKSTATUS_PPP_Msk (0x3ul << TAL_BRKSTATUS_PPP_Pos) +#define TAL_BRKSTATUS_PPP(value) ((TAL_BRKSTATUS_PPP_Msk & ((value) << TAL_BRKSTATUS_PPP_Pos))) +#define TAL_BRKSTATUS_EVBRK_Pos 12 /**< \brief (TAL_BRKSTATUS) Event Break Request */ +#define TAL_BRKSTATUS_EVBRK_Msk (0x3ul << TAL_BRKSTATUS_EVBRK_Pos) +#define TAL_BRKSTATUS_EVBRK(value) ((TAL_BRKSTATUS_EVBRK_Msk & ((value) << TAL_BRKSTATUS_EVBRK_Pos))) +#define TAL_BRKSTATUS_EXTBRK_Pos 14 /**< \brief (TAL_BRKSTATUS) External Break Request */ +#define TAL_BRKSTATUS_EXTBRK_Msk (0x3ul << TAL_BRKSTATUS_EXTBRK_Pos) +#define TAL_BRKSTATUS_EXTBRK(value) ((TAL_BRKSTATUS_EXTBRK_Msk & ((value) << TAL_BRKSTATUS_EXTBRK_Pos))) +#define TAL_BRKSTATUS_MASK 0xF00Ful /**< \brief (TAL_BRKSTATUS) MASK Register */ + +/* -------- TAL_CTICTRLA : (TAL Offset: 0x10) (R/W 8) CTIS Cross-Trigger Interface n Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ACTION:2; /*!< bit: 0.. 1 Action when global break issued */ + uint8_t RESTART:1; /*!< bit: 2 Action when global restart issued */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_CTICTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_CTICTRLA_OFFSET 0x10 /**< \brief (TAL_CTICTRLA offset) Cross-Trigger Interface n Control A */ +#define TAL_CTICTRLA_RESETVALUE 0x00ul /**< \brief (TAL_CTICTRLA reset_value) Cross-Trigger Interface n Control A */ + +#define TAL_CTICTRLA_ACTION_Pos 0 /**< \brief (TAL_CTICTRLA) Action when global break issued */ +#define TAL_CTICTRLA_ACTION_Msk (0x3ul << TAL_CTICTRLA_ACTION_Pos) +#define TAL_CTICTRLA_ACTION(value) ((TAL_CTICTRLA_ACTION_Msk & ((value) << TAL_CTICTRLA_ACTION_Pos))) +#define TAL_CTICTRLA_ACTION_BREAK_Val 0x0ul /**< \brief (TAL_CTICTRLA) Break when requested */ +#define TAL_CTICTRLA_ACTION_INTERRUPT_Val 0x1ul /**< \brief (TAL_CTICTRLA) Trigger DBG interrupt instead of break */ +#define TAL_CTICTRLA_ACTION_IGNORE_Val 0x2ul /**< \brief (TAL_CTICTRLA) Ignore break request */ +#define TAL_CTICTRLA_ACTION_BREAK (TAL_CTICTRLA_ACTION_BREAK_Val << TAL_CTICTRLA_ACTION_Pos) +#define TAL_CTICTRLA_ACTION_INTERRUPT (TAL_CTICTRLA_ACTION_INTERRUPT_Val << TAL_CTICTRLA_ACTION_Pos) +#define TAL_CTICTRLA_ACTION_IGNORE (TAL_CTICTRLA_ACTION_IGNORE_Val << TAL_CTICTRLA_ACTION_Pos) +#define TAL_CTICTRLA_RESTART_Pos 2 /**< \brief (TAL_CTICTRLA) Action when global restart issued */ +#define TAL_CTICTRLA_RESTART (0x1ul << TAL_CTICTRLA_RESTART_Pos) +#define TAL_CTICTRLA_MASK 0x07ul /**< \brief (TAL_CTICTRLA) MASK Register */ + +/* -------- TAL_CTIMASK : (TAL Offset: 0x11) (R/W 8) CTIS Cross-Trigger Interface n Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ + uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ + uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_CTIMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_CTIMASK_OFFSET 0x11 /**< \brief (TAL_CTIMASK offset) Cross-Trigger Interface n Mask */ +#define TAL_CTIMASK_RESETVALUE 0x00ul /**< \brief (TAL_CTIMASK reset_value) Cross-Trigger Interface n Mask */ + +#define TAL_CTIMASK_CM0P_Pos 0 /**< \brief (TAL_CTIMASK) CM0P Break Master */ +#define TAL_CTIMASK_CM0P (0x1ul << TAL_CTIMASK_CM0P_Pos) +#define TAL_CTIMASK_PPP_Pos 1 /**< \brief (TAL_CTIMASK) PPP Break Master */ +#define TAL_CTIMASK_PPP (0x1ul << TAL_CTIMASK_PPP_Pos) +#define TAL_CTIMASK_EVBRK_Pos 6 /**< \brief (TAL_CTIMASK) Event Break Master */ +#define TAL_CTIMASK_EVBRK (0x1ul << TAL_CTIMASK_EVBRK_Pos) +#define TAL_CTIMASK_EXTBRK_Pos 7 /**< \brief (TAL_CTIMASK) External Break Master */ +#define TAL_CTIMASK_EXTBRK (0x1ul << TAL_CTIMASK_EXTBRK_Pos) +#define TAL_CTIMASK_MASK 0xC3ul /**< \brief (TAL_CTIMASK) MASK Register */ + +/* -------- TAL_INTSTATUS : (TAL Offset: 0x20) (R/ 8) Interrupt n Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t IRQ0:1; /*!< bit: 0 Interrupt Status for Interrupt Request 0 within Interrupt n */ + uint8_t IRQ1:1; /*!< bit: 1 Interrupt Status for Interrupt Request 1 within Interrupt n */ + uint8_t IRQ2:1; /*!< bit: 2 Interrupt Status for Interrupt Request 2 within Interrupt n */ + uint8_t IRQ3:1; /*!< bit: 3 Interrupt Status for Interrupt Request 3 within Interrupt n */ + uint8_t IRQ4:1; /*!< bit: 4 Interrupt Status for Interrupt Request 4 within Interrupt n */ + uint8_t IRQ5:1; /*!< bit: 5 Interrupt Status for Interrupt Request 5 within Interrupt n */ + uint8_t IRQ6:1; /*!< bit: 6 Interrupt Status for Interrupt Request 6 within Interrupt n */ + uint8_t IRQ7:1; /*!< bit: 7 Interrupt Status for Interrupt Request 7 within Interrupt n */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t IRQ:8; /*!< bit: 0.. 7 Interrupt Status for Interrupt Request x within Interrupt n */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTSTATUS_OFFSET 0x20 /**< \brief (TAL_INTSTATUS offset) Interrupt n Status */ +#define TAL_INTSTATUS_RESETVALUE 0x00ul /**< \brief (TAL_INTSTATUS reset_value) Interrupt n Status */ + +#define TAL_INTSTATUS_IRQ0_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 0 within Interrupt n */ +#define TAL_INTSTATUS_IRQ0 (1 << TAL_INTSTATUS_IRQ0_Pos) +#define TAL_INTSTATUS_IRQ1_Pos 1 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 1 within Interrupt n */ +#define TAL_INTSTATUS_IRQ1 (1 << TAL_INTSTATUS_IRQ1_Pos) +#define TAL_INTSTATUS_IRQ2_Pos 2 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 2 within Interrupt n */ +#define TAL_INTSTATUS_IRQ2 (1 << TAL_INTSTATUS_IRQ2_Pos) +#define TAL_INTSTATUS_IRQ3_Pos 3 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 3 within Interrupt n */ +#define TAL_INTSTATUS_IRQ3 (1 << TAL_INTSTATUS_IRQ3_Pos) +#define TAL_INTSTATUS_IRQ4_Pos 4 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 4 within Interrupt n */ +#define TAL_INTSTATUS_IRQ4 (1 << TAL_INTSTATUS_IRQ4_Pos) +#define TAL_INTSTATUS_IRQ5_Pos 5 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 5 within Interrupt n */ +#define TAL_INTSTATUS_IRQ5 (1 << TAL_INTSTATUS_IRQ5_Pos) +#define TAL_INTSTATUS_IRQ6_Pos 6 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 6 within Interrupt n */ +#define TAL_INTSTATUS_IRQ6 (1 << TAL_INTSTATUS_IRQ6_Pos) +#define TAL_INTSTATUS_IRQ7_Pos 7 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 7 within Interrupt n */ +#define TAL_INTSTATUS_IRQ7 (1 << TAL_INTSTATUS_IRQ7_Pos) +#define TAL_INTSTATUS_IRQ_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request x within Interrupt n */ +#define TAL_INTSTATUS_IRQ_Msk (0xFFul << TAL_INTSTATUS_IRQ_Pos) +#define TAL_INTSTATUS_IRQ(value) ((TAL_INTSTATUS_IRQ_Msk & ((value) << TAL_INTSTATUS_IRQ_Pos))) +#define TAL_INTSTATUS_MASK 0xFFul /**< \brief (TAL_INTSTATUS) MASK Register */ + +/* -------- TAL_DMACPUSEL0 : (TAL Offset: 0x40) (R/W 32) DMA Channel Interrupts CPU Select 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CH0:1; /*!< bit: 0 DMA Channel 0 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 1 Reserved */ + uint32_t CH1:1; /*!< bit: 2 DMA Channel 1 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t CH2:1; /*!< bit: 4 DMA Channel 2 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t CH3:1; /*!< bit: 6 DMA Channel 3 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t CH4:1; /*!< bit: 8 DMA Channel 4 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 9 Reserved */ + uint32_t CH5:1; /*!< bit: 10 DMA Channel 5 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t CH6:1; /*!< bit: 12 DMA Channel 6 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 13 Reserved */ + uint32_t CH7:1; /*!< bit: 14 DMA Channel 7 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CH8:1; /*!< bit: 16 DMA Channel 8 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 17 Reserved */ + uint32_t CH9:1; /*!< bit: 18 DMA Channel 9 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t CH10:1; /*!< bit: 20 DMA Channel 10 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 21 Reserved */ + uint32_t CH11:1; /*!< bit: 22 DMA Channel 11 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t CH12:1; /*!< bit: 24 DMA Channel 12 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 25 Reserved */ + uint32_t CH13:1; /*!< bit: 26 DMA Channel 13 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t CH14:1; /*!< bit: 28 DMA Channel 14 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t CH15:1; /*!< bit: 30 DMA Channel 15 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TAL_DMACPUSEL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_DMACPUSEL0_OFFSET 0x40 /**< \brief (TAL_DMACPUSEL0 offset) DMA Channel Interrupts CPU Select 0 */ +#define TAL_DMACPUSEL0_RESETVALUE 0x00000000ul /**< \brief (TAL_DMACPUSEL0 reset_value) DMA Channel Interrupts CPU Select 0 */ + +#define TAL_DMACPUSEL0_CH0_Pos 0 /**< \brief (TAL_DMACPUSEL0) DMA Channel 0 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH0_Msk (0x1ul << TAL_DMACPUSEL0_CH0_Pos) +#define TAL_DMACPUSEL0_CH0(value) ((TAL_DMACPUSEL0_CH0_Msk & ((value) << TAL_DMACPUSEL0_CH0_Pos))) +#define TAL_DMACPUSEL0_CH1_Pos 2 /**< \brief (TAL_DMACPUSEL0) DMA Channel 1 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH1_Msk (0x1ul << TAL_DMACPUSEL0_CH1_Pos) +#define TAL_DMACPUSEL0_CH1(value) ((TAL_DMACPUSEL0_CH1_Msk & ((value) << TAL_DMACPUSEL0_CH1_Pos))) +#define TAL_DMACPUSEL0_CH2_Pos 4 /**< \brief (TAL_DMACPUSEL0) DMA Channel 2 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH2_Msk (0x1ul << TAL_DMACPUSEL0_CH2_Pos) +#define TAL_DMACPUSEL0_CH2(value) ((TAL_DMACPUSEL0_CH2_Msk & ((value) << TAL_DMACPUSEL0_CH2_Pos))) +#define TAL_DMACPUSEL0_CH3_Pos 6 /**< \brief (TAL_DMACPUSEL0) DMA Channel 3 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH3_Msk (0x1ul << TAL_DMACPUSEL0_CH3_Pos) +#define TAL_DMACPUSEL0_CH3(value) ((TAL_DMACPUSEL0_CH3_Msk & ((value) << TAL_DMACPUSEL0_CH3_Pos))) +#define TAL_DMACPUSEL0_CH4_Pos 8 /**< \brief (TAL_DMACPUSEL0) DMA Channel 4 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH4_Msk (0x1ul << TAL_DMACPUSEL0_CH4_Pos) +#define TAL_DMACPUSEL0_CH4(value) ((TAL_DMACPUSEL0_CH4_Msk & ((value) << TAL_DMACPUSEL0_CH4_Pos))) +#define TAL_DMACPUSEL0_CH5_Pos 10 /**< \brief (TAL_DMACPUSEL0) DMA Channel 5 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH5_Msk (0x1ul << TAL_DMACPUSEL0_CH5_Pos) +#define TAL_DMACPUSEL0_CH5(value) ((TAL_DMACPUSEL0_CH5_Msk & ((value) << TAL_DMACPUSEL0_CH5_Pos))) +#define TAL_DMACPUSEL0_CH6_Pos 12 /**< \brief (TAL_DMACPUSEL0) DMA Channel 6 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH6_Msk (0x1ul << TAL_DMACPUSEL0_CH6_Pos) +#define TAL_DMACPUSEL0_CH6(value) ((TAL_DMACPUSEL0_CH6_Msk & ((value) << TAL_DMACPUSEL0_CH6_Pos))) +#define TAL_DMACPUSEL0_CH7_Pos 14 /**< \brief (TAL_DMACPUSEL0) DMA Channel 7 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH7_Msk (0x1ul << TAL_DMACPUSEL0_CH7_Pos) +#define TAL_DMACPUSEL0_CH7(value) ((TAL_DMACPUSEL0_CH7_Msk & ((value) << TAL_DMACPUSEL0_CH7_Pos))) +#define TAL_DMACPUSEL0_CH8_Pos 16 /**< \brief (TAL_DMACPUSEL0) DMA Channel 8 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH8_Msk (0x1ul << TAL_DMACPUSEL0_CH8_Pos) +#define TAL_DMACPUSEL0_CH8(value) ((TAL_DMACPUSEL0_CH8_Msk & ((value) << TAL_DMACPUSEL0_CH8_Pos))) +#define TAL_DMACPUSEL0_CH9_Pos 18 /**< \brief (TAL_DMACPUSEL0) DMA Channel 9 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH9_Msk (0x1ul << TAL_DMACPUSEL0_CH9_Pos) +#define TAL_DMACPUSEL0_CH9(value) ((TAL_DMACPUSEL0_CH9_Msk & ((value) << TAL_DMACPUSEL0_CH9_Pos))) +#define TAL_DMACPUSEL0_CH10_Pos 20 /**< \brief (TAL_DMACPUSEL0) DMA Channel 10 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH10_Msk (0x1ul << TAL_DMACPUSEL0_CH10_Pos) +#define TAL_DMACPUSEL0_CH10(value) ((TAL_DMACPUSEL0_CH10_Msk & ((value) << TAL_DMACPUSEL0_CH10_Pos))) +#define TAL_DMACPUSEL0_CH11_Pos 22 /**< \brief (TAL_DMACPUSEL0) DMA Channel 11 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH11_Msk (0x1ul << TAL_DMACPUSEL0_CH11_Pos) +#define TAL_DMACPUSEL0_CH11(value) ((TAL_DMACPUSEL0_CH11_Msk & ((value) << TAL_DMACPUSEL0_CH11_Pos))) +#define TAL_DMACPUSEL0_CH12_Pos 24 /**< \brief (TAL_DMACPUSEL0) DMA Channel 12 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH12_Msk (0x1ul << TAL_DMACPUSEL0_CH12_Pos) +#define TAL_DMACPUSEL0_CH12(value) ((TAL_DMACPUSEL0_CH12_Msk & ((value) << TAL_DMACPUSEL0_CH12_Pos))) +#define TAL_DMACPUSEL0_CH13_Pos 26 /**< \brief (TAL_DMACPUSEL0) DMA Channel 13 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH13_Msk (0x1ul << TAL_DMACPUSEL0_CH13_Pos) +#define TAL_DMACPUSEL0_CH13(value) ((TAL_DMACPUSEL0_CH13_Msk & ((value) << TAL_DMACPUSEL0_CH13_Pos))) +#define TAL_DMACPUSEL0_CH14_Pos 28 /**< \brief (TAL_DMACPUSEL0) DMA Channel 14 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH14_Msk (0x1ul << TAL_DMACPUSEL0_CH14_Pos) +#define TAL_DMACPUSEL0_CH14(value) ((TAL_DMACPUSEL0_CH14_Msk & ((value) << TAL_DMACPUSEL0_CH14_Pos))) +#define TAL_DMACPUSEL0_CH15_Pos 30 /**< \brief (TAL_DMACPUSEL0) DMA Channel 15 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH15_Msk (0x1ul << TAL_DMACPUSEL0_CH15_Pos) +#define TAL_DMACPUSEL0_CH15(value) ((TAL_DMACPUSEL0_CH15_Msk & ((value) << TAL_DMACPUSEL0_CH15_Pos))) +#define TAL_DMACPUSEL0_MASK 0x55555555ul /**< \brief (TAL_DMACPUSEL0) MASK Register */ + +/* -------- TAL_EVCPUSEL0 : (TAL Offset: 0x48) (R/W 32) EVSYS Channel Interrupts CPU Select 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CH0:1; /*!< bit: 0 Event Channel 0 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 1 Reserved */ + uint32_t CH1:1; /*!< bit: 2 Event Channel 1 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t CH2:1; /*!< bit: 4 Event Channel 2 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t CH3:1; /*!< bit: 6 Event Channel 3 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t CH4:1; /*!< bit: 8 Event Channel 4 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 9 Reserved */ + uint32_t CH5:1; /*!< bit: 10 Event Channel 5 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t CH6:1; /*!< bit: 12 Event Channel 6 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 13 Reserved */ + uint32_t CH7:1; /*!< bit: 14 Event Channel 7 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CH8:1; /*!< bit: 16 Event Channel 8 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 17 Reserved */ + uint32_t CH9:1; /*!< bit: 18 Event Channel 9 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t CH10:1; /*!< bit: 20 Event Channel 10 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 21 Reserved */ + uint32_t CH11:1; /*!< bit: 22 Event Channel 11 Interrupt CPU Select */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TAL_EVCPUSEL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_EVCPUSEL0_OFFSET 0x48 /**< \brief (TAL_EVCPUSEL0 offset) EVSYS Channel Interrupts CPU Select 0 */ +#define TAL_EVCPUSEL0_RESETVALUE 0x00000000ul /**< \brief (TAL_EVCPUSEL0 reset_value) EVSYS Channel Interrupts CPU Select 0 */ + +#define TAL_EVCPUSEL0_CH0_Pos 0 /**< \brief (TAL_EVCPUSEL0) Event Channel 0 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH0_Msk (0x1ul << TAL_EVCPUSEL0_CH0_Pos) +#define TAL_EVCPUSEL0_CH0(value) ((TAL_EVCPUSEL0_CH0_Msk & ((value) << TAL_EVCPUSEL0_CH0_Pos))) +#define TAL_EVCPUSEL0_CH1_Pos 2 /**< \brief (TAL_EVCPUSEL0) Event Channel 1 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH1_Msk (0x1ul << TAL_EVCPUSEL0_CH1_Pos) +#define TAL_EVCPUSEL0_CH1(value) ((TAL_EVCPUSEL0_CH1_Msk & ((value) << TAL_EVCPUSEL0_CH1_Pos))) +#define TAL_EVCPUSEL0_CH2_Pos 4 /**< \brief (TAL_EVCPUSEL0) Event Channel 2 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH2_Msk (0x1ul << TAL_EVCPUSEL0_CH2_Pos) +#define TAL_EVCPUSEL0_CH2(value) ((TAL_EVCPUSEL0_CH2_Msk & ((value) << TAL_EVCPUSEL0_CH2_Pos))) +#define TAL_EVCPUSEL0_CH3_Pos 6 /**< \brief (TAL_EVCPUSEL0) Event Channel 3 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH3_Msk (0x1ul << TAL_EVCPUSEL0_CH3_Pos) +#define TAL_EVCPUSEL0_CH3(value) ((TAL_EVCPUSEL0_CH3_Msk & ((value) << TAL_EVCPUSEL0_CH3_Pos))) +#define TAL_EVCPUSEL0_CH4_Pos 8 /**< \brief (TAL_EVCPUSEL0) Event Channel 4 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH4_Msk (0x1ul << TAL_EVCPUSEL0_CH4_Pos) +#define TAL_EVCPUSEL0_CH4(value) ((TAL_EVCPUSEL0_CH4_Msk & ((value) << TAL_EVCPUSEL0_CH4_Pos))) +#define TAL_EVCPUSEL0_CH5_Pos 10 /**< \brief (TAL_EVCPUSEL0) Event Channel 5 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH5_Msk (0x1ul << TAL_EVCPUSEL0_CH5_Pos) +#define TAL_EVCPUSEL0_CH5(value) ((TAL_EVCPUSEL0_CH5_Msk & ((value) << TAL_EVCPUSEL0_CH5_Pos))) +#define TAL_EVCPUSEL0_CH6_Pos 12 /**< \brief (TAL_EVCPUSEL0) Event Channel 6 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH6_Msk (0x1ul << TAL_EVCPUSEL0_CH6_Pos) +#define TAL_EVCPUSEL0_CH6(value) ((TAL_EVCPUSEL0_CH6_Msk & ((value) << TAL_EVCPUSEL0_CH6_Pos))) +#define TAL_EVCPUSEL0_CH7_Pos 14 /**< \brief (TAL_EVCPUSEL0) Event Channel 7 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH7_Msk (0x1ul << TAL_EVCPUSEL0_CH7_Pos) +#define TAL_EVCPUSEL0_CH7(value) ((TAL_EVCPUSEL0_CH7_Msk & ((value) << TAL_EVCPUSEL0_CH7_Pos))) +#define TAL_EVCPUSEL0_CH8_Pos 16 /**< \brief (TAL_EVCPUSEL0) Event Channel 8 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH8_Msk (0x1ul << TAL_EVCPUSEL0_CH8_Pos) +#define TAL_EVCPUSEL0_CH8(value) ((TAL_EVCPUSEL0_CH8_Msk & ((value) << TAL_EVCPUSEL0_CH8_Pos))) +#define TAL_EVCPUSEL0_CH9_Pos 18 /**< \brief (TAL_EVCPUSEL0) Event Channel 9 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH9_Msk (0x1ul << TAL_EVCPUSEL0_CH9_Pos) +#define TAL_EVCPUSEL0_CH9(value) ((TAL_EVCPUSEL0_CH9_Msk & ((value) << TAL_EVCPUSEL0_CH9_Pos))) +#define TAL_EVCPUSEL0_CH10_Pos 20 /**< \brief (TAL_EVCPUSEL0) Event Channel 10 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH10_Msk (0x1ul << TAL_EVCPUSEL0_CH10_Pos) +#define TAL_EVCPUSEL0_CH10(value) ((TAL_EVCPUSEL0_CH10_Msk & ((value) << TAL_EVCPUSEL0_CH10_Pos))) +#define TAL_EVCPUSEL0_CH11_Pos 22 /**< \brief (TAL_EVCPUSEL0) Event Channel 11 Interrupt CPU Select */ +#define TAL_EVCPUSEL0_CH11_Msk (0x1ul << TAL_EVCPUSEL0_CH11_Pos) +#define TAL_EVCPUSEL0_CH11(value) ((TAL_EVCPUSEL0_CH11_Msk & ((value) << TAL_EVCPUSEL0_CH11_Pos))) +#define TAL_EVCPUSEL0_MASK 0x00555555ul /**< \brief (TAL_EVCPUSEL0) MASK Register */ + +/* -------- TAL_EICCPUSEL0 : (TAL Offset: 0x50) (R/W 32) EIC External Interrupts CPU Select 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 CPU Select */ + uint32_t :1; /*!< bit: 1 Reserved */ + uint32_t EXTINT1:1; /*!< bit: 2 External Interrupt 1 CPU Select */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t EXTINT2:1; /*!< bit: 4 External Interrupt 2 CPU Select */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t EXTINT3:1; /*!< bit: 6 External Interrupt 3 CPU Select */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t EXTINT4:1; /*!< bit: 8 External Interrupt 4 CPU Select */ + uint32_t :1; /*!< bit: 9 Reserved */ + uint32_t EXTINT5:1; /*!< bit: 10 External Interrupt 5 CPU Select */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t EXTINT6:1; /*!< bit: 12 External Interrupt 6 CPU Select */ + uint32_t :1; /*!< bit: 13 Reserved */ + uint32_t EXTINT7:1; /*!< bit: 14 External Interrupt 7 CPU Select */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t EXTINT8:1; /*!< bit: 16 External Interrupt 8 CPU Select */ + uint32_t :1; /*!< bit: 17 Reserved */ + uint32_t EXTINT9:1; /*!< bit: 18 External Interrupt 9 CPU Select */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t EXTINT10:1; /*!< bit: 20 External Interrupt 10 CPU Select */ + uint32_t :1; /*!< bit: 21 Reserved */ + uint32_t EXTINT11:1; /*!< bit: 22 External Interrupt 11 CPU Select */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t EXTINT12:1; /*!< bit: 24 External Interrupt 12 CPU Select */ + uint32_t :1; /*!< bit: 25 Reserved */ + uint32_t EXTINT13:1; /*!< bit: 26 External Interrupt 13 CPU Select */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t EXTINT14:1; /*!< bit: 28 External Interrupt 14 CPU Select */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t EXTINT15:1; /*!< bit: 30 External Interrupt 15 CPU Select */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TAL_EICCPUSEL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_EICCPUSEL0_OFFSET 0x50 /**< \brief (TAL_EICCPUSEL0 offset) EIC External Interrupts CPU Select 0 */ +#define TAL_EICCPUSEL0_RESETVALUE 0x00000000ul /**< \brief (TAL_EICCPUSEL0 reset_value) EIC External Interrupts CPU Select 0 */ + +#define TAL_EICCPUSEL0_EXTINT0_Pos 0 /**< \brief (TAL_EICCPUSEL0) External Interrupt 0 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT0_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT0_Pos) +#define TAL_EICCPUSEL0_EXTINT0(value) ((TAL_EICCPUSEL0_EXTINT0_Msk & ((value) << TAL_EICCPUSEL0_EXTINT0_Pos))) +#define TAL_EICCPUSEL0_EXTINT1_Pos 2 /**< \brief (TAL_EICCPUSEL0) External Interrupt 1 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT1_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT1_Pos) +#define TAL_EICCPUSEL0_EXTINT1(value) ((TAL_EICCPUSEL0_EXTINT1_Msk & ((value) << TAL_EICCPUSEL0_EXTINT1_Pos))) +#define TAL_EICCPUSEL0_EXTINT2_Pos 4 /**< \brief (TAL_EICCPUSEL0) External Interrupt 2 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT2_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT2_Pos) +#define TAL_EICCPUSEL0_EXTINT2(value) ((TAL_EICCPUSEL0_EXTINT2_Msk & ((value) << TAL_EICCPUSEL0_EXTINT2_Pos))) +#define TAL_EICCPUSEL0_EXTINT3_Pos 6 /**< \brief (TAL_EICCPUSEL0) External Interrupt 3 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT3_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT3_Pos) +#define TAL_EICCPUSEL0_EXTINT3(value) ((TAL_EICCPUSEL0_EXTINT3_Msk & ((value) << TAL_EICCPUSEL0_EXTINT3_Pos))) +#define TAL_EICCPUSEL0_EXTINT4_Pos 8 /**< \brief (TAL_EICCPUSEL0) External Interrupt 4 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT4_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT4_Pos) +#define TAL_EICCPUSEL0_EXTINT4(value) ((TAL_EICCPUSEL0_EXTINT4_Msk & ((value) << TAL_EICCPUSEL0_EXTINT4_Pos))) +#define TAL_EICCPUSEL0_EXTINT5_Pos 10 /**< \brief (TAL_EICCPUSEL0) External Interrupt 5 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT5_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT5_Pos) +#define TAL_EICCPUSEL0_EXTINT5(value) ((TAL_EICCPUSEL0_EXTINT5_Msk & ((value) << TAL_EICCPUSEL0_EXTINT5_Pos))) +#define TAL_EICCPUSEL0_EXTINT6_Pos 12 /**< \brief (TAL_EICCPUSEL0) External Interrupt 6 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT6_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT6_Pos) +#define TAL_EICCPUSEL0_EXTINT6(value) ((TAL_EICCPUSEL0_EXTINT6_Msk & ((value) << TAL_EICCPUSEL0_EXTINT6_Pos))) +#define TAL_EICCPUSEL0_EXTINT7_Pos 14 /**< \brief (TAL_EICCPUSEL0) External Interrupt 7 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT7_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT7_Pos) +#define TAL_EICCPUSEL0_EXTINT7(value) ((TAL_EICCPUSEL0_EXTINT7_Msk & ((value) << TAL_EICCPUSEL0_EXTINT7_Pos))) +#define TAL_EICCPUSEL0_EXTINT8_Pos 16 /**< \brief (TAL_EICCPUSEL0) External Interrupt 8 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT8_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT8_Pos) +#define TAL_EICCPUSEL0_EXTINT8(value) ((TAL_EICCPUSEL0_EXTINT8_Msk & ((value) << TAL_EICCPUSEL0_EXTINT8_Pos))) +#define TAL_EICCPUSEL0_EXTINT9_Pos 18 /**< \brief (TAL_EICCPUSEL0) External Interrupt 9 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT9_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT9_Pos) +#define TAL_EICCPUSEL0_EXTINT9(value) ((TAL_EICCPUSEL0_EXTINT9_Msk & ((value) << TAL_EICCPUSEL0_EXTINT9_Pos))) +#define TAL_EICCPUSEL0_EXTINT10_Pos 20 /**< \brief (TAL_EICCPUSEL0) External Interrupt 10 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT10_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT10_Pos) +#define TAL_EICCPUSEL0_EXTINT10(value) ((TAL_EICCPUSEL0_EXTINT10_Msk & ((value) << TAL_EICCPUSEL0_EXTINT10_Pos))) +#define TAL_EICCPUSEL0_EXTINT11_Pos 22 /**< \brief (TAL_EICCPUSEL0) External Interrupt 11 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT11_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT11_Pos) +#define TAL_EICCPUSEL0_EXTINT11(value) ((TAL_EICCPUSEL0_EXTINT11_Msk & ((value) << TAL_EICCPUSEL0_EXTINT11_Pos))) +#define TAL_EICCPUSEL0_EXTINT12_Pos 24 /**< \brief (TAL_EICCPUSEL0) External Interrupt 12 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT12_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT12_Pos) +#define TAL_EICCPUSEL0_EXTINT12(value) ((TAL_EICCPUSEL0_EXTINT12_Msk & ((value) << TAL_EICCPUSEL0_EXTINT12_Pos))) +#define TAL_EICCPUSEL0_EXTINT13_Pos 26 /**< \brief (TAL_EICCPUSEL0) External Interrupt 13 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT13_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT13_Pos) +#define TAL_EICCPUSEL0_EXTINT13(value) ((TAL_EICCPUSEL0_EXTINT13_Msk & ((value) << TAL_EICCPUSEL0_EXTINT13_Pos))) +#define TAL_EICCPUSEL0_EXTINT14_Pos 28 /**< \brief (TAL_EICCPUSEL0) External Interrupt 14 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT14_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT14_Pos) +#define TAL_EICCPUSEL0_EXTINT14(value) ((TAL_EICCPUSEL0_EXTINT14_Msk & ((value) << TAL_EICCPUSEL0_EXTINT14_Pos))) +#define TAL_EICCPUSEL0_EXTINT15_Pos 30 /**< \brief (TAL_EICCPUSEL0) External Interrupt 15 CPU Select */ +#define TAL_EICCPUSEL0_EXTINT15_Msk (0x1ul << TAL_EICCPUSEL0_EXTINT15_Pos) +#define TAL_EICCPUSEL0_EXTINT15(value) ((TAL_EICCPUSEL0_EXTINT15_Msk & ((value) << TAL_EICCPUSEL0_EXTINT15_Pos))) +#define TAL_EICCPUSEL0_MASK 0x55555555ul /**< \brief (TAL_EICCPUSEL0) MASK Register */ + +/* -------- TAL_INTCPUSEL0 : (TAL Offset: 0x58) (R/W 32) Interrupts CPU Select 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SYSTEM:1; /*!< bit: 0 SYSTEM Interrupt CPU Select */ + uint32_t :1; /*!< bit: 1 Reserved */ + uint32_t WDT:1; /*!< bit: 2 WDT Interrupt CPU Select */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RTC:1; /*!< bit: 4 RTC Interrupt CPU Select */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t NVMCTRL:1; /*!< bit: 8 NVMCTRL Interrupt CPU Select */ + uint32_t :3; /*!< bit: 9..11 Reserved */ + uint32_t USB:1; /*!< bit: 12 USB Interrupt CPU Select */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t SERCOM0:1; /*!< bit: 16 SERCOM0 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 17 Reserved */ + uint32_t SERCOM1:1; /*!< bit: 18 SERCOM1 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t SERCOM2:1; /*!< bit: 20 SERCOM2 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 21 Reserved */ + uint32_t SERCOM3:1; /*!< bit: 22 SERCOM3 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t SERCOM4:1; /*!< bit: 24 SERCOM4 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 25 Reserved */ + uint32_t SERCOM5:1; /*!< bit: 26 SERCOM5 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t TCC0:1; /*!< bit: 28 TCC0 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t TCC1:1; /*!< bit: 30 TCC1 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TAL_INTCPUSEL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTCPUSEL0_OFFSET 0x58 /**< \brief (TAL_INTCPUSEL0 offset) Interrupts CPU Select 0 */ +#define TAL_INTCPUSEL0_RESETVALUE 0x00000000ul /**< \brief (TAL_INTCPUSEL0 reset_value) Interrupts CPU Select 0 */ + +#define TAL_INTCPUSEL0_SYSTEM_Pos 0 /**< \brief (TAL_INTCPUSEL0) SYSTEM Interrupt CPU Select */ +#define TAL_INTCPUSEL0_SYSTEM_Msk (0x1ul << TAL_INTCPUSEL0_SYSTEM_Pos) +#define TAL_INTCPUSEL0_SYSTEM(value) ((TAL_INTCPUSEL0_SYSTEM_Msk & ((value) << TAL_INTCPUSEL0_SYSTEM_Pos))) +#define TAL_INTCPUSEL0_WDT_Pos 2 /**< \brief (TAL_INTCPUSEL0) WDT Interrupt CPU Select */ +#define TAL_INTCPUSEL0_WDT_Msk (0x1ul << TAL_INTCPUSEL0_WDT_Pos) +#define TAL_INTCPUSEL0_WDT(value) ((TAL_INTCPUSEL0_WDT_Msk & ((value) << TAL_INTCPUSEL0_WDT_Pos))) +#define TAL_INTCPUSEL0_RTC_Pos 4 /**< \brief (TAL_INTCPUSEL0) RTC Interrupt CPU Select */ +#define TAL_INTCPUSEL0_RTC_Msk (0x1ul << TAL_INTCPUSEL0_RTC_Pos) +#define TAL_INTCPUSEL0_RTC(value) ((TAL_INTCPUSEL0_RTC_Msk & ((value) << TAL_INTCPUSEL0_RTC_Pos))) +#define TAL_INTCPUSEL0_NVMCTRL_Pos 8 /**< \brief (TAL_INTCPUSEL0) NVMCTRL Interrupt CPU Select */ +#define TAL_INTCPUSEL0_NVMCTRL_Msk (0x1ul << TAL_INTCPUSEL0_NVMCTRL_Pos) +#define TAL_INTCPUSEL0_NVMCTRL(value) ((TAL_INTCPUSEL0_NVMCTRL_Msk & ((value) << TAL_INTCPUSEL0_NVMCTRL_Pos))) +#define TAL_INTCPUSEL0_USB_Pos 12 /**< \brief (TAL_INTCPUSEL0) USB Interrupt CPU Select */ +#define TAL_INTCPUSEL0_USB_Msk (0x1ul << TAL_INTCPUSEL0_USB_Pos) +#define TAL_INTCPUSEL0_USB(value) ((TAL_INTCPUSEL0_USB_Msk & ((value) << TAL_INTCPUSEL0_USB_Pos))) +#define TAL_INTCPUSEL0_SERCOM0_Pos 16 /**< \brief (TAL_INTCPUSEL0) SERCOM0 Interrupt CPU Select */ +#define TAL_INTCPUSEL0_SERCOM0_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM0_Pos) +#define TAL_INTCPUSEL0_SERCOM0(value) ((TAL_INTCPUSEL0_SERCOM0_Msk & ((value) << TAL_INTCPUSEL0_SERCOM0_Pos))) +#define TAL_INTCPUSEL0_SERCOM1_Pos 18 /**< \brief (TAL_INTCPUSEL0) SERCOM1 Interrupt CPU Select */ +#define TAL_INTCPUSEL0_SERCOM1_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM1_Pos) +#define TAL_INTCPUSEL0_SERCOM1(value) ((TAL_INTCPUSEL0_SERCOM1_Msk & ((value) << TAL_INTCPUSEL0_SERCOM1_Pos))) +#define TAL_INTCPUSEL0_SERCOM2_Pos 20 /**< \brief (TAL_INTCPUSEL0) SERCOM2 Interrupt CPU Select */ +#define TAL_INTCPUSEL0_SERCOM2_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM2_Pos) +#define TAL_INTCPUSEL0_SERCOM2(value) ((TAL_INTCPUSEL0_SERCOM2_Msk & ((value) << TAL_INTCPUSEL0_SERCOM2_Pos))) +#define TAL_INTCPUSEL0_SERCOM3_Pos 22 /**< \brief (TAL_INTCPUSEL0) SERCOM3 Interrupt CPU Select */ +#define TAL_INTCPUSEL0_SERCOM3_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM3_Pos) +#define TAL_INTCPUSEL0_SERCOM3(value) ((TAL_INTCPUSEL0_SERCOM3_Msk & ((value) << TAL_INTCPUSEL0_SERCOM3_Pos))) +#define TAL_INTCPUSEL0_SERCOM4_Pos 24 /**< \brief (TAL_INTCPUSEL0) SERCOM4 Interrupt CPU Select */ +#define TAL_INTCPUSEL0_SERCOM4_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM4_Pos) +#define TAL_INTCPUSEL0_SERCOM4(value) ((TAL_INTCPUSEL0_SERCOM4_Msk & ((value) << TAL_INTCPUSEL0_SERCOM4_Pos))) +#define TAL_INTCPUSEL0_SERCOM5_Pos 26 /**< \brief (TAL_INTCPUSEL0) SERCOM5 Interrupt CPU Select */ +#define TAL_INTCPUSEL0_SERCOM5_Msk (0x1ul << TAL_INTCPUSEL0_SERCOM5_Pos) +#define TAL_INTCPUSEL0_SERCOM5(value) ((TAL_INTCPUSEL0_SERCOM5_Msk & ((value) << TAL_INTCPUSEL0_SERCOM5_Pos))) +#define TAL_INTCPUSEL0_TCC0_Pos 28 /**< \brief (TAL_INTCPUSEL0) TCC0 Interrupt CPU Select */ +#define TAL_INTCPUSEL0_TCC0_Msk (0x1ul << TAL_INTCPUSEL0_TCC0_Pos) +#define TAL_INTCPUSEL0_TCC0(value) ((TAL_INTCPUSEL0_TCC0_Msk & ((value) << TAL_INTCPUSEL0_TCC0_Pos))) +#define TAL_INTCPUSEL0_TCC1_Pos 30 /**< \brief (TAL_INTCPUSEL0) TCC1 Interrupt CPU Select */ +#define TAL_INTCPUSEL0_TCC1_Msk (0x1ul << TAL_INTCPUSEL0_TCC1_Pos) +#define TAL_INTCPUSEL0_TCC1(value) ((TAL_INTCPUSEL0_TCC1_Msk & ((value) << TAL_INTCPUSEL0_TCC1_Pos))) +#define TAL_INTCPUSEL0_MASK 0x55551115ul /**< \brief (TAL_INTCPUSEL0) MASK Register */ + +/* -------- TAL_INTCPUSEL1 : (TAL Offset: 0x5C) (R/W 32) Interrupts CPU Select 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TCC2:1; /*!< bit: 0 TCC2 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 1 Reserved */ + uint32_t TC0:1; /*!< bit: 2 TC0 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t TC1:1; /*!< bit: 4 TC1 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t TC2:1; /*!< bit: 6 TC2 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TC3:1; /*!< bit: 8 TC3 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 9 Reserved */ + uint32_t TC4:1; /*!< bit: 10 TC4 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t ADC:1; /*!< bit: 12 ADC Interrupt CPU Select */ + uint32_t :1; /*!< bit: 13 Reserved */ + uint32_t AC:1; /*!< bit: 14 AC Interrupt CPU Select */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t DAC:1; /*!< bit: 16 DAC Interrupt CPU Select */ + uint32_t :1; /*!< bit: 17 Reserved */ + uint32_t PTC:1; /*!< bit: 18 PTC Interrupt CPU Select */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t AES:1; /*!< bit: 20 AES Interrupt CPU Select */ + uint32_t :1; /*!< bit: 21 Reserved */ + uint32_t TRNG:1; /*!< bit: 22 TRNG Interrupt CPU Select */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t PICOP:1; /*!< bit: 24 PICOP Interrupt CPU Select */ + uint32_t :7; /*!< bit: 25..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TAL_INTCPUSEL1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTCPUSEL1_OFFSET 0x5C /**< \brief (TAL_INTCPUSEL1 offset) Interrupts CPU Select 1 */ +#define TAL_INTCPUSEL1_RESETVALUE 0x00000000ul /**< \brief (TAL_INTCPUSEL1 reset_value) Interrupts CPU Select 1 */ + +#define TAL_INTCPUSEL1_TCC2_Pos 0 /**< \brief (TAL_INTCPUSEL1) TCC2 Interrupt CPU Select */ +#define TAL_INTCPUSEL1_TCC2_Msk (0x1ul << TAL_INTCPUSEL1_TCC2_Pos) +#define TAL_INTCPUSEL1_TCC2(value) ((TAL_INTCPUSEL1_TCC2_Msk & ((value) << TAL_INTCPUSEL1_TCC2_Pos))) +#define TAL_INTCPUSEL1_TC0_Pos 2 /**< \brief (TAL_INTCPUSEL1) TC0 Interrupt CPU Select */ +#define TAL_INTCPUSEL1_TC0_Msk (0x1ul << TAL_INTCPUSEL1_TC0_Pos) +#define TAL_INTCPUSEL1_TC0(value) ((TAL_INTCPUSEL1_TC0_Msk & ((value) << TAL_INTCPUSEL1_TC0_Pos))) +#define TAL_INTCPUSEL1_TC1_Pos 4 /**< \brief (TAL_INTCPUSEL1) TC1 Interrupt CPU Select */ +#define TAL_INTCPUSEL1_TC1_Msk (0x1ul << TAL_INTCPUSEL1_TC1_Pos) +#define TAL_INTCPUSEL1_TC1(value) ((TAL_INTCPUSEL1_TC1_Msk & ((value) << TAL_INTCPUSEL1_TC1_Pos))) +#define TAL_INTCPUSEL1_TC2_Pos 6 /**< \brief (TAL_INTCPUSEL1) TC2 Interrupt CPU Select */ +#define TAL_INTCPUSEL1_TC2_Msk (0x1ul << TAL_INTCPUSEL1_TC2_Pos) +#define TAL_INTCPUSEL1_TC2(value) ((TAL_INTCPUSEL1_TC2_Msk & ((value) << TAL_INTCPUSEL1_TC2_Pos))) +#define TAL_INTCPUSEL1_TC3_Pos 8 /**< \brief (TAL_INTCPUSEL1) TC3 Interrupt CPU Select */ +#define TAL_INTCPUSEL1_TC3_Msk (0x1ul << TAL_INTCPUSEL1_TC3_Pos) +#define TAL_INTCPUSEL1_TC3(value) ((TAL_INTCPUSEL1_TC3_Msk & ((value) << TAL_INTCPUSEL1_TC3_Pos))) +#define TAL_INTCPUSEL1_TC4_Pos 10 /**< \brief (TAL_INTCPUSEL1) TC4 Interrupt CPU Select */ +#define TAL_INTCPUSEL1_TC4_Msk (0x1ul << TAL_INTCPUSEL1_TC4_Pos) +#define TAL_INTCPUSEL1_TC4(value) ((TAL_INTCPUSEL1_TC4_Msk & ((value) << TAL_INTCPUSEL1_TC4_Pos))) +#define TAL_INTCPUSEL1_ADC_Pos 12 /**< \brief (TAL_INTCPUSEL1) ADC Interrupt CPU Select */ +#define TAL_INTCPUSEL1_ADC_Msk (0x1ul << TAL_INTCPUSEL1_ADC_Pos) +#define TAL_INTCPUSEL1_ADC(value) ((TAL_INTCPUSEL1_ADC_Msk & ((value) << TAL_INTCPUSEL1_ADC_Pos))) +#define TAL_INTCPUSEL1_AC_Pos 14 /**< \brief (TAL_INTCPUSEL1) AC Interrupt CPU Select */ +#define TAL_INTCPUSEL1_AC_Msk (0x1ul << TAL_INTCPUSEL1_AC_Pos) +#define TAL_INTCPUSEL1_AC(value) ((TAL_INTCPUSEL1_AC_Msk & ((value) << TAL_INTCPUSEL1_AC_Pos))) +#define TAL_INTCPUSEL1_DAC_Pos 16 /**< \brief (TAL_INTCPUSEL1) DAC Interrupt CPU Select */ +#define TAL_INTCPUSEL1_DAC_Msk (0x1ul << TAL_INTCPUSEL1_DAC_Pos) +#define TAL_INTCPUSEL1_DAC(value) ((TAL_INTCPUSEL1_DAC_Msk & ((value) << TAL_INTCPUSEL1_DAC_Pos))) +#define TAL_INTCPUSEL1_PTC_Pos 18 /**< \brief (TAL_INTCPUSEL1) PTC Interrupt CPU Select */ +#define TAL_INTCPUSEL1_PTC_Msk (0x1ul << TAL_INTCPUSEL1_PTC_Pos) +#define TAL_INTCPUSEL1_PTC(value) ((TAL_INTCPUSEL1_PTC_Msk & ((value) << TAL_INTCPUSEL1_PTC_Pos))) +#define TAL_INTCPUSEL1_AES_Pos 20 /**< \brief (TAL_INTCPUSEL1) AES Interrupt CPU Select */ +#define TAL_INTCPUSEL1_AES_Msk (0x1ul << TAL_INTCPUSEL1_AES_Pos) +#define TAL_INTCPUSEL1_AES(value) ((TAL_INTCPUSEL1_AES_Msk & ((value) << TAL_INTCPUSEL1_AES_Pos))) +#define TAL_INTCPUSEL1_TRNG_Pos 22 /**< \brief (TAL_INTCPUSEL1) TRNG Interrupt CPU Select */ +#define TAL_INTCPUSEL1_TRNG_Msk (0x1ul << TAL_INTCPUSEL1_TRNG_Pos) +#define TAL_INTCPUSEL1_TRNG(value) ((TAL_INTCPUSEL1_TRNG_Msk & ((value) << TAL_INTCPUSEL1_TRNG_Pos))) +#define TAL_INTCPUSEL1_PICOP_Pos 24 /**< \brief (TAL_INTCPUSEL1) PICOP Interrupt CPU Select */ +#define TAL_INTCPUSEL1_PICOP_Msk (0x1ul << TAL_INTCPUSEL1_PICOP_Pos) +#define TAL_INTCPUSEL1_PICOP(value) ((TAL_INTCPUSEL1_PICOP_Msk & ((value) << TAL_INTCPUSEL1_PICOP_Pos))) +#define TAL_INTCPUSEL1_MASK 0x01555555ul /**< \brief (TAL_INTCPUSEL1) MASK Register */ + +/* -------- TAL_IRQTRIG : (TAL Offset: 0x60) (R/W 16) Interrupt Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ENABLE:1; /*!< bit: 0 Trigger Enable */ + uint16_t IRQNUM:5; /*!< bit: 1.. 5 Interrupt Request Number */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t OVERRIDE:8; /*!< bit: 8..15 Interrupt Request Override Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TAL_IRQTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_IRQTRIG_OFFSET 0x60 /**< \brief (TAL_IRQTRIG offset) Interrupt Trigger */ +#define TAL_IRQTRIG_RESETVALUE 0x0000ul /**< \brief (TAL_IRQTRIG reset_value) Interrupt Trigger */ + +#define TAL_IRQTRIG_ENABLE_Pos 0 /**< \brief (TAL_IRQTRIG) Trigger Enable */ +#define TAL_IRQTRIG_ENABLE (0x1ul << TAL_IRQTRIG_ENABLE_Pos) +#define TAL_IRQTRIG_IRQNUM_Pos 1 /**< \brief (TAL_IRQTRIG) Interrupt Request Number */ +#define TAL_IRQTRIG_IRQNUM_Msk (0x1Ful << TAL_IRQTRIG_IRQNUM_Pos) +#define TAL_IRQTRIG_IRQNUM(value) ((TAL_IRQTRIG_IRQNUM_Msk & ((value) << TAL_IRQTRIG_IRQNUM_Pos))) +#define TAL_IRQTRIG_OVERRIDE_Pos 8 /**< \brief (TAL_IRQTRIG) Interrupt Request Override Value */ +#define TAL_IRQTRIG_OVERRIDE_Msk (0xFFul << TAL_IRQTRIG_OVERRIDE_Pos) +#define TAL_IRQTRIG_OVERRIDE(value) ((TAL_IRQTRIG_OVERRIDE_Msk & ((value) << TAL_IRQTRIG_OVERRIDE_Pos))) +#define TAL_IRQTRIG_MASK 0xFF3Ful /**< \brief (TAL_IRQTRIG) MASK Register */ + +/** \brief TalCtis hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO TAL_CTICTRLA_Type CTICTRLA; /**< \brief Offset: 0x00 (R/W 8) Cross-Trigger Interface n Control A */ + __IO TAL_CTIMASK_Type CTIMASK; /**< \brief Offset: 0x01 (R/W 8) Cross-Trigger Interface n Mask */ +} TalCtis; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief TAL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO TAL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + RoReg8 Reserved1[0x3]; + __IO TAL_RSTCTRL_Type RSTCTRL; /**< \brief Offset: 0x04 (R/W 8) Reset Control */ + __IO TAL_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x05 (R/W 8) External Break Control */ + __IO TAL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 8) Event Control */ + RoReg8 Reserved2[0x1]; + __IO TAL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ + __IO TAL_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ + __IO TAL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ + __IO TAL_GLOBMASK_Type GLOBMASK; /**< \brief Offset: 0x0B (R/W 8) Global Break Requests Mask */ + __O TAL_HALT_Type HALT; /**< \brief Offset: 0x0C ( /W 8) Debug Halt Request */ + __O TAL_RESTART_Type RESTART; /**< \brief Offset: 0x0D ( /W 8) Debug Restart Request */ + __I TAL_BRKSTATUS_Type BRKSTATUS; /**< \brief Offset: 0x0E (R/ 16) Break Request Status */ + TalCtis Ctis[4]; /**< \brief Offset: 0x10 TalCtis groups [CTI_NUM] */ + RoReg8 Reserved3[0x8]; + __I TAL_INTSTATUS_Type INTSTATUS[29]; /**< \brief Offset: 0x20 (R/ 8) Interrupt n Status */ + RoReg8 Reserved4[0x3]; + __IO TAL_DMACPUSEL0_Type DMACPUSEL0; /**< \brief Offset: 0x40 (R/W 32) DMA Channel Interrupts CPU Select 0 */ + RoReg8 Reserved5[0x4]; + __IO TAL_EVCPUSEL0_Type EVCPUSEL0; /**< \brief Offset: 0x48 (R/W 32) EVSYS Channel Interrupts CPU Select 0 */ + RoReg8 Reserved6[0x4]; + __IO TAL_EICCPUSEL0_Type EICCPUSEL0; /**< \brief Offset: 0x50 (R/W 32) EIC External Interrupts CPU Select 0 */ + RoReg8 Reserved7[0x4]; + __IO TAL_INTCPUSEL0_Type INTCPUSEL0; /**< \brief Offset: 0x58 (R/W 32) Interrupts CPU Select 0 */ + __IO TAL_INTCPUSEL1_Type INTCPUSEL1; /**< \brief Offset: 0x5C (R/W 32) Interrupts CPU Select 1 */ + __IO TAL_IRQTRIG_Type IRQTRIG; /**< \brief Offset: 0x60 (R/W 16) Interrupt Trigger */ +} Tal; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_TAL_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tc.h new file mode 100644 index 0000000000..9a9a1c93bc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tc.h @@ -0,0 +1,846 @@ +/** + * \file + * + * \brief Component description for TC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TC_COMPONENT_ +#define _SAML21_TC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR TC */ +/* ========================================================================== */ +/** \addtogroup SAML21_TC Basic Timer Counter */ +/*@{*/ + +#define TC_U2249 +#define REV_TC 0x200 + +/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */ + uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */ + uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */ + uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */ + uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ +#define TC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TC_CTRLA reset_value) Control A */ + +#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ +#define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos) +#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ +#define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos) +#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */ +#define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos) +#define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))) +#define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */ +#define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */ +#define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */ +#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) +#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) +#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) +#define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ +#define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos) +#define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))) +#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */ +#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */ +#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */ +#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) +#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) +#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) +#define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */ +#define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos) +#define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */ +#define TC_CTRLA_ONDEMAND (0x1ul << TC_CTRLA_ONDEMAND_Pos) +#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ +#define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))) +#define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */ +#define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */ +#define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */ +#define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */ +#define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */ +#define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */ +#define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */ +#define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */ +#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */ +#define TC_CTRLA_ALOCK (0x1ul << TC_CTRLA_ALOCK_Pos) +#define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */ +#define TC_CTRLA_CAPTEN0 (1 << TC_CTRLA_CAPTEN0_Pos) +#define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */ +#define TC_CTRLA_CAPTEN1 (1 << TC_CTRLA_CAPTEN1_Pos) +#define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */ +#define TC_CTRLA_CAPTEN_Msk (0x3ul << TC_CTRLA_CAPTEN_Pos) +#define TC_CTRLA_CAPTEN(value) ((TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))) +#define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */ +#define TC_CTRLA_COPEN0 (1 << TC_CTRLA_COPEN0_Pos) +#define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */ +#define TC_CTRLA_COPEN1 (1 << TC_CTRLA_COPEN1_Pos) +#define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */ +#define TC_CTRLA_COPEN_Msk (0x3ul << TC_CTRLA_COPEN_Pos) +#define TC_CTRLA_COPEN(value) ((TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))) +#define TC_CTRLA_MASK 0x00330FFFul /**< \brief (TC_CTRLA) MASK Register */ + +/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ + uint8_t :2; /*!< bit: 3.. 4 Reserved */ + uint8_t CMD:3; /*!< bit: 5.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_CTRLBCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ +#define TC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ + +#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ +#define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos) +#define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */ +#define TC_CTRLBCLR_LUPD (0x1ul << TC_CTRLBCLR_LUPD_Pos) +#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */ +#define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos) +#define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */ +#define TC_CTRLBCLR_CMD_Msk (0x7ul << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))) +#define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */ +#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */ +#define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */ +#define TC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */ +#define TC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */ +#define TC_CTRLBCLR_CMD_DMATRG_Val 0x5ul /**< \brief (TC_CTRLBCLR) Generate DMA triggers */ +#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_CMD_DMATRG (TC_CTRLBCLR_CMD_DMATRG_Val << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_MASK 0xE7ul /**< \brief (TC_CTRLBCLR) MASK Register */ + +/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ + uint8_t :2; /*!< bit: 3.. 4 Reserved */ + uint8_t CMD:3; /*!< bit: 5.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_CTRLBSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ +#define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */ + +#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ +#define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos) +#define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */ +#define TC_CTRLBSET_LUPD (0x1ul << TC_CTRLBSET_LUPD_Pos) +#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */ +#define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos) +#define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */ +#define TC_CTRLBSET_CMD_Msk (0x7ul << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))) +#define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */ +#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */ +#define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */ +#define TC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TC_CTRLBSET) Force update of double-buffered register */ +#define TC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */ +#define TC_CTRLBSET_CMD_DMATRG_Val 0x5ul /**< \brief (TC_CTRLBSET) Generate DMA triggers */ +#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_CMD_DMATRG (TC_CTRLBSET_CMD_DMATRG_Val << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_MASK 0xE7ul /**< \brief (TC_CTRLBSET) MASK Register */ + +/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */ + uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */ + uint16_t :3; /*!< bit: 9..11 Reserved */ + uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */ + uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :12; /*!< bit: 0..11 Reserved */ + uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */ +#define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */ + +#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ +#define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))) +#define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */ +#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ +#define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */ +#define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */ +#define TC_EVCTRL_EVACT_STAMP_Val 0x4ul /**< \brief (TC_EVCTRL) Time stamp capture */ +#define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */ +#define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */ +#define TC_EVCTRL_EVACT_PW_Val 0x7ul /**< \brief (TC_EVCTRL) Pulse width capture */ +#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */ +#define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos) +#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */ +#define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos) +#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */ +#define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos) +#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */ +#define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos) +#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */ +#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos) +#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */ +#define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos) +#define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))) +#define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */ + +/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */ + uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */ + uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ +#define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */ +#define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos) +#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */ +#define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos) +#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */ +#define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos) +#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */ +#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos) +#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */ +#define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos) +#define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))) +#define TC_INTENCLR_MASK 0x33ul /**< \brief (TC_INTENCLR) MASK Register */ + +/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */ + uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */ + uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ +#define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ + +#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */ +#define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos) +#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */ +#define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos) +#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */ +#define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos) +#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */ +#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos) +#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */ +#define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos) +#define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))) +#define TC_INTENSET_MASK 0x33ul /**< \brief (TC_INTENSET) MASK Register */ + +/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */ + uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */ + uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */ +#define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos) +#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */ +#define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos) +#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */ +#define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos) +#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */ +#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos) +#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */ +#define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos) +#define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))) +#define TC_INTFLAG_MASK 0x33ul /**< \brief (TC_INTFLAG) MASK Register */ + +/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */ + uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */ + uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */ + uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */ +#define TC_STATUS_RESETVALUE 0x01ul /**< \brief (TC_STATUS reset_value) Status */ + +#define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */ +#define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos) +#define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */ +#define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos) +#define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */ +#define TC_STATUS_PERBUFV (0x1ul << TC_STATUS_PERBUFV_Pos) +#define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */ +#define TC_STATUS_CCBUFV0 (1 << TC_STATUS_CCBUFV0_Pos) +#define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */ +#define TC_STATUS_CCBUFV1 (1 << TC_STATUS_CCBUFV1_Pos) +#define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */ +#define TC_STATUS_CCBUFV_Msk (0x3ul << TC_STATUS_CCBUFV_Pos) +#define TC_STATUS_CCBUFV(value) ((TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))) +#define TC_STATUS_MASK 0x3Bul /**< \brief (TC_STATUS) MASK Register */ + +/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_WAVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */ +#define TC_WAVE_RESETVALUE 0x00ul /**< \brief (TC_WAVE reset_value) Waveform Generation Control */ + +#define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */ +#define TC_WAVE_WAVEGEN_Msk (0x3ul << TC_WAVE_WAVEGEN_Pos) +#define TC_WAVE_WAVEGEN(value) ((TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))) +#define TC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_WAVE) Normal frequency */ +#define TC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_WAVE) Match frequency */ +#define TC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_WAVE) Normal PWM */ +#define TC_WAVE_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_WAVE) Match PWM */ +#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos) +#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos) +#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos) +#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos) +#define TC_WAVE_MASK 0x03ul /**< \brief (TC_WAVE) MASK Register */ + +/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */ + uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TC_DRVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */ +#define TC_DRVCTRL_RESETVALUE 0x00ul /**< \brief (TC_DRVCTRL reset_value) Control C */ + +#define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */ +#define TC_DRVCTRL_INVEN0 (1 << TC_DRVCTRL_INVEN0_Pos) +#define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */ +#define TC_DRVCTRL_INVEN1 (1 << TC_DRVCTRL_INVEN1_Pos) +#define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */ +#define TC_DRVCTRL_INVEN_Msk (0x3ul << TC_DRVCTRL_INVEN_Pos) +#define TC_DRVCTRL_INVEN(value) ((TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))) +#define TC_DRVCTRL_MASK 0x03ul /**< \brief (TC_DRVCTRL) MASK Register */ + +/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */ +#define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */ + +#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */ +#define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos) +#define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */ + +/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 swrst */ + uint32_t ENABLE:1; /*!< bit: 1 enable */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB */ + uint32_t STATUS:1; /*!< bit: 3 STATUS */ + uint32_t COUNT:1; /*!< bit: 4 Counter */ + uint32_t PER:1; /*!< bit: 5 Period */ + uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */ + uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :6; /*!< bit: 0.. 5 Reserved */ + uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */ +#define TC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */ + +#define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */ +#define TC_SYNCBUSY_SWRST (0x1ul << TC_SYNCBUSY_SWRST_Pos) +#define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */ +#define TC_SYNCBUSY_ENABLE (0x1ul << TC_SYNCBUSY_ENABLE_Pos) +#define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */ +#define TC_SYNCBUSY_CTRLB (0x1ul << TC_SYNCBUSY_CTRLB_Pos) +#define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */ +#define TC_SYNCBUSY_STATUS (0x1ul << TC_SYNCBUSY_STATUS_Pos) +#define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */ +#define TC_SYNCBUSY_COUNT (0x1ul << TC_SYNCBUSY_COUNT_Pos) +#define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */ +#define TC_SYNCBUSY_PER (0x1ul << TC_SYNCBUSY_PER_Pos) +#define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */ +#define TC_SYNCBUSY_CC0 (1 << TC_SYNCBUSY_CC0_Pos) +#define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */ +#define TC_SYNCBUSY_CC1 (1 << TC_SYNCBUSY_CC1_Pos) +#define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */ +#define TC_SYNCBUSY_CC_Msk (0x3ul << TC_SYNCBUSY_CC_Pos) +#define TC_SYNCBUSY_CC(value) ((TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))) +#define TC_SYNCBUSY_MASK 0x000000FFul /**< \brief (TC_SYNCBUSY) MASK Register */ + +/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TC_COUNT16_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */ +#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */ + +#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */ +#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos) +#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))) +#define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */ + +/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TC_COUNT32_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */ +#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */ + +#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */ +#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos) +#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))) +#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */ + +/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_COUNT8_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */ +#define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */ + +#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ +#define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos) +#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))) +#define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */ + +/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_COUNT8_PER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */ +#define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */ + +#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ +#define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos) +#define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))) +#define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */ + +/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TC_COUNT16_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */ +#define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */ + +#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */ +#define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos) +#define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))) +#define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */ + +/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TC_COUNT32_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */ +#define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */ + +#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */ +#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos) +#define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))) +#define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */ + +/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_COUNT8_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */ +#define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */ + +#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */ +#define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos) +#define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))) +#define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */ + +/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PERB:8; /*!< bit: 0.. 7 Period Buffer Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_COUNT8_PERBUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */ +#define TC_COUNT8_PERBUF_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */ + +#define TC_COUNT8_PERBUF_PERB_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */ +#define TC_COUNT8_PERBUF_PERB_Msk (0xFFul << TC_COUNT8_PERBUF_PERB_Pos) +#define TC_COUNT8_PERBUF_PERB(value) ((TC_COUNT8_PERBUF_PERB_Msk & ((value) << TC_COUNT8_PERBUF_PERB_Pos))) +#define TC_COUNT8_PERBUF_MASK 0xFFul /**< \brief (TC_COUNT8_PERBUF) MASK Register */ + +/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TC_COUNT16_CCBUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */ +#define TC_COUNT16_CCBUF_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */ + +#define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */ +#define TC_COUNT16_CCBUF_CCBUF_Msk (0xFFFFul << TC_COUNT16_CCBUF_CCBUF_Pos) +#define TC_COUNT16_CCBUF_CCBUF(value) ((TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))) +#define TC_COUNT16_CCBUF_MASK 0xFFFFul /**< \brief (TC_COUNT16_CCBUF) MASK Register */ + +/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TC_COUNT32_CCBUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */ +#define TC_COUNT32_CCBUF_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */ + +#define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */ +#define TC_COUNT32_CCBUF_CCBUF_Msk (0xFFFFFFFFul << TC_COUNT32_CCBUF_CCBUF_Pos) +#define TC_COUNT32_CCBUF_CCBUF(value) ((TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))) +#define TC_COUNT32_CCBUF_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CCBUF) MASK Register */ + +/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_COUNT8_CCBUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */ +#define TC_COUNT8_CCBUF_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */ + +#define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */ +#define TC_COUNT8_CCBUF_CCBUF_Msk (0xFFul << TC_COUNT8_CCBUF_CCBUF_Pos) +#define TC_COUNT8_CCBUF_CCBUF(value) ((TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))) +#define TC_COUNT8_CCBUF_MASK 0xFFul /**< \brief (TC_COUNT8_CCBUF) MASK Register */ + +/** \brief TC_COUNT8 hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* 8-bit Counter Mode */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ + __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ + __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ + __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ + __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ + __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */ + RoReg8 Reserved2[0x6]; + __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */ + __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */ + RoReg8 Reserved3[0x11]; + __IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */ + __IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */ +} TcCount8; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief TC_COUNT16 hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* 16-bit Counter Mode */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ + __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ + __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ + __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ + __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ + __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */ + RoReg8 Reserved2[0x6]; + __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */ + RoReg8 Reserved3[0x10]; + __IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */ +} TcCount16; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief TC_COUNT32 hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* 32-bit Counter Mode */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ + __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ + __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ + __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ + __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ + __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */ + RoReg8 Reserved2[0x4]; + __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */ + RoReg8 Reserved3[0xC]; + __IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */ +} TcCount32; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ + TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ + TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_TC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tcc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tcc.h new file mode 100644 index 0000000000..3730a728f3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_tcc.h @@ -0,0 +1,1828 @@ +/** + * \file + * + * \brief Component description for TCC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TCC_COMPONENT_ +#define _SAML21_TCC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR TCC */ +/* ========================================================================== */ +/** \addtogroup SAML21_TCC Timer Counter Control */ +/*@{*/ + +#define TCC_U2213 +#define REV_TCC 0x300 + +/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t :3; /*!< bit: 2.. 4 Reserved */ + uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ + uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ + uint32_t MSYNC:1; /*!< bit: 15 Master Synchronization (only for TCC Slave Instance) */ + uint32_t :7; /*!< bit: 16..22 Reserved */ + uint32_t DTRG:1; /*!< bit: 23 DMA Trigger Mode */ + uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ + uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ + uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ + uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :24; /*!< bit: 0..23 Reserved */ + uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ +#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */ + +#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ +#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos) +#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ +#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos) +#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ +#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))) +#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */ +#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ +#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ +#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ +#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ +#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))) +#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */ +#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */ +#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */ +#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */ +#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */ +#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */ +#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */ +#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */ +#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ +#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos) +#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ +#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))) +#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ +#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ +#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ +#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ +#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos) +#define TCC_CTRLA_MSYNC_Pos 15 /**< \brief (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) */ +#define TCC_CTRLA_MSYNC (0x1ul << TCC_CTRLA_MSYNC_Pos) +#define TCC_CTRLA_DTRG_Pos 23 /**< \brief (TCC_CTRLA) DMA Trigger Mode */ +#define TCC_CTRLA_DTRG (0x1ul << TCC_CTRLA_DTRG_Pos) +#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ +#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos) +#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ +#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos) +#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ +#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos) +#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ +#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos) +#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ +#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos) +#define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))) +#define TCC_CTRLA_MASK 0x0F80FF63ul /**< \brief (TCC_CTRLA) MASK Register */ + +/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_CTRLBCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ +#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ + +#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ +#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos) +#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ +#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos) +#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ +#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos) +#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ +#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))) +#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ +#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ +#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ +#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ +#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ +#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))) +#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */ +#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ +#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */ +#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update or double buffered registers */ +#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ +#define TCC_CTRLBCLR_CMD_DMATRG_Val 0x5ul /**< \brief (TCC_CTRLBCLR) Generate DMA triggers */ +#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_DMATRG (TCC_CTRLBCLR_CMD_DMATRG_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */ + +/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_CTRLBSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ +#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ + +#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ +#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos) +#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ +#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos) +#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ +#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos) +#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ +#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))) +#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ +#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ +#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ +#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ +#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ +#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))) +#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */ +#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ +#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */ +#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update or double buffered registers */ +#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ +#define TCC_CTRLBSET_CMD_DMATRG_Val 0x5ul /**< \brief (TCC_CTRLBSET) Generate DMA triggers */ +#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_DMATRG (TCC_CTRLBSET_CMD_DMATRG_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */ + +/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ + uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ + uint32_t STATUS:1; /*!< bit: 3 Status Busy */ + uint32_t COUNT:1; /*!< bit: 4 Count Busy */ + uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ + uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ + uint32_t PER:1; /*!< bit: 7 Period Busy */ + uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ + uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ + uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ + uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ +#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ + +#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ +#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos) +#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ +#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos) +#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ +#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos) +#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ +#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos) +#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ +#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos) +#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ +#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos) +#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ +#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos) +#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period Busy */ +#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos) +#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ +#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos) +#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ +#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos) +#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ +#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos) +#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ +#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos) +#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ +#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos) +#define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))) +#define TCC_SYNCBUSY_MASK 0x00000FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */ + +/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ + uint32_t BLANKPRESC:1; /*!< bit: 15 Fault A Blanking Prescaler */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_FCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ +#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ + +#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ +#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))) +#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */ +#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ +#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ +#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ +#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ +#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos) +#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ +#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos) +#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ +#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))) +#define TCC_FCTRLA_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLA) Blanking applied from start of the ramp */ +#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ +#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ +#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ +#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ +#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos) +#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ +#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))) +#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */ +#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */ +#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */ +#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */ +#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ +#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))) +#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ +#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ +#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ +#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ +#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ +#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))) +#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */ +#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */ +#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */ +#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */ +#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */ +#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */ +#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ +#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */ +#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLA) Fault A Blanking Prescaler */ +#define TCC_FCTRLA_BLANKPRESC (0x1ul << TCC_FCTRLA_BLANKPRESC_Pos) +#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ +#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos) +#define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))) +#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ +#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos) +#define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))) +#define TCC_FCTRLA_MASK 0x0FFFFFFBul /**< \brief (TCC_FCTRLA) MASK Register */ + +/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ + uint32_t BLANKPRESC:1; /*!< bit: 15 Fault B Blanking Prescaler */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_FCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ +#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ + +#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ +#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))) +#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */ +#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ +#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ +#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ +#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ +#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos) +#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ +#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos) +#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ +#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))) +#define TCC_FCTRLB_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLB) Blanking applied from start of the ramp */ +#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ +#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ +#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ +#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ +#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos) +#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ +#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))) +#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */ +#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */ +#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */ +#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */ +#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ +#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))) +#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ +#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ +#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ +#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ +#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ +#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))) +#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */ +#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */ +#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */ +#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */ +#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */ +#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */ +#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ +#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */ +#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLB) Fault B Blanking Prescaler */ +#define TCC_FCTRLB_BLANKPRESC (0x1ul << TCC_FCTRLB_BLANKPRESC_Pos) +#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ +#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos) +#define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))) +#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ +#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos) +#define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))) +#define TCC_FCTRLB_MASK 0x0FFFFFFBul /**< \brief (TCC_FCTRLB) MASK Register */ + +/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ + uint32_t :6; /*!< bit: 2.. 7 Reserved */ + uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ + uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ + uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ + uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ + uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WEXCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ +#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ + +#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ +#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos) +#define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))) +#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ +#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos) +#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ +#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos) +#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ +#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos) +#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ +#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos) +#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ +#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos) +#define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))) +#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ +#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos) +#define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))) +#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ +#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos) +#define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))) +#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */ + +/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ + uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ + uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ + uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ + uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ + uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ + uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ + uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ + uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ + uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ + uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ + uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ + uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ + uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ + uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ + uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ + uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ + uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ + uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ + uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ + uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ + uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ + uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ + uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ + uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ + uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ + uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ + uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_DRVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ +#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ + +#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ +#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos) +#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ +#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos) +#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ +#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos) +#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ +#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos) +#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ +#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos) +#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ +#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos) +#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ +#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos) +#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ +#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos) +#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ +#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos) +#define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))) +#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ +#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos) +#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ +#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos) +#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ +#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos) +#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ +#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos) +#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ +#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos) +#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ +#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos) +#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ +#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos) +#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ +#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos) +#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ +#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos) +#define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))) +#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ +#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos) +#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ +#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos) +#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ +#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos) +#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ +#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos) +#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ +#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos) +#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ +#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos) +#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ +#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos) +#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ +#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos) +#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ +#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos) +#define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))) +#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ +#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos) +#define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))) +#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ +#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos) +#define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))) +#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */ + +/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ +#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ + +#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ +#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos) +#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ +#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos) +#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */ + +/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ + uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ + uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ + uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ + uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ + uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ + uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ + uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ + uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ + uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ + uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ + uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ + uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ + uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ + uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ + uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :12; /*!< bit: 0..11 Reserved */ + uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ + uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ + uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ +#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */ + +#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ +#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))) +#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ +#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ +#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */ +#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */ +#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */ +#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ +#define TCC_EVCTRL_EVACT0_STAMP_Val 0x6ul /**< \brief (TCC_EVCTRL) Stamp capture */ +#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ +#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ +#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))) +#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ +#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ +#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */ +#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */ +#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */ +#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ +#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ +#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ +#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ +#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))) +#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ +#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ +#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ +#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ +#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ +#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos) +#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ +#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos) +#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ +#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos) +#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ +#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos) +#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ +#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos) +#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ +#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos) +#define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))) +#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ +#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos) +#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ +#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos) +#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ +#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos) +#define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))) +#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ +#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos) +#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ +#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos) +#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ +#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos) +#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ +#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos) +#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ +#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos) +#define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))) +#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ +#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos) +#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ +#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos) +#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ +#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos) +#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ +#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos) +#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ +#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos) +#define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))) +#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */ + +/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ +#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ +#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos) +#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ +#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos) +#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ +#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos) +#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ +#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos) +#define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */ +#define TCC_INTENCLR_UFS (0x1ul << TCC_INTENCLR_UFS_Pos) +#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ +#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos) +#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ +#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos) +#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ +#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos) +#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ +#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos) +#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ +#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos) +#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ +#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos) +#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ +#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos) +#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ +#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos) +#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ +#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos) +#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ +#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos) +#define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))) +#define TCC_INTENCLR_MASK 0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */ + +/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ +#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ + +#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ +#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos) +#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ +#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos) +#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ +#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos) +#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ +#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos) +#define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */ +#define TCC_INTENSET_UFS (0x1ul << TCC_INTENSET_UFS_Pos) +#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ +#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos) +#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ +#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos) +#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ +#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos) +#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ +#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos) +#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ +#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos) +#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ +#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos) +#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ +#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos) +#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ +#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos) +#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ +#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos) +#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ +#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos) +#define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))) +#define TCC_INTENSET_MASK 0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */ + +/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow */ + uint32_t TRG:1; /*!< bit: 1 Retrigger */ + uint32_t CNT:1; /*!< bit: 2 Counter */ + uint32_t ERR:1; /*!< bit: 3 Error */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ +#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos) +#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ +#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos) +#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ +#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos) +#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ +#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos) +#define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */ +#define TCC_INTFLAG_UFS (0x1ul << TCC_INTFLAG_UFS_Pos) +#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ +#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos) +#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ +#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos) +#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ +#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos) +#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ +#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos) +#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ +#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos) +#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ +#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos) +#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ +#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos) +#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ +#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos) +#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ +#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos) +#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ +#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos) +#define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))) +#define TCC_INTFLAG_MASK 0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */ + +/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t STOP:1; /*!< bit: 0 Stop */ + uint32_t IDX:1; /*!< bit: 1 Ramp */ + uint32_t UFS:1; /*!< bit: 2 Non-recoverable Update Fault State */ + uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ + uint32_t SLAVE:1; /*!< bit: 4 Slave */ + uint32_t PATTBUFV:1; /*!< bit: 5 Pattern Buffer Valid */ + uint32_t WAVEBUFV:1; /*!< bit: 6 Wave Buffer Valid */ + uint32_t PERBUFV:1; /*!< bit: 7 Period Buffer Valid */ + uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ + uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ + uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ + uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ + uint32_t CCBUFV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ + uint32_t CCBUFV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ + uint32_t CCBUFV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ + uint32_t CCBUFV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ + uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ + uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ + uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t CCBUFV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ +#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */ + +#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ +#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos) +#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ +#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos) +#define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-recoverable Update Fault State */ +#define TCC_STATUS_UFS (0x1ul << TCC_STATUS_UFS_Pos) +#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ +#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos) +#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ +#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos) +#define TCC_STATUS_PATTBUFV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ +#define TCC_STATUS_PATTBUFV (0x1ul << TCC_STATUS_PATTBUFV_Pos) +#define TCC_STATUS_WAVEBUFV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */ +#define TCC_STATUS_WAVEBUFV (0x1ul << TCC_STATUS_WAVEBUFV_Pos) +#define TCC_STATUS_PERBUFV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ +#define TCC_STATUS_PERBUFV (0x1ul << TCC_STATUS_PERBUFV_Pos) +#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ +#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos) +#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ +#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos) +#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ +#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos) +#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ +#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos) +#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ +#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos) +#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ +#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos) +#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ +#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos) +#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ +#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos) +#define TCC_STATUS_CCBUFV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ +#define TCC_STATUS_CCBUFV0 (1 << TCC_STATUS_CCBUFV0_Pos) +#define TCC_STATUS_CCBUFV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ +#define TCC_STATUS_CCBUFV1 (1 << TCC_STATUS_CCBUFV1_Pos) +#define TCC_STATUS_CCBUFV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ +#define TCC_STATUS_CCBUFV2 (1 << TCC_STATUS_CCBUFV2_Pos) +#define TCC_STATUS_CCBUFV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ +#define TCC_STATUS_CCBUFV3 (1 << TCC_STATUS_CCBUFV3_Pos) +#define TCC_STATUS_CCBUFV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ +#define TCC_STATUS_CCBUFV_Msk (0xFul << TCC_STATUS_CCBUFV_Pos) +#define TCC_STATUS_CCBUFV(value) ((TCC_STATUS_CCBUFV_Msk & ((value) << TCC_STATUS_CCBUFV_Pos))) +#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ +#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos) +#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ +#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos) +#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ +#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos) +#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ +#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos) +#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ +#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos) +#define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))) +#define TCC_STATUS_MASK 0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */ + +/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t :6; /*!< bit: 0.. 5 Reserved */ + uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ +#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */ + +// DITH4 mode +#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ +#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos) +#define TCC_COUNT_DITH4_COUNT(value) ((TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))) +#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ +#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos) +#define TCC_COUNT_DITH5_COUNT(value) ((TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))) +#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ +#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos) +#define TCC_COUNT_DITH6_COUNT(value) ((TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))) +#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */ + +#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ +#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos) +#define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))) +#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */ + +/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ + uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ + uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ + uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ + uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ + uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ + uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ + uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ + uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ + uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ + uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ + uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ + uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ + uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ + uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ + uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ + uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TCC_PATT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ +#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */ + +#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ +#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos) +#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ +#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos) +#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ +#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos) +#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ +#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos) +#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ +#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos) +#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ +#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos) +#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ +#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos) +#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ +#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos) +#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ +#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos) +#define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))) +#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ +#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos) +#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ +#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos) +#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ +#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos) +#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ +#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos) +#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ +#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos) +#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ +#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos) +#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ +#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos) +#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ +#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos) +#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ +#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos) +#define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))) +#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */ + +/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ + uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ + uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ + uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ + uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ + uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ + uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ + uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ + uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ + uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ + uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WAVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ +#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */ + +#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ +#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))) +#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */ +#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */ +#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */ +#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */ +#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ +#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ +#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ +#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ +#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))) +#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */ +#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVE) Critical RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ +#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos) +#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ +#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos) +#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ +#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos) +#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ +#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos) +#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ +#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos) +#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ +#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos) +#define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))) +#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ +#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos) +#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ +#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos) +#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ +#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos) +#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ +#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos) +#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ +#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos) +#define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))) +#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ +#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos) +#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ +#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos) +#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ +#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos) +#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ +#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos) +#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ +#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos) +#define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))) +#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */ + +/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t PER:20; /*!< bit: 4..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t PER:19; /*!< bit: 5..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t PER:18; /*!< bit: 6..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PER:24; /*!< bit: 0..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_PER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ +#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */ + +// DITH4 mode +#define TCC_PER_DITH4_DITHER_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ +#define TCC_PER_DITH4_DITHER_Msk (0xFul << TCC_PER_DITH4_DITHER_Pos) +#define TCC_PER_DITH4_DITHER(value) ((TCC_PER_DITH4_DITHER_Msk & ((value) << TCC_PER_DITH4_DITHER_Pos))) +#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ +#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos) +#define TCC_PER_DITH4_PER(value) ((TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))) +#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_PER_DITH5_DITHER_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ +#define TCC_PER_DITH5_DITHER_Msk (0x1Ful << TCC_PER_DITH5_DITHER_Pos) +#define TCC_PER_DITH5_DITHER(value) ((TCC_PER_DITH5_DITHER_Msk & ((value) << TCC_PER_DITH5_DITHER_Pos))) +#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ +#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos) +#define TCC_PER_DITH5_PER(value) ((TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))) +#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_PER_DITH6_DITHER_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ +#define TCC_PER_DITH6_DITHER_Msk (0x3Ful << TCC_PER_DITH6_DITHER_Pos) +#define TCC_PER_DITH6_DITHER(value) ((TCC_PER_DITH6_DITHER_Msk & ((value) << TCC_PER_DITH6_DITHER_Pos))) +#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ +#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos) +#define TCC_PER_DITH6_PER(value) ((TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))) +#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */ + +#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ +#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos) +#define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))) +#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */ + +/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ +#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */ + +// DITH4 mode +#define TCC_CC_DITH4_DITHER_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ +#define TCC_CC_DITH4_DITHER_Msk (0xFul << TCC_CC_DITH4_DITHER_Pos) +#define TCC_CC_DITH4_DITHER(value) ((TCC_CC_DITH4_DITHER_Msk & ((value) << TCC_CC_DITH4_DITHER_Pos))) +#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ +#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos) +#define TCC_CC_DITH4_CC(value) ((TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))) +#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_CC_DITH5_DITHER_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ +#define TCC_CC_DITH5_DITHER_Msk (0x1Ful << TCC_CC_DITH5_DITHER_Pos) +#define TCC_CC_DITH5_DITHER(value) ((TCC_CC_DITH5_DITHER_Msk & ((value) << TCC_CC_DITH5_DITHER_Pos))) +#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ +#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos) +#define TCC_CC_DITH5_CC(value) ((TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))) +#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_CC_DITH6_DITHER_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ +#define TCC_CC_DITH6_DITHER_Msk (0x3Ful << TCC_CC_DITH6_DITHER_Pos) +#define TCC_CC_DITH6_DITHER(value) ((TCC_CC_DITH6_DITHER_Msk & ((value) << TCC_CC_DITH6_DITHER_Pos))) +#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ +#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos) +#define TCC_CC_DITH6_CC(value) ((TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))) +#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */ + +#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ +#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos) +#define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))) +#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */ + +/* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ + uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ + uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ + uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ + uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ + uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ + uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ + uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ + uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ + uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ + uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ + uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ + uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ + uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ + uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ + uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ + uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TCC_PATTBUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PATTBUF_OFFSET 0x64 /**< \brief (TCC_PATTBUF offset) Pattern Buffer */ +#define TCC_PATTBUF_RESETVALUE 0x0000ul /**< \brief (TCC_PATTBUF reset_value) Pattern Buffer */ + +#define TCC_PATTBUF_PGEB0_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer */ +#define TCC_PATTBUF_PGEB0 (1 << TCC_PATTBUF_PGEB0_Pos) +#define TCC_PATTBUF_PGEB1_Pos 1 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer */ +#define TCC_PATTBUF_PGEB1 (1 << TCC_PATTBUF_PGEB1_Pos) +#define TCC_PATTBUF_PGEB2_Pos 2 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer */ +#define TCC_PATTBUF_PGEB2 (1 << TCC_PATTBUF_PGEB2_Pos) +#define TCC_PATTBUF_PGEB3_Pos 3 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer */ +#define TCC_PATTBUF_PGEB3 (1 << TCC_PATTBUF_PGEB3_Pos) +#define TCC_PATTBUF_PGEB4_Pos 4 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer */ +#define TCC_PATTBUF_PGEB4 (1 << TCC_PATTBUF_PGEB4_Pos) +#define TCC_PATTBUF_PGEB5_Pos 5 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer */ +#define TCC_PATTBUF_PGEB5 (1 << TCC_PATTBUF_PGEB5_Pos) +#define TCC_PATTBUF_PGEB6_Pos 6 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer */ +#define TCC_PATTBUF_PGEB6 (1 << TCC_PATTBUF_PGEB6_Pos) +#define TCC_PATTBUF_PGEB7_Pos 7 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer */ +#define TCC_PATTBUF_PGEB7 (1 << TCC_PATTBUF_PGEB7_Pos) +#define TCC_PATTBUF_PGEB_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable Buffer */ +#define TCC_PATTBUF_PGEB_Msk (0xFFul << TCC_PATTBUF_PGEB_Pos) +#define TCC_PATTBUF_PGEB(value) ((TCC_PATTBUF_PGEB_Msk & ((value) << TCC_PATTBUF_PGEB_Pos))) +#define TCC_PATTBUF_PGVB0_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable */ +#define TCC_PATTBUF_PGVB0 (1 << TCC_PATTBUF_PGVB0_Pos) +#define TCC_PATTBUF_PGVB1_Pos 9 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable */ +#define TCC_PATTBUF_PGVB1 (1 << TCC_PATTBUF_PGVB1_Pos) +#define TCC_PATTBUF_PGVB2_Pos 10 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable */ +#define TCC_PATTBUF_PGVB2 (1 << TCC_PATTBUF_PGVB2_Pos) +#define TCC_PATTBUF_PGVB3_Pos 11 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable */ +#define TCC_PATTBUF_PGVB3 (1 << TCC_PATTBUF_PGVB3_Pos) +#define TCC_PATTBUF_PGVB4_Pos 12 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable */ +#define TCC_PATTBUF_PGVB4 (1 << TCC_PATTBUF_PGVB4_Pos) +#define TCC_PATTBUF_PGVB5_Pos 13 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable */ +#define TCC_PATTBUF_PGVB5 (1 << TCC_PATTBUF_PGVB5_Pos) +#define TCC_PATTBUF_PGVB6_Pos 14 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable */ +#define TCC_PATTBUF_PGVB6 (1 << TCC_PATTBUF_PGVB6_Pos) +#define TCC_PATTBUF_PGVB7_Pos 15 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable */ +#define TCC_PATTBUF_PGVB7 (1 << TCC_PATTBUF_PGVB7_Pos) +#define TCC_PATTBUF_PGVB_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable */ +#define TCC_PATTBUF_PGVB_Msk (0xFFul << TCC_PATTBUF_PGVB_Pos) +#define TCC_PATTBUF_PGVB(value) ((TCC_PATTBUF_PGVB_Msk & ((value) << TCC_PATTBUF_PGVB_Pos))) +#define TCC_PATTBUF_MASK 0xFFFFul /**< \brief (TCC_PATTBUF) MASK Register */ + +/* -------- TCC_WAVEBUF : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ + uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ + uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ + uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ + uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ + uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ + uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ + uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ + uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ + uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ + uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WAVEBUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WAVEBUF_OFFSET 0x68 /**< \brief (TCC_WAVEBUF offset) Waveform Control Buffer */ +#define TCC_WAVEBUF_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEBUF reset_value) Waveform Control Buffer */ + +#define TCC_WAVEBUF_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEBUF) Waveform Generation Buffer */ +#define TCC_WAVEBUF_WAVEGENB_Msk (0x7ul << TCC_WAVEBUF_WAVEGENB_Pos) +#define TCC_WAVEBUF_WAVEGENB(value) ((TCC_WAVEBUF_WAVEGENB_Msk & ((value) << TCC_WAVEBUF_WAVEGENB_Pos))) +#define TCC_WAVEBUF_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEBUF) Normal frequency */ +#define TCC_WAVEBUF_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEBUF) Match frequency */ +#define TCC_WAVEBUF_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEBUF) Normal PWM */ +#define TCC_WAVEBUF_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEBUF) Dual-slope critical */ +#define TCC_WAVEBUF_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEBUF) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ +#define TCC_WAVEBUF_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEBUF) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ +#define TCC_WAVEBUF_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEBUF) Dual-slope with interrupt/event condition when COUNT reaches TOP */ +#define TCC_WAVEBUF_WAVEGENB_NFRQ (TCC_WAVEBUF_WAVEGENB_NFRQ_Val << TCC_WAVEBUF_WAVEGENB_Pos) +#define TCC_WAVEBUF_WAVEGENB_MFRQ (TCC_WAVEBUF_WAVEGENB_MFRQ_Val << TCC_WAVEBUF_WAVEGENB_Pos) +#define TCC_WAVEBUF_WAVEGENB_NPWM (TCC_WAVEBUF_WAVEGENB_NPWM_Val << TCC_WAVEBUF_WAVEGENB_Pos) +#define TCC_WAVEBUF_WAVEGENB_DSCRITICAL (TCC_WAVEBUF_WAVEGENB_DSCRITICAL_Val << TCC_WAVEBUF_WAVEGENB_Pos) +#define TCC_WAVEBUF_WAVEGENB_DSBOTTOM (TCC_WAVEBUF_WAVEGENB_DSBOTTOM_Val << TCC_WAVEBUF_WAVEGENB_Pos) +#define TCC_WAVEBUF_WAVEGENB_DSBOTH (TCC_WAVEBUF_WAVEGENB_DSBOTH_Val << TCC_WAVEBUF_WAVEGENB_Pos) +#define TCC_WAVEBUF_WAVEGENB_DSTOP (TCC_WAVEBUF_WAVEGENB_DSTOP_Val << TCC_WAVEBUF_WAVEGENB_Pos) +#define TCC_WAVEBUF_RAMPB_Pos 4 /**< \brief (TCC_WAVEBUF) Ramp Mode Buffer */ +#define TCC_WAVEBUF_RAMPB_Msk (0x3ul << TCC_WAVEBUF_RAMPB_Pos) +#define TCC_WAVEBUF_RAMPB(value) ((TCC_WAVEBUF_RAMPB_Msk & ((value) << TCC_WAVEBUF_RAMPB_Pos))) +#define TCC_WAVEBUF_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEBUF) RAMP1 operation */ +#define TCC_WAVEBUF_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEBUF) Alternative RAMP2 operation */ +#define TCC_WAVEBUF_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEBUF) RAMP2 operation */ +#define TCC_WAVEBUF_RAMPB_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVEBUF) Critical RAMP2 operation */ +#define TCC_WAVEBUF_RAMPB_RAMP1 (TCC_WAVEBUF_RAMPB_RAMP1_Val << TCC_WAVEBUF_RAMPB_Pos) +#define TCC_WAVEBUF_RAMPB_RAMP2A (TCC_WAVEBUF_RAMPB_RAMP2A_Val << TCC_WAVEBUF_RAMPB_Pos) +#define TCC_WAVEBUF_RAMPB_RAMP2 (TCC_WAVEBUF_RAMPB_RAMP2_Val << TCC_WAVEBUF_RAMPB_Pos) +#define TCC_WAVEBUF_RAMPB_RAMP2C (TCC_WAVEBUF_RAMPB_RAMP2C_Val << TCC_WAVEBUF_RAMPB_Pos) +#define TCC_WAVEBUF_CIPERENB_Pos 7 /**< \brief (TCC_WAVEBUF) Circular Period Enable Buffer */ +#define TCC_WAVEBUF_CIPERENB (0x1ul << TCC_WAVEBUF_CIPERENB_Pos) +#define TCC_WAVEBUF_CICCENB0_Pos 8 /**< \brief (TCC_WAVEBUF) Circular Channel 0 Enable Buffer */ +#define TCC_WAVEBUF_CICCENB0 (1 << TCC_WAVEBUF_CICCENB0_Pos) +#define TCC_WAVEBUF_CICCENB1_Pos 9 /**< \brief (TCC_WAVEBUF) Circular Channel 1 Enable Buffer */ +#define TCC_WAVEBUF_CICCENB1 (1 << TCC_WAVEBUF_CICCENB1_Pos) +#define TCC_WAVEBUF_CICCENB2_Pos 10 /**< \brief (TCC_WAVEBUF) Circular Channel 2 Enable Buffer */ +#define TCC_WAVEBUF_CICCENB2 (1 << TCC_WAVEBUF_CICCENB2_Pos) +#define TCC_WAVEBUF_CICCENB3_Pos 11 /**< \brief (TCC_WAVEBUF) Circular Channel 3 Enable Buffer */ +#define TCC_WAVEBUF_CICCENB3 (1 << TCC_WAVEBUF_CICCENB3_Pos) +#define TCC_WAVEBUF_CICCENB_Pos 8 /**< \brief (TCC_WAVEBUF) Circular Channel x Enable Buffer */ +#define TCC_WAVEBUF_CICCENB_Msk (0xFul << TCC_WAVEBUF_CICCENB_Pos) +#define TCC_WAVEBUF_CICCENB(value) ((TCC_WAVEBUF_CICCENB_Msk & ((value) << TCC_WAVEBUF_CICCENB_Pos))) +#define TCC_WAVEBUF_POLB0_Pos 16 /**< \brief (TCC_WAVEBUF) Channel 0 Polarity Buffer */ +#define TCC_WAVEBUF_POLB0 (1 << TCC_WAVEBUF_POLB0_Pos) +#define TCC_WAVEBUF_POLB1_Pos 17 /**< \brief (TCC_WAVEBUF) Channel 1 Polarity Buffer */ +#define TCC_WAVEBUF_POLB1 (1 << TCC_WAVEBUF_POLB1_Pos) +#define TCC_WAVEBUF_POLB2_Pos 18 /**< \brief (TCC_WAVEBUF) Channel 2 Polarity Buffer */ +#define TCC_WAVEBUF_POLB2 (1 << TCC_WAVEBUF_POLB2_Pos) +#define TCC_WAVEBUF_POLB3_Pos 19 /**< \brief (TCC_WAVEBUF) Channel 3 Polarity Buffer */ +#define TCC_WAVEBUF_POLB3 (1 << TCC_WAVEBUF_POLB3_Pos) +#define TCC_WAVEBUF_POLB_Pos 16 /**< \brief (TCC_WAVEBUF) Channel x Polarity Buffer */ +#define TCC_WAVEBUF_POLB_Msk (0xFul << TCC_WAVEBUF_POLB_Pos) +#define TCC_WAVEBUF_POLB(value) ((TCC_WAVEBUF_POLB_Msk & ((value) << TCC_WAVEBUF_POLB_Pos))) +#define TCC_WAVEBUF_SWAPB0_Pos 24 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair 0 Buffer */ +#define TCC_WAVEBUF_SWAPB0 (1 << TCC_WAVEBUF_SWAPB0_Pos) +#define TCC_WAVEBUF_SWAPB1_Pos 25 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair 1 Buffer */ +#define TCC_WAVEBUF_SWAPB1 (1 << TCC_WAVEBUF_SWAPB1_Pos) +#define TCC_WAVEBUF_SWAPB2_Pos 26 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair 2 Buffer */ +#define TCC_WAVEBUF_SWAPB2 (1 << TCC_WAVEBUF_SWAPB2_Pos) +#define TCC_WAVEBUF_SWAPB3_Pos 27 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair 3 Buffer */ +#define TCC_WAVEBUF_SWAPB3 (1 << TCC_WAVEBUF_SWAPB3_Pos) +#define TCC_WAVEBUF_SWAPB_Pos 24 /**< \brief (TCC_WAVEBUF) Swap DTI Output Pair x Buffer */ +#define TCC_WAVEBUF_SWAPB_Msk (0xFul << TCC_WAVEBUF_SWAPB_Pos) +#define TCC_WAVEBUF_SWAPB(value) ((TCC_WAVEBUF_SWAPB_Msk & ((value) << TCC_WAVEBUF_SWAPB_Pos))) +#define TCC_WAVEBUF_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEBUF) MASK Register */ + +/* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERBUF:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t PERBUF:20; /*!< bit: 4..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t PERBUF:19; /*!< bit: 5..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t PERBUF:18; /*!< bit: 6..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PERBUF:24; /*!< bit: 0..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_PERBUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PERBUF_OFFSET 0x6C /**< \brief (TCC_PERBUF offset) Period Buffer */ +#define TCC_PERBUF_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERBUF reset_value) Period Buffer */ + +// DITH4 mode +#define TCC_PERBUF_DITH4_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH4) Dithering Buffer Cycle Number */ +#define TCC_PERBUF_DITH4_DITHERBUF_Msk (0xFul << TCC_PERBUF_DITH4_DITHERBUF_Pos) +#define TCC_PERBUF_DITH4_DITHERBUF(value) ((TCC_PERBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH4_DITHERBUF_Pos))) +#define TCC_PERBUF_DITH4_PERBUF_Pos 4 /**< \brief (TCC_PERBUF_DITH4) Period Buffer Value */ +#define TCC_PERBUF_DITH4_PERBUF_Msk (0xFFFFFul << TCC_PERBUF_DITH4_PERBUF_Pos) +#define TCC_PERBUF_DITH4_PERBUF(value) ((TCC_PERBUF_DITH4_PERBUF_Msk & ((value) << TCC_PERBUF_DITH4_PERBUF_Pos))) +#define TCC_PERBUF_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERBUF_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_PERBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH5) Dithering Buffer Cycle Number */ +#define TCC_PERBUF_DITH5_DITHERBUF_Msk (0x1Ful << TCC_PERBUF_DITH5_DITHERBUF_Pos) +#define TCC_PERBUF_DITH5_DITHERBUF(value) ((TCC_PERBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH5_DITHERBUF_Pos))) +#define TCC_PERBUF_DITH5_PERBUF_Pos 5 /**< \brief (TCC_PERBUF_DITH5) Period Buffer Value */ +#define TCC_PERBUF_DITH5_PERBUF_Msk (0x7FFFFul << TCC_PERBUF_DITH5_PERBUF_Pos) +#define TCC_PERBUF_DITH5_PERBUF(value) ((TCC_PERBUF_DITH5_PERBUF_Msk & ((value) << TCC_PERBUF_DITH5_PERBUF_Pos))) +#define TCC_PERBUF_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERBUF_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_PERBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH6) Dithering Buffer Cycle Number */ +#define TCC_PERBUF_DITH6_DITHERBUF_Msk (0x3Ful << TCC_PERBUF_DITH6_DITHERBUF_Pos) +#define TCC_PERBUF_DITH6_DITHERBUF(value) ((TCC_PERBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH6_DITHERBUF_Pos))) +#define TCC_PERBUF_DITH6_PERBUF_Pos 6 /**< \brief (TCC_PERBUF_DITH6) Period Buffer Value */ +#define TCC_PERBUF_DITH6_PERBUF_Msk (0x3FFFFul << TCC_PERBUF_DITH6_PERBUF_Pos) +#define TCC_PERBUF_DITH6_PERBUF(value) ((TCC_PERBUF_DITH6_PERBUF_Msk & ((value) << TCC_PERBUF_DITH6_PERBUF_Pos))) +#define TCC_PERBUF_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERBUF_DITH6) MASK Register */ + +#define TCC_PERBUF_PERBUF_Pos 0 /**< \brief (TCC_PERBUF) Period Buffer Value */ +#define TCC_PERBUF_PERBUF_Msk (0xFFFFFFul << TCC_PERBUF_PERBUF_Pos) +#define TCC_PERBUF_PERBUF(value) ((TCC_PERBUF_PERBUF_Msk & ((value) << TCC_PERBUF_PERBUF_Pos))) +#define TCC_PERBUF_MASK 0x00FFFFFFul /**< \brief (TCC_PERBUF) MASK Register */ + +/* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t CCBUF:4; /*!< bit: 0.. 3 Channel Compare/Capture Buffer Value */ + uint32_t DITHERBUF:20; /*!< bit: 4..23 Dithering Buffer Cycle Number */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t CCBUF:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t CCBUF:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CCBUF:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CCBUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CCBUF_OFFSET 0x70 /**< \brief (TCC_CCBUF offset) Compare and Capture Buffer */ +#define TCC_CCBUF_RESETVALUE 0x00000000ul /**< \brief (TCC_CCBUF reset_value) Compare and Capture Buffer */ + +// DITH4 mode +#define TCC_CCBUF_DITH4_CCBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH4) Channel Compare/Capture Buffer Value */ +#define TCC_CCBUF_DITH4_CCBUF_Msk (0xFul << TCC_CCBUF_DITH4_CCBUF_Pos) +#define TCC_CCBUF_DITH4_CCBUF(value) ((TCC_CCBUF_DITH4_CCBUF_Msk & ((value) << TCC_CCBUF_DITH4_CCBUF_Pos))) +#define TCC_CCBUF_DITH4_DITHERBUF_Pos 4 /**< \brief (TCC_CCBUF_DITH4) Dithering Buffer Cycle Number */ +#define TCC_CCBUF_DITH4_DITHERBUF_Msk (0xFFFFFul << TCC_CCBUF_DITH4_DITHERBUF_Pos) +#define TCC_CCBUF_DITH4_DITHERBUF(value) ((TCC_CCBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH4_DITHERBUF_Pos))) +#define TCC_CCBUF_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCBUF_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_CCBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH5) Dithering Buffer Cycle Number */ +#define TCC_CCBUF_DITH5_DITHERBUF_Msk (0x1Ful << TCC_CCBUF_DITH5_DITHERBUF_Pos) +#define TCC_CCBUF_DITH5_DITHERBUF(value) ((TCC_CCBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH5_DITHERBUF_Pos))) +#define TCC_CCBUF_DITH5_CCBUF_Pos 5 /**< \brief (TCC_CCBUF_DITH5) Channel Compare/Capture Buffer Value */ +#define TCC_CCBUF_DITH5_CCBUF_Msk (0x7FFFFul << TCC_CCBUF_DITH5_CCBUF_Pos) +#define TCC_CCBUF_DITH5_CCBUF(value) ((TCC_CCBUF_DITH5_CCBUF_Msk & ((value) << TCC_CCBUF_DITH5_CCBUF_Pos))) +#define TCC_CCBUF_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCBUF_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_CCBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH6) Dithering Buffer Cycle Number */ +#define TCC_CCBUF_DITH6_DITHERBUF_Msk (0x3Ful << TCC_CCBUF_DITH6_DITHERBUF_Pos) +#define TCC_CCBUF_DITH6_DITHERBUF(value) ((TCC_CCBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH6_DITHERBUF_Pos))) +#define TCC_CCBUF_DITH6_CCBUF_Pos 6 /**< \brief (TCC_CCBUF_DITH6) Channel Compare/Capture Buffer Value */ +#define TCC_CCBUF_DITH6_CCBUF_Msk (0x3FFFFul << TCC_CCBUF_DITH6_CCBUF_Pos) +#define TCC_CCBUF_DITH6_CCBUF(value) ((TCC_CCBUF_DITH6_CCBUF_Msk & ((value) << TCC_CCBUF_DITH6_CCBUF_Pos))) +#define TCC_CCBUF_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCBUF_DITH6) MASK Register */ + +#define TCC_CCBUF_CCBUF_Pos 0 /**< \brief (TCC_CCBUF) Channel Compare/Capture Buffer Value */ +#define TCC_CCBUF_CCBUF_Msk (0xFFFFFFul << TCC_CCBUF_CCBUF_Pos) +#define TCC_CCBUF_CCBUF(value) ((TCC_CCBUF_CCBUF_Msk & ((value) << TCC_CCBUF_CCBUF_Pos))) +#define TCC_CCBUF_MASK 0x00FFFFFFul /**< \brief (TCC_CCBUF) MASK Register */ + +/** \brief TCC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + RoReg8 Reserved1[0x2]; + __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ + __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ + __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ + __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ + RoReg8 Reserved2[0x2]; + __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ + RoReg8 Reserved3[0x1]; + __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ + __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ + __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ + __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ + __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ + __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ + __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ + RoReg8 Reserved4[0x2]; + __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ + __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ + __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ + RoReg8 Reserved5[0x10]; + __IO TCC_PATTBUF_Type PATTBUF; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ + RoReg8 Reserved6[0x2]; + __IO TCC_WAVEBUF_Type WAVEBUF; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ + __IO TCC_PERBUF_Type PERBUF; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ + __IO TCC_CCBUF_Type CCBUF[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ +} Tcc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_TCC_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_trng.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_trng.h new file mode 100644 index 0000000000..831ce0993f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_trng.h @@ -0,0 +1,189 @@ +/** + * \file + * + * \brief Component description for TRNG + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TRNG_COMPONENT_ +#define _SAML21_TRNG_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR TRNG */ +/* ========================================================================== */ +/** \addtogroup SAML21_TRNG True Random Generator */ +/*@{*/ + +#define TRNG_U2242 +#define REV_TRNG 0x100 + +/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TRNG_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */ +#define TRNG_CTRLA_RESETVALUE 0x00ul /**< \brief (TRNG_CTRLA reset_value) Control A */ + +#define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */ +#define TRNG_CTRLA_ENABLE (0x1ul << TRNG_CTRLA_ENABLE_Pos) +#define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */ +#define TRNG_CTRLA_RUNSTDBY (0x1ul << TRNG_CTRLA_RUNSTDBY_Pos) +#define TRNG_CTRLA_MASK 0x42ul /**< \brief (TRNG_CTRLA) MASK Register */ + +/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TRNG_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */ +#define TRNG_EVCTRL_RESETVALUE 0x00ul /**< \brief (TRNG_EVCTRL reset_value) Event Control */ + +#define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */ +#define TRNG_EVCTRL_DATARDYEO (0x1ul << TRNG_EVCTRL_DATARDYEO_Pos) +#define TRNG_EVCTRL_MASK 0x01ul /**< \brief (TRNG_EVCTRL) MASK Register */ + +/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TRNG_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */ +#define TRNG_INTENCLR_RESETVALUE 0x00ul /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */ + +#define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */ +#define TRNG_INTENCLR_DATARDY (0x1ul << TRNG_INTENCLR_DATARDY_Pos) +#define TRNG_INTENCLR_MASK 0x01ul /**< \brief (TRNG_INTENCLR) MASK Register */ + +/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TRNG_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */ +#define TRNG_INTENSET_RESETVALUE 0x00ul /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */ + +#define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */ +#define TRNG_INTENSET_DATARDY (0x1ul << TRNG_INTENSET_DATARDY_Pos) +#define TRNG_INTENSET_MASK 0x01ul /**< \brief (TRNG_INTENSET) MASK Register */ + +/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TRNG_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */ +#define TRNG_INTFLAG_RESETVALUE 0x00ul /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */ +#define TRNG_INTFLAG_DATARDY (0x1ul << TRNG_INTFLAG_DATARDY_Pos) +#define TRNG_INTFLAG_MASK 0x01ul /**< \brief (TRNG_INTFLAG) MASK Register */ + +/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 Output Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TRNG_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */ +#define TRNG_DATA_RESETVALUE 0x00000000ul /**< \brief (TRNG_DATA reset_value) Output Data */ + +#define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */ +#define TRNG_DATA_DATA_Msk (0xFFFFFFFFul << TRNG_DATA_DATA_Pos) +#define TRNG_DATA_DATA(value) ((TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))) +#define TRNG_DATA_MASK 0xFFFFFFFFul /**< \brief (TRNG_DATA) MASK Register */ + +/** \brief TRNG hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + RoReg8 Reserved1[0x3]; + __IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */ + RoReg8 Reserved2[0x3]; + __IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ + __IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ + __IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved3[0x15]; + __I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_TRNG_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_usb.h new file mode 100644 index 0000000000..e3a91afabc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_usb.h @@ -0,0 +1,1773 @@ +/** + * \file + * + * \brief Component description for USB + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_USB_COMPONENT_ +#define _SAML21_USB_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR USB */ +/* ========================================================================== */ +/** \addtogroup SAML21_USB Universal Serial Bus */ +/*@{*/ + +#define USB_U2222 +#define REV_USB 0x110 + +/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t MODE:1; /*!< bit: 7 Operating Mode */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */ +#define USB_CTRLA_RESETVALUE 0x00ul /**< \brief (USB_CTRLA reset_value) Control A */ + +#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */ +#define USB_CTRLA_SWRST (0x1ul << USB_CTRLA_SWRST_Pos) +#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */ +#define USB_CTRLA_ENABLE (0x1ul << USB_CTRLA_ENABLE_Pos) +#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */ +#define USB_CTRLA_RUNSTDBY (0x1ul << USB_CTRLA_RUNSTDBY_Pos) +#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */ +#define USB_CTRLA_MODE (0x1ul << USB_CTRLA_MODE_Pos) +#define USB_CTRLA_MODE_DEVICE_Val 0x0ul /**< \brief (USB_CTRLA) Device Mode */ +#define USB_CTRLA_MODE_HOST_Val 0x1ul /**< \brief (USB_CTRLA) Host Mode */ +#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos) +#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos) +#define USB_CTRLA_MASK 0x87ul /**< \brief (USB_CTRLA) MASK Register */ + +/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */ +#define USB_SYNCBUSY_RESETVALUE 0x00ul /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */ + +#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */ +#define USB_SYNCBUSY_SWRST (0x1ul << USB_SYNCBUSY_SWRST_Pos) +#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */ +#define USB_SYNCBUSY_ENABLE (0x1ul << USB_SYNCBUSY_ENABLE_Pos) +#define USB_SYNCBUSY_MASK 0x03ul /**< \brief (USB_SYNCBUSY) MASK Register */ + +/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DETACH:1; /*!< bit: 0 Detach */ + uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ + uint16_t NREPLY:1; /*!< bit: 4 No Reply */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ + uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ + uint16_t GNAK:1; /*!< bit: 9 Global NAK */ + uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */ +#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */ + +#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */ +#define USB_DEVICE_CTRLB_DETACH (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos) +#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */ +#define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos) +#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */ +#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_SPDCONF(value) ((USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))) +#define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */ +#define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */ +#define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */ +#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */ +#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */ +#define USB_DEVICE_CTRLB_NREPLY (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos) +#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */ +#define USB_DEVICE_CTRLB_TSTJ (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos) +#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */ +#define USB_DEVICE_CTRLB_TSTK (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos) +#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */ +#define USB_DEVICE_CTRLB_TSTPCKT (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos) +#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */ +#define USB_DEVICE_CTRLB_OPMODE2 (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos) +#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */ +#define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */ +#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK(value) ((USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))) +#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */ +#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */ +#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */ +#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) STALL */ +#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_MASK 0x0FFFul /**< \brief (USB_DEVICE_CTRLB) MASK Register */ + +/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ + uint16_t AUTORESUME:1; /*!< bit: 4 Auto Resume Enable */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ + uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ + uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ + uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */ +#define USB_HOST_CTRLB_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */ + +#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */ +#define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos) +#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */ +#define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos) +#define USB_HOST_CTRLB_SPDCONF(value) ((USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))) +#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */ +#define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */ +#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) +#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos) +#define USB_HOST_CTRLB_AUTORESUME_Pos 4 /**< \brief (USB_HOST_CTRLB) Auto Resume Enable */ +#define USB_HOST_CTRLB_AUTORESUME (0x1ul << USB_HOST_CTRLB_AUTORESUME_Pos) +#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */ +#define USB_HOST_CTRLB_TSTJ (0x1ul << USB_HOST_CTRLB_TSTJ_Pos) +#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */ +#define USB_HOST_CTRLB_TSTK (0x1ul << USB_HOST_CTRLB_TSTK_Pos) +#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */ +#define USB_HOST_CTRLB_SOFE (0x1ul << USB_HOST_CTRLB_SOFE_Pos) +#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */ +#define USB_HOST_CTRLB_BUSRESET (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos) +#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */ +#define USB_HOST_CTRLB_VBUSOK (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos) +#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */ +#define USB_HOST_CTRLB_L1RESUME (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos) +#define USB_HOST_CTRLB_MASK 0x0F7Eul /**< \brief (USB_HOST_CTRLB) MASK Register */ + +/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ + uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_DADD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */ +#define USB_DEVICE_DADD_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */ + +#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */ +#define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos) +#define USB_DEVICE_DADD_DADD(value) ((USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))) +#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */ +#define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos) +#define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */ + +/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_HSOFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */ +#define USB_HOST_HSOFC_RESETVALUE 0x00ul /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */ + +#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */ +#define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos) +#define USB_HOST_HSOFC_FLENC(value) ((USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))) +#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */ +#define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos) +#define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */ + +/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */ +#define USB_DEVICE_STATUS_RESETVALUE 0x40ul /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */ + +#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */ +#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos) +#define USB_DEVICE_STATUS_SPEED(value) ((USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))) +#define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */ +#define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */ +#define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */ +#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) +#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos) +#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) +#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */ +#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos) +#define USB_DEVICE_STATUS_LINESTATE(value) ((USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))) +#define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */ +#define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */ +#define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */ +#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos) +#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos) +#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos) +#define USB_DEVICE_STATUS_MASK 0xCCul /**< \brief (USB_DEVICE_STATUS) MASK Register */ + +/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */ +#define USB_HOST_STATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_STATUS reset_value) HOST Status */ + +#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */ +#define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos) +#define USB_HOST_STATUS_SPEED(value) ((USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))) +#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */ +#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos) +#define USB_HOST_STATUS_LINESTATE(value) ((USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))) +#define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */ + +/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_FSMSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */ +#define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */ + +#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */ +#define USB_FSMSTATUS_FSMSTATE_Msk (0x3Ful << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE(value) ((USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))) +#define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */ +#define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */ +#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */ +#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul /**< \brief (USB_FSMSTATUS) SLEEP (L1) */ +#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */ +#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */ +#define USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */ +#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_MASK 0x3Ful /**< \brief (USB_FSMSTATUS) MASK Register */ + +/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :1; /*!< bit: 14 Reserved */ + uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_FNUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */ +#define USB_DEVICE_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */ + +#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */ +#define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos) +#define USB_DEVICE_FNUM_MFNUM(value) ((USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))) +#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */ +#define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos) +#define USB_DEVICE_FNUM_FNUM(value) ((USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))) +#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */ +#define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos) +#define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */ + +/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_FNUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */ +#define USB_HOST_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */ + +#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */ +#define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos) +#define USB_HOST_FNUM_MFNUM(value) ((USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))) +#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */ +#define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos) +#define USB_HOST_FNUM_FNUM(value) ((USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))) +#define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */ + +/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_FLENHIGH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */ +#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */ + +#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */ +#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos) +#define USB_HOST_FLENHIGH_FLENHIGH(value) ((USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))) +#define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */ + +/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */ +#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */ + +#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */ +#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos) +#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */ +#define USB_DEVICE_INTENCLR_MSOF (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos) +#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */ +#define USB_DEVICE_INTENCLR_SOF (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos) +#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */ +#define USB_DEVICE_INTENCLR_EORST (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos) +#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */ +#define USB_DEVICE_INTENCLR_WAKEUP (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos) +#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */ +#define USB_DEVICE_INTENCLR_EORSM (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos) +#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */ +#define USB_DEVICE_INTENCLR_UPRSM (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos) +#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */ +#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos) +#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */ +#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos) +#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */ +#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos) +#define USB_DEVICE_INTENCLR_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENCLR) MASK Register */ + +/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ + uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ + uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */ +#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */ + +#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */ +#define USB_HOST_INTENCLR_HSOF (0x1ul << USB_HOST_INTENCLR_HSOF_Pos) +#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */ +#define USB_HOST_INTENCLR_RST (0x1ul << USB_HOST_INTENCLR_RST_Pos) +#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */ +#define USB_HOST_INTENCLR_WAKEUP (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos) +#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */ +#define USB_HOST_INTENCLR_DNRSM (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos) +#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */ +#define USB_HOST_INTENCLR_UPRSM (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos) +#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */ +#define USB_HOST_INTENCLR_RAMACER (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos) +#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */ +#define USB_HOST_INTENCLR_DCONN (0x1ul << USB_HOST_INTENCLR_DCONN_Pos) +#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */ +#define USB_HOST_INTENCLR_DDISC (0x1ul << USB_HOST_INTENCLR_DDISC_Pos) +#define USB_HOST_INTENCLR_MASK 0x03FCul /**< \brief (USB_HOST_INTENCLR) MASK Register */ + +/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */ +#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */ + +#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */ +#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos) +#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */ +#define USB_DEVICE_INTENSET_MSOF (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos) +#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */ +#define USB_DEVICE_INTENSET_SOF (0x1ul << USB_DEVICE_INTENSET_SOF_Pos) +#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */ +#define USB_DEVICE_INTENSET_EORST (0x1ul << USB_DEVICE_INTENSET_EORST_Pos) +#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */ +#define USB_DEVICE_INTENSET_WAKEUP (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos) +#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */ +#define USB_DEVICE_INTENSET_EORSM (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos) +#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */ +#define USB_DEVICE_INTENSET_UPRSM (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos) +#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */ +#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos) +#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */ +#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos) +#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */ +#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos) +#define USB_DEVICE_INTENSET_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENSET) MASK Register */ + +/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ + uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */ +#define USB_HOST_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */ + +#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */ +#define USB_HOST_INTENSET_HSOF (0x1ul << USB_HOST_INTENSET_HSOF_Pos) +#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */ +#define USB_HOST_INTENSET_RST (0x1ul << USB_HOST_INTENSET_RST_Pos) +#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */ +#define USB_HOST_INTENSET_WAKEUP (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos) +#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */ +#define USB_HOST_INTENSET_DNRSM (0x1ul << USB_HOST_INTENSET_DNRSM_Pos) +#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */ +#define USB_HOST_INTENSET_UPRSM (0x1ul << USB_HOST_INTENSET_UPRSM_Pos) +#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */ +#define USB_HOST_INTENSET_RAMACER (0x1ul << USB_HOST_INTENSET_RAMACER_Pos) +#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */ +#define USB_HOST_INTENSET_DCONN (0x1ul << USB_HOST_INTENSET_DCONN_Pos) +#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */ +#define USB_HOST_INTENSET_DDISC (0x1ul << USB_HOST_INTENSET_DDISC_Pos) +#define USB_HOST_INTENSET_MASK 0x03FCul /**< \brief (USB_HOST_INTENSET) MASK Register */ + +/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ + uint16_t EORST:1; /*!< bit: 3 End of Reset */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */ +#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */ + +#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */ +#define USB_DEVICE_INTFLAG_SUSPEND (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos) +#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */ +#define USB_DEVICE_INTFLAG_MSOF (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos) +#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */ +#define USB_DEVICE_INTFLAG_SOF (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos) +#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */ +#define USB_DEVICE_INTFLAG_EORST (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos) +#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */ +#define USB_DEVICE_INTFLAG_WAKEUP (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos) +#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */ +#define USB_DEVICE_INTFLAG_EORSM (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos) +#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */ +#define USB_DEVICE_INTFLAG_UPRSM (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos) +#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */ +#define USB_DEVICE_INTFLAG_RAMACER (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos) +#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */ +#define USB_DEVICE_INTFLAG_LPMNYET (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos) +#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */ +#define USB_DEVICE_INTFLAG_LPMSUSP (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos) +#define USB_DEVICE_INTFLAG_MASK 0x03FFul /**< \brief (USB_DEVICE_INTFLAG) MASK Register */ + +/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ + uint16_t RST:1; /*!< bit: 3 Bus Reset */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + uint16_t DNRSM:1; /*!< bit: 5 Downstream */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + uint16_t DCONN:1; /*!< bit: 8 Device Connection */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */ +#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */ + +#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */ +#define USB_HOST_INTFLAG_HSOF (0x1ul << USB_HOST_INTFLAG_HSOF_Pos) +#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */ +#define USB_HOST_INTFLAG_RST (0x1ul << USB_HOST_INTFLAG_RST_Pos) +#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */ +#define USB_HOST_INTFLAG_WAKEUP (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos) +#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */ +#define USB_HOST_INTFLAG_DNRSM (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos) +#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */ +#define USB_HOST_INTFLAG_UPRSM (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos) +#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */ +#define USB_HOST_INTFLAG_RAMACER (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos) +#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */ +#define USB_HOST_INTFLAG_DCONN (0x1ul << USB_HOST_INTFLAG_DCONN_Pos) +#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */ +#define USB_HOST_INTFLAG_DDISC (0x1ul << USB_HOST_INTFLAG_DDISC_Pos) +#define USB_HOST_INTFLAG_MASK 0x03FCul /**< \brief (USB_HOST_INTFLAG) MASK Register */ + +/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPINTSMRY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */ +#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */ + +#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT(value) ((USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))) +#define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */ + +/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_PINTSMRY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */ +#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */ + +#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos) +#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos) +#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos) +#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos) +#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos) +#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos) +#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos) +#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos) +#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */ +#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos) +#define USB_HOST_PINTSMRY_EPINT(value) ((USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))) +#define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */ + +/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_DESCADD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */ +#define USB_DESCADD_RESETVALUE 0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */ + +#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */ +#define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos) +#define USB_DESCADD_DESCADD(value) ((USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))) +#define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */ + +/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_PADCAL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */ +#define USB_PADCAL_RESETVALUE 0x0000ul /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */ + +#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */ +#define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos) +#define USB_PADCAL_TRANSP(value) ((USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))) +#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */ +#define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos) +#define USB_PADCAL_TRANSN(value) ((USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))) +#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */ +#define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos) +#define USB_PADCAL_TRIM(value) ((USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))) +#define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */ + +/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ + uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */ +#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */ + +#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */ +#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos) +#define USB_DEVICE_EPCFG_EPTYPE0(value) ((USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))) +#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */ +#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos) +#define USB_DEVICE_EPCFG_EPTYPE1(value) ((USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))) +#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */ +#define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos) +#define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */ + +/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ + uint8_t BK:1; /*!< bit: 2 Pipe Bank */ + uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */ +#define USB_HOST_PCFG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */ + +#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */ +#define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos) +#define USB_HOST_PCFG_PTOKEN(value) ((USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))) +#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */ +#define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos) +#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */ +#define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos) +#define USB_HOST_PCFG_PTYPE(value) ((USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))) +#define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */ + +/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_BINTERVAL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */ +#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */ + +#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */ +#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos) +#define USB_HOST_BINTERVAL_BITINTERVAL(value) ((USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))) +#define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */ + +/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPSTATUSCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */ +#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */ + +#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */ +#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) +#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */ +#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos) +#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Current Bank Clear */ +#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos) +#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */ +#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) +#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */ +#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) +#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */ +#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) +#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) ((USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))) +#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */ +#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos) +#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */ +#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos) +#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */ + +/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PSTATUSCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */ +#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */ + +#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */ +#define USB_HOST_PSTATUSCLR_DTGL (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos) +#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */ +#define USB_HOST_PSTATUSCLR_CURBK (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos) +#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */ +#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos) +#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */ +#define USB_HOST_PSTATUSCLR_BK0RDY (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos) +#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */ +#define USB_HOST_PSTATUSCLR_BK1RDY (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos) +#define USB_HOST_PSTATUSCLR_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */ + +/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPSTATUSSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */ +#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */ + +#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */ +#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) +#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */ +#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos) +#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */ +#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos) +#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */ +#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) +#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */ +#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) +#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */ +#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) +#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) ((USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))) +#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */ +#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos) +#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */ +#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos) +#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */ + +/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PSTATUSSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */ +#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */ + +#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */ +#define USB_HOST_PSTATUSSET_DTGL (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos) +#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */ +#define USB_HOST_PSTATUSSET_CURBK (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos) +#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */ +#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos) +#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */ +#define USB_HOST_PSTATUSSET_BK0RDY (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos) +#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */ +#define USB_HOST_PSTATUSSET_BK1RDY (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos) +#define USB_HOST_PSTATUSSET_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSSET) MASK Register */ + +/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */ +#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */ + +#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */ +#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos) +#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */ +#define USB_DEVICE_EPSTATUS_DTGLIN (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos) +#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */ +#define USB_DEVICE_EPSTATUS_CURBK (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos) +#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */ +#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos) +#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */ +#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos) +#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */ +#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos) +#define USB_DEVICE_EPSTATUS_STALLRQ(value) ((USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))) +#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */ +#define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos) +#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */ +#define USB_DEVICE_EPSTATUS_BK1RDY (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos) +#define USB_DEVICE_EPSTATUS_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */ + +/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */ +#define USB_HOST_PSTATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */ + +#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */ +#define USB_HOST_PSTATUS_DTGL (0x1ul << USB_HOST_PSTATUS_DTGL_Pos) +#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */ +#define USB_HOST_PSTATUS_CURBK (0x1ul << USB_HOST_PSTATUS_CURBK_Pos) +#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */ +#define USB_HOST_PSTATUS_PFREEZE (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos) +#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */ +#define USB_HOST_PSTATUS_BK0RDY (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos) +#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */ +#define USB_HOST_PSTATUS_BK1RDY (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos) +#define USB_HOST_PSTATUS_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUS) MASK Register */ + +/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */ +#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */ + +#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */ +#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos) +#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */ +#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos) +#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */ +#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos) +#define USB_DEVICE_EPINTFLAG_TRCPT(value) ((USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))) +#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */ +#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos) +#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */ +#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos) +#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */ +#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos) +#define USB_DEVICE_EPINTFLAG_TRFAIL(value) ((USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))) +#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */ +#define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos) +#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */ +#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos) +#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */ +#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos) +#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */ +#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos) +#define USB_DEVICE_EPINTFLAG_STALL(value) ((USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))) +#define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */ + +/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */ +#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */ + +#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */ +#define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos) +#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */ +#define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos) +#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */ +#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos) +#define USB_HOST_PINTFLAG_TRCPT(value) ((USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))) +#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */ +#define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos) +#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */ +#define USB_HOST_PINTFLAG_PERR (0x1ul << USB_HOST_PINTFLAG_PERR_Pos) +#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */ +#define USB_HOST_PINTFLAG_TXSTP (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos) +#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */ +#define USB_HOST_PINTFLAG_STALL (0x1ul << USB_HOST_PINTFLAG_STALL_Pos) +#define USB_HOST_PINTFLAG_MASK 0x3Ful /**< \brief (USB_HOST_PINTFLAG) MASK Register */ + +/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ +#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ + +#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos) +#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos) +#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos) +#define USB_DEVICE_EPINTENCLR_TRCPT(value) ((USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))) +#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos) +#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos) +#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos) +#define USB_DEVICE_EPINTENCLR_TRFAIL(value) ((USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))) +#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos) +#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos) +#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos) +#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos) +#define USB_DEVICE_EPINTENCLR_STALL(value) ((USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))) +#define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */ + +/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ + uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */ +#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */ + +#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */ +#define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos) +#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */ +#define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos) +#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */ +#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos) +#define USB_HOST_PINTENCLR_TRCPT(value) ((USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))) +#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */ +#define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos) +#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */ +#define USB_HOST_PINTENCLR_PERR (0x1ul << USB_HOST_PINTENCLR_PERR_Pos) +#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */ +#define USB_HOST_PINTENCLR_TXSTP (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos) +#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */ +#define USB_HOST_PINTENCLR_STALL (0x1ul << USB_HOST_PINTENCLR_STALL_Pos) +#define USB_HOST_PINTENCLR_MASK 0x3Ful /**< \brief (USB_HOST_PINTENCLR) MASK Register */ + +/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */ +#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */ + +#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos) +#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos) +#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos) +#define USB_DEVICE_EPINTENSET_TRCPT(value) ((USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))) +#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos) +#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos) +#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos) +#define USB_DEVICE_EPINTENSET_TRFAIL(value) ((USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))) +#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos) +#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */ +#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos) +#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */ +#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos) +#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */ +#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos) +#define USB_DEVICE_EPINTENSET_STALL(value) ((USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))) +#define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */ + +/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */ +#define USB_HOST_PINTENSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */ + +#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */ +#define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos) +#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */ +#define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos) +#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */ +#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos) +#define USB_HOST_PINTENSET_TRCPT(value) ((USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))) +#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */ +#define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos) +#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */ +#define USB_HOST_PINTENSET_PERR (0x1ul << USB_HOST_PINTENSET_PERR_Pos) +#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */ +#define USB_HOST_PINTENSET_TXSTP (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos) +#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */ +#define USB_HOST_PINTENSET_STALL (0x1ul << USB_HOST_PINTENSET_STALL_Pos) +#define USB_HOST_PINTENSET_MASK 0x3Ful /**< \brief (USB_HOST_PINTENSET) MASK Register */ + +/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_DEVICE_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ + +#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */ +#define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos) +#define USB_DEVICE_ADDR_ADDR(value) ((USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))) +#define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */ + +/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_HOST_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ + +#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */ +#define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos) +#define USB_HOST_ADDR_ADDR(value) ((USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))) +#define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */ + +/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_DEVICE_PCKSIZE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ + +#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */ +#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) +#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) ((USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))) +#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */ +#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) +#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))) +#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */ +#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos) +#define USB_DEVICE_PCKSIZE_SIZE(value) ((USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))) +#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */ +#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos) +#define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */ + +/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_HOST_PCKSIZE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */ + +#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */ +#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) +#define USB_HOST_PCKSIZE_BYTE_COUNT(value) ((USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))) +#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */ +#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) +#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))) +#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */ +#define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos) +#define USB_HOST_PCKSIZE_SIZE(value) ((USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))) +#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */ +#define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos) +#define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */ + +/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_EXTREG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */ + +#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */ +#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos) +#define USB_DEVICE_EXTREG_SUBPID(value) ((USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))) +#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */ +#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos) +#define USB_DEVICE_EXTREG_VARIABLE(value) ((USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))) +#define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */ + +/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_EXTREG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */ + +#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */ +#define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos) +#define USB_HOST_EXTREG_SUBPID(value) ((USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))) +#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */ +#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos) +#define USB_HOST_EXTREG_VARIABLE(value) ((USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))) +#define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */ + +/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_STATUS_BK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ + +#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */ +#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos) +#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */ +#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) +#define USB_DEVICE_STATUS_BK_MASK 0x03ul /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */ + +/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_STATUS_BK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */ + +#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */ +#define USB_HOST_STATUS_BK_CRCERR (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos) +#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */ +#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos) +#define USB_HOST_STATUS_BK_MASK 0x03ul /**< \brief (USB_HOST_STATUS_BK) MASK Register */ + +/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ + uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_CTRL_PIPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */ +#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */ + +#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */ +#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos) +#define USB_HOST_CTRL_PIPE_PDADDR(value) ((USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))) +#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */ +#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos) +#define USB_HOST_CTRL_PIPE_PEPNUM(value) ((USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))) +#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */ +#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos) +#define USB_HOST_CTRL_PIPE_PERMAX(value) ((USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))) +#define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */ + +/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ + uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ + uint16_t PIDER:1; /*!< bit: 2 PID Error */ + uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ + uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ + uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_STATUS_PIPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */ + +#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */ +#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos) +#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */ +#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos) +#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */ +#define USB_HOST_STATUS_PIPE_PIDER (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos) +#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */ +#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos) +#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */ +#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos) +#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */ +#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos) +#define USB_HOST_STATUS_PIPE_ERCNT(value) ((USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))) +#define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */ + +/** \brief UsbDeviceDescBank SRAM registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ + __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ + __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ + __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ + RoReg8 Reserved1[0x5]; +} UsbDeviceDescBank; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief UsbHostDescBank SRAM registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ + __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ + __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ + __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ + RoReg8 Reserved1[0x1]; + __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ + __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ +} UsbHostDescBank; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief UsbDeviceEndpoint hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ + RoReg8 Reserved1[0x3]; + __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ + __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ + __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ + __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ + __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ + __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ + RoReg8 Reserved2[0x16]; +} UsbDeviceEndpoint; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief UsbHostPipe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ + RoReg8 Reserved1[0x2]; + __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ + __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ + __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ + __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ + __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ + __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ + __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ + RoReg8 Reserved2[0x16]; +} UsbHostPipe; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief USB_DEVICE APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USB is Device */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + RoReg8 Reserved2[0x5]; + __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ + __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ + RoReg8 Reserved3[0x1]; + __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ + RoReg8 Reserved5[0x2]; + __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ +} UsbDevice; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief USB_HOST hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USB is Host */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + RoReg8 Reserved2[0x5]; + __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ + __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ + RoReg8 Reserved3[0x1]; + __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ + __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ + RoReg8 Reserved5[0x1]; + __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ +} UsbHost; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief USB_DEVICE Descriptor SRAM registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USB is Device */ + UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ +} UsbDeviceDescriptor; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief USB_HOST Descriptor SRAM registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USB is Host */ + UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ +} UsbHostDescriptor; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#ifdef __GNUC__ +#define SECTION_USB_DESCRIPTOR __attribute__ ((section(".hsram"))) +#elif defined(__ICCARM__) +#define SECTION_USB_DESCRIPTOR @".hsram" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ + UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ +} Usb; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_USB_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_wdt.h new file mode 100644 index 0000000000..2d76e72c47 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_wdt.h @@ -0,0 +1,317 @@ +/** + * \file + * + * \brief Component description for WDT + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_WDT_COMPONENT_ +#define _SAML21_WDT_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR WDT */ +/* ========================================================================== */ +/** \addtogroup SAML21_WDT Watchdog Timer */ +/*@{*/ + +#define WDT_U2251 +#define REV_WDT 0x100 + +/* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_CTRLA_OFFSET 0x0 /**< \brief (WDT_CTRLA offset) Control */ +#define WDT_CTRLA_RESETVALUE 0x00ul /**< \brief (WDT_CTRLA reset_value) Control */ + +#define WDT_CTRLA_ENABLE_Pos 1 /**< \brief (WDT_CTRLA) Enable */ +#define WDT_CTRLA_ENABLE (0x1ul << WDT_CTRLA_ENABLE_Pos) +#define WDT_CTRLA_WEN_Pos 2 /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */ +#define WDT_CTRLA_WEN (0x1ul << WDT_CTRLA_WEN_Pos) +#define WDT_CTRLA_ALWAYSON_Pos 7 /**< \brief (WDT_CTRLA) Always-On */ +#define WDT_CTRLA_ALWAYSON (0x1ul << WDT_CTRLA_ALWAYSON_Pos) +#define WDT_CTRLA_MASK 0x86ul /**< \brief (WDT_CTRLA) MASK Register */ + +/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ + uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_CONFIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */ +#define WDT_CONFIG_RESETVALUE 0xBBul /**< \brief (WDT_CONFIG reset_value) Configuration */ + +#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */ +#define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))) +#define WDT_CONFIG_PER_CYC8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ +#define WDT_CONFIG_PER_CYC16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ +#define WDT_CONFIG_PER_CYC32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ +#define WDT_CONFIG_PER_CYC64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ +#define WDT_CONFIG_PER_CYC128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ +#define WDT_CONFIG_PER_CYC256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ +#define WDT_CONFIG_PER_CYC512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ +#define WDT_CONFIG_PER_CYC1024_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ +#define WDT_CONFIG_PER_CYC2048_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ +#define WDT_CONFIG_PER_CYC4096_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ +#define WDT_CONFIG_PER_CYC8192_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ +#define WDT_CONFIG_PER_CYC16384_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ +#define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */ +#define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))) +#define WDT_CONFIG_WINDOW_CYC8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC1024_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC2048_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC4096_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC8192_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC16384_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ +#define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_MASK 0xFFul /**< \brief (WDT_CONFIG) MASK Register */ + +/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_EWCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */ +#define WDT_EWCTRL_RESETVALUE 0x0Bul /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */ + +#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */ +#define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))) +#define WDT_EWCTRL_EWOFFSET_CYC8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC64_Val 0x3ul /**< \brief (WDT_EWCTRL) 64 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC128_Val 0x4ul /**< \brief (WDT_EWCTRL) 128 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC256_Val 0x5ul /**< \brief (WDT_EWCTRL) 256 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC512_Val 0x6ul /**< \brief (WDT_EWCTRL) 512 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC1024_Val 0x7ul /**< \brief (WDT_EWCTRL) 1024 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC2048_Val 0x8ul /**< \brief (WDT_EWCTRL) 2048 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC4096_Val 0x9ul /**< \brief (WDT_EWCTRL) 4096 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC8192_Val 0xAul /**< \brief (WDT_EWCTRL) 8192 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC16384_Val 0xBul /**< \brief (WDT_EWCTRL) 16384 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_MASK 0x0Ful /**< \brief (WDT_EWCTRL) MASK Register */ + +/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */ +#define WDT_INTENCLR_RESETVALUE 0x00ul /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */ + +#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */ +#define WDT_INTENCLR_EW (0x1ul << WDT_INTENCLR_EW_Pos) +#define WDT_INTENCLR_MASK 0x01ul /**< \brief (WDT_INTENCLR) MASK Register */ + +/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */ +#define WDT_INTENSET_RESETVALUE 0x00ul /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */ + +#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */ +#define WDT_INTENSET_EW (0x1ul << WDT_INTENSET_EW_Pos) +#define WDT_INTENSET_MASK 0x01ul /**< \brief (WDT_INTENSET) MASK Register */ + +/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */ +#define WDT_INTFLAG_RESETVALUE 0x00ul /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */ +#define WDT_INTFLAG_EW (0x1ul << WDT_INTFLAG_EW_Pos) +#define WDT_INTFLAG_MASK 0x01ul /**< \brief (WDT_INTFLAG) MASK Register */ + +/* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ + uint32_t WEN:1; /*!< bit: 2 Window Enable Busy */ + uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Busy */ + uint32_t CLEAR:1; /*!< bit: 4 Clear Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} WDT_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_SYNCBUSY_OFFSET 0x8 /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */ +#define WDT_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */ + +#define WDT_SYNCBUSY_ENABLE_Pos 1 /**< \brief (WDT_SYNCBUSY) Enable Busy */ +#define WDT_SYNCBUSY_ENABLE (0x1ul << WDT_SYNCBUSY_ENABLE_Pos) +#define WDT_SYNCBUSY_WEN_Pos 2 /**< \brief (WDT_SYNCBUSY) Window Enable Busy */ +#define WDT_SYNCBUSY_WEN (0x1ul << WDT_SYNCBUSY_WEN_Pos) +#define WDT_SYNCBUSY_ALWAYSON_Pos 3 /**< \brief (WDT_SYNCBUSY) Always-On Busy */ +#define WDT_SYNCBUSY_ALWAYSON (0x1ul << WDT_SYNCBUSY_ALWAYSON_Pos) +#define WDT_SYNCBUSY_CLEAR_Pos 4 /**< \brief (WDT_SYNCBUSY) Clear Busy */ +#define WDT_SYNCBUSY_CLEAR (0x1ul << WDT_SYNCBUSY_CLEAR_Pos) +#define WDT_SYNCBUSY_MASK 0x0000001Eul /**< \brief (WDT_SYNCBUSY) MASK Register */ + +/* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_CLEAR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_CLEAR_OFFSET 0xC /**< \brief (WDT_CLEAR offset) Clear */ +#define WDT_CLEAR_RESETVALUE 0x00ul /**< \brief (WDT_CLEAR reset_value) Clear */ + +#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */ +#define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos) +#define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))) +#define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */ +#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos) +#define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */ + +/** \brief WDT hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */ + __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ + __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ + RoReg8 Reserved1[0x1]; + __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved2[0x1]; + __I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */ + __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_WDT_COMPONENT_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ac.h new file mode 100644 index 0000000000..c931887c67 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ac.h @@ -0,0 +1,91 @@ +/** + * \file + * + * \brief Instance description for AC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_AC_INSTANCE_ +#define _SAML21_AC_INSTANCE_ + +/* ========== Register definition for AC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AC_CTRLA (0x43001000U) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (0x43001001U) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (0x43001002U) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (0x43001004U) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (0x43001005U) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (0x43001006U) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (0x43001007U) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (0x43001008U) /**< \brief (AC) Status B */ +#define REG_AC_DBGCTRL (0x43001009U) /**< \brief (AC) Debug Control */ +#define REG_AC_WINCTRL (0x4300100AU) /**< \brief (AC) Window Control */ +#define REG_AC_SCALER0 (0x4300100CU) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (0x4300100DU) /**< \brief (AC) Scaler 1 */ +#define REG_AC_COMPCTRL0 (0x43001010U) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (0x43001014U) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SYNCBUSY (0x43001020U) /**< \brief (AC) Synchronization Busy */ +#else +#define REG_AC_CTRLA (*(RwReg8 *)0x43001000U) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (*(WoReg8 *)0x43001001U) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (*(RwReg16*)0x43001002U) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (*(RwReg8 *)0x43001004U) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (*(RwReg8 *)0x43001005U) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (*(RwReg8 *)0x43001006U) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (*(RoReg8 *)0x43001007U) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (*(RoReg8 *)0x43001008U) /**< \brief (AC) Status B */ +#define REG_AC_DBGCTRL (*(RwReg8 *)0x43001009U) /**< \brief (AC) Debug Control */ +#define REG_AC_WINCTRL (*(RwReg8 *)0x4300100AU) /**< \brief (AC) Window Control */ +#define REG_AC_SCALER0 (*(RwReg8 *)0x4300100CU) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (*(RwReg8 *)0x4300100DU) /**< \brief (AC) Scaler 1 */ +#define REG_AC_COMPCTRL0 (*(RwReg *)0x43001010U) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (*(RwReg *)0x43001014U) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SYNCBUSY (*(RoReg *)0x43001020U) /**< \brief (AC) Synchronization Busy */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AC peripheral ========== */ +#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG +#define AC_GCLK_ID 31 // Index of Generic Clock +#define AC_NUM_CMP 2 // Number of comparators +#define AC_PAIRS 1 // Number of pairs of comparators + +#endif /* _SAML21_AC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_adc.h new file mode 100644 index 0000000000..2073853b65 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_adc.h @@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for ADC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_ADC_INSTANCE_ +#define _SAML21_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CTRLA (0x43000C00U) /**< \brief (ADC) Control A */ +#define REG_ADC_CTRLB (0x43000C01U) /**< \brief (ADC) Control B */ +#define REG_ADC_REFCTRL (0x43000C02U) /**< \brief (ADC) Reference Control */ +#define REG_ADC_EVCTRL (0x43000C03U) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (0x43000C04U) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (0x43000C05U) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (0x43000C06U) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_SEQSTATUS (0x43000C07U) /**< \brief (ADC) Sequence Status */ +#define REG_ADC_INPUTCTRL (0x43000C08U) /**< \brief (ADC) Input Control */ +#define REG_ADC_CTRLC (0x43000C0AU) /**< \brief (ADC) Control C */ +#define REG_ADC_AVGCTRL (0x43000C0CU) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (0x43000C0DU) /**< \brief (ADC) Sample Time Control */ +#define REG_ADC_WINLT (0x43000C0EU) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (0x43000C10U) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (0x43000C12U) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (0x43000C14U) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_SWTRIG (0x43000C18U) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_DBGCTRL (0x43000C1CU) /**< \brief (ADC) Debug Control */ +#define REG_ADC_SYNCBUSY (0x43000C20U) /**< \brief (ADC) Synchronization Busy */ +#define REG_ADC_RESULT (0x43000C24U) /**< \brief (ADC) Result */ +#define REG_ADC_SEQCTRL (0x43000C28U) /**< \brief (ADC) Sequence Control */ +#define REG_ADC_CALIB (0x43000C2CU) /**< \brief (ADC) Calibration */ +#else +#define REG_ADC_CTRLA (*(RwReg8 *)0x43000C00U) /**< \brief (ADC) Control A */ +#define REG_ADC_CTRLB (*(RwReg8 *)0x43000C01U) /**< \brief (ADC) Control B */ +#define REG_ADC_REFCTRL (*(RwReg8 *)0x43000C02U) /**< \brief (ADC) Reference Control */ +#define REG_ADC_EVCTRL (*(RwReg8 *)0x43000C03U) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (*(RwReg8 *)0x43000C04U) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (*(RwReg8 *)0x43000C05U) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (*(RwReg8 *)0x43000C06U) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_SEQSTATUS (*(RoReg8 *)0x43000C07U) /**< \brief (ADC) Sequence Status */ +#define REG_ADC_INPUTCTRL (*(RwReg16*)0x43000C08U) /**< \brief (ADC) Input Control */ +#define REG_ADC_CTRLC (*(RwReg16*)0x43000C0AU) /**< \brief (ADC) Control C */ +#define REG_ADC_AVGCTRL (*(RwReg8 *)0x43000C0CU) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x43000C0DU) /**< \brief (ADC) Sample Time Control */ +#define REG_ADC_WINLT (*(RwReg16*)0x43000C0EU) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (*(RwReg16*)0x43000C10U) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (*(RwReg16*)0x43000C12U) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (*(RwReg16*)0x43000C14U) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_SWTRIG (*(RwReg8 *)0x43000C18U) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_DBGCTRL (*(RwReg8 *)0x43000C1CU) /**< \brief (ADC) Debug Control */ +#define REG_ADC_SYNCBUSY (*(RoReg16*)0x43000C20U) /**< \brief (ADC) Synchronization Busy */ +#define REG_ADC_RESULT (*(RoReg16*)0x43000C24U) /**< \brief (ADC) Result */ +#define REG_ADC_SEQCTRL (*(RwReg *)0x43000C28U) /**< \brief (ADC) Sequence Control */ +#define REG_ADC_CALIB (*(RwReg16*)0x43000C2CU) /**< \brief (ADC) Calibration */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for ADC peripheral ========== */ +#define ADC_DMAC_ID_RESRDY 37 // index of DMA RESRDY trigger +#define ADC_EXTCHANNEL_MSB 19 // Number of external channels +#define ADC_GCLK_ID 30 // index of Generic Clock +#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield +#define ADC_RESULT_MSB 15 // Size of Result + +#endif /* _SAML21_ADC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_aes.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_aes.h new file mode 100644 index 0000000000..9189f19068 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_aes.h @@ -0,0 +1,119 @@ +/** + * \file + * + * \brief Instance description for AES + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_AES_INSTANCE_ +#define _SAML21_AES_INSTANCE_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AES_CTRLA (0x42003400U) /**< \brief (AES) Control A */ +#define REG_AES_CTRLB (0x42003404U) /**< \brief (AES) Control B */ +#define REG_AES_INTENCLR (0x42003405U) /**< \brief (AES) Interrupt Enable Clear */ +#define REG_AES_INTENSET (0x42003406U) /**< \brief (AES) Interrupt Enable Set */ +#define REG_AES_INTFLAG (0x42003407U) /**< \brief (AES) Interrupt Flag Status */ +#define REG_AES_DATABUFPTR (0x42003408U) /**< \brief (AES) Data buffer pointer */ +#define REG_AES_DBGCTRL (0x42003409U) /**< \brief (AES) Debug control */ +#define REG_AES_KEYWORD0 (0x4200340CU) /**< \brief (AES) Keyword 0 */ +#define REG_AES_KEYWORD1 (0x42003410U) /**< \brief (AES) Keyword 1 */ +#define REG_AES_KEYWORD2 (0x42003414U) /**< \brief (AES) Keyword 2 */ +#define REG_AES_KEYWORD3 (0x42003418U) /**< \brief (AES) Keyword 3 */ +#define REG_AES_KEYWORD4 (0x4200341CU) /**< \brief (AES) Keyword 4 */ +#define REG_AES_KEYWORD5 (0x42003420U) /**< \brief (AES) Keyword 5 */ +#define REG_AES_KEYWORD6 (0x42003424U) /**< \brief (AES) Keyword 6 */ +#define REG_AES_KEYWORD7 (0x42003428U) /**< \brief (AES) Keyword 7 */ +#define REG_AES_INDATA (0x42003438U) /**< \brief (AES) Indata */ +#define REG_AES_INTVECTV0 (0x4200343CU) /**< \brief (AES) Initialisation Vector 0 */ +#define REG_AES_INTVECTV1 (0x42003440U) /**< \brief (AES) Initialisation Vector 1 */ +#define REG_AES_INTVECTV2 (0x42003444U) /**< \brief (AES) Initialisation Vector 2 */ +#define REG_AES_INTVECTV3 (0x42003448U) /**< \brief (AES) Initialisation Vector 3 */ +#define REG_AES_HASHKEY0 (0x4200345CU) /**< \brief (AES) Hash key 0 */ +#define REG_AES_HASHKEY1 (0x42003460U) /**< \brief (AES) Hash key 1 */ +#define REG_AES_HASHKEY2 (0x42003464U) /**< \brief (AES) Hash key 2 */ +#define REG_AES_HASHKEY3 (0x42003468U) /**< \brief (AES) Hash key 3 */ +#define REG_AES_GHASH0 (0x4200346CU) /**< \brief (AES) Galois Hash 0 */ +#define REG_AES_GHASH1 (0x42003470U) /**< \brief (AES) Galois Hash 1 */ +#define REG_AES_GHASH2 (0x42003474U) /**< \brief (AES) Galois Hash 2 */ +#define REG_AES_GHASH3 (0x42003478U) /**< \brief (AES) Galois Hash 3 */ +#define REG_AES_CIPLEN (0x42003480U) /**< \brief (AES) Cipher Length */ +#define REG_AES_RANDSEED (0x42003484U) /**< \brief (AES) Random Seed */ +#else +#define REG_AES_CTRLA (*(RwReg *)0x42003400U) /**< \brief (AES) Control A */ +#define REG_AES_CTRLB (*(RwReg8 *)0x42003404U) /**< \brief (AES) Control B */ +#define REG_AES_INTENCLR (*(RwReg8 *)0x42003405U) /**< \brief (AES) Interrupt Enable Clear */ +#define REG_AES_INTENSET (*(RwReg8 *)0x42003406U) /**< \brief (AES) Interrupt Enable Set */ +#define REG_AES_INTFLAG (*(RwReg8 *)0x42003407U) /**< \brief (AES) Interrupt Flag Status */ +#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42003408U) /**< \brief (AES) Data buffer pointer */ +#define REG_AES_DBGCTRL (*(WoReg8 *)0x42003409U) /**< \brief (AES) Debug control */ +#define REG_AES_KEYWORD0 (*(WoReg *)0x4200340CU) /**< \brief (AES) Keyword 0 */ +#define REG_AES_KEYWORD1 (*(WoReg *)0x42003410U) /**< \brief (AES) Keyword 1 */ +#define REG_AES_KEYWORD2 (*(WoReg *)0x42003414U) /**< \brief (AES) Keyword 2 */ +#define REG_AES_KEYWORD3 (*(WoReg *)0x42003418U) /**< \brief (AES) Keyword 3 */ +#define REG_AES_KEYWORD4 (*(WoReg *)0x4200341CU) /**< \brief (AES) Keyword 4 */ +#define REG_AES_KEYWORD5 (*(WoReg *)0x42003420U) /**< \brief (AES) Keyword 5 */ +#define REG_AES_KEYWORD6 (*(WoReg *)0x42003424U) /**< \brief (AES) Keyword 6 */ +#define REG_AES_KEYWORD7 (*(WoReg *)0x42003428U) /**< \brief (AES) Keyword 7 */ +#define REG_AES_INDATA (*(RwReg *)0x42003438U) /**< \brief (AES) Indata */ +#define REG_AES_INTVECTV0 (*(WoReg *)0x4200343CU) /**< \brief (AES) Initialisation Vector 0 */ +#define REG_AES_INTVECTV1 (*(WoReg *)0x42003440U) /**< \brief (AES) Initialisation Vector 1 */ +#define REG_AES_INTVECTV2 (*(WoReg *)0x42003444U) /**< \brief (AES) Initialisation Vector 2 */ +#define REG_AES_INTVECTV3 (*(WoReg *)0x42003448U) /**< \brief (AES) Initialisation Vector 3 */ +#define REG_AES_HASHKEY0 (*(RwReg *)0x4200345CU) /**< \brief (AES) Hash key 0 */ +#define REG_AES_HASHKEY1 (*(RwReg *)0x42003460U) /**< \brief (AES) Hash key 1 */ +#define REG_AES_HASHKEY2 (*(RwReg *)0x42003464U) /**< \brief (AES) Hash key 2 */ +#define REG_AES_HASHKEY3 (*(RwReg *)0x42003468U) /**< \brief (AES) Hash key 3 */ +#define REG_AES_GHASH0 (*(RwReg *)0x4200346CU) /**< \brief (AES) Galois Hash 0 */ +#define REG_AES_GHASH1 (*(RwReg *)0x42003470U) /**< \brief (AES) Galois Hash 1 */ +#define REG_AES_GHASH2 (*(RwReg *)0x42003474U) /**< \brief (AES) Galois Hash 2 */ +#define REG_AES_GHASH3 (*(RwReg *)0x42003478U) /**< \brief (AES) Galois Hash 3 */ +#define REG_AES_CIPLEN (*(RwReg *)0x42003480U) /**< \brief (AES) Cipher Length */ +#define REG_AES_RANDSEED (*(RwReg *)0x42003484U) /**< \brief (AES) Random Seed */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AES peripheral ========== */ +#define AES_DMAC_ID_RD 45 // DMA DATA Read trigger +#define AES_DMAC_ID_WR 44 // DMA DATA Write trigger + +#endif /* _SAML21_AES_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ccl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ccl.h new file mode 100644 index 0000000000..b543ccbe99 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_ccl.h @@ -0,0 +1,75 @@ +/** + * \file + * + * \brief Instance description for CCL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_CCL_INSTANCE_ +#define _SAML21_CCL_INSTANCE_ + +/* ========== Register definition for CCL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CCL_CTRL (0x43001C00U) /**< \brief (CCL) Control */ +#define REG_CCL_SEQCTRL0 (0x43001C04U) /**< \brief (CCL) SEQ Control x 0 */ +#define REG_CCL_SEQCTRL1 (0x43001C05U) /**< \brief (CCL) SEQ Control x 1 */ +#define REG_CCL_LUTCTRL0 (0x43001C08U) /**< \brief (CCL) LUT Control x 0 */ +#define REG_CCL_LUTCTRL1 (0x43001C0CU) /**< \brief (CCL) LUT Control x 1 */ +#define REG_CCL_LUTCTRL2 (0x43001C10U) /**< \brief (CCL) LUT Control x 2 */ +#define REG_CCL_LUTCTRL3 (0x43001C14U) /**< \brief (CCL) LUT Control x 3 */ +#else +#define REG_CCL_CTRL (*(RwReg8 *)0x43001C00U) /**< \brief (CCL) Control */ +#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x43001C04U) /**< \brief (CCL) SEQ Control x 0 */ +#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x43001C05U) /**< \brief (CCL) SEQ Control x 1 */ +#define REG_CCL_LUTCTRL0 (*(RwReg *)0x43001C08U) /**< \brief (CCL) LUT Control x 0 */ +#define REG_CCL_LUTCTRL1 (*(RwReg *)0x43001C0CU) /**< \brief (CCL) LUT Control x 1 */ +#define REG_CCL_LUTCTRL2 (*(RwReg *)0x43001C10U) /**< \brief (CCL) LUT Control x 2 */ +#define REG_CCL_LUTCTRL3 (*(RwReg *)0x43001C14U) /**< \brief (CCL) LUT Control x 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for CCL peripheral ========== */ +#define CCL_GCLK_ID 34 // GCLK index for CCL +#define CCL_IO_NUM 12 // Numer of input pins +#define CCL_LUT_NUM 4 // Number of LUT in a CCL +#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL + +#endif /* _SAML21_CCL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dac.h new file mode 100644 index 0000000000..c46b407e53 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dac.h @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief Instance description for DAC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_DAC_INSTANCE_ +#define _SAML21_DAC_INSTANCE_ + +/* ========== Register definition for DAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DAC_CTRLA (0x42003000U) /**< \brief (DAC) Control A */ +#define REG_DAC_CTRLB (0x42003001U) /**< \brief (DAC) Control B */ +#define REG_DAC_EVCTRL (0x42003002U) /**< \brief (DAC) Event Control */ +#define REG_DAC_INTENCLR (0x42003004U) /**< \brief (DAC) Interrupt Enable Clear */ +#define REG_DAC_INTENSET (0x42003005U) /**< \brief (DAC) Interrupt Enable Set */ +#define REG_DAC_INTFLAG (0x42003006U) /**< \brief (DAC) Interrupt Flag Status and Clear */ +#define REG_DAC_STATUS (0x42003007U) /**< \brief (DAC) Status */ +#define REG_DAC_SYNCBUSY (0x42003008U) /**< \brief (DAC) Synchronization Busy */ +#define REG_DAC_DACCTRL0 (0x4200300CU) /**< \brief (DAC) DAC 0 Control */ +#define REG_DAC_DACCTRL1 (0x4200300EU) /**< \brief (DAC) DAC 1 Control */ +#define REG_DAC_DATA0 (0x42003010U) /**< \brief (DAC) DAC 0 Data */ +#define REG_DAC_DATA1 (0x42003012U) /**< \brief (DAC) DAC 1 Data */ +#define REG_DAC_DATABUF0 (0x42003014U) /**< \brief (DAC) DAC 0 Data Buffer */ +#define REG_DAC_DATABUF1 (0x42003016U) /**< \brief (DAC) DAC 1 Data Buffer */ +#define REG_DAC_DBGCTRL (0x42003018U) /**< \brief (DAC) Debug Control */ +#else +#define REG_DAC_CTRLA (*(RwReg8 *)0x42003000U) /**< \brief (DAC) Control A */ +#define REG_DAC_CTRLB (*(RwReg8 *)0x42003001U) /**< \brief (DAC) Control B */ +#define REG_DAC_EVCTRL (*(RwReg8 *)0x42003002U) /**< \brief (DAC) Event Control */ +#define REG_DAC_INTENCLR (*(RwReg8 *)0x42003004U) /**< \brief (DAC) Interrupt Enable Clear */ +#define REG_DAC_INTENSET (*(RwReg8 *)0x42003005U) /**< \brief (DAC) Interrupt Enable Set */ +#define REG_DAC_INTFLAG (*(RwReg8 *)0x42003006U) /**< \brief (DAC) Interrupt Flag Status and Clear */ +#define REG_DAC_STATUS (*(RoReg8 *)0x42003007U) /**< \brief (DAC) Status */ +#define REG_DAC_SYNCBUSY (*(RoReg *)0x42003008U) /**< \brief (DAC) Synchronization Busy */ +#define REG_DAC_DACCTRL0 (*(RwReg16*)0x4200300CU) /**< \brief (DAC) DAC 0 Control */ +#define REG_DAC_DACCTRL1 (*(RwReg16*)0x4200300EU) /**< \brief (DAC) DAC 1 Control */ +#define REG_DAC_DATA0 (*(WoReg16*)0x42003010U) /**< \brief (DAC) DAC 0 Data */ +#define REG_DAC_DATA1 (*(WoReg16*)0x42003012U) /**< \brief (DAC) DAC 1 Data */ +#define REG_DAC_DATABUF0 (*(WoReg16*)0x42003014U) /**< \brief (DAC) DAC 0 Data Buffer */ +#define REG_DAC_DATABUF1 (*(WoReg16*)0x42003016U) /**< \brief (DAC) DAC 1 Data Buffer */ +#define REG_DAC_DBGCTRL (*(RwReg8 *)0x42003018U) /**< \brief (DAC) Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DAC peripheral ========== */ +#define DAC_DAC_NUM 2 // Number of DACs +#define DAC_DATA_SIZE 12 // Number of bits in data +#define DAC_DMAC_ID_EMPTY_0 38 +#define DAC_DMAC_ID_EMPTY_1 39 +#define DAC_DMAC_ID_EMPTY_LSB 38 +#define DAC_DMAC_ID_EMPTY_MSB 39 +#define DAC_DMAC_ID_EMPTY_SIZE 2 +#define DAC_GCLK_ID 32 // Index of Generic Clock + +#endif /* _SAML21_DAC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dmac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dmac.h new file mode 100644 index 0000000000..6eb9c47b77 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dmac.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief Instance description for DMAC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_DMAC_INSTANCE_ +#define _SAML21_DMAC_INSTANCE_ + +/* ========== Register definition for DMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC_CTRL (0x44000400U) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (0x44000402U) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (0x44000404U) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (0x44000408U) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (0x4400040CU) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (0x4400040DU) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_SWTRIGCTRL (0x44000410U) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (0x44000414U) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (0x44000420U) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (0x44000424U) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (0x44000428U) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (0x4400042CU) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (0x44000430U) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (0x44000434U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (0x44000438U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (0x4400043FU) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (0x44000440U) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (0x44000444U) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (0x4400044CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (0x4400044DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (0x4400044EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (0x4400044FU) /**< \brief (DMAC) Channel Status */ +#else +#define REG_DMAC_CTRL (*(RwReg16*)0x44000400U) /**< \brief (DMAC) Control */ +#define REG_DMAC_CRCCTRL (*(RwReg16*)0x44000402U) /**< \brief (DMAC) CRC Control */ +#define REG_DMAC_CRCDATAIN (*(RwReg *)0x44000404U) /**< \brief (DMAC) CRC Data Input */ +#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x44000408U) /**< \brief (DMAC) CRC Checksum */ +#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4400040CU) /**< \brief (DMAC) CRC Status */ +#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4400040DU) /**< \brief (DMAC) Debug Control */ +#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x44000410U) /**< \brief (DMAC) Software Trigger Control */ +#define REG_DMAC_PRICTRL0 (*(RwReg *)0x44000414U) /**< \brief (DMAC) Priority Control 0 */ +#define REG_DMAC_INTPEND (*(RwReg16*)0x44000420U) /**< \brief (DMAC) Interrupt Pending */ +#define REG_DMAC_INTSTATUS (*(RoReg *)0x44000424U) /**< \brief (DMAC) Interrupt Status */ +#define REG_DMAC_BUSYCH (*(RoReg *)0x44000428U) /**< \brief (DMAC) Busy Channels */ +#define REG_DMAC_PENDCH (*(RoReg *)0x4400042CU) /**< \brief (DMAC) Pending Channels */ +#define REG_DMAC_ACTIVE (*(RoReg *)0x44000430U) /**< \brief (DMAC) Active Channel and Levels */ +#define REG_DMAC_BASEADDR (*(RwReg *)0x44000434U) /**< \brief (DMAC) Descriptor Memory Section Base Address */ +#define REG_DMAC_WRBADDR (*(RwReg *)0x44000438U) /**< \brief (DMAC) Write-Back Memory Section Base Address */ +#define REG_DMAC_CHID (*(RwReg8 *)0x4400043FU) /**< \brief (DMAC) Channel ID */ +#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x44000440U) /**< \brief (DMAC) Channel Control A */ +#define REG_DMAC_CHCTRLB (*(RwReg *)0x44000444U) /**< \brief (DMAC) Channel Control B */ +#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4400044CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */ +#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4400044DU) /**< \brief (DMAC) Channel Interrupt Enable Set */ +#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4400044EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ +#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4400044FU) /**< \brief (DMAC) Channel Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DMAC peripheral ========== */ +#define DMAC_CH_BITS 4 // Number of bits to select channel +#define DMAC_CH_NUM 16 // Number of channels +#define DMAC_CLK_AHB_ID 11 // AHB clock index +#define DMAC_EVIN_NUM 8 // Number of input events +#define DMAC_EVOUT_NUM 8 // Number of output events +#define DMAC_LVL_BITS 2 // Number of bit to select level priority +#define DMAC_LVL_NUM 4 // Enable priority level number +#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value +#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value +#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value +#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source +#define DMAC_TRIG_NUM 46 // Number of peripheral triggers + +#endif /* _SAML21_DMAC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dsu.h new file mode 100644 index 0000000000..b2261ccb3e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_dsu.h @@ -0,0 +1,112 @@ +/** + * \file + * + * \brief Instance description for DSU + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_DSU_INSTANCE_ +#define _SAML21_DSU_INSTANCE_ + +/* ========== Register definition for DSU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */ +#define REG_DSU_DCFG0 (0x410020F0U) /**< \brief (DSU) Device Configuration 0 */ +#define REG_DSU_DCFG1 (0x410020F4U) /**< \brief (DSU) Device Configuration 1 */ +#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ +#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ +#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ +#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID5 (0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */ +#define REG_DSU_PID6 (0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */ +#define REG_DSU_PID7 (0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */ +#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ +#else +#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */ +#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */ +#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */ +#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */ +#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */ +#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */ +#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ +#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ +#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */ +#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0U) /**< \brief (DSU) Device Configuration 0 */ +#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4U) /**< \brief (DSU) Device Configuration 1 */ +#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ +#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ +#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ +#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ +#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ +#define REG_DSU_PID5 (*(RoReg *)0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */ +#define REG_DSU_PID6 (*(RoReg *)0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */ +#define REG_DSU_PID7 (*(RoReg *)0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */ +#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ +#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ +#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ +#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ +#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ +#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ +#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ +#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DSU peripheral ========== */ +#define DSU_CLK_AHB_ID 5 + +#endif /* _SAML21_DSU_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_eic.h new file mode 100644 index 0000000000..7ccbfeaff8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_eic.h @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief Instance description for EIC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_EIC_INSTANCE_ +#define _SAML21_EIC_INSTANCE_ + +/* ========== Register definition for EIC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EIC_CTRLA (0x40002400U) /**< \brief (EIC) Control */ +#define REG_EIC_NMICTRL (0x40002401U) /**< \brief (EIC) NMI Control */ +#define REG_EIC_NMIFLAG (0x40002402U) /**< \brief (EIC) NMI Interrupt Flag */ +#define REG_EIC_SYNCBUSY (0x40002404U) /**< \brief (EIC) Syncbusy register */ +#define REG_EIC_EVCTRL (0x40002408U) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (0x4000240CU) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (0x40002410U) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (0x40002414U) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_EIC_ASYNCH (0x40002418U) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ +#define REG_EIC_CONFIG0 (0x4000241CU) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (0x40002420U) /**< \brief (EIC) Configuration 1 */ +#else +#define REG_EIC_CTRLA (*(RwReg8 *)0x40002400U) /**< \brief (EIC) Control */ +#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002401U) /**< \brief (EIC) NMI Control */ +#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002402U) /**< \brief (EIC) NMI Interrupt Flag */ +#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002404U) /**< \brief (EIC) Syncbusy register */ +#define REG_EIC_EVCTRL (*(RwReg *)0x40002408U) /**< \brief (EIC) Event Control */ +#define REG_EIC_INTENCLR (*(RwReg *)0x4000240CU) /**< \brief (EIC) Interrupt Enable Clear */ +#define REG_EIC_INTENSET (*(RwReg *)0x40002410U) /**< \brief (EIC) Interrupt Enable Set */ +#define REG_EIC_INTFLAG (*(RwReg *)0x40002414U) /**< \brief (EIC) Interrupt Flag Status and Clear */ +#define REG_EIC_EIC_ASYNCH (*(RwReg *)0x40002418U) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ +#define REG_EIC_CONFIG0 (*(RwReg *)0x4000241CU) /**< \brief (EIC) Configuration 0 */ +#define REG_EIC_CONFIG1 (*(RwReg *)0x40002420U) /**< \brief (EIC) Configuration 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EIC peripheral ========== */ +#define EIC_EXTINT_NUM 16 +#define EIC_GCLK_ID 3 +#define EIC_NUMBER_OF_CONFIG_REGS 2 +#define EIC_NUMBER_OF_INTERRUPTS 16 + +#endif /* _SAML21_EIC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_evsys.h new file mode 100644 index 0000000000..fc69aefa97 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_evsys.h @@ -0,0 +1,338 @@ +/** + * \file + * + * \brief Instance description for EVSYS + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_EVSYS_INSTANCE_ +#define _SAML21_EVSYS_INSTANCE_ + +/* ========== Register definition for EVSYS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EVSYS_CTRLA (0x43000000U) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHSTATUS (0x4300000CU) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (0x43000010U) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (0x43000014U) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (0x43000018U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#define REG_EVSYS_SWEVT (0x4300001CU) /**< \brief (EVSYS) Software Event */ +#define REG_EVSYS_CHANNEL0 (0x43000020U) /**< \brief (EVSYS) Channel 0 */ +#define REG_EVSYS_CHANNEL1 (0x43000024U) /**< \brief (EVSYS) Channel 1 */ +#define REG_EVSYS_CHANNEL2 (0x43000028U) /**< \brief (EVSYS) Channel 2 */ +#define REG_EVSYS_CHANNEL3 (0x4300002CU) /**< \brief (EVSYS) Channel 3 */ +#define REG_EVSYS_CHANNEL4 (0x43000030U) /**< \brief (EVSYS) Channel 4 */ +#define REG_EVSYS_CHANNEL5 (0x43000034U) /**< \brief (EVSYS) Channel 5 */ +#define REG_EVSYS_CHANNEL6 (0x43000038U) /**< \brief (EVSYS) Channel 6 */ +#define REG_EVSYS_CHANNEL7 (0x4300003CU) /**< \brief (EVSYS) Channel 7 */ +#define REG_EVSYS_CHANNEL8 (0x43000040U) /**< \brief (EVSYS) Channel 8 */ +#define REG_EVSYS_CHANNEL9 (0x43000044U) /**< \brief (EVSYS) Channel 9 */ +#define REG_EVSYS_CHANNEL10 (0x43000048U) /**< \brief (EVSYS) Channel 10 */ +#define REG_EVSYS_CHANNEL11 (0x4300004CU) /**< \brief (EVSYS) Channel 11 */ +#define REG_EVSYS_USER0 (0x43000080U) /**< \brief (EVSYS) User Multiplexer 0 */ +#define REG_EVSYS_USER1 (0x43000084U) /**< \brief (EVSYS) User Multiplexer 1 */ +#define REG_EVSYS_USER2 (0x43000088U) /**< \brief (EVSYS) User Multiplexer 2 */ +#define REG_EVSYS_USER3 (0x4300008CU) /**< \brief (EVSYS) User Multiplexer 3 */ +#define REG_EVSYS_USER4 (0x43000090U) /**< \brief (EVSYS) User Multiplexer 4 */ +#define REG_EVSYS_USER5 (0x43000094U) /**< \brief (EVSYS) User Multiplexer 5 */ +#define REG_EVSYS_USER6 (0x43000098U) /**< \brief (EVSYS) User Multiplexer 6 */ +#define REG_EVSYS_USER7 (0x4300009CU) /**< \brief (EVSYS) User Multiplexer 7 */ +#define REG_EVSYS_USER8 (0x430000A0U) /**< \brief (EVSYS) User Multiplexer 8 */ +#define REG_EVSYS_USER9 (0x430000A4U) /**< \brief (EVSYS) User Multiplexer 9 */ +#define REG_EVSYS_USER10 (0x430000A8U) /**< \brief (EVSYS) User Multiplexer 10 */ +#define REG_EVSYS_USER11 (0x430000ACU) /**< \brief (EVSYS) User Multiplexer 11 */ +#define REG_EVSYS_USER12 (0x430000B0U) /**< \brief (EVSYS) User Multiplexer 12 */ +#define REG_EVSYS_USER13 (0x430000B4U) /**< \brief (EVSYS) User Multiplexer 13 */ +#define REG_EVSYS_USER14 (0x430000B8U) /**< \brief (EVSYS) User Multiplexer 14 */ +#define REG_EVSYS_USER15 (0x430000BCU) /**< \brief (EVSYS) User Multiplexer 15 */ +#define REG_EVSYS_USER16 (0x430000C0U) /**< \brief (EVSYS) User Multiplexer 16 */ +#define REG_EVSYS_USER17 (0x430000C4U) /**< \brief (EVSYS) User Multiplexer 17 */ +#define REG_EVSYS_USER18 (0x430000C8U) /**< \brief (EVSYS) User Multiplexer 18 */ +#define REG_EVSYS_USER19 (0x430000CCU) /**< \brief (EVSYS) User Multiplexer 19 */ +#define REG_EVSYS_USER20 (0x430000D0U) /**< \brief (EVSYS) User Multiplexer 20 */ +#define REG_EVSYS_USER21 (0x430000D4U) /**< \brief (EVSYS) User Multiplexer 21 */ +#define REG_EVSYS_USER22 (0x430000D8U) /**< \brief (EVSYS) User Multiplexer 22 */ +#define REG_EVSYS_USER23 (0x430000DCU) /**< \brief (EVSYS) User Multiplexer 23 */ +#define REG_EVSYS_USER24 (0x430000E0U) /**< \brief (EVSYS) User Multiplexer 24 */ +#define REG_EVSYS_USER25 (0x430000E4U) /**< \brief (EVSYS) User Multiplexer 25 */ +#define REG_EVSYS_USER26 (0x430000E8U) /**< \brief (EVSYS) User Multiplexer 26 */ +#define REG_EVSYS_USER27 (0x430000ECU) /**< \brief (EVSYS) User Multiplexer 27 */ +#define REG_EVSYS_USER28 (0x430000F0U) /**< \brief (EVSYS) User Multiplexer 28 */ +#define REG_EVSYS_USER29 (0x430000F4U) /**< \brief (EVSYS) User Multiplexer 29 */ +#define REG_EVSYS_USER30 (0x430000F8U) /**< \brief (EVSYS) User Multiplexer 30 */ +#define REG_EVSYS_USER31 (0x430000FCU) /**< \brief (EVSYS) User Multiplexer 31 */ +#define REG_EVSYS_USER32 (0x43000100U) /**< \brief (EVSYS) User Multiplexer 32 */ +#define REG_EVSYS_USER33 (0x43000104U) /**< \brief (EVSYS) User Multiplexer 33 */ +#define REG_EVSYS_USER34 (0x43000108U) /**< \brief (EVSYS) User Multiplexer 34 */ +#define REG_EVSYS_USER35 (0x4300010CU) /**< \brief (EVSYS) User Multiplexer 35 */ +#define REG_EVSYS_USER36 (0x43000110U) /**< \brief (EVSYS) User Multiplexer 36 */ +#define REG_EVSYS_USER37 (0x43000114U) /**< \brief (EVSYS) User Multiplexer 37 */ +#define REG_EVSYS_USER38 (0x43000118U) /**< \brief (EVSYS) User Multiplexer 38 */ +#define REG_EVSYS_USER39 (0x4300011CU) /**< \brief (EVSYS) User Multiplexer 39 */ +#define REG_EVSYS_USER40 (0x43000120U) /**< \brief (EVSYS) User Multiplexer 40 */ +#define REG_EVSYS_USER41 (0x43000124U) /**< \brief (EVSYS) User Multiplexer 41 */ +#define REG_EVSYS_USER42 (0x43000128U) /**< \brief (EVSYS) User Multiplexer 42 */ +#define REG_EVSYS_USER43 (0x4300012CU) /**< \brief (EVSYS) User Multiplexer 43 */ +#define REG_EVSYS_USER44 (0x43000130U) /**< \brief (EVSYS) User Multiplexer 44 */ +#else +#define REG_EVSYS_CTRLA (*(RwReg8 *)0x43000000U) /**< \brief (EVSYS) Control */ +#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4300000CU) /**< \brief (EVSYS) Channel Status */ +#define REG_EVSYS_INTENCLR (*(RwReg *)0x43000010U) /**< \brief (EVSYS) Interrupt Enable Clear */ +#define REG_EVSYS_INTENSET (*(RwReg *)0x43000014U) /**< \brief (EVSYS) Interrupt Enable Set */ +#define REG_EVSYS_INTFLAG (*(RwReg *)0x43000018U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ +#define REG_EVSYS_SWEVT (*(WoReg *)0x4300001CU) /**< \brief (EVSYS) Software Event */ +#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x43000020U) /**< \brief (EVSYS) Channel 0 */ +#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x43000024U) /**< \brief (EVSYS) Channel 1 */ +#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x43000028U) /**< \brief (EVSYS) Channel 2 */ +#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4300002CU) /**< \brief (EVSYS) Channel 3 */ +#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x43000030U) /**< \brief (EVSYS) Channel 4 */ +#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x43000034U) /**< \brief (EVSYS) Channel 5 */ +#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x43000038U) /**< \brief (EVSYS) Channel 6 */ +#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4300003CU) /**< \brief (EVSYS) Channel 7 */ +#define REG_EVSYS_CHANNEL8 (*(RwReg *)0x43000040U) /**< \brief (EVSYS) Channel 8 */ +#define REG_EVSYS_CHANNEL9 (*(RwReg *)0x43000044U) /**< \brief (EVSYS) Channel 9 */ +#define REG_EVSYS_CHANNEL10 (*(RwReg *)0x43000048U) /**< \brief (EVSYS) Channel 10 */ +#define REG_EVSYS_CHANNEL11 (*(RwReg *)0x4300004CU) /**< \brief (EVSYS) Channel 11 */ +#define REG_EVSYS_USER0 (*(RwReg *)0x43000080U) /**< \brief (EVSYS) User Multiplexer 0 */ +#define REG_EVSYS_USER1 (*(RwReg *)0x43000084U) /**< \brief (EVSYS) User Multiplexer 1 */ +#define REG_EVSYS_USER2 (*(RwReg *)0x43000088U) /**< \brief (EVSYS) User Multiplexer 2 */ +#define REG_EVSYS_USER3 (*(RwReg *)0x4300008CU) /**< \brief (EVSYS) User Multiplexer 3 */ +#define REG_EVSYS_USER4 (*(RwReg *)0x43000090U) /**< \brief (EVSYS) User Multiplexer 4 */ +#define REG_EVSYS_USER5 (*(RwReg *)0x43000094U) /**< \brief (EVSYS) User Multiplexer 5 */ +#define REG_EVSYS_USER6 (*(RwReg *)0x43000098U) /**< \brief (EVSYS) User Multiplexer 6 */ +#define REG_EVSYS_USER7 (*(RwReg *)0x4300009CU) /**< \brief (EVSYS) User Multiplexer 7 */ +#define REG_EVSYS_USER8 (*(RwReg *)0x430000A0U) /**< \brief (EVSYS) User Multiplexer 8 */ +#define REG_EVSYS_USER9 (*(RwReg *)0x430000A4U) /**< \brief (EVSYS) User Multiplexer 9 */ +#define REG_EVSYS_USER10 (*(RwReg *)0x430000A8U) /**< \brief (EVSYS) User Multiplexer 10 */ +#define REG_EVSYS_USER11 (*(RwReg *)0x430000ACU) /**< \brief (EVSYS) User Multiplexer 11 */ +#define REG_EVSYS_USER12 (*(RwReg *)0x430000B0U) /**< \brief (EVSYS) User Multiplexer 12 */ +#define REG_EVSYS_USER13 (*(RwReg *)0x430000B4U) /**< \brief (EVSYS) User Multiplexer 13 */ +#define REG_EVSYS_USER14 (*(RwReg *)0x430000B8U) /**< \brief (EVSYS) User Multiplexer 14 */ +#define REG_EVSYS_USER15 (*(RwReg *)0x430000BCU) /**< \brief (EVSYS) User Multiplexer 15 */ +#define REG_EVSYS_USER16 (*(RwReg *)0x430000C0U) /**< \brief (EVSYS) User Multiplexer 16 */ +#define REG_EVSYS_USER17 (*(RwReg *)0x430000C4U) /**< \brief (EVSYS) User Multiplexer 17 */ +#define REG_EVSYS_USER18 (*(RwReg *)0x430000C8U) /**< \brief (EVSYS) User Multiplexer 18 */ +#define REG_EVSYS_USER19 (*(RwReg *)0x430000CCU) /**< \brief (EVSYS) User Multiplexer 19 */ +#define REG_EVSYS_USER20 (*(RwReg *)0x430000D0U) /**< \brief (EVSYS) User Multiplexer 20 */ +#define REG_EVSYS_USER21 (*(RwReg *)0x430000D4U) /**< \brief (EVSYS) User Multiplexer 21 */ +#define REG_EVSYS_USER22 (*(RwReg *)0x430000D8U) /**< \brief (EVSYS) User Multiplexer 22 */ +#define REG_EVSYS_USER23 (*(RwReg *)0x430000DCU) /**< \brief (EVSYS) User Multiplexer 23 */ +#define REG_EVSYS_USER24 (*(RwReg *)0x430000E0U) /**< \brief (EVSYS) User Multiplexer 24 */ +#define REG_EVSYS_USER25 (*(RwReg *)0x430000E4U) /**< \brief (EVSYS) User Multiplexer 25 */ +#define REG_EVSYS_USER26 (*(RwReg *)0x430000E8U) /**< \brief (EVSYS) User Multiplexer 26 */ +#define REG_EVSYS_USER27 (*(RwReg *)0x430000ECU) /**< \brief (EVSYS) User Multiplexer 27 */ +#define REG_EVSYS_USER28 (*(RwReg *)0x430000F0U) /**< \brief (EVSYS) User Multiplexer 28 */ +#define REG_EVSYS_USER29 (*(RwReg *)0x430000F4U) /**< \brief (EVSYS) User Multiplexer 29 */ +#define REG_EVSYS_USER30 (*(RwReg *)0x430000F8U) /**< \brief (EVSYS) User Multiplexer 30 */ +#define REG_EVSYS_USER31 (*(RwReg *)0x430000FCU) /**< \brief (EVSYS) User Multiplexer 31 */ +#define REG_EVSYS_USER32 (*(RwReg *)0x43000100U) /**< \brief (EVSYS) User Multiplexer 32 */ +#define REG_EVSYS_USER33 (*(RwReg *)0x43000104U) /**< \brief (EVSYS) User Multiplexer 33 */ +#define REG_EVSYS_USER34 (*(RwReg *)0x43000108U) /**< \brief (EVSYS) User Multiplexer 34 */ +#define REG_EVSYS_USER35 (*(RwReg *)0x4300010CU) /**< \brief (EVSYS) User Multiplexer 35 */ +#define REG_EVSYS_USER36 (*(RwReg *)0x43000110U) /**< \brief (EVSYS) User Multiplexer 36 */ +#define REG_EVSYS_USER37 (*(RwReg *)0x43000114U) /**< \brief (EVSYS) User Multiplexer 37 */ +#define REG_EVSYS_USER38 (*(RwReg *)0x43000118U) /**< \brief (EVSYS) User Multiplexer 38 */ +#define REG_EVSYS_USER39 (*(RwReg *)0x4300011CU) /**< \brief (EVSYS) User Multiplexer 39 */ +#define REG_EVSYS_USER40 (*(RwReg *)0x43000120U) /**< \brief (EVSYS) User Multiplexer 40 */ +#define REG_EVSYS_USER41 (*(RwReg *)0x43000124U) /**< \brief (EVSYS) User Multiplexer 41 */ +#define REG_EVSYS_USER42 (*(RwReg *)0x43000128U) /**< \brief (EVSYS) User Multiplexer 42 */ +#define REG_EVSYS_USER43 (*(RwReg *)0x4300012CU) /**< \brief (EVSYS) User Multiplexer 43 */ +#define REG_EVSYS_USER44 (*(RwReg *)0x43000130U) /**< \brief (EVSYS) User Multiplexer 44 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EVSYS peripheral ========== */ +#define EVSYS_CHANNELS 12 // Number of Channels +#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel +#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1 +#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators +#define EVSYS_GCLK_ID_0 5 +#define EVSYS_GCLK_ID_1 6 +#define EVSYS_GCLK_ID_2 7 +#define EVSYS_GCLK_ID_3 8 +#define EVSYS_GCLK_ID_4 9 +#define EVSYS_GCLK_ID_5 10 +#define EVSYS_GCLK_ID_6 11 +#define EVSYS_GCLK_ID_7 12 +#define EVSYS_GCLK_ID_8 13 +#define EVSYS_GCLK_ID_9 14 +#define EVSYS_GCLK_ID_10 15 +#define EVSYS_GCLK_ID_11 16 +#define EVSYS_GCLK_ID_LSB 5 +#define EVSYS_GCLK_ID_MSB 16 +#define EVSYS_GCLK_ID_SIZE 12 +#define EVSYS_GENERATORS 83 // Total Number of Event Generators +#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator +#define EVSYS_USERS 45 // Total Number of Event Users +#define EVSYS_USERS_BITS 6 // Number of bits to select Event User + +// GENERATORS +#define EVSYS_ID_GEN_RTC_CMP_0 1 +#define EVSYS_ID_GEN_RTC_CMP_1 2 +#define EVSYS_ID_GEN_RTC_OVF 3 +#define EVSYS_ID_GEN_RTC_PER_0 4 +#define EVSYS_ID_GEN_RTC_PER_1 5 +#define EVSYS_ID_GEN_RTC_PER_2 6 +#define EVSYS_ID_GEN_RTC_PER_3 7 +#define EVSYS_ID_GEN_RTC_PER_4 8 +#define EVSYS_ID_GEN_RTC_PER_5 9 +#define EVSYS_ID_GEN_RTC_PER_6 10 +#define EVSYS_ID_GEN_RTC_PER_7 11 +#define EVSYS_ID_GEN_EIC_EXTINT_0 12 +#define EVSYS_ID_GEN_EIC_EXTINT_1 13 +#define EVSYS_ID_GEN_EIC_EXTINT_2 14 +#define EVSYS_ID_GEN_EIC_EXTINT_3 15 +#define EVSYS_ID_GEN_EIC_EXTINT_4 16 +#define EVSYS_ID_GEN_EIC_EXTINT_5 17 +#define EVSYS_ID_GEN_EIC_EXTINT_6 18 +#define EVSYS_ID_GEN_EIC_EXTINT_7 19 +#define EVSYS_ID_GEN_EIC_EXTINT_8 20 +#define EVSYS_ID_GEN_EIC_EXTINT_9 21 +#define EVSYS_ID_GEN_EIC_EXTINT_10 22 +#define EVSYS_ID_GEN_EIC_EXTINT_11 23 +#define EVSYS_ID_GEN_EIC_EXTINT_12 24 +#define EVSYS_ID_GEN_EIC_EXTINT_13 25 +#define EVSYS_ID_GEN_EIC_EXTINT_14 26 +#define EVSYS_ID_GEN_EIC_EXTINT_15 27 +#define EVSYS_ID_GEN_DMAC_CH_0 28 +#define EVSYS_ID_GEN_DMAC_CH_1 29 +#define EVSYS_ID_GEN_DMAC_CH_2 30 +#define EVSYS_ID_GEN_DMAC_CH_3 31 +#define EVSYS_ID_GEN_DMAC_CH_4 32 +#define EVSYS_ID_GEN_DMAC_CH_5 33 +#define EVSYS_ID_GEN_DMAC_CH_6 34 +#define EVSYS_ID_GEN_DMAC_CH_7 35 +#define EVSYS_ID_GEN_TCC0_OVF 36 +#define EVSYS_ID_GEN_TCC0_TRG 37 +#define EVSYS_ID_GEN_TCC0_CNT 38 +#define EVSYS_ID_GEN_TCC0_MCX_0 39 +#define EVSYS_ID_GEN_TCC0_MCX_1 40 +#define EVSYS_ID_GEN_TCC0_MCX_2 41 +#define EVSYS_ID_GEN_TCC0_MCX_3 42 +#define EVSYS_ID_GEN_TCC1_OVF 43 +#define EVSYS_ID_GEN_TCC1_TRG 44 +#define EVSYS_ID_GEN_TCC1_CNT 45 +#define EVSYS_ID_GEN_TCC1_MCX_0 46 +#define EVSYS_ID_GEN_TCC1_MCX_1 47 +#define EVSYS_ID_GEN_TCC2_OVF 48 +#define EVSYS_ID_GEN_TCC2_TRG 49 +#define EVSYS_ID_GEN_TCC2_CNT 50 +#define EVSYS_ID_GEN_TCC2_MCX_0 51 +#define EVSYS_ID_GEN_TCC2_MCX_1 52 +#define EVSYS_ID_GEN_TC0_OVF 53 +#define EVSYS_ID_GEN_TC0_MCX_0 54 +#define EVSYS_ID_GEN_TC0_MCX_1 55 +#define EVSYS_ID_GEN_TC1_OVF 56 +#define EVSYS_ID_GEN_TC1_MCX_0 57 +#define EVSYS_ID_GEN_TC1_MCX_1 58 +#define EVSYS_ID_GEN_TC2_OVF 59 +#define EVSYS_ID_GEN_TC2_MCX_0 60 +#define EVSYS_ID_GEN_TC2_MCX_1 61 +#define EVSYS_ID_GEN_TC3_OVF 62 +#define EVSYS_ID_GEN_TC3_MCX_0 63 +#define EVSYS_ID_GEN_TC3_MCX_1 64 +#define EVSYS_ID_GEN_TC4_OVF 65 +#define EVSYS_ID_GEN_TC4_MCX_0 66 +#define EVSYS_ID_GEN_TC4_MCX_1 67 +#define EVSYS_ID_GEN_ADC_RESRDY 68 +#define EVSYS_ID_GEN_ADC_WINMON 69 +#define EVSYS_ID_GEN_AC_COMP_0 70 +#define EVSYS_ID_GEN_AC_COMP_1 71 +#define EVSYS_ID_GEN_AC_WIN_0 72 +#define EVSYS_ID_GEN_DAC_EMPTY_0 73 +#define EVSYS_ID_GEN_DAC_EMPTY_1 74 +#define EVSYS_ID_GEN_PTC_EOC 75 +#define EVSYS_ID_GEN_PTC_WCOMP 76 +#define EVSYS_ID_GEN_TRNG_READY 77 +#define EVSYS_ID_GEN_CCL_LUTOUT_0 78 +#define EVSYS_ID_GEN_CCL_LUTOUT_1 79 +#define EVSYS_ID_GEN_CCL_LUTOUT_2 80 +#define EVSYS_ID_GEN_CCL_LUTOUT_3 81 +#define EVSYS_ID_GEN_PAC_ACCERR 82 +#define EVSYS_ID_GEN_TAL_BRK 83 + +// USERS +#define EVSYS_ID_USER_PORT_EV_0 0 +#define EVSYS_ID_USER_PORT_EV_1 1 +#define EVSYS_ID_USER_PORT_EV_2 2 +#define EVSYS_ID_USER_PORT_EV_3 3 +#define EVSYS_ID_USER_DMAC_CH_0 4 +#define EVSYS_ID_USER_DMAC_CH_1 5 +#define EVSYS_ID_USER_DMAC_CH_2 6 +#define EVSYS_ID_USER_DMAC_CH_3 7 +#define EVSYS_ID_USER_DMAC_CH_4 8 +#define EVSYS_ID_USER_DMAC_CH_5 9 +#define EVSYS_ID_USER_DMAC_CH_6 10 +#define EVSYS_ID_USER_DMAC_CH_7 11 +#define EVSYS_ID_USER_TCC0_EV_0 12 +#define EVSYS_ID_USER_TCC0_EV_1 13 +#define EVSYS_ID_USER_TCC0_MC_0 14 +#define EVSYS_ID_USER_TCC0_MC_1 15 +#define EVSYS_ID_USER_TCC0_MC_2 16 +#define EVSYS_ID_USER_TCC0_MC_3 17 +#define EVSYS_ID_USER_TCC1_EV_0 18 +#define EVSYS_ID_USER_TCC1_EV_1 19 +#define EVSYS_ID_USER_TCC1_MC_0 20 +#define EVSYS_ID_USER_TCC1_MC_1 21 +#define EVSYS_ID_USER_TCC2_EV_0 22 +#define EVSYS_ID_USER_TCC2_EV_1 23 +#define EVSYS_ID_USER_TCC2_MC_0 24 +#define EVSYS_ID_USER_TCC2_MC_1 25 +#define EVSYS_ID_USER_TC0_EVU 26 +#define EVSYS_ID_USER_TC1_EVU 27 +#define EVSYS_ID_USER_TC2_EVU 28 +#define EVSYS_ID_USER_TC3_EVU 29 +#define EVSYS_ID_USER_TC4_EVU 30 +#define EVSYS_ID_USER_ADC_START 31 +#define EVSYS_ID_USER_ADC_SYNC 32 +#define EVSYS_ID_USER_AC_SOC_0 33 +#define EVSYS_ID_USER_AC_SOC_1 34 +#define EVSYS_ID_USER_DAC_START_0 35 +#define EVSYS_ID_USER_DAC_START_1 36 +#define EVSYS_ID_USER_PTC_STCONV 37 +#define EVSYS_ID_USER_CCL_LUTIN_0 38 +#define EVSYS_ID_USER_CCL_LUTIN_1 39 +#define EVSYS_ID_USER_CCL_LUTIN_2 40 +#define EVSYS_ID_USER_CCL_LUTIN_3 41 +#define EVSYS_ID_USER_TAL_BRK 42 +#define EVSYS_ID_USER_MTB_START 43 +#define EVSYS_ID_USER_MTB_STOP 44 + +#endif /* _SAML21_EVSYS_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_gclk.h new file mode 100644 index 0000000000..329c69cd52 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_gclk.h @@ -0,0 +1,167 @@ +/** + * \file + * + * \brief Instance description for GCLK + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_GCLK_INSTANCE_ +#define _SAML21_GCLK_INSTANCE_ + +/* ========== Register definition for GCLK peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GCLK_CTRLA (0x40001800U) /**< \brief (GCLK) Control */ +#define REG_GCLK_SYNCBUSY (0x40001804U) /**< \brief (GCLK) Synchronization Busy */ +#define REG_GCLK_GENCTRL0 (0x40001820U) /**< \brief (GCLK) Generic Clock Generator Control 0 */ +#define REG_GCLK_GENCTRL1 (0x40001824U) /**< \brief (GCLK) Generic Clock Generator Control 1 */ +#define REG_GCLK_GENCTRL2 (0x40001828U) /**< \brief (GCLK) Generic Clock Generator Control 2 */ +#define REG_GCLK_GENCTRL3 (0x4000182CU) /**< \brief (GCLK) Generic Clock Generator Control 3 */ +#define REG_GCLK_GENCTRL4 (0x40001830U) /**< \brief (GCLK) Generic Clock Generator Control 4 */ +#define REG_GCLK_GENCTRL5 (0x40001834U) /**< \brief (GCLK) Generic Clock Generator Control 5 */ +#define REG_GCLK_GENCTRL6 (0x40001838U) /**< \brief (GCLK) Generic Clock Generator Control 6 */ +#define REG_GCLK_GENCTRL7 (0x4000183CU) /**< \brief (GCLK) Generic Clock Generator Control 7 */ +#define REG_GCLK_GENCTRL8 (0x40001840U) /**< \brief (GCLK) Generic Clock Generator Control 8 */ +#define REG_GCLK_PCHCTRL0 (0x40001880U) /**< \brief (GCLK) Peripheral Clock Control 0 */ +#define REG_GCLK_PCHCTRL1 (0x40001884U) /**< \brief (GCLK) Peripheral Clock Control 1 */ +#define REG_GCLK_PCHCTRL2 (0x40001888U) /**< \brief (GCLK) Peripheral Clock Control 2 */ +#define REG_GCLK_PCHCTRL3 (0x4000188CU) /**< \brief (GCLK) Peripheral Clock Control 3 */ +#define REG_GCLK_PCHCTRL4 (0x40001890U) /**< \brief (GCLK) Peripheral Clock Control 4 */ +#define REG_GCLK_PCHCTRL5 (0x40001894U) /**< \brief (GCLK) Peripheral Clock Control 5 */ +#define REG_GCLK_PCHCTRL6 (0x40001898U) /**< \brief (GCLK) Peripheral Clock Control 6 */ +#define REG_GCLK_PCHCTRL7 (0x4000189CU) /**< \brief (GCLK) Peripheral Clock Control 7 */ +#define REG_GCLK_PCHCTRL8 (0x400018A0U) /**< \brief (GCLK) Peripheral Clock Control 8 */ +#define REG_GCLK_PCHCTRL9 (0x400018A4U) /**< \brief (GCLK) Peripheral Clock Control 9 */ +#define REG_GCLK_PCHCTRL10 (0x400018A8U) /**< \brief (GCLK) Peripheral Clock Control 10 */ +#define REG_GCLK_PCHCTRL11 (0x400018ACU) /**< \brief (GCLK) Peripheral Clock Control 11 */ +#define REG_GCLK_PCHCTRL12 (0x400018B0U) /**< \brief (GCLK) Peripheral Clock Control 12 */ +#define REG_GCLK_PCHCTRL13 (0x400018B4U) /**< \brief (GCLK) Peripheral Clock Control 13 */ +#define REG_GCLK_PCHCTRL14 (0x400018B8U) /**< \brief (GCLK) Peripheral Clock Control 14 */ +#define REG_GCLK_PCHCTRL15 (0x400018BCU) /**< \brief (GCLK) Peripheral Clock Control 15 */ +#define REG_GCLK_PCHCTRL16 (0x400018C0U) /**< \brief (GCLK) Peripheral Clock Control 16 */ +#define REG_GCLK_PCHCTRL17 (0x400018C4U) /**< \brief (GCLK) Peripheral Clock Control 17 */ +#define REG_GCLK_PCHCTRL18 (0x400018C8U) /**< \brief (GCLK) Peripheral Clock Control 18 */ +#define REG_GCLK_PCHCTRL19 (0x400018CCU) /**< \brief (GCLK) Peripheral Clock Control 19 */ +#define REG_GCLK_PCHCTRL20 (0x400018D0U) /**< \brief (GCLK) Peripheral Clock Control 20 */ +#define REG_GCLK_PCHCTRL21 (0x400018D4U) /**< \brief (GCLK) Peripheral Clock Control 21 */ +#define REG_GCLK_PCHCTRL22 (0x400018D8U) /**< \brief (GCLK) Peripheral Clock Control 22 */ +#define REG_GCLK_PCHCTRL23 (0x400018DCU) /**< \brief (GCLK) Peripheral Clock Control 23 */ +#define REG_GCLK_PCHCTRL24 (0x400018E0U) /**< \brief (GCLK) Peripheral Clock Control 24 */ +#define REG_GCLK_PCHCTRL25 (0x400018E4U) /**< \brief (GCLK) Peripheral Clock Control 25 */ +#define REG_GCLK_PCHCTRL26 (0x400018E8U) /**< \brief (GCLK) Peripheral Clock Control 26 */ +#define REG_GCLK_PCHCTRL27 (0x400018ECU) /**< \brief (GCLK) Peripheral Clock Control 27 */ +#define REG_GCLK_PCHCTRL28 (0x400018F0U) /**< \brief (GCLK) Peripheral Clock Control 28 */ +#define REG_GCLK_PCHCTRL29 (0x400018F4U) /**< \brief (GCLK) Peripheral Clock Control 29 */ +#define REG_GCLK_PCHCTRL30 (0x400018F8U) /**< \brief (GCLK) Peripheral Clock Control 30 */ +#define REG_GCLK_PCHCTRL31 (0x400018FCU) /**< \brief (GCLK) Peripheral Clock Control 31 */ +#define REG_GCLK_PCHCTRL32 (0x40001900U) /**< \brief (GCLK) Peripheral Clock Control 32 */ +#define REG_GCLK_PCHCTRL33 (0x40001904U) /**< \brief (GCLK) Peripheral Clock Control 33 */ +#define REG_GCLK_PCHCTRL34 (0x40001908U) /**< \brief (GCLK) Peripheral Clock Control 34 */ +#define REG_GCLK_PCHCTRL35 (0x4000190CU) /**< \brief (GCLK) Peripheral Clock Control 35 */ +#else +#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001800U) /**< \brief (GCLK) Control */ +#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001804U) /**< \brief (GCLK) Synchronization Busy */ +#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001820U) /**< \brief (GCLK) Generic Clock Generator Control 0 */ +#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001824U) /**< \brief (GCLK) Generic Clock Generator Control 1 */ +#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001828U) /**< \brief (GCLK) Generic Clock Generator Control 2 */ +#define REG_GCLK_GENCTRL3 (*(RwReg *)0x4000182CU) /**< \brief (GCLK) Generic Clock Generator Control 3 */ +#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001830U) /**< \brief (GCLK) Generic Clock Generator Control 4 */ +#define REG_GCLK_GENCTRL5 (*(RwReg *)0x40001834U) /**< \brief (GCLK) Generic Clock Generator Control 5 */ +#define REG_GCLK_GENCTRL6 (*(RwReg *)0x40001838U) /**< \brief (GCLK) Generic Clock Generator Control 6 */ +#define REG_GCLK_GENCTRL7 (*(RwReg *)0x4000183CU) /**< \brief (GCLK) Generic Clock Generator Control 7 */ +#define REG_GCLK_GENCTRL8 (*(RwReg *)0x40001840U) /**< \brief (GCLK) Generic Clock Generator Control 8 */ +#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001880U) /**< \brief (GCLK) Peripheral Clock Control 0 */ +#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001884U) /**< \brief (GCLK) Peripheral Clock Control 1 */ +#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001888U) /**< \brief (GCLK) Peripheral Clock Control 2 */ +#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x4000188CU) /**< \brief (GCLK) Peripheral Clock Control 3 */ +#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001890U) /**< \brief (GCLK) Peripheral Clock Control 4 */ +#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001894U) /**< \brief (GCLK) Peripheral Clock Control 5 */ +#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001898U) /**< \brief (GCLK) Peripheral Clock Control 6 */ +#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x4000189CU) /**< \brief (GCLK) Peripheral Clock Control 7 */ +#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x400018A0U) /**< \brief (GCLK) Peripheral Clock Control 8 */ +#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x400018A4U) /**< \brief (GCLK) Peripheral Clock Control 9 */ +#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x400018A8U) /**< \brief (GCLK) Peripheral Clock Control 10 */ +#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x400018ACU) /**< \brief (GCLK) Peripheral Clock Control 11 */ +#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x400018B0U) /**< \brief (GCLK) Peripheral Clock Control 12 */ +#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x400018B4U) /**< \brief (GCLK) Peripheral Clock Control 13 */ +#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x400018B8U) /**< \brief (GCLK) Peripheral Clock Control 14 */ +#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x400018BCU) /**< \brief (GCLK) Peripheral Clock Control 15 */ +#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x400018C0U) /**< \brief (GCLK) Peripheral Clock Control 16 */ +#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x400018C4U) /**< \brief (GCLK) Peripheral Clock Control 17 */ +#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x400018C8U) /**< \brief (GCLK) Peripheral Clock Control 18 */ +#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x400018CCU) /**< \brief (GCLK) Peripheral Clock Control 19 */ +#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x400018D0U) /**< \brief (GCLK) Peripheral Clock Control 20 */ +#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x400018D4U) /**< \brief (GCLK) Peripheral Clock Control 21 */ +#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x400018D8U) /**< \brief (GCLK) Peripheral Clock Control 22 */ +#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x400018DCU) /**< \brief (GCLK) Peripheral Clock Control 23 */ +#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x400018E0U) /**< \brief (GCLK) Peripheral Clock Control 24 */ +#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x400018E4U) /**< \brief (GCLK) Peripheral Clock Control 25 */ +#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x400018E8U) /**< \brief (GCLK) Peripheral Clock Control 26 */ +#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x400018ECU) /**< \brief (GCLK) Peripheral Clock Control 27 */ +#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x400018F0U) /**< \brief (GCLK) Peripheral Clock Control 28 */ +#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x400018F4U) /**< \brief (GCLK) Peripheral Clock Control 29 */ +#define REG_GCLK_PCHCTRL30 (*(RwReg *)0x400018F8U) /**< \brief (GCLK) Peripheral Clock Control 30 */ +#define REG_GCLK_PCHCTRL31 (*(RwReg *)0x400018FCU) /**< \brief (GCLK) Peripheral Clock Control 31 */ +#define REG_GCLK_PCHCTRL32 (*(RwReg *)0x40001900U) /**< \brief (GCLK) Peripheral Clock Control 32 */ +#define REG_GCLK_PCHCTRL33 (*(RwReg *)0x40001904U) /**< \brief (GCLK) Peripheral Clock Control 33 */ +#define REG_GCLK_PCHCTRL34 (*(RwReg *)0x40001908U) /**< \brief (GCLK) Peripheral Clock Control 34 */ +#define REG_GCLK_PCHCTRL35 (*(RwReg *)0x4000190CU) /**< \brief (GCLK) Peripheral Clock Control 35 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for GCLK peripheral ========== */ +#define GCLK_GENDIV_BITS 16 +#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators +#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 +#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 +#define GCLK_NUM 36 // Number of Generic Clock Users +#define GCLK_SOURCE_BITS 4 +#define GCLK_SOURCE_DFLL48M 7 +#define GCLK_SOURCE_FDPLL 8 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC16M 6 +#define GCLK_SOURCE_OSC32K 4 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 5 + +#endif /* _SAML21_GCLK_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mclk.h new file mode 100644 index 0000000000..20fb36f8fe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mclk.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Instance description for MCLK + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_MCLK_INSTANCE_ +#define _SAML21_MCLK_INSTANCE_ + +/* ========== Register definition for MCLK peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MCLK_CTRLA (0x40000400U) /**< \brief (MCLK) Control A */ +#define REG_MCLK_INTENCLR (0x40000401U) /**< \brief (MCLK) Interrupt Enable Clear */ +#define REG_MCLK_INTENSET (0x40000402U) /**< \brief (MCLK) Interrupt Enable Set */ +#define REG_MCLK_INTFLAG (0x40000403U) /**< \brief (MCLK) Interrupt Flag Status and Clear */ +#define REG_MCLK_CPUDIV (0x40000404U) /**< \brief (MCLK) CPU Clock Division */ +#define REG_MCLK_LPDIV (0x40000405U) /**< \brief (MCLK) Low-Power Clock Division */ +#define REG_MCLK_BUPDIV (0x40000406U) /**< \brief (MCLK) Backup Clock Division */ +#define REG_MCLK_AHBMASK (0x40000410U) /**< \brief (MCLK) AHB Mask */ +#define REG_MCLK_APBAMASK (0x40000414U) /**< \brief (MCLK) APBA Mask */ +#define REG_MCLK_APBBMASK (0x40000418U) /**< \brief (MCLK) APBB Mask */ +#define REG_MCLK_APBCMASK (0x4000041CU) /**< \brief (MCLK) APBC Mask */ +#define REG_MCLK_APBDMASK (0x40000420U) /**< \brief (MCLK) APBD Mask */ +#define REG_MCLK_APBEMASK (0x40000424U) /**< \brief (MCLK) APBE Mask */ +#else +#define REG_MCLK_CTRLA (*(RwReg8 *)0x40000400U) /**< \brief (MCLK) Control A */ +#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000401U) /**< \brief (MCLK) Interrupt Enable Clear */ +#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000402U) /**< \brief (MCLK) Interrupt Enable Set */ +#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000403U) /**< \brief (MCLK) Interrupt Flag Status and Clear */ +#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000404U) /**< \brief (MCLK) CPU Clock Division */ +#define REG_MCLK_LPDIV (*(RwReg8 *)0x40000405U) /**< \brief (MCLK) Low-Power Clock Division */ +#define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000406U) /**< \brief (MCLK) Backup Clock Division */ +#define REG_MCLK_AHBMASK (*(RwReg *)0x40000410U) /**< \brief (MCLK) AHB Mask */ +#define REG_MCLK_APBAMASK (*(RwReg *)0x40000414U) /**< \brief (MCLK) APBA Mask */ +#define REG_MCLK_APBBMASK (*(RwReg *)0x40000418U) /**< \brief (MCLK) APBB Mask */ +#define REG_MCLK_APBCMASK (*(RwReg *)0x4000041CU) /**< \brief (MCLK) APBC Mask */ +#define REG_MCLK_APBDMASK (*(RwReg *)0x40000420U) /**< \brief (MCLK) APBD Mask */ +#define REG_MCLK_APBEMASK (*(RwReg *)0x40000424U) /**< \brief (MCLK) APBE Mask */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for MCLK peripheral ========== */ +#define MCLK_CTRLA_MCSEL_GCLK 1 +#define MCLK_CTRLA_MCSEL_OSC8M 0 +#define MCLK_MCLK_CLK_APB_NUM 5 +#define MCLK_SYSTEM_CLOCK 4000000 // System Clock Frequency at Reset + +#endif /* _SAML21_MCLK_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mtb.h new file mode 100644 index 0000000000..e9b493f437 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_mtb.h @@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for MTB + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_MTB_INSTANCE_ +#define _SAML21_MTB_INSTANCE_ + +/* ========== Register definition for MTB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) Peripheral Identification 4 */ +#define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) Peripheral Identification 5 */ +#define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) Peripheral Identification 6 */ +#define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) Peripheral Identification 7 */ +#define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) Peripheral Identification 0 */ +#define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) Peripheral Identification 1 */ +#define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) Peripheral Identification 2 */ +#define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) Peripheral Identification 3 */ +#define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) Component Identification 0 */ +#define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) Component Identification 1 */ +#define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) Component Identification 2 */ +#define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) Component Identification 3 */ +#else +#define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */ +#define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */ +#define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */ +#define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */ +#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ +#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ +#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ +#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ +#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ +#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ +#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ +#define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ +#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */ +#define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) Peripheral Identification 4 */ +#define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) Peripheral Identification 5 */ +#define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) Peripheral Identification 6 */ +#define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) Peripheral Identification 7 */ +#define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) Peripheral Identification 0 */ +#define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) Peripheral Identification 1 */ +#define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) Peripheral Identification 2 */ +#define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) Peripheral Identification 3 */ +#define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) Component Identification 0 */ +#define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) Component Identification 1 */ +#define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) Component Identification 2 */ +#define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) Component Identification 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML21_MTB_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_nvmctrl.h new file mode 100644 index 0000000000..568eba5d6a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_nvmctrl.h @@ -0,0 +1,98 @@ +/** + * \file + * + * \brief Instance description for NVMCTRL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_NVMCTRL_INSTANCE_ +#define _SAML21_NVMCTRL_INSTANCE_ + +/* ========== Register definition for NVMCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */ +#else +#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */ +#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */ +#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ +#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ +#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ +#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ +#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */ +#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */ +#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for NVMCTRL peripheral ========== */ +#define NVMCTRL_AUX0_ADDRESS 0x00804000 +#define NVMCTRL_AUX1_ADDRESS 0x00806000 +#define NVMCTRL_AUX2_ADDRESS 0x00808000 +#define NVMCTRL_AUX3_ADDRESS 0x0080A000 +#define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register +#define NVMCTRL_CLK_AHB_ID_PICACHU 15 // Index of PICACHU AHB Clock +#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF +#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_GCLK_ID 35 // Index of Generic Clock for test +#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 +#define NVMCTRL_PAGES 4096 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 +#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 +#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF +#define NVMCTRL_RWWEE_PAGES 128 +#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area + +#endif /* _SAML21_NVMCTRL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_opamp.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_opamp.h new file mode 100644 index 0000000000..0432eadc5d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_opamp.h @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Instance description for OPAMP + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_OPAMP_INSTANCE_ +#define _SAML21_OPAMP_INSTANCE_ + +/* ========== Register definition for OPAMP peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_OPAMP_CTRLA (0x43001800U) /**< \brief (OPAMP) Control A */ +#define REG_OPAMP_STATUS (0x43001802U) /**< \brief (OPAMP) Status */ +#define REG_OPAMP_OPAMPCTRL0 (0x43001804U) /**< \brief (OPAMP) OPAMP 0 Control */ +#define REG_OPAMP_OPAMPCTRL1 (0x43001808U) /**< \brief (OPAMP) OPAMP 1 Control */ +#define REG_OPAMP_OPAMPCTRL2 (0x4300180CU) /**< \brief (OPAMP) OPAMP 2 Control */ +#else +#define REG_OPAMP_CTRLA (*(RwReg8 *)0x43001800U) /**< \brief (OPAMP) Control A */ +#define REG_OPAMP_STATUS (*(RoReg8 *)0x43001802U) /**< \brief (OPAMP) Status */ +#define REG_OPAMP_OPAMPCTRL0 (*(RwReg *)0x43001804U) /**< \brief (OPAMP) OPAMP 0 Control */ +#define REG_OPAMP_OPAMPCTRL1 (*(RwReg *)0x43001808U) /**< \brief (OPAMP) OPAMP 1 Control */ +#define REG_OPAMP_OPAMPCTRL2 (*(RwReg *)0x4300180CU) /**< \brief (OPAMP) OPAMP 2 Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML21_OPAMP_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_osc32kctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_osc32kctrl.h new file mode 100644 index 0000000000..d8887c9da8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_osc32kctrl.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Instance description for OSC32KCTRL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_OSC32KCTRL_INSTANCE_ +#define _SAML21_OSC32KCTRL_INSTANCE_ + +/* ========== Register definition for OSC32KCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_OSC32KCTRL_INTENCLR (0x40001000U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ +#define REG_OSC32KCTRL_INTENSET (0x40001004U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ +#define REG_OSC32KCTRL_INTFLAG (0x40001008U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ +#define REG_OSC32KCTRL_STATUS (0x4000100CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */ +#define REG_OSC32KCTRL_RTCCTRL (0x40001010U) /**< \brief (OSC32KCTRL) Clock selection */ +#define REG_OSC32KCTRL_XOSC32K (0x40001014U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_OSC32KCTRL_OSC32K (0x40001018U) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */ +#define REG_OSC32KCTRL_OSCULP32K (0x4000101CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#else +#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001000U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ +#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001004U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ +#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001008U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ +#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000100CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */ +#define REG_OSC32KCTRL_RTCCTRL (*(RwReg *)0x40001010U) /**< \brief (OSC32KCTRL) Clock selection */ +#define REG_OSC32KCTRL_XOSC32K (*(RwReg *)0x40001014U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_OSC32KCTRL_OSC32K (*(RwReg *)0x40001018U) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */ +#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000101CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for OSC32KCTRL peripheral ========== */ +#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 + +#endif /* _SAML21_OSC32KCTRL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_oscctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_oscctrl.h new file mode 100644 index 0000000000..298e0e3719 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_oscctrl.h @@ -0,0 +1,98 @@ +/** + * \file + * + * \brief Instance description for OSCCTRL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_OSCCTRL_INSTANCE_ +#define _SAML21_OSCCTRL_INSTANCE_ + +/* ========== Register definition for OSCCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_OSCCTRL_INTENCLR (0x40000C00U) /**< \brief (OSCCTRL) Interrupt Enable Clear */ +#define REG_OSCCTRL_INTENSET (0x40000C04U) /**< \brief (OSCCTRL) Interrupt Enable Set */ +#define REG_OSCCTRL_INTFLAG (0x40000C08U) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ +#define REG_OSCCTRL_STATUS (0x40000C0CU) /**< \brief (OSCCTRL) Power and Clocks Status */ +#define REG_OSCCTRL_XOSCCTRL (0x40000C10U) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_OSCCTRL_OSC16MCTRL (0x40000C14U) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ +#define REG_OSCCTRL_DFLLCTRL (0x40000C18U) /**< \brief (OSCCTRL) DFLL48M Control */ +#define REG_OSCCTRL_DFLLVAL (0x40000C1CU) /**< \brief (OSCCTRL) DFLL48M Value */ +#define REG_OSCCTRL_DFLLMUL (0x40000C20U) /**< \brief (OSCCTRL) DFLL48M Multiplier */ +#define REG_OSCCTRL_DFLLSYNC (0x40000C24U) /**< \brief (OSCCTRL) DFLL48M Synchronization */ +#define REG_OSCCTRL_DPLLCTRLA (0x40000C28U) /**< \brief (OSCCTRL) DPLL Control */ +#define REG_OSCCTRL_DPLLRATIO (0x40000C2CU) /**< \brief (OSCCTRL) DPLL Ratio Control */ +#define REG_OSCCTRL_DPLLCTRLB (0x40000C30U) /**< \brief (OSCCTRL) Digital Core Configuration */ +#define REG_OSCCTRL_DPLLPRESC (0x40000C34U) /**< \brief (OSCCTRL) DPLL Prescaler */ +#define REG_OSCCTRL_DPLLSYNCBUSY (0x40000C38U) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ +#define REG_OSCCTRL_DPLLSTATUS (0x40000C3CU) /**< \brief (OSCCTRL) DPLL Status */ +#else +#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40000C00U) /**< \brief (OSCCTRL) Interrupt Enable Clear */ +#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40000C04U) /**< \brief (OSCCTRL) Interrupt Enable Set */ +#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40000C08U) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ +#define REG_OSCCTRL_STATUS (*(RoReg *)0x40000C0CU) /**< \brief (OSCCTRL) Power and Clocks Status */ +#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40000C10U) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40000C14U) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ +#define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40000C18U) /**< \brief (OSCCTRL) DFLL48M Control */ +#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40000C1CU) /**< \brief (OSCCTRL) DFLL48M Value */ +#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40000C20U) /**< \brief (OSCCTRL) DFLL48M Multiplier */ +#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40000C24U) /**< \brief (OSCCTRL) DFLL48M Synchronization */ +#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40000C28U) /**< \brief (OSCCTRL) DPLL Control */ +#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x40000C2CU) /**< \brief (OSCCTRL) DPLL Ratio Control */ +#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40000C30U) /**< \brief (OSCCTRL) Digital Core Configuration */ +#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40000C34U) /**< \brief (OSCCTRL) DPLL Prescaler */ +#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40000C38U) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ +#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x40000C3CU) /**< \brief (OSCCTRL) DPLL Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for OSCCTRL peripheral ========== */ +#define OSCCTRL_DFLL48M_COARSE_MSB 5 +#define OSCCTRL_DFLL48M_FINE_MSB 9 +#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 +#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL +#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K +#define OSCCTRL_DFLL48M_VERSION 0x310 +#define OSCCTRL_FDPLL_VERSION 0x200 +#define OSCCTRL_OSC16M_VERSION 0x100 +#define OSCCTRL_XOSC_VERSION 0x120 + +#endif /* _SAML21_OSCCTRL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pac.h new file mode 100644 index 0000000000..8c0ab56d0c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pac.h @@ -0,0 +1,91 @@ +/** + * \file + * + * \brief Instance description for PAC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_PAC_INSTANCE_ +#define _SAML21_PAC_INSTANCE_ + +/* ========== Register definition for PAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC_WRCTRL (0x44000000U) /**< \brief (PAC) Write control */ +#define REG_PAC_EVCTRL (0x44000004U) /**< \brief (PAC) Event control */ +#define REG_PAC_INTENCLR (0x44000008U) /**< \brief (PAC) Interrupt enable clear */ +#define REG_PAC_INTENSET (0x44000009U) /**< \brief (PAC) Interrupt enable set */ +#define REG_PAC_INTFLAGAHB (0x44000010U) /**< \brief (PAC) Bridge interrupt flag status */ +#define REG_PAC_INTFLAGA (0x44000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ +#define REG_PAC_INTFLAGB (0x44000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ +#define REG_PAC_INTFLAGC (0x4400001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ +#define REG_PAC_INTFLAGD (0x44000020U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */ +#define REG_PAC_INTFLAGE (0x44000024U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge E */ +#define REG_PAC_STATUSA (0x44000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */ +#define REG_PAC_STATUSB (0x44000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */ +#define REG_PAC_STATUSC (0x4400003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */ +#define REG_PAC_STATUSD (0x44000040U) /**< \brief (PAC) Peripheral write protection status - Bridge D */ +#define REG_PAC_STATUSE (0x44000044U) /**< \brief (PAC) Peripheral write protection status - Bridge E */ +#else +#define REG_PAC_WRCTRL (*(RwReg *)0x44000000U) /**< \brief (PAC) Write control */ +#define REG_PAC_EVCTRL (*(RwReg8 *)0x44000004U) /**< \brief (PAC) Event control */ +#define REG_PAC_INTENCLR (*(RwReg8 *)0x44000008U) /**< \brief (PAC) Interrupt enable clear */ +#define REG_PAC_INTENSET (*(RwReg8 *)0x44000009U) /**< \brief (PAC) Interrupt enable set */ +#define REG_PAC_INTFLAGAHB (*(RwReg *)0x44000010U) /**< \brief (PAC) Bridge interrupt flag status */ +#define REG_PAC_INTFLAGA (*(RwReg *)0x44000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ +#define REG_PAC_INTFLAGB (*(RwReg *)0x44000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ +#define REG_PAC_INTFLAGC (*(RwReg *)0x4400001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ +#define REG_PAC_INTFLAGD (*(RwReg *)0x44000020U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */ +#define REG_PAC_INTFLAGE (*(RwReg *)0x44000024U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge E */ +#define REG_PAC_STATUSA (*(RoReg *)0x44000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */ +#define REG_PAC_STATUSB (*(RoReg *)0x44000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */ +#define REG_PAC_STATUSC (*(RoReg *)0x4400003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */ +#define REG_PAC_STATUSD (*(RoReg *)0x44000040U) /**< \brief (PAC) Peripheral write protection status - Bridge D */ +#define REG_PAC_STATUSE (*(RoReg *)0x44000044U) /**< \brief (PAC) Peripheral write protection status - Bridge E */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC peripheral ========== */ +#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock +#define PAC_CLK_AHB_ID 14 // AHB clock index +#define PAC_HPB_NUM 5 // Number of bridges AHB/APB +#define PAC_INTFLAG_NUM 6 // Number of intflag registers + +#endif /* _SAML21_PAC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pm.h new file mode 100644 index 0000000000..a80807deca --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_pm.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Instance description for PM + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_PM_INSTANCE_ +#define _SAML21_PM_INSTANCE_ + +/* ========== Register definition for PM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PM_CTRLA (0x40000000U) /**< \brief (PM) Control A */ +#define REG_PM_SLEEPCFG (0x40000001U) /**< \brief (PM) Sleep Configuration */ +#define REG_PM_PLCFG (0x40000002U) /**< \brief (PM) Performance Level Configuration */ +#define REG_PM_INTENCLR (0x40000004U) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (0x40000005U) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (0x40000006U) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_STDBYCFG (0x40000008U) /**< \brief (PM) Standby Configuration */ +#define REG_PM_PWSAKDLY (0x4000000CU) /**< \brief (PM) Power Switch Acknowledge Delay */ +#else +#define REG_PM_CTRLA (*(RwReg8 *)0x40000000U) /**< \brief (PM) Control A */ +#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000001U) /**< \brief (PM) Sleep Configuration */ +#define REG_PM_PLCFG (*(RwReg8 *)0x40000002U) /**< \brief (PM) Performance Level Configuration */ +#define REG_PM_INTENCLR (*(RwReg8 *)0x40000004U) /**< \brief (PM) Interrupt Enable Clear */ +#define REG_PM_INTENSET (*(RwReg8 *)0x40000005U) /**< \brief (PM) Interrupt Enable Set */ +#define REG_PM_INTFLAG (*(RwReg8 *)0x40000006U) /**< \brief (PM) Interrupt Flag Status and Clear */ +#define REG_PM_STDBYCFG (*(RwReg16*)0x40000008U) /**< \brief (PM) Standby Configuration */ +#define REG_PM_PWSAKDLY (*(RwReg8 *)0x4000000CU) /**< \brief (PM) Power Switch Acknowledge Delay */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PM peripheral ========== */ +#define PM_PD_NUM 3 // Number of switchable Power Domain + +#endif /* _SAML21_PM_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_port.h new file mode 100644 index 0000000000..2f7dc01257 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_port.h @@ -0,0 +1,144 @@ +/** + * \file + * + * \brief Instance description for PORT + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_PORT_INSTANCE_ +#define _SAML21_PORT_INSTANCE_ + +/* ========== Register definition for PORT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PORT_DIR0 (0x40002800U) /**< \brief (PORT) Data Direction 0 */ +#define REG_PORT_DIRCLR0 (0x40002804U) /**< \brief (PORT) Data Direction Clear 0 */ +#define REG_PORT_DIRSET0 (0x40002808U) /**< \brief (PORT) Data Direction Set 0 */ +#define REG_PORT_DIRTGL0 (0x4000280CU) /**< \brief (PORT) Data Direction Toggle 0 */ +#define REG_PORT_OUT0 (0x40002810U) /**< \brief (PORT) Data Output Value 0 */ +#define REG_PORT_OUTCLR0 (0x40002814U) /**< \brief (PORT) Data Output Value Clear 0 */ +#define REG_PORT_OUTSET0 (0x40002818U) /**< \brief (PORT) Data Output Value Set 0 */ +#define REG_PORT_OUTTGL0 (0x4000281CU) /**< \brief (PORT) Data Output Value Toggle 0 */ +#define REG_PORT_IN0 (0x40002820U) /**< \brief (PORT) Data Input Value 0 */ +#define REG_PORT_CTRL0 (0x40002824U) /**< \brief (PORT) Control 0 */ +#define REG_PORT_WRCONFIG0 (0x40002828U) /**< \brief (PORT) Write Configuration 0 */ +#define REG_PORT_EVCTRL0 (0x4000282CU) /**< \brief (PORT) Event Input Control 0 */ +#define REG_PORT_PMUX0 (0x40002830U) /**< \brief (PORT) Peripheral Multiplexing 0 */ +#define REG_PORT_PINCFG0 (0x40002840U) /**< \brief (PORT) Pin Configuration 0 */ +#define REG_PORT_DIR1 (0x40002880U) /**< \brief (PORT) Data Direction 1 */ +#define REG_PORT_DIRCLR1 (0x40002884U) /**< \brief (PORT) Data Direction Clear 1 */ +#define REG_PORT_DIRSET1 (0x40002888U) /**< \brief (PORT) Data Direction Set 1 */ +#define REG_PORT_DIRTGL1 (0x4000288CU) /**< \brief (PORT) Data Direction Toggle 1 */ +#define REG_PORT_OUT1 (0x40002890U) /**< \brief (PORT) Data Output Value 1 */ +#define REG_PORT_OUTCLR1 (0x40002894U) /**< \brief (PORT) Data Output Value Clear 1 */ +#define REG_PORT_OUTSET1 (0x40002898U) /**< \brief (PORT) Data Output Value Set 1 */ +#define REG_PORT_OUTTGL1 (0x4000289CU) /**< \brief (PORT) Data Output Value Toggle 1 */ +#define REG_PORT_IN1 (0x400028A0U) /**< \brief (PORT) Data Input Value 1 */ +#define REG_PORT_CTRL1 (0x400028A4U) /**< \brief (PORT) Control 1 */ +#define REG_PORT_WRCONFIG1 (0x400028A8U) /**< \brief (PORT) Write Configuration 1 */ +#define REG_PORT_EVCTRL1 (0x400028ACU) /**< \brief (PORT) Event Input Control 1 */ +#define REG_PORT_PMUX1 (0x400028B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ +#define REG_PORT_PINCFG1 (0x400028C0U) /**< \brief (PORT) Pin Configuration 1 */ +#else +#define REG_PORT_DIR0 (*(RwReg *)0x40002800U) /**< \brief (PORT) Data Direction 0 */ +#define REG_PORT_DIRCLR0 (*(RwReg *)0x40002804U) /**< \brief (PORT) Data Direction Clear 0 */ +#define REG_PORT_DIRSET0 (*(RwReg *)0x40002808U) /**< \brief (PORT) Data Direction Set 0 */ +#define REG_PORT_DIRTGL0 (*(RwReg *)0x4000280CU) /**< \brief (PORT) Data Direction Toggle 0 */ +#define REG_PORT_OUT0 (*(RwReg *)0x40002810U) /**< \brief (PORT) Data Output Value 0 */ +#define REG_PORT_OUTCLR0 (*(RwReg *)0x40002814U) /**< \brief (PORT) Data Output Value Clear 0 */ +#define REG_PORT_OUTSET0 (*(RwReg *)0x40002818U) /**< \brief (PORT) Data Output Value Set 0 */ +#define REG_PORT_OUTTGL0 (*(RwReg *)0x4000281CU) /**< \brief (PORT) Data Output Value Toggle 0 */ +#define REG_PORT_IN0 (*(RoReg *)0x40002820U) /**< \brief (PORT) Data Input Value 0 */ +#define REG_PORT_CTRL0 (*(RwReg *)0x40002824U) /**< \brief (PORT) Control 0 */ +#define REG_PORT_WRCONFIG0 (*(WoReg *)0x40002828U) /**< \brief (PORT) Write Configuration 0 */ +#define REG_PORT_EVCTRL0 (*(RwReg *)0x4000282CU) /**< \brief (PORT) Event Input Control 0 */ +#define REG_PORT_PMUX0 (*(RwReg *)0x40002830U) /**< \brief (PORT) Peripheral Multiplexing 0 */ +#define REG_PORT_PINCFG0 (*(RwReg *)0x40002840U) /**< \brief (PORT) Pin Configuration 0 */ +#define REG_PORT_DIR1 (*(RwReg *)0x40002880U) /**< \brief (PORT) Data Direction 1 */ +#define REG_PORT_DIRCLR1 (*(RwReg *)0x40002884U) /**< \brief (PORT) Data Direction Clear 1 */ +#define REG_PORT_DIRSET1 (*(RwReg *)0x40002888U) /**< \brief (PORT) Data Direction Set 1 */ +#define REG_PORT_DIRTGL1 (*(RwReg *)0x4000288CU) /**< \brief (PORT) Data Direction Toggle 1 */ +#define REG_PORT_OUT1 (*(RwReg *)0x40002890U) /**< \brief (PORT) Data Output Value 1 */ +#define REG_PORT_OUTCLR1 (*(RwReg *)0x40002894U) /**< \brief (PORT) Data Output Value Clear 1 */ +#define REG_PORT_OUTSET1 (*(RwReg *)0x40002898U) /**< \brief (PORT) Data Output Value Set 1 */ +#define REG_PORT_OUTTGL1 (*(RwReg *)0x4000289CU) /**< \brief (PORT) Data Output Value Toggle 1 */ +#define REG_PORT_IN1 (*(RoReg *)0x400028A0U) /**< \brief (PORT) Data Input Value 1 */ +#define REG_PORT_CTRL1 (*(RwReg *)0x400028A4U) /**< \brief (PORT) Control 1 */ +#define REG_PORT_WRCONFIG1 (*(WoReg *)0x400028A8U) /**< \brief (PORT) Write Configuration 1 */ +#define REG_PORT_EVCTRL1 (*(RwReg *)0x400028ACU) /**< \brief (PORT) Event Input Control 1 */ +#define REG_PORT_PMUX1 (*(RwReg *)0x400028B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */ +#define REG_PORT_PINCFG1 (*(RwReg *)0x400028C0U) /**< \brief (PORT) Pin Configuration 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PORT peripheral ========== */ +#define PORT_BITS 84 +#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } +#define PORT_DRVSTR 1 // DRVSTR supported? +#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000D0000 } +#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF, 0x00000000 } +#define PORT_EV_NUM 4 +#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } +#define PORT_ODRAIN 0 // ODRAIN supported? +#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } +#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } +#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x000D0000 } +#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x00000000 } +#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } +#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x000D0000 } +#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } +#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CFC7, 0x00000000 } +#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } +#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } +#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } +#define PORT_SLEWLIM 0 // SLEWLIM supported? +#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } +#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } + +#endif /* _SAML21_PORT_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rstc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rstc.h new file mode 100644 index 0000000000..9b8b23f51d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rstc.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Instance description for RSTC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_RSTC_INSTANCE_ +#define _SAML21_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RSTC_RCAUSE (0x40000800U) /**< \brief (RSTC) Reset Cause */ +#define REG_RSTC_BKUPEXIT (0x40000802U) /**< \brief (RSTC) Backup Exit Source */ +#define REG_RSTC_WKDBCONF (0x40000804U) /**< \brief (RSTC) Wakeup Debounce Configuration */ +#define REG_RSTC_WKPOL (0x40000808U) /**< \brief (RSTC) Wakeup Polarity */ +#define REG_RSTC_WKEN (0x4000080CU) /**< \brief (RSTC) Wakeup Enable */ +#define REG_RSTC_WKCAUSE (0x40000810U) /**< \brief (RSTC) Wakeup Cause */ +#else +#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000800U) /**< \brief (RSTC) Reset Cause */ +#define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000802U) /**< \brief (RSTC) Backup Exit Source */ +#define REG_RSTC_WKDBCONF (*(RwReg8 *)0x40000804U) /**< \brief (RSTC) Wakeup Debounce Configuration */ +#define REG_RSTC_WKPOL (*(RwReg16*)0x40000808U) /**< \brief (RSTC) Wakeup Polarity */ +#define REG_RSTC_WKEN (*(RwReg16*)0x4000080CU) /**< \brief (RSTC) Wakeup Enable */ +#define REG_RSTC_WKCAUSE (*(RwReg16*)0x40000810U) /**< \brief (RSTC) Wakeup Cause */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RSTC peripheral ========== */ +#define RSTC_NUMBER_OF_EXTWAKE 8 // number of external wakeup line + +#endif /* _SAML21_RSTC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rtc.h new file mode 100644 index 0000000000..7e399616d1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_rtc.h @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Instance description for RTC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_RTC_INSTANCE_ +#define _SAML21_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_DBGCTRL (0x4000200EU) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (0x40002014U) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_GP0 (0x40002040U) /**< \brief (RTC) General Purpose 0 */ +#define REG_RTC_GP1 (0x40002044U) /**< \brief (RTC) General Purpose 1 */ +#define REG_RTC_GP2 (0x40002048U) /**< \brief (RTC) General Purpose 2 */ +#define REG_RTC_GP3 (0x4000204CU) /**< \brief (RTC) General Purpose 3 */ +#define REG_RTC_MODE0_CTRLA (0x40002000U) /**< \brief (RTC) MODE0 Control A */ +#define REG_RTC_MODE0_EVCTRL (0x40002004U) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (0x40002008U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (0x4000200AU) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (0x4000200CU) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_SYNCBUSY (0x40002010U) /**< \brief (RTC) MODE0 Synchronization Busy Status */ +#define REG_RTC_MODE0_COUNT (0x40002018U) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (0x40002020U) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE1_CTRLA (0x40002000U) /**< \brief (RTC) MODE1 Control A */ +#define REG_RTC_MODE1_EVCTRL (0x40002004U) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (0x40002008U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (0x4000200AU) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (0x4000200CU) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_SYNCBUSY (0x40002010U) /**< \brief (RTC) MODE1 Synchronization Busy Status */ +#define REG_RTC_MODE1_COUNT (0x40002018U) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (0x4000201CU) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (0x40002020U) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (0x40002022U) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE2_CTRLA (0x40002000U) /**< \brief (RTC) MODE2 Control A */ +#define REG_RTC_MODE2_EVCTRL (0x40002004U) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (0x40002008U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (0x4000200AU) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (0x4000200CU) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_SYNCBUSY (0x40002010U) /**< \brief (RTC) MODE2 Synchronization Busy Status */ +#define REG_RTC_MODE2_CLOCK (0x40002018U) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002020U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (0x40002024U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#else +#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000200EU) /**< \brief (RTC) Debug Control */ +#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002014U) /**< \brief (RTC) Frequency Correction */ +#define REG_RTC_GP0 (*(RwReg *)0x40002040U) /**< \brief (RTC) General Purpose 0 */ +#define REG_RTC_GP1 (*(RwReg *)0x40002044U) /**< \brief (RTC) General Purpose 1 */ +#define REG_RTC_GP2 (*(RwReg *)0x40002048U) /**< \brief (RTC) General Purpose 2 */ +#define REG_RTC_GP3 (*(RwReg *)0x4000204CU) /**< \brief (RTC) General Purpose 3 */ +#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002000U) /**< \brief (RTC) MODE0 Control A */ +#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002004U) /**< \brief (RTC) MODE0 Event Control */ +#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002008U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ +#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000200AU) /**< \brief (RTC) MODE0 Interrupt Enable Set */ +#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000200CU) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002010U) /**< \brief (RTC) MODE0 Synchronization Busy Status */ +#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002018U) /**< \brief (RTC) MODE0 Counter Value */ +#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002020U) /**< \brief (RTC) MODE0 Compare 0 Value */ +#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002000U) /**< \brief (RTC) MODE1 Control A */ +#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002004U) /**< \brief (RTC) MODE1 Event Control */ +#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002008U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ +#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000200AU) /**< \brief (RTC) MODE1 Interrupt Enable Set */ +#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000200CU) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002010U) /**< \brief (RTC) MODE1 Synchronization Busy Status */ +#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002018U) /**< \brief (RTC) MODE1 Counter Value */ +#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000201CU) /**< \brief (RTC) MODE1 Counter Period */ +#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002020U) /**< \brief (RTC) MODE1 Compare 0 Value */ +#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002022U) /**< \brief (RTC) MODE1 Compare 1 Value */ +#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002000U) /**< \brief (RTC) MODE2 Control A */ +#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002004U) /**< \brief (RTC) MODE2 Event Control */ +#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002008U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ +#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000200AU) /**< \brief (RTC) MODE2 Interrupt Enable Set */ +#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000200CU) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ +#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002010U) /**< \brief (RTC) MODE2 Synchronization Busy Status */ +#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002018U) /**< \brief (RTC) MODE2 Clock Value */ +#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002020U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ +#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x40002024U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RTC peripheral ========== */ +#define RTC_ALARM_NUM 1 // Number of Alarms +#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators +#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators +#define RTC_GPR_NUM 4 // Number of General-Purpose Registers +#define RTC_PER_NUM 8 // Number of Periodic Intervals + +#endif /* _SAML21_RTC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom0.h new file mode 100644 index 0000000000..59a7b1ea64 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom0.h @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief Instance description for SERCOM0 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_SERCOM0_INSTANCE_ +#define _SAML21_SERCOM0_INSTANCE_ + +/* ========== Register definition for SERCOM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM0_I2CM_CTRLA (0x42000000U) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (0x42000004U) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (0x4200000CU) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (0x42000014U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (0x42000016U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (0x42000018U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (0x4200001AU) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200001CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */ +#define REG_SERCOM0_I2CM_ADDR (0x42000024U) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (0x42000028U) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (0x42000030U) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (0x42000000U) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (0x42000004U) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (0x42000014U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (0x42000016U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (0x42000018U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (0x4200001AU) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200001CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */ +#define REG_SERCOM0_I2CS_ADDR (0x42000024U) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (0x42000028U) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (0x42000000U) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (0x42000004U) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (0x4200000CU) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (0x42000014U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (0x42000016U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (0x42000018U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (0x4200001AU) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (0x4200001CU) /**< \brief (SERCOM0) SPI Synchronization Busy */ +#define REG_SERCOM0_SPI_ADDR (0x42000024U) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (0x42000028U) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (0x42000030U) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (0x42000000U) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (0x42000004U) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_BAUD (0x4200000CU) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (0x4200000EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (0x42000014U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (0x42000016U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (0x42000018U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (0x4200001AU) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (0x4200001CU) /**< \brief (SERCOM0) USART Synchronization Busy */ +#define REG_SERCOM0_USART_DATA (0x42000028U) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (0x42000030U) /**< \brief (SERCOM0) USART Debug Control */ +#else +#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000000U) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000004U) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200000CU) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000014U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000016U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000018U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200001AU) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200001CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */ +#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000024U) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000028U) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000030U) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000000U) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000004U) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000014U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000016U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000018U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200001AU) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200001CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */ +#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000024U) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000028U) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000000U) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000004U) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200000CU) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000014U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000016U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000018U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200001AU) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200001CU) /**< \brief (SERCOM0) SPI Synchronization Busy */ +#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000024U) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000028U) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000030U) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000000U) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000004U) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200000CU) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200000EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000014U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000016U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000018U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200001AU) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200001CU) /**< \brief (SERCOM0) USART Synchronization Busy */ +#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000028U) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000030U) /**< \brief (SERCOM0) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM0 peripheral ========== */ +#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger +#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger +#define SERCOM0_GCLK_ID_CORE 18 +#define SERCOM0_GCLK_ID_SLOW 17 +#define SERCOM0_INT_MSB 6 +#define SERCOM0_PMSB 3 + +#endif /* _SAML21_SERCOM0_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom1.h new file mode 100644 index 0000000000..c4529e0ca2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom1.h @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief Instance description for SERCOM1 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_SERCOM1_INSTANCE_ +#define _SAML21_SERCOM1_INSTANCE_ + +/* ========== Register definition for SERCOM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM1_I2CM_CTRLA (0x42000400U) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (0x42000404U) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (0x4200040CU) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (0x42000414U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (0x42000416U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (0x42000418U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (0x4200041AU) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */ +#define REG_SERCOM1_I2CM_ADDR (0x42000424U) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (0x42000428U) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (0x42000430U) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (0x42000400U) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (0x42000404U) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (0x42000414U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (0x42000416U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (0x42000418U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (0x4200041AU) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */ +#define REG_SERCOM1_I2CS_ADDR (0x42000424U) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (0x42000428U) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (0x42000400U) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (0x42000404U) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (0x4200040CU) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (0x42000414U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (0x42000416U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (0x42000418U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (0x4200041AU) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM1) SPI Synchronization Busy */ +#define REG_SERCOM1_SPI_ADDR (0x42000424U) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (0x42000428U) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (0x42000430U) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (0x42000400U) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (0x42000404U) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_BAUD (0x4200040CU) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (0x4200040EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (0x42000414U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (0x42000416U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (0x42000418U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (0x4200041AU) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM1) USART Synchronization Busy */ +#define REG_SERCOM1_USART_DATA (0x42000428U) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (0x42000430U) /**< \brief (SERCOM1) USART Debug Control */ +#else +#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200040CU) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */ +#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000428U) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */ +#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000428U) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200040CU) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM1) SPI Synchronization Busy */ +#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000428U) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4200040CU) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4200040EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM1) USART Synchronization Busy */ +#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000428U) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM1) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM1 peripheral ========== */ +#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger +#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger +#define SERCOM1_GCLK_ID_CORE 19 +#define SERCOM1_GCLK_ID_SLOW 17 +#define SERCOM1_INT_MSB 6 +#define SERCOM1_PMSB 3 + +#endif /* _SAML21_SERCOM1_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom2.h new file mode 100644 index 0000000000..6a0ef98004 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom2.h @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief Instance description for SERCOM2 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_SERCOM2_INSTANCE_ +#define _SAML21_SERCOM2_INSTANCE_ + +/* ========== Register definition for SERCOM2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM2_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */ +#define REG_SERCOM2_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (0x42000828U) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */ +#define REG_SERCOM2_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (0x42000828U) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM2) SPI Synchronization Busy */ +#define REG_SERCOM2_SPI_ADDR (0x42000824U) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (0x42000828U) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (0x42000800U) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (0x42000804U) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_BAUD (0x4200080CU) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (0x4200080EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (0x42000816U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (0x4200081AU) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM2) USART Synchronization Busy */ +#define REG_SERCOM2_USART_DATA (0x42000828U) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM2) USART Debug Control */ +#else +#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */ +#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */ +#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM2) SPI Synchronization Busy */ +#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM2) USART Synchronization Busy */ +#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM2) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM2 peripheral ========== */ +#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger +#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger +#define SERCOM2_GCLK_ID_CORE 20 +#define SERCOM2_GCLK_ID_SLOW 17 +#define SERCOM2_INT_MSB 6 +#define SERCOM2_PMSB 3 + +#endif /* _SAML21_SERCOM2_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom3.h new file mode 100644 index 0000000000..c5b619764e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom3.h @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief Instance description for SERCOM3 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_SERCOM3_INSTANCE_ +#define _SAML21_SERCOM3_INSTANCE_ + +/* ========== Register definition for SERCOM3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM3_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */ +#define REG_SERCOM3_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */ +#define REG_SERCOM3_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM3) SPI Synchronization Busy */ +#define REG_SERCOM3_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (0x42000C28U) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM3) USART Synchronization Busy */ +#define REG_SERCOM3_USART_DATA (0x42000C28U) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM3) USART Debug Control */ +#else +#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */ +#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */ +#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM3) SPI Synchronization Busy */ +#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM3) USART Synchronization Busy */ +#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM3) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM3 peripheral ========== */ +#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger +#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger +#define SERCOM3_GCLK_ID_CORE 21 +#define SERCOM3_GCLK_ID_SLOW 17 +#define SERCOM3_INT_MSB 6 +#define SERCOM3_PMSB 3 + +#endif /* _SAML21_SERCOM3_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom4.h new file mode 100644 index 0000000000..29febfb5b0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom4.h @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief Instance description for SERCOM4 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_SERCOM4_INSTANCE_ +#define _SAML21_SERCOM4_INSTANCE_ + +/* ========== Register definition for SERCOM4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM4_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */ +#define REG_SERCOM4_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (0x42001028U) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */ +#define REG_SERCOM4_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (0x42001028U) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM4) SPI Synchronization Busy */ +#define REG_SERCOM4_SPI_ADDR (0x42001024U) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (0x42001028U) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (0x42001000U) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (0x42001004U) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_BAUD (0x4200100CU) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (0x4200100EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (0x42001016U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (0x4200101AU) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM4) USART Synchronization Busy */ +#define REG_SERCOM4_USART_DATA (0x42001028U) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM4) USART Debug Control */ +#else +#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */ +#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */ +#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM4) SPI Synchronization Busy */ +#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM4) USART Synchronization Busy */ +#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM4) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM4 peripheral ========== */ +#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger +#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger +#define SERCOM4_GCLK_ID_CORE 22 +#define SERCOM4_GCLK_ID_SLOW 17 +#define SERCOM4_INT_MSB 6 +#define SERCOM4_PMSB 3 + +#endif /* _SAML21_SERCOM4_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom5.h new file mode 100644 index 0000000000..a6eecaac8b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_sercom5.h @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief Instance description for SERCOM5 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_SERCOM5_INSTANCE_ +#define _SAML21_SERCOM5_INSTANCE_ + +/* ========== Register definition for SERCOM5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM5_I2CM_CTRLA (0x43000400U) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (0x43000404U) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (0x4300040CU) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (0x43000414U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (0x43000416U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (0x43000418U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (0x4300041AU) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (0x4300041CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */ +#define REG_SERCOM5_I2CM_ADDR (0x43000424U) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (0x43000428U) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (0x43000430U) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (0x43000400U) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (0x43000404U) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (0x43000414U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (0x43000416U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (0x43000418U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (0x4300041AU) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (0x4300041CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */ +#define REG_SERCOM5_I2CS_ADDR (0x43000424U) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (0x43000428U) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (0x43000400U) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (0x43000404U) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (0x4300040CU) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (0x43000414U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (0x43000416U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (0x43000418U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (0x4300041AU) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (0x4300041CU) /**< \brief (SERCOM5) SPI Synchronization Busy */ +#define REG_SERCOM5_SPI_ADDR (0x43000424U) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (0x43000428U) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (0x43000430U) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (0x43000400U) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (0x43000404U) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_BAUD (0x4300040CU) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (0x4300040EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (0x43000414U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (0x43000416U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (0x43000418U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (0x4300041AU) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (0x4300041CU) /**< \brief (SERCOM5) USART Synchronization Busy */ +#define REG_SERCOM5_USART_DATA (0x43000428U) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (0x43000430U) /**< \brief (SERCOM5) USART Debug Control */ +#else +#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x43000400U) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x43000404U) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4300040CU) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x43000414U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x43000416U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x43000418U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4300041AU) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4300041CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */ +#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x43000424U) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x43000428U) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x43000430U) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x43000400U) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x43000404U) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x43000414U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x43000416U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x43000418U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4300041AU) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4300041CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */ +#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x43000424U) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x43000428U) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x43000400U) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x43000404U) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4300040CU) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x43000414U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x43000416U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x43000418U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4300041AU) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4300041CU) /**< \brief (SERCOM5) SPI Synchronization Busy */ +#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x43000424U) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x43000428U) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x43000430U) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x43000400U) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x43000404U) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4300040CU) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4300040EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x43000414U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x43000416U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x43000418U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4300041AU) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4300041CU) /**< \brief (SERCOM5) USART Synchronization Busy */ +#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x43000428U) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x43000430U) /**< \brief (SERCOM5) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM5 peripheral ========== */ +#define SERCOM5_DMAC_ID_RX // Index of DMA RX trigger +#define SERCOM5_DMAC_ID_TX // Index of DMA TX trigger +#define SERCOM5_GCLK_ID_CORE 24 +#define SERCOM5_GCLK_ID_SLOW 23 +#define SERCOM5_INT_MSB 3 +#define SERCOM5_PMSB 3 + +#endif /* _SAML21_SERCOM5_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_supc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_supc.h new file mode 100644 index 0000000000..26f8402d99 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_supc.h @@ -0,0 +1,82 @@ +/** + * \file + * + * \brief Instance description for SUPC + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_SUPC_INSTANCE_ +#define _SAML21_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SUPC_INTENCLR (0x40001400U) /**< \brief (SUPC) Interrupt Enable Clear */ +#define REG_SUPC_INTENSET (0x40001404U) /**< \brief (SUPC) Interrupt Enable Set */ +#define REG_SUPC_INTFLAG (0x40001408U) /**< \brief (SUPC) Interrupt Flag Status and Clear */ +#define REG_SUPC_STATUS (0x4000140CU) /**< \brief (SUPC) Power and Clocks Status */ +#define REG_SUPC_BOD33 (0x40001410U) /**< \brief (SUPC) BOD33 Control */ +#define REG_SUPC_BOD12 (0x40001414U) /**< \brief (SUPC) BOD12 Control */ +#define REG_SUPC_VREG (0x40001418U) /**< \brief (SUPC) VREG Control */ +#define REG_SUPC_VREF (0x4000141CU) /**< \brief (SUPC) VREF Control */ +#define REG_SUPC_BBPS (0x40001420U) /**< \brief (SUPC) Battery Backup Power Switch */ +#define REG_SUPC_BKOUT (0x40001424U) /**< \brief (SUPC) Backup Output Control */ +#define REG_SUPC_BKIN (0x40001428U) /**< \brief (SUPC) Backup Input Control */ +#else +#define REG_SUPC_INTENCLR (*(RwReg *)0x40001400U) /**< \brief (SUPC) Interrupt Enable Clear */ +#define REG_SUPC_INTENSET (*(RwReg *)0x40001404U) /**< \brief (SUPC) Interrupt Enable Set */ +#define REG_SUPC_INTFLAG (*(RwReg *)0x40001408U) /**< \brief (SUPC) Interrupt Flag Status and Clear */ +#define REG_SUPC_STATUS (*(RoReg *)0x4000140CU) /**< \brief (SUPC) Power and Clocks Status */ +#define REG_SUPC_BOD33 (*(RwReg *)0x40001410U) /**< \brief (SUPC) BOD33 Control */ +#define REG_SUPC_BOD12 (*(RwReg *)0x40001414U) /**< \brief (SUPC) BOD12 Control */ +#define REG_SUPC_VREG (*(RwReg *)0x40001418U) /**< \brief (SUPC) VREG Control */ +#define REG_SUPC_VREF (*(RwReg *)0x4000141CU) /**< \brief (SUPC) VREF Control */ +#define REG_SUPC_BBPS (*(RwReg *)0x40001420U) /**< \brief (SUPC) Battery Backup Power Switch */ +#define REG_SUPC_BKOUT (*(RwReg *)0x40001424U) /**< \brief (SUPC) Backup Output Control */ +#define REG_SUPC_BKIN (*(RoReg *)0x40001428U) /**< \brief (SUPC) Backup Input Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SUPC peripheral ========== */ +#define SUPC_BOD12_CALIB_MSB 5 +#define SUPC_BOD33_CALIB_MSB 5 +#define SUPC_SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number + +#endif /* _SAML21_SUPC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tal.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tal.h new file mode 100644 index 0000000000..6dc5b256c2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tal.h @@ -0,0 +1,171 @@ +/** + * \file + * + * \brief Instance description for TAL + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TAL_INSTANCE_ +#define _SAML21_TAL_INSTANCE_ + +/* ========== Register definition for TAL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TAL_CTRLA (0x40002C00U) /**< \brief (TAL) Control A */ +#define REG_TAL_RSTCTRL (0x40002C04U) /**< \brief (TAL) Reset Control */ +#define REG_TAL_EXTCTRL (0x40002C05U) /**< \brief (TAL) External Break Control */ +#define REG_TAL_EVCTRL (0x40002C06U) /**< \brief (TAL) Event Control */ +#define REG_TAL_INTENCLR (0x40002C08U) /**< \brief (TAL) Interrupt Enable Clear */ +#define REG_TAL_INTENSET (0x40002C09U) /**< \brief (TAL) Interrupt Enable Set */ +#define REG_TAL_INTFLAG (0x40002C0AU) /**< \brief (TAL) Interrupt Flag Status and Clear */ +#define REG_TAL_GLOBMASK (0x40002C0BU) /**< \brief (TAL) Global Break Requests Mask */ +#define REG_TAL_HALT (0x40002C0CU) /**< \brief (TAL) Debug Halt Request */ +#define REG_TAL_RESTART (0x40002C0DU) /**< \brief (TAL) Debug Restart Request */ +#define REG_TAL_BRKSTATUS (0x40002C0EU) /**< \brief (TAL) Break Request Status */ +#define REG_TAL_CTICTRLA0 (0x40002C10U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */ +#define REG_TAL_CTIMASK0 (0x40002C11U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */ +#define REG_TAL_CTICTRLA1 (0x40002C12U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */ +#define REG_TAL_CTIMASK1 (0x40002C13U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */ +#define REG_TAL_CTICTRLA2 (0x40002C14U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */ +#define REG_TAL_CTIMASK2 (0x40002C15U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */ +#define REG_TAL_CTICTRLA3 (0x40002C16U) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */ +#define REG_TAL_CTIMASK3 (0x40002C17U) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */ +#define REG_TAL_INTSTATUS0 (0x40002C20U) /**< \brief (TAL) Interrupt 0 Status */ +#define REG_TAL_INTSTATUS1 (0x40002C21U) /**< \brief (TAL) Interrupt 1 Status */ +#define REG_TAL_INTSTATUS2 (0x40002C22U) /**< \brief (TAL) Interrupt 2 Status */ +#define REG_TAL_INTSTATUS3 (0x40002C23U) /**< \brief (TAL) Interrupt 3 Status */ +#define REG_TAL_INTSTATUS4 (0x40002C24U) /**< \brief (TAL) Interrupt 4 Status */ +#define REG_TAL_INTSTATUS5 (0x40002C25U) /**< \brief (TAL) Interrupt 5 Status */ +#define REG_TAL_INTSTATUS6 (0x40002C26U) /**< \brief (TAL) Interrupt 6 Status */ +#define REG_TAL_INTSTATUS7 (0x40002C27U) /**< \brief (TAL) Interrupt 7 Status */ +#define REG_TAL_INTSTATUS8 (0x40002C28U) /**< \brief (TAL) Interrupt 8 Status */ +#define REG_TAL_INTSTATUS9 (0x40002C29U) /**< \brief (TAL) Interrupt 9 Status */ +#define REG_TAL_INTSTATUS10 (0x40002C2AU) /**< \brief (TAL) Interrupt 10 Status */ +#define REG_TAL_INTSTATUS11 (0x40002C2BU) /**< \brief (TAL) Interrupt 11 Status */ +#define REG_TAL_INTSTATUS12 (0x40002C2CU) /**< \brief (TAL) Interrupt 12 Status */ +#define REG_TAL_INTSTATUS13 (0x40002C2DU) /**< \brief (TAL) Interrupt 13 Status */ +#define REG_TAL_INTSTATUS14 (0x40002C2EU) /**< \brief (TAL) Interrupt 14 Status */ +#define REG_TAL_INTSTATUS15 (0x40002C2FU) /**< \brief (TAL) Interrupt 15 Status */ +#define REG_TAL_INTSTATUS16 (0x40002C30U) /**< \brief (TAL) Interrupt 16 Status */ +#define REG_TAL_INTSTATUS17 (0x40002C31U) /**< \brief (TAL) Interrupt 17 Status */ +#define REG_TAL_INTSTATUS18 (0x40002C32U) /**< \brief (TAL) Interrupt 18 Status */ +#define REG_TAL_INTSTATUS19 (0x40002C33U) /**< \brief (TAL) Interrupt 19 Status */ +#define REG_TAL_INTSTATUS20 (0x40002C34U) /**< \brief (TAL) Interrupt 20 Status */ +#define REG_TAL_INTSTATUS21 (0x40002C35U) /**< \brief (TAL) Interrupt 21 Status */ +#define REG_TAL_INTSTATUS22 (0x40002C36U) /**< \brief (TAL) Interrupt 22 Status */ +#define REG_TAL_INTSTATUS23 (0x40002C37U) /**< \brief (TAL) Interrupt 23 Status */ +#define REG_TAL_INTSTATUS24 (0x40002C38U) /**< \brief (TAL) Interrupt 24 Status */ +#define REG_TAL_INTSTATUS25 (0x40002C39U) /**< \brief (TAL) Interrupt 25 Status */ +#define REG_TAL_INTSTATUS26 (0x40002C3AU) /**< \brief (TAL) Interrupt 26 Status */ +#define REG_TAL_INTSTATUS27 (0x40002C3BU) /**< \brief (TAL) Interrupt 27 Status */ +#define REG_TAL_INTSTATUS28 (0x40002C3CU) /**< \brief (TAL) Interrupt 28 Status */ +#define REG_TAL_DMACPUSEL0 (0x40002C40U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */ +#define REG_TAL_EVCPUSEL0 (0x40002C48U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */ +#define REG_TAL_EICCPUSEL0 (0x40002C50U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */ +#define REG_TAL_INTCPUSEL0 (0x40002C58U) /**< \brief (TAL) Interrupts CPU Select 0 */ +#define REG_TAL_INTCPUSEL1 (0x40002C5CU) /**< \brief (TAL) Interrupts CPU Select 1 */ +#define REG_TAL_IRQTRIG (0x40002C60U) /**< \brief (TAL) Interrupt Trigger */ +#else +#define REG_TAL_CTRLA (*(RwReg8 *)0x40002C00U) /**< \brief (TAL) Control A */ +#define REG_TAL_RSTCTRL (*(RwReg8 *)0x40002C04U) /**< \brief (TAL) Reset Control */ +#define REG_TAL_EXTCTRL (*(RwReg8 *)0x40002C05U) /**< \brief (TAL) External Break Control */ +#define REG_TAL_EVCTRL (*(RwReg8 *)0x40002C06U) /**< \brief (TAL) Event Control */ +#define REG_TAL_INTENCLR (*(RwReg8 *)0x40002C08U) /**< \brief (TAL) Interrupt Enable Clear */ +#define REG_TAL_INTENSET (*(RwReg8 *)0x40002C09U) /**< \brief (TAL) Interrupt Enable Set */ +#define REG_TAL_INTFLAG (*(RwReg8 *)0x40002C0AU) /**< \brief (TAL) Interrupt Flag Status and Clear */ +#define REG_TAL_GLOBMASK (*(RwReg8 *)0x40002C0BU) /**< \brief (TAL) Global Break Requests Mask */ +#define REG_TAL_HALT (*(WoReg8 *)0x40002C0CU) /**< \brief (TAL) Debug Halt Request */ +#define REG_TAL_RESTART (*(WoReg8 *)0x40002C0DU) /**< \brief (TAL) Debug Restart Request */ +#define REG_TAL_BRKSTATUS (*(RoReg16*)0x40002C0EU) /**< \brief (TAL) Break Request Status */ +#define REG_TAL_CTICTRLA0 (*(RwReg8 *)0x40002C10U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */ +#define REG_TAL_CTIMASK0 (*(RwReg8 *)0x40002C11U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */ +#define REG_TAL_CTICTRLA1 (*(RwReg8 *)0x40002C12U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */ +#define REG_TAL_CTIMASK1 (*(RwReg8 *)0x40002C13U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */ +#define REG_TAL_CTICTRLA2 (*(RwReg8 *)0x40002C14U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */ +#define REG_TAL_CTIMASK2 (*(RwReg8 *)0x40002C15U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */ +#define REG_TAL_CTICTRLA3 (*(RwReg8 *)0x40002C16U) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */ +#define REG_TAL_CTIMASK3 (*(RwReg8 *)0x40002C17U) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */ +#define REG_TAL_INTSTATUS0 (*(RoReg8 *)0x40002C20U) /**< \brief (TAL) Interrupt 0 Status */ +#define REG_TAL_INTSTATUS1 (*(RoReg8 *)0x40002C21U) /**< \brief (TAL) Interrupt 1 Status */ +#define REG_TAL_INTSTATUS2 (*(RoReg8 *)0x40002C22U) /**< \brief (TAL) Interrupt 2 Status */ +#define REG_TAL_INTSTATUS3 (*(RoReg8 *)0x40002C23U) /**< \brief (TAL) Interrupt 3 Status */ +#define REG_TAL_INTSTATUS4 (*(RoReg8 *)0x40002C24U) /**< \brief (TAL) Interrupt 4 Status */ +#define REG_TAL_INTSTATUS5 (*(RoReg8 *)0x40002C25U) /**< \brief (TAL) Interrupt 5 Status */ +#define REG_TAL_INTSTATUS6 (*(RoReg8 *)0x40002C26U) /**< \brief (TAL) Interrupt 6 Status */ +#define REG_TAL_INTSTATUS7 (*(RoReg8 *)0x40002C27U) /**< \brief (TAL) Interrupt 7 Status */ +#define REG_TAL_INTSTATUS8 (*(RoReg8 *)0x40002C28U) /**< \brief (TAL) Interrupt 8 Status */ +#define REG_TAL_INTSTATUS9 (*(RoReg8 *)0x40002C29U) /**< \brief (TAL) Interrupt 9 Status */ +#define REG_TAL_INTSTATUS10 (*(RoReg8 *)0x40002C2AU) /**< \brief (TAL) Interrupt 10 Status */ +#define REG_TAL_INTSTATUS11 (*(RoReg8 *)0x40002C2BU) /**< \brief (TAL) Interrupt 11 Status */ +#define REG_TAL_INTSTATUS12 (*(RoReg8 *)0x40002C2CU) /**< \brief (TAL) Interrupt 12 Status */ +#define REG_TAL_INTSTATUS13 (*(RoReg8 *)0x40002C2DU) /**< \brief (TAL) Interrupt 13 Status */ +#define REG_TAL_INTSTATUS14 (*(RoReg8 *)0x40002C2EU) /**< \brief (TAL) Interrupt 14 Status */ +#define REG_TAL_INTSTATUS15 (*(RoReg8 *)0x40002C2FU) /**< \brief (TAL) Interrupt 15 Status */ +#define REG_TAL_INTSTATUS16 (*(RoReg8 *)0x40002C30U) /**< \brief (TAL) Interrupt 16 Status */ +#define REG_TAL_INTSTATUS17 (*(RoReg8 *)0x40002C31U) /**< \brief (TAL) Interrupt 17 Status */ +#define REG_TAL_INTSTATUS18 (*(RoReg8 *)0x40002C32U) /**< \brief (TAL) Interrupt 18 Status */ +#define REG_TAL_INTSTATUS19 (*(RoReg8 *)0x40002C33U) /**< \brief (TAL) Interrupt 19 Status */ +#define REG_TAL_INTSTATUS20 (*(RoReg8 *)0x40002C34U) /**< \brief (TAL) Interrupt 20 Status */ +#define REG_TAL_INTSTATUS21 (*(RoReg8 *)0x40002C35U) /**< \brief (TAL) Interrupt 21 Status */ +#define REG_TAL_INTSTATUS22 (*(RoReg8 *)0x40002C36U) /**< \brief (TAL) Interrupt 22 Status */ +#define REG_TAL_INTSTATUS23 (*(RoReg8 *)0x40002C37U) /**< \brief (TAL) Interrupt 23 Status */ +#define REG_TAL_INTSTATUS24 (*(RoReg8 *)0x40002C38U) /**< \brief (TAL) Interrupt 24 Status */ +#define REG_TAL_INTSTATUS25 (*(RoReg8 *)0x40002C39U) /**< \brief (TAL) Interrupt 25 Status */ +#define REG_TAL_INTSTATUS26 (*(RoReg8 *)0x40002C3AU) /**< \brief (TAL) Interrupt 26 Status */ +#define REG_TAL_INTSTATUS27 (*(RoReg8 *)0x40002C3BU) /**< \brief (TAL) Interrupt 27 Status */ +#define REG_TAL_INTSTATUS28 (*(RoReg8 *)0x40002C3CU) /**< \brief (TAL) Interrupt 28 Status */ +#define REG_TAL_DMACPUSEL0 (*(RwReg *)0x40002C40U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */ +#define REG_TAL_EVCPUSEL0 (*(RwReg *)0x40002C48U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */ +#define REG_TAL_EICCPUSEL0 (*(RwReg *)0x40002C50U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */ +#define REG_TAL_INTCPUSEL0 (*(RwReg *)0x40002C58U) /**< \brief (TAL) Interrupts CPU Select 0 */ +#define REG_TAL_INTCPUSEL1 (*(RwReg *)0x40002C5CU) /**< \brief (TAL) Interrupts CPU Select 1 */ +#define REG_TAL_IRQTRIG (*(RwReg16*)0x40002C60U) /**< \brief (TAL) Interrupt Trigger */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TAL peripheral ========== */ +#define TAL_CPU_NUM 2 // Number of CPUs +#define TAL_CTI_NUM 4 // Number of Cross-Trigger Interfaces +#define TAL_DMA_CH_NUM 16 // Number of DMAC Channels +#define TAL_EV_CH_NUM 12 // Number of EVSYS Channels +#define TAL_EXTINT_NUM 16 // Number of EIC External Interrrupts +#define TAL_INT_NUM 29 // Number of Interrupt Requests + +#endif /* _SAML21_TAL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc0.h new file mode 100644 index 0000000000..f85c1279fd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc0.h @@ -0,0 +1,126 @@ +/** + * \file + * + * \brief Instance description for TC0 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TC0_INSTANCE_ +#define _SAML21_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CTRLA (0x42002000U) /**< \brief (TC0) Control A */ +#define REG_TC0_CTRLBCLR (0x42002004U) /**< \brief (TC0) Control B Clear */ +#define REG_TC0_CTRLBSET (0x42002005U) /**< \brief (TC0) Control B Set */ +#define REG_TC0_EVCTRL (0x42002006U) /**< \brief (TC0) Event Control */ +#define REG_TC0_INTENCLR (0x42002008U) /**< \brief (TC0) Interrupt Enable Clear */ +#define REG_TC0_INTENSET (0x42002009U) /**< \brief (TC0) Interrupt Enable Set */ +#define REG_TC0_INTFLAG (0x4200200AU) /**< \brief (TC0) Interrupt Flag Status and Clear */ +#define REG_TC0_STATUS (0x4200200BU) /**< \brief (TC0) Status */ +#define REG_TC0_WAVE (0x4200200CU) /**< \brief (TC0) Waveform Generation Control */ +#define REG_TC0_DRVCTRL (0x4200200DU) /**< \brief (TC0) Control C */ +#define REG_TC0_DBGCTRL (0x4200200FU) /**< \brief (TC0) Debug Control */ +#define REG_TC0_SYNCBUSY (0x42002010U) /**< \brief (TC0) Synchronization Status */ +#define REG_TC0_COUNT16_COUNT (0x42002014U) /**< \brief (TC0) COUNT16 Count */ +#define REG_TC0_COUNT16_CC0 (0x4200201CU) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ +#define REG_TC0_COUNT16_CC1 (0x4200201EU) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ +#define REG_TC0_COUNT16_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT16_CCBUF1 (0x42002032U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT32_COUNT (0x42002014U) /**< \brief (TC0) COUNT32 Count */ +#define REG_TC0_COUNT32_CC0 (0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ +#define REG_TC0_COUNT32_CC1 (0x42002020U) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ +#define REG_TC0_COUNT32_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT32_CCBUF1 (0x42002034U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT8_COUNT (0x42002014U) /**< \brief (TC0) COUNT8 Count */ +#define REG_TC0_COUNT8_PER (0x4200201BU) /**< \brief (TC0) COUNT8 Period */ +#define REG_TC0_COUNT8_CC0 (0x4200201CU) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ +#define REG_TC0_COUNT8_CC1 (0x4200201DU) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ +#define REG_TC0_COUNT8_PERBUF (0x4200202FU) /**< \brief (TC0) COUNT8 Period Buffer */ +#define REG_TC0_COUNT8_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT8_CCBUF1 (0x42002031U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TC0) Control A */ +#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TC0) Control B Clear */ +#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TC0) Control B Set */ +#define REG_TC0_EVCTRL (*(RwReg16*)0x42002006U) /**< \brief (TC0) Event Control */ +#define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008U) /**< \brief (TC0) Interrupt Enable Clear */ +#define REG_TC0_INTENSET (*(RwReg8 *)0x42002009U) /**< \brief (TC0) Interrupt Enable Set */ +#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AU) /**< \brief (TC0) Interrupt Flag Status and Clear */ +#define REG_TC0_STATUS (*(RwReg8 *)0x4200200BU) /**< \brief (TC0) Status */ +#define REG_TC0_WAVE (*(RwReg8 *)0x4200200CU) /**< \brief (TC0) Waveform Generation Control */ +#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DU) /**< \brief (TC0) Control C */ +#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FU) /**< \brief (TC0) Debug Control */ +#define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010U) /**< \brief (TC0) Synchronization Status */ +#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002014U) /**< \brief (TC0) COUNT16 Count */ +#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200201CU) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ +#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201EU) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ +#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42002030U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42002032U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014U) /**< \brief (TC0) COUNT32 Count */ +#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ +#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020U) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ +#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014U) /**< \brief (TC0) COUNT8 Count */ +#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200201BU) /**< \brief (TC0) COUNT8 Period */ +#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200201CU) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ +#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200201DU) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ +#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200202FU) /**< \brief (TC0) COUNT8 Period Buffer */ +#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42002030U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42002031U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC0 peripheral ========== */ +#define TC0_CC_NUM 2 +#define TC0_DMAC_ID_MC_0 23 +#define TC0_DMAC_ID_MC_1 24 +#define TC0_DMAC_ID_MC_LSB 23 +#define TC0_DMAC_ID_MC_MSB 24 +#define TC0_DMAC_ID_MC_SIZE 2 +#define TC0_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger +#define TC0_EXT 0 +#define TC0_GCLK_ID 27 +#define TC0_MASTER 1 +#define TC0_OW_NUM 2 + +#endif /* _SAML21_TC0_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc1.h new file mode 100644 index 0000000000..e958297223 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc1.h @@ -0,0 +1,126 @@ +/** + * \file + * + * \brief Instance description for TC1 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TC1_INSTANCE_ +#define _SAML21_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC1_CTRLA (0x42002400U) /**< \brief (TC1) Control A */ +#define REG_TC1_CTRLBCLR (0x42002404U) /**< \brief (TC1) Control B Clear */ +#define REG_TC1_CTRLBSET (0x42002405U) /**< \brief (TC1) Control B Set */ +#define REG_TC1_EVCTRL (0x42002406U) /**< \brief (TC1) Event Control */ +#define REG_TC1_INTENCLR (0x42002408U) /**< \brief (TC1) Interrupt Enable Clear */ +#define REG_TC1_INTENSET (0x42002409U) /**< \brief (TC1) Interrupt Enable Set */ +#define REG_TC1_INTFLAG (0x4200240AU) /**< \brief (TC1) Interrupt Flag Status and Clear */ +#define REG_TC1_STATUS (0x4200240BU) /**< \brief (TC1) Status */ +#define REG_TC1_WAVE (0x4200240CU) /**< \brief (TC1) Waveform Generation Control */ +#define REG_TC1_DRVCTRL (0x4200240DU) /**< \brief (TC1) Control C */ +#define REG_TC1_DBGCTRL (0x4200240FU) /**< \brief (TC1) Debug Control */ +#define REG_TC1_SYNCBUSY (0x42002410U) /**< \brief (TC1) Synchronization Status */ +#define REG_TC1_COUNT16_COUNT (0x42002414U) /**< \brief (TC1) COUNT16 Count */ +#define REG_TC1_COUNT16_CC0 (0x4200241CU) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ +#define REG_TC1_COUNT16_CC1 (0x4200241EU) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ +#define REG_TC1_COUNT16_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT16_CCBUF1 (0x42002432U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT32_COUNT (0x42002414U) /**< \brief (TC1) COUNT32 Count */ +#define REG_TC1_COUNT32_CC0 (0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ +#define REG_TC1_COUNT32_CC1 (0x42002420U) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ +#define REG_TC1_COUNT32_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT32_CCBUF1 (0x42002434U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT8_COUNT (0x42002414U) /**< \brief (TC1) COUNT8 Count */ +#define REG_TC1_COUNT8_PER (0x4200241BU) /**< \brief (TC1) COUNT8 Period */ +#define REG_TC1_COUNT8_CC0 (0x4200241CU) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ +#define REG_TC1_COUNT8_CC1 (0x4200241DU) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ +#define REG_TC1_COUNT8_PERBUF (0x4200242FU) /**< \brief (TC1) COUNT8 Period Buffer */ +#define REG_TC1_COUNT8_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT8_CCBUF1 (0x42002431U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TC1) Control A */ +#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TC1) Control B Clear */ +#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TC1) Control B Set */ +#define REG_TC1_EVCTRL (*(RwReg16*)0x42002406U) /**< \brief (TC1) Event Control */ +#define REG_TC1_INTENCLR (*(RwReg8 *)0x42002408U) /**< \brief (TC1) Interrupt Enable Clear */ +#define REG_TC1_INTENSET (*(RwReg8 *)0x42002409U) /**< \brief (TC1) Interrupt Enable Set */ +#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240AU) /**< \brief (TC1) Interrupt Flag Status and Clear */ +#define REG_TC1_STATUS (*(RwReg8 *)0x4200240BU) /**< \brief (TC1) Status */ +#define REG_TC1_WAVE (*(RwReg8 *)0x4200240CU) /**< \brief (TC1) Waveform Generation Control */ +#define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200240DU) /**< \brief (TC1) Control C */ +#define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200240FU) /**< \brief (TC1) Debug Control */ +#define REG_TC1_SYNCBUSY (*(RoReg *)0x42002410U) /**< \brief (TC1) Synchronization Status */ +#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002414U) /**< \brief (TC1) COUNT16 Count */ +#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x4200241CU) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ +#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241EU) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ +#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x42002430U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x42002432U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002414U) /**< \brief (TC1) COUNT32 Count */ +#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ +#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42002420U) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ +#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42002430U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42002434U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002414U) /**< \brief (TC1) COUNT8 Count */ +#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x4200241BU) /**< \brief (TC1) COUNT8 Period */ +#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x4200241CU) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ +#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x4200241DU) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ +#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x4200242FU) /**< \brief (TC1) COUNT8 Period Buffer */ +#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x42002430U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x42002431U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC1 peripheral ========== */ +#define TC1_CC_NUM 2 +#define TC1_DMAC_ID_MC_0 26 +#define TC1_DMAC_ID_MC_1 27 +#define TC1_DMAC_ID_MC_LSB 26 +#define TC1_DMAC_ID_MC_MSB 27 +#define TC1_DMAC_ID_MC_SIZE 2 +#define TC1_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger +#define TC1_EXT 0 +#define TC1_GCLK_ID 27 +#define TC1_MASTER 0 +#define TC1_OW_NUM 2 + +#endif /* _SAML21_TC1_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc2.h new file mode 100644 index 0000000000..495b772ab9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc2.h @@ -0,0 +1,126 @@ +/** + * \file + * + * \brief Instance description for TC2 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TC2_INSTANCE_ +#define _SAML21_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC2_CTRLA (0x42002800U) /**< \brief (TC2) Control A */ +#define REG_TC2_CTRLBCLR (0x42002804U) /**< \brief (TC2) Control B Clear */ +#define REG_TC2_CTRLBSET (0x42002805U) /**< \brief (TC2) Control B Set */ +#define REG_TC2_EVCTRL (0x42002806U) /**< \brief (TC2) Event Control */ +#define REG_TC2_INTENCLR (0x42002808U) /**< \brief (TC2) Interrupt Enable Clear */ +#define REG_TC2_INTENSET (0x42002809U) /**< \brief (TC2) Interrupt Enable Set */ +#define REG_TC2_INTFLAG (0x4200280AU) /**< \brief (TC2) Interrupt Flag Status and Clear */ +#define REG_TC2_STATUS (0x4200280BU) /**< \brief (TC2) Status */ +#define REG_TC2_WAVE (0x4200280CU) /**< \brief (TC2) Waveform Generation Control */ +#define REG_TC2_DRVCTRL (0x4200280DU) /**< \brief (TC2) Control C */ +#define REG_TC2_DBGCTRL (0x4200280FU) /**< \brief (TC2) Debug Control */ +#define REG_TC2_SYNCBUSY (0x42002810U) /**< \brief (TC2) Synchronization Status */ +#define REG_TC2_COUNT16_COUNT (0x42002814U) /**< \brief (TC2) COUNT16 Count */ +#define REG_TC2_COUNT16_CC0 (0x4200281CU) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ +#define REG_TC2_COUNT16_CC1 (0x4200281EU) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ +#define REG_TC2_COUNT16_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT16_CCBUF1 (0x42002832U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT32_COUNT (0x42002814U) /**< \brief (TC2) COUNT32 Count */ +#define REG_TC2_COUNT32_CC0 (0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ +#define REG_TC2_COUNT32_CC1 (0x42002820U) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ +#define REG_TC2_COUNT32_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT32_CCBUF1 (0x42002834U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT8_COUNT (0x42002814U) /**< \brief (TC2) COUNT8 Count */ +#define REG_TC2_COUNT8_PER (0x4200281BU) /**< \brief (TC2) COUNT8 Period */ +#define REG_TC2_COUNT8_CC0 (0x4200281CU) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ +#define REG_TC2_COUNT8_CC1 (0x4200281DU) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ +#define REG_TC2_COUNT8_PERBUF (0x4200282FU) /**< \brief (TC2) COUNT8 Period Buffer */ +#define REG_TC2_COUNT8_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT8_CCBUF1 (0x42002831U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TC2) Control A */ +#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TC2) Control B Clear */ +#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TC2) Control B Set */ +#define REG_TC2_EVCTRL (*(RwReg16*)0x42002806U) /**< \brief (TC2) Event Control */ +#define REG_TC2_INTENCLR (*(RwReg8 *)0x42002808U) /**< \brief (TC2) Interrupt Enable Clear */ +#define REG_TC2_INTENSET (*(RwReg8 *)0x42002809U) /**< \brief (TC2) Interrupt Enable Set */ +#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280AU) /**< \brief (TC2) Interrupt Flag Status and Clear */ +#define REG_TC2_STATUS (*(RwReg8 *)0x4200280BU) /**< \brief (TC2) Status */ +#define REG_TC2_WAVE (*(RwReg8 *)0x4200280CU) /**< \brief (TC2) Waveform Generation Control */ +#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200280DU) /**< \brief (TC2) Control C */ +#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200280FU) /**< \brief (TC2) Debug Control */ +#define REG_TC2_SYNCBUSY (*(RoReg *)0x42002810U) /**< \brief (TC2) Synchronization Status */ +#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002814U) /**< \brief (TC2) COUNT16 Count */ +#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200281CU) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ +#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281EU) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ +#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42002830U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42002832U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002814U) /**< \brief (TC2) COUNT32 Count */ +#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ +#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42002820U) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ +#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42002830U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42002834U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002814U) /**< \brief (TC2) COUNT8 Count */ +#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200281BU) /**< \brief (TC2) COUNT8 Period */ +#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200281CU) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ +#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200281DU) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ +#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200282FU) /**< \brief (TC2) COUNT8 Period Buffer */ +#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42002830U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42002831U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC2 peripheral ========== */ +#define TC2_CC_NUM 2 +#define TC2_DMAC_ID_MC_0 29 +#define TC2_DMAC_ID_MC_1 30 +#define TC2_DMAC_ID_MC_LSB 29 +#define TC2_DMAC_ID_MC_MSB 30 +#define TC2_DMAC_ID_MC_SIZE 2 +#define TC2_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger +#define TC2_EXT 0 +#define TC2_GCLK_ID 28 +#define TC2_MASTER 1 +#define TC2_OW_NUM 2 + +#endif /* _SAML21_TC2_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc3.h new file mode 100644 index 0000000000..2ff7883a82 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc3.h @@ -0,0 +1,126 @@ +/** + * \file + * + * \brief Instance description for TC3 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TC3_INSTANCE_ +#define _SAML21_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */ +#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */ +#define REG_TC3_EVCTRL (0x42002C06U) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (0x42002C0BU) /**< \brief (TC3) Status */ +#define REG_TC3_WAVE (0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */ +#define REG_TC3_DRVCTRL (0x42002C0DU) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (0x42002C0FU) /**< \brief (TC3) Debug Control */ +#define REG_TC3_SYNCBUSY (0x42002C10U) /**< \brief (TC3) Synchronization Status */ +#define REG_TC3_COUNT16_COUNT (0x42002C14U) /**< \brief (TC3) COUNT16 Count */ +#define REG_TC3_COUNT16_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ +#define REG_TC3_COUNT16_CC1 (0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ +#define REG_TC3_COUNT16_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT16_CCBUF1 (0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT32_COUNT (0x42002C14U) /**< \brief (TC3) COUNT32 Count */ +#define REG_TC3_COUNT32_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ +#define REG_TC3_COUNT32_CC1 (0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ +#define REG_TC3_COUNT32_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT32_CCBUF1 (0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT8_COUNT (0x42002C14U) /**< \brief (TC3) COUNT8 Count */ +#define REG_TC3_COUNT8_PER (0x42002C1BU) /**< \brief (TC3) COUNT8 Period */ +#define REG_TC3_COUNT8_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ +#define REG_TC3_COUNT8_CC1 (0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ +#define REG_TC3_COUNT8_PERBUF (0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */ +#define REG_TC3_COUNT8_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT8_CCBUF1 (0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC3_CTRLA (*(RwReg *)0x42002C00U) /**< \brief (TC3) Control A */ +#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */ +#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06U) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BU) /**< \brief (TC3) Status */ +#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */ +#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FU) /**< \brief (TC3) Debug Control */ +#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10U) /**< \brief (TC3) Synchronization Status */ +#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14U) /**< \brief (TC3) COUNT16 Count */ +#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ +#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ +#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14U) /**< \brief (TC3) COUNT32 Count */ +#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ +#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ +#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Count */ +#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BU) /**< \brief (TC3) COUNT8 Period */ +#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ +#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ +#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */ +#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC3 peripheral ========== */ +#define TC3_CC_NUM 2 +#define TC3_DMAC_ID_MC_0 32 +#define TC3_DMAC_ID_MC_1 33 +#define TC3_DMAC_ID_MC_LSB 32 +#define TC3_DMAC_ID_MC_MSB 33 +#define TC3_DMAC_ID_MC_SIZE 2 +#define TC3_DMAC_ID_OVF 31 // Indexes of DMA Overflow trigger +#define TC3_EXT 0 +#define TC3_GCLK_ID 28 +#define TC3_MASTER 0 +#define TC3_OW_NUM 2 + +#endif /* _SAML21_TC3_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc4.h new file mode 100644 index 0000000000..f811d2fa76 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tc4.h @@ -0,0 +1,126 @@ +/** + * \file + * + * \brief Instance description for TC4 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TC4_INSTANCE_ +#define _SAML21_TC4_INSTANCE_ + +/* ========== Register definition for TC4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC4_CTRLA (0x43000800U) /**< \brief (TC4) Control A */ +#define REG_TC4_CTRLBCLR (0x43000804U) /**< \brief (TC4) Control B Clear */ +#define REG_TC4_CTRLBSET (0x43000805U) /**< \brief (TC4) Control B Set */ +#define REG_TC4_EVCTRL (0x43000806U) /**< \brief (TC4) Event Control */ +#define REG_TC4_INTENCLR (0x43000808U) /**< \brief (TC4) Interrupt Enable Clear */ +#define REG_TC4_INTENSET (0x43000809U) /**< \brief (TC4) Interrupt Enable Set */ +#define REG_TC4_INTFLAG (0x4300080AU) /**< \brief (TC4) Interrupt Flag Status and Clear */ +#define REG_TC4_STATUS (0x4300080BU) /**< \brief (TC4) Status */ +#define REG_TC4_WAVE (0x4300080CU) /**< \brief (TC4) Waveform Generation Control */ +#define REG_TC4_DRVCTRL (0x4300080DU) /**< \brief (TC4) Control C */ +#define REG_TC4_DBGCTRL (0x4300080FU) /**< \brief (TC4) Debug Control */ +#define REG_TC4_SYNCBUSY (0x43000810U) /**< \brief (TC4) Synchronization Status */ +#define REG_TC4_COUNT16_COUNT (0x43000814U) /**< \brief (TC4) COUNT16 Count */ +#define REG_TC4_COUNT16_CC0 (0x4300081CU) /**< \brief (TC4) COUNT16 Compare and Capture 0 */ +#define REG_TC4_COUNT16_CC1 (0x4300081EU) /**< \brief (TC4) COUNT16 Compare and Capture 1 */ +#define REG_TC4_COUNT16_CCBUF0 (0x43000830U) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC4_COUNT16_CCBUF1 (0x43000832U) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC4_COUNT32_COUNT (0x43000814U) /**< \brief (TC4) COUNT32 Count */ +#define REG_TC4_COUNT32_CC0 (0x4300081CU) /**< \brief (TC4) COUNT32 Compare and Capture 0 */ +#define REG_TC4_COUNT32_CC1 (0x43000820U) /**< \brief (TC4) COUNT32 Compare and Capture 1 */ +#define REG_TC4_COUNT32_CCBUF0 (0x43000830U) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC4_COUNT32_CCBUF1 (0x43000834U) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC4_COUNT8_COUNT (0x43000814U) /**< \brief (TC4) COUNT8 Count */ +#define REG_TC4_COUNT8_PER (0x4300081BU) /**< \brief (TC4) COUNT8 Period */ +#define REG_TC4_COUNT8_CC0 (0x4300081CU) /**< \brief (TC4) COUNT8 Compare and Capture 0 */ +#define REG_TC4_COUNT8_CC1 (0x4300081DU) /**< \brief (TC4) COUNT8 Compare and Capture 1 */ +#define REG_TC4_COUNT8_PERBUF (0x4300082FU) /**< \brief (TC4) COUNT8 Period Buffer */ +#define REG_TC4_COUNT8_CCBUF0 (0x43000830U) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC4_COUNT8_CCBUF1 (0x43000831U) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC4_CTRLA (*(RwReg *)0x43000800U) /**< \brief (TC4) Control A */ +#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x43000804U) /**< \brief (TC4) Control B Clear */ +#define REG_TC4_CTRLBSET (*(RwReg8 *)0x43000805U) /**< \brief (TC4) Control B Set */ +#define REG_TC4_EVCTRL (*(RwReg16*)0x43000806U) /**< \brief (TC4) Event Control */ +#define REG_TC4_INTENCLR (*(RwReg8 *)0x43000808U) /**< \brief (TC4) Interrupt Enable Clear */ +#define REG_TC4_INTENSET (*(RwReg8 *)0x43000809U) /**< \brief (TC4) Interrupt Enable Set */ +#define REG_TC4_INTFLAG (*(RwReg8 *)0x4300080AU) /**< \brief (TC4) Interrupt Flag Status and Clear */ +#define REG_TC4_STATUS (*(RwReg8 *)0x4300080BU) /**< \brief (TC4) Status */ +#define REG_TC4_WAVE (*(RwReg8 *)0x4300080CU) /**< \brief (TC4) Waveform Generation Control */ +#define REG_TC4_DRVCTRL (*(RwReg8 *)0x4300080DU) /**< \brief (TC4) Control C */ +#define REG_TC4_DBGCTRL (*(RwReg8 *)0x4300080FU) /**< \brief (TC4) Debug Control */ +#define REG_TC4_SYNCBUSY (*(RoReg *)0x43000810U) /**< \brief (TC4) Synchronization Status */ +#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x43000814U) /**< \brief (TC4) COUNT16 Count */ +#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x4300081CU) /**< \brief (TC4) COUNT16 Compare and Capture 0 */ +#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4300081EU) /**< \brief (TC4) COUNT16 Compare and Capture 1 */ +#define REG_TC4_COUNT16_CCBUF0 (*(RwReg16*)0x43000830U) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC4_COUNT16_CCBUF1 (*(RwReg16*)0x43000832U) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x43000814U) /**< \brief (TC4) COUNT32 Count */ +#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x4300081CU) /**< \brief (TC4) COUNT32 Compare and Capture 0 */ +#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x43000820U) /**< \brief (TC4) COUNT32 Compare and Capture 1 */ +#define REG_TC4_COUNT32_CCBUF0 (*(RwReg *)0x43000830U) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC4_COUNT32_CCBUF1 (*(RwReg *)0x43000834U) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x43000814U) /**< \brief (TC4) COUNT8 Count */ +#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x4300081BU) /**< \brief (TC4) COUNT8 Period */ +#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x4300081CU) /**< \brief (TC4) COUNT8 Compare and Capture 0 */ +#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x4300081DU) /**< \brief (TC4) COUNT8 Compare and Capture 1 */ +#define REG_TC4_COUNT8_PERBUF (*(RwReg8 *)0x4300082FU) /**< \brief (TC4) COUNT8 Period Buffer */ +#define REG_TC4_COUNT8_CCBUF0 (*(RwReg8 *)0x43000830U) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC4_COUNT8_CCBUF1 (*(RwReg8 *)0x43000831U) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC4 peripheral ========== */ +#define TC4_CC_NUM 2 +#define TC4_DMAC_ID_MC_0 35 +#define TC4_DMAC_ID_MC_1 36 +#define TC4_DMAC_ID_MC_LSB 35 +#define TC4_DMAC_ID_MC_MSB 36 +#define TC4_DMAC_ID_MC_SIZE 2 +#define TC4_DMAC_ID_OVF 34 // Indexes of DMA Overflow trigger +#define TC4_EXT 0 +#define TC4_GCLK_ID 29 +#define TC4_MASTER 0 +#define TC4_OW_NUM 2 + +#endif /* _SAML21_TC4_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc0.h new file mode 100644 index 0000000000..6846434f64 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc0.h @@ -0,0 +1,134 @@ +/** + * \file + * + * \brief Instance description for TCC0 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TCC0_INSTANCE_ +#define _SAML21_TCC0_INSTANCE_ + +/* ========== Register definition for TCC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC0_CTRLA (0x42001400U) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (0x42001404U) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (0x42001405U) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (0x42001408U) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (0x4200140CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (0x42001410U) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (0x42001414U) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (0x42001418U) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (0x4200141EU) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (0x42001420U) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (0x42001424U) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (0x42001428U) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (0x4200142CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (0x42001430U) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (0x42001434U) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (0x42001438U) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (0x4200143CU) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (0x42001440U) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (0x42001444U) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (0x42001448U) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (0x4200144CU) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (0x42001450U) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTBUF (0x42001464U) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_WAVEBUF (0x42001468U) /**< \brief (TCC0) Waveform Control Buffer */ +#define REG_TCC0_PERBUF (0x4200146CU) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCBUF0 (0x42001470U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCBUF1 (0x42001474U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCBUF2 (0x42001478U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCBUF3 (0x4200147CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#else +#define REG_TCC0_CTRLA (*(RwReg *)0x42001400U) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001404U) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001405U) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001408U) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (*(RwReg *)0x4200140CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (*(RwReg *)0x42001410U) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (*(RwReg *)0x42001414U) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (*(RwReg *)0x42001418U) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200141EU) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (*(RwReg *)0x42001420U) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (*(RwReg *)0x42001424U) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (*(RwReg *)0x42001428U) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (*(RwReg *)0x4200142CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (*(RwReg *)0x42001430U) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (*(RwReg *)0x42001434U) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (*(RwReg16*)0x42001438U) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (*(RwReg *)0x4200143CU) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (*(RwReg *)0x42001440U) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (*(RwReg *)0x42001444U) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (*(RwReg *)0x42001448U) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (*(RwReg *)0x4200144CU) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (*(RwReg *)0x42001450U) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTBUF (*(RwReg16*)0x42001464U) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_WAVEBUF (*(RwReg *)0x42001468U) /**< \brief (TCC0) Waveform Control Buffer */ +#define REG_TCC0_PERBUF (*(RwReg *)0x4200146CU) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCBUF0 (*(RwReg *)0x42001470U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCBUF1 (*(RwReg *)0x42001474U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCBUF2 (*(RwReg *)0x42001478U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCBUF3 (*(RwReg *)0x4200147CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC0 peripheral ========== */ +#define TCC0_CC_NUM 4 // Number of Compare/Capture units +#define TCC0_DITHERING 1 // Dithering feature implemented +#define TCC0_DMAC_ID_MC_0 12 +#define TCC0_DMAC_ID_MC_1 13 +#define TCC0_DMAC_ID_MC_2 14 +#define TCC0_DMAC_ID_MC_3 15 +#define TCC0_DMAC_ID_MC_LSB 12 +#define TCC0_DMAC_ID_MC_MSB 15 +#define TCC0_DMAC_ID_MC_SIZE 4 +#define TCC0_DMAC_ID_OVF 11 // DMA overflow/underflow/retrigger trigger +#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented +#define TCC0_EXT 31 // Coding of implemented extended features +#define TCC0_GCLK_ID 25 // Index of Generic Clock +#define TCC0_OTMX 1 // Output Matrix feature implemented +#define TCC0_OW_NUM 8 // Number of Output Waveforms +#define TCC0_PG 1 // Pattern Generation feature implemented +#define TCC0_SIZE 24 +#define TCC0_SWAP 1 // DTI outputs swap feature implemented +#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAML21_TCC0_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc1.h new file mode 100644 index 0000000000..9507b3a5cd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc1.h @@ -0,0 +1,122 @@ +/** + * \file + * + * \brief Instance description for TCC1 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TCC1_INSTANCE_ +#define _SAML21_TCC1_INSTANCE_ + +/* ========== Register definition for TCC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC1_CTRLA (0x42001800U) /**< \brief (TCC1) Control A */ +#define REG_TCC1_CTRLBCLR (0x42001804U) /**< \brief (TCC1) Control B Clear */ +#define REG_TCC1_CTRLBSET (0x42001805U) /**< \brief (TCC1) Control B Set */ +#define REG_TCC1_SYNCBUSY (0x42001808U) /**< \brief (TCC1) Synchronization Busy */ +#define REG_TCC1_FCTRLA (0x4200180CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ +#define REG_TCC1_FCTRLB (0x42001810U) /**< \brief (TCC1) Recoverable Fault B Configuration */ +#define REG_TCC1_DRVCTRL (0x42001818U) /**< \brief (TCC1) Driver Control */ +#define REG_TCC1_DBGCTRL (0x4200181EU) /**< \brief (TCC1) Debug Control */ +#define REG_TCC1_EVCTRL (0x42001820U) /**< \brief (TCC1) Event Control */ +#define REG_TCC1_INTENCLR (0x42001824U) /**< \brief (TCC1) Interrupt Enable Clear */ +#define REG_TCC1_INTENSET (0x42001828U) /**< \brief (TCC1) Interrupt Enable Set */ +#define REG_TCC1_INTFLAG (0x4200182CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ +#define REG_TCC1_STATUS (0x42001830U) /**< \brief (TCC1) Status */ +#define REG_TCC1_COUNT (0x42001834U) /**< \brief (TCC1) Count */ +#define REG_TCC1_PATT (0x42001838U) /**< \brief (TCC1) Pattern */ +#define REG_TCC1_WAVE (0x4200183CU) /**< \brief (TCC1) Waveform Control */ +#define REG_TCC1_PER (0x42001840U) /**< \brief (TCC1) Period */ +#define REG_TCC1_CC0 (0x42001844U) /**< \brief (TCC1) Compare and Capture 0 */ +#define REG_TCC1_CC1 (0x42001848U) /**< \brief (TCC1) Compare and Capture 1 */ +#define REG_TCC1_PATTBUF (0x42001864U) /**< \brief (TCC1) Pattern Buffer */ +#define REG_TCC1_WAVEBUF (0x42001868U) /**< \brief (TCC1) Waveform Control Buffer */ +#define REG_TCC1_PERBUF (0x4200186CU) /**< \brief (TCC1) Period Buffer */ +#define REG_TCC1_CCBUF0 (0x42001870U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ +#define REG_TCC1_CCBUF1 (0x42001874U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ +#else +#define REG_TCC1_CTRLA (*(RwReg *)0x42001800U) /**< \brief (TCC1) Control A */ +#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42001804U) /**< \brief (TCC1) Control B Clear */ +#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42001805U) /**< \brief (TCC1) Control B Set */ +#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42001808U) /**< \brief (TCC1) Synchronization Busy */ +#define REG_TCC1_FCTRLA (*(RwReg *)0x4200180CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ +#define REG_TCC1_FCTRLB (*(RwReg *)0x42001810U) /**< \brief (TCC1) Recoverable Fault B Configuration */ +#define REG_TCC1_DRVCTRL (*(RwReg *)0x42001818U) /**< \brief (TCC1) Driver Control */ +#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200181EU) /**< \brief (TCC1) Debug Control */ +#define REG_TCC1_EVCTRL (*(RwReg *)0x42001820U) /**< \brief (TCC1) Event Control */ +#define REG_TCC1_INTENCLR (*(RwReg *)0x42001824U) /**< \brief (TCC1) Interrupt Enable Clear */ +#define REG_TCC1_INTENSET (*(RwReg *)0x42001828U) /**< \brief (TCC1) Interrupt Enable Set */ +#define REG_TCC1_INTFLAG (*(RwReg *)0x4200182CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ +#define REG_TCC1_STATUS (*(RwReg *)0x42001830U) /**< \brief (TCC1) Status */ +#define REG_TCC1_COUNT (*(RwReg *)0x42001834U) /**< \brief (TCC1) Count */ +#define REG_TCC1_PATT (*(RwReg16*)0x42001838U) /**< \brief (TCC1) Pattern */ +#define REG_TCC1_WAVE (*(RwReg *)0x4200183CU) /**< \brief (TCC1) Waveform Control */ +#define REG_TCC1_PER (*(RwReg *)0x42001840U) /**< \brief (TCC1) Period */ +#define REG_TCC1_CC0 (*(RwReg *)0x42001844U) /**< \brief (TCC1) Compare and Capture 0 */ +#define REG_TCC1_CC1 (*(RwReg *)0x42001848U) /**< \brief (TCC1) Compare and Capture 1 */ +#define REG_TCC1_PATTBUF (*(RwReg16*)0x42001864U) /**< \brief (TCC1) Pattern Buffer */ +#define REG_TCC1_WAVEBUF (*(RwReg *)0x42001868U) /**< \brief (TCC1) Waveform Control Buffer */ +#define REG_TCC1_PERBUF (*(RwReg *)0x4200186CU) /**< \brief (TCC1) Period Buffer */ +#define REG_TCC1_CCBUF0 (*(RwReg *)0x42001870U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ +#define REG_TCC1_CCBUF1 (*(RwReg *)0x42001874U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC1 peripheral ========== */ +#define TCC1_CC_NUM 2 // Number of Compare/Capture units +#define TCC1_DITHERING 1 // Dithering feature implemented +#define TCC1_DMAC_ID_MC_0 17 +#define TCC1_DMAC_ID_MC_1 18 +#define TCC1_DMAC_ID_MC_LSB 17 +#define TCC1_DMAC_ID_MC_MSB 18 +#define TCC1_DMAC_ID_MC_SIZE 2 +#define TCC1_DMAC_ID_OVF 16 // DMA overflow/underflow/retrigger trigger +#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented +#define TCC1_EXT 24 // Coding of implemented extended features +#define TCC1_GCLK_ID 25 // Index of Generic Clock +#define TCC1_OTMX 0 // Output Matrix feature implemented +#define TCC1_OW_NUM 4 // Number of Output Waveforms +#define TCC1_PG 1 // Pattern Generation feature implemented +#define TCC1_SIZE 24 +#define TCC1_SWAP 0 // DTI outputs swap feature implemented +#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAML21_TCC1_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc2.h new file mode 100644 index 0000000000..a1af67f879 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_tcc2.h @@ -0,0 +1,118 @@ +/** + * \file + * + * \brief Instance description for TCC2 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TCC2_INSTANCE_ +#define _SAML21_TCC2_INSTANCE_ + +/* ========== Register definition for TCC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC2_CTRLA (0x42001C00U) /**< \brief (TCC2) Control A */ +#define REG_TCC2_CTRLBCLR (0x42001C04U) /**< \brief (TCC2) Control B Clear */ +#define REG_TCC2_CTRLBSET (0x42001C05U) /**< \brief (TCC2) Control B Set */ +#define REG_TCC2_SYNCBUSY (0x42001C08U) /**< \brief (TCC2) Synchronization Busy */ +#define REG_TCC2_FCTRLA (0x42001C0CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ +#define REG_TCC2_FCTRLB (0x42001C10U) /**< \brief (TCC2) Recoverable Fault B Configuration */ +#define REG_TCC2_DRVCTRL (0x42001C18U) /**< \brief (TCC2) Driver Control */ +#define REG_TCC2_DBGCTRL (0x42001C1EU) /**< \brief (TCC2) Debug Control */ +#define REG_TCC2_EVCTRL (0x42001C20U) /**< \brief (TCC2) Event Control */ +#define REG_TCC2_INTENCLR (0x42001C24U) /**< \brief (TCC2) Interrupt Enable Clear */ +#define REG_TCC2_INTENSET (0x42001C28U) /**< \brief (TCC2) Interrupt Enable Set */ +#define REG_TCC2_INTFLAG (0x42001C2CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ +#define REG_TCC2_STATUS (0x42001C30U) /**< \brief (TCC2) Status */ +#define REG_TCC2_COUNT (0x42001C34U) /**< \brief (TCC2) Count */ +#define REG_TCC2_WAVE (0x42001C3CU) /**< \brief (TCC2) Waveform Control */ +#define REG_TCC2_PER (0x42001C40U) /**< \brief (TCC2) Period */ +#define REG_TCC2_CC0 (0x42001C44U) /**< \brief (TCC2) Compare and Capture 0 */ +#define REG_TCC2_CC1 (0x42001C48U) /**< \brief (TCC2) Compare and Capture 1 */ +#define REG_TCC2_WAVEBUF (0x42001C68U) /**< \brief (TCC2) Waveform Control Buffer */ +#define REG_TCC2_PERBUF (0x42001C6CU) /**< \brief (TCC2) Period Buffer */ +#define REG_TCC2_CCBUF0 (0x42001C70U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ +#define REG_TCC2_CCBUF1 (0x42001C74U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ +#else +#define REG_TCC2_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (TCC2) Control A */ +#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42001C04U) /**< \brief (TCC2) Control B Clear */ +#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42001C05U) /**< \brief (TCC2) Control B Set */ +#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42001C08U) /**< \brief (TCC2) Synchronization Busy */ +#define REG_TCC2_FCTRLA (*(RwReg *)0x42001C0CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ +#define REG_TCC2_FCTRLB (*(RwReg *)0x42001C10U) /**< \brief (TCC2) Recoverable Fault B Configuration */ +#define REG_TCC2_DRVCTRL (*(RwReg *)0x42001C18U) /**< \brief (TCC2) Driver Control */ +#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x42001C1EU) /**< \brief (TCC2) Debug Control */ +#define REG_TCC2_EVCTRL (*(RwReg *)0x42001C20U) /**< \brief (TCC2) Event Control */ +#define REG_TCC2_INTENCLR (*(RwReg *)0x42001C24U) /**< \brief (TCC2) Interrupt Enable Clear */ +#define REG_TCC2_INTENSET (*(RwReg *)0x42001C28U) /**< \brief (TCC2) Interrupt Enable Set */ +#define REG_TCC2_INTFLAG (*(RwReg *)0x42001C2CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ +#define REG_TCC2_STATUS (*(RwReg *)0x42001C30U) /**< \brief (TCC2) Status */ +#define REG_TCC2_COUNT (*(RwReg *)0x42001C34U) /**< \brief (TCC2) Count */ +#define REG_TCC2_WAVE (*(RwReg *)0x42001C3CU) /**< \brief (TCC2) Waveform Control */ +#define REG_TCC2_PER (*(RwReg *)0x42001C40U) /**< \brief (TCC2) Period */ +#define REG_TCC2_CC0 (*(RwReg *)0x42001C44U) /**< \brief (TCC2) Compare and Capture 0 */ +#define REG_TCC2_CC1 (*(RwReg *)0x42001C48U) /**< \brief (TCC2) Compare and Capture 1 */ +#define REG_TCC2_WAVEBUF (*(RwReg *)0x42001C68U) /**< \brief (TCC2) Waveform Control Buffer */ +#define REG_TCC2_PERBUF (*(RwReg *)0x42001C6CU) /**< \brief (TCC2) Period Buffer */ +#define REG_TCC2_CCBUF0 (*(RwReg *)0x42001C70U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ +#define REG_TCC2_CCBUF1 (*(RwReg *)0x42001C74U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC2 peripheral ========== */ +#define TCC2_CC_NUM 2 // Number of Compare/Capture units +#define TCC2_DITHERING 0 // Dithering feature implemented +#define TCC2_DMAC_ID_MC_0 20 +#define TCC2_DMAC_ID_MC_1 21 +#define TCC2_DMAC_ID_MC_LSB 20 +#define TCC2_DMAC_ID_MC_MSB 21 +#define TCC2_DMAC_ID_MC_SIZE 2 +#define TCC2_DMAC_ID_OVF 19 // DMA overflow/underflow/retrigger trigger +#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented +#define TCC2_EXT 0 // Coding of implemented extended features +#define TCC2_GCLK_ID 26 // Index of Generic Clock +#define TCC2_OTMX 0 // Output Matrix feature implemented +#define TCC2_OW_NUM 2 // Number of Output Waveforms +#define TCC2_PG 0 // Pattern Generation feature implemented +#define TCC2_SIZE 16 +#define TCC2_SWAP 0 // DTI outputs swap feature implemented +#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif /* _SAML21_TCC2_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_trng.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_trng.h new file mode 100644 index 0000000000..b6793ad1a2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_trng.h @@ -0,0 +1,68 @@ +/** + * \file + * + * \brief Instance description for TRNG + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_TRNG_INSTANCE_ +#define _SAML21_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TRNG_CTRLA (0x42003800U) /**< \brief (TRNG) Control A */ +#define REG_TRNG_EVCTRL (0x42003804U) /**< \brief (TRNG) Event Control */ +#define REG_TRNG_INTENCLR (0x42003808U) /**< \brief (TRNG) Interrupt Enable Clear */ +#define REG_TRNG_INTENSET (0x42003809U) /**< \brief (TRNG) Interrupt Enable Set */ +#define REG_TRNG_INTFLAG (0x4200380AU) /**< \brief (TRNG) Interrupt Flag Status and Clear */ +#define REG_TRNG_DATA (0x42003820U) /**< \brief (TRNG) Output Data */ +#else +#define REG_TRNG_CTRLA (*(RwReg8 *)0x42003800U) /**< \brief (TRNG) Control A */ +#define REG_TRNG_EVCTRL (*(RwReg8 *)0x42003804U) /**< \brief (TRNG) Event Control */ +#define REG_TRNG_INTENCLR (*(RwReg8 *)0x42003808U) /**< \brief (TRNG) Interrupt Enable Clear */ +#define REG_TRNG_INTENSET (*(RwReg8 *)0x42003809U) /**< \brief (TRNG) Interrupt Enable Set */ +#define REG_TRNG_INTFLAG (*(RwReg8 *)0x4200380AU) /**< \brief (TRNG) Interrupt Flag Status and Clear */ +#define REG_TRNG_DATA (*(RoReg *)0x42003820U) /**< \brief (TRNG) Output Data */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML21_TRNG_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_usb.h new file mode 100644 index 0000000000..6ab18bccb6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_usb.h @@ -0,0 +1,345 @@ +/** + * \file + * + * \brief Instance description for USB + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_USB_INSTANCE_ +#define _SAML21_USB_INSTANCE_ + +/* ========== Register definition for USB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USB_CTRLA (0x41000000U) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (0x41000002U) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_FSMSTATUS (0x4100000DU) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (0x41000024U) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (0x41000028U) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (0x41000008U) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (0x4100000AU) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (0x4100000CU) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (0x41000010U) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (0x41000014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (0x41000018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (0x4100001CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (0x41000020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (0x41000008U) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (0x4100000AU) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (0x4100000CU) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (0x41000010U) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (0x41000012U) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (0x41000014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (0x41000018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (0x4100001CU) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (0x41000020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (0x41000100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41000103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41000104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41000105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (0x41000106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41000107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41000108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (0x41000109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (0x41000120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41000123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41000124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41000125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (0x41000126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41000127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41000128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (0x41000129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (0x41000140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41000143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41000144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41000145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (0x41000146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41000147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41000148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (0x41000149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (0x41000160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41000163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41000164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41000165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (0x41000166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41000167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41000168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (0x41000169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (0x41000180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41000183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41000184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41000185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (0x41000186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41000187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41000188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (0x41000189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (0x410001A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410001A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410001A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410001A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (0x410001A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410001A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410001A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (0x410001A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (0x410001C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410001C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410001C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410001C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (0x410001C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410001C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410001C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (0x410001C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (0x410001E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410001E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410001E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410001E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (0x410001E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410001E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410001E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (0x410001E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#else +#define REG_USB_CTRLA (*(RwReg8 *)0x41000000U) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002U) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DU) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (*(RwReg *)0x41000024U) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (*(RwReg16*)0x41000028U) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41000008U) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AU) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CU) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41000010U) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41000014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41000018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100001CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41000020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41000008U) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100000AU) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100000CU) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (*(RwReg16*)0x41000010U) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41000012U) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41000014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41000018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100001CU) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41000020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41000100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41000103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41000104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41000105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41000106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41000107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41000108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41000109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41000120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41000123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41000124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41000125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41000126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41000127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41000128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41000129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41000140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41000143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41000144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41000145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41000146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41000147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41000148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41000149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41000160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41000163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41000164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41000165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41000166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41000167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41000168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41000169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41000180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41000183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41000184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41000185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41000186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41000187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41000188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41000189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410001A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410001A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410001A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410001A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410001A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410001A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410001A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410001A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410001C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410001C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410001C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410001C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410001C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410001C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410001C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410001C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410001E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410001E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410001E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410001E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410001E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410001E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410001E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410001E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for USB peripheral ========== */ +#define USB_EPT_NBR 8 // Number of USB end points (obsolete) +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 4 // Index of Generic Clock +#define USB_PIPE_NUM 8 // Number of USB pipes + +#endif /* _SAML21_USB_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_wdt.h new file mode 100644 index 0000000000..faf3b75ea9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/instance/ins_wdt.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_WDT_INSTANCE_ +#define _SAML21_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRLA (0x40001C00U) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40001C01U) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40001C02U) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40001C04U) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40001C05U) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40001C06U) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (0x40001C08U) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (0x40001C0CU) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRLA (*(RwReg8 *)0x40001C00U) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40001C01U) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001C02U) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001C04U) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40001C05U) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001C06U) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (*(RoReg *)0x40001C08U) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x40001C0CU) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAML21_WDT_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e15a.h new file mode 100644 index 0000000000..ac918a04c5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e15a.h @@ -0,0 +1,757 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML21E15A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21E15A_PIO_ +#define _SAML21E15A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +/* ========== PORT definition for RSTC peripheral ========== */ +#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ +#define MUX_PA00A_RSTC_EXTWAKE0 0L +#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) +#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) +#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ +#define MUX_PA01A_RSTC_EXTWAKE1 0L +#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) +#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) +#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ +#define MUX_PA02A_RSTC_EXTWAKE2 0L +#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) +#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) +#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ +#define MUX_PA03A_RSTC_EXTWAKE3 0L +#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) +#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) +#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ +#define MUX_PA04A_RSTC_EXTWAKE4 0L +#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) +#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) +#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ +#define MUX_PA05A_RSTC_EXTWAKE5 0L +#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) +#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) +#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ +#define MUX_PA06A_RSTC_EXTWAKE6 0L +#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) +#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) +#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ +#define MUX_PA07A_RSTC_EXTWAKE7 0L +#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) +#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 1L +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (1ul << 2) +#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 1L +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (1ul << 5) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC4_WO0 4L +#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) +#define PORT_PA18E_TC4_WO0 (1ul << 18) +#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC4_WO0 4L +#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) +#define PORT_PA14E_TC4_WO0 (1ul << 14) +#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC4_WO1 4L +#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) +#define PORT_PA19E_TC4_WO1 (1ul << 19) +#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC4_WO1 4L +#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) +#define PORT_PA15E_TC4_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for OPAMP peripheral ========== */ +#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ +#define MUX_PA02B_OPAMP_OANEG0 1L +#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) +#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) +#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ +#define MUX_PA07B_OPAMP_OAOUT0 1L +#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) +#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) +#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ +#define MUX_PA04B_OPAMP_OAOUT2 1L +#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) +#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) +#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ +#define MUX_PA06B_OPAMP_OAPOS0 1L +#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) +#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) +#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ +#define MUX_PA05B_OPAMP_OAPOS2 1L +#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) +#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) + +#endif /* _SAML21E15A_PIO_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e16a.h new file mode 100644 index 0000000000..0457c5ee96 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e16a.h @@ -0,0 +1,757 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML21E16A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21E16A_PIO_ +#define _SAML21E16A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +/* ========== PORT definition for RSTC peripheral ========== */ +#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ +#define MUX_PA00A_RSTC_EXTWAKE0 0L +#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) +#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) +#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ +#define MUX_PA01A_RSTC_EXTWAKE1 0L +#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) +#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) +#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ +#define MUX_PA02A_RSTC_EXTWAKE2 0L +#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) +#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) +#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ +#define MUX_PA03A_RSTC_EXTWAKE3 0L +#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) +#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) +#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ +#define MUX_PA04A_RSTC_EXTWAKE4 0L +#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) +#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) +#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ +#define MUX_PA05A_RSTC_EXTWAKE5 0L +#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) +#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) +#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ +#define MUX_PA06A_RSTC_EXTWAKE6 0L +#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) +#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) +#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ +#define MUX_PA07A_RSTC_EXTWAKE7 0L +#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) +#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 1L +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (1ul << 2) +#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 1L +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (1ul << 5) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC4_WO0 4L +#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) +#define PORT_PA18E_TC4_WO0 (1ul << 18) +#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC4_WO0 4L +#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) +#define PORT_PA14E_TC4_WO0 (1ul << 14) +#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC4_WO1 4L +#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) +#define PORT_PA19E_TC4_WO1 (1ul << 19) +#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC4_WO1 4L +#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) +#define PORT_PA15E_TC4_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for OPAMP peripheral ========== */ +#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ +#define MUX_PA02B_OPAMP_OANEG0 1L +#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) +#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) +#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ +#define MUX_PA07B_OPAMP_OAOUT0 1L +#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) +#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) +#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ +#define MUX_PA04B_OPAMP_OAOUT2 1L +#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) +#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) +#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ +#define MUX_PA06B_OPAMP_OAPOS0 1L +#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) +#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) +#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ +#define MUX_PA05B_OPAMP_OAPOS2 1L +#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) +#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) + +#endif /* _SAML21E16A_PIO_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e17a.h new file mode 100644 index 0000000000..1ed2a183cc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21e17a.h @@ -0,0 +1,757 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML21E17A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21E17A_PIO_ +#define _SAML21E17A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +/* ========== PORT definition for RSTC peripheral ========== */ +#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ +#define MUX_PA00A_RSTC_EXTWAKE0 0L +#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) +#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) +#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ +#define MUX_PA01A_RSTC_EXTWAKE1 0L +#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) +#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) +#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ +#define MUX_PA02A_RSTC_EXTWAKE2 0L +#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) +#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) +#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ +#define MUX_PA03A_RSTC_EXTWAKE3 0L +#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) +#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) +#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ +#define MUX_PA04A_RSTC_EXTWAKE4 0L +#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) +#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) +#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ +#define MUX_PA05A_RSTC_EXTWAKE5 0L +#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) +#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) +#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ +#define MUX_PA06A_RSTC_EXTWAKE6 0L +#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) +#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) +#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ +#define MUX_PA07A_RSTC_EXTWAKE7 0L +#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) +#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 1L +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (1ul << 2) +#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 1L +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (1ul << 5) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC4_WO0 4L +#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) +#define PORT_PA18E_TC4_WO0 (1ul << 18) +#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC4_WO0 4L +#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) +#define PORT_PA14E_TC4_WO0 (1ul << 14) +#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC4_WO1 4L +#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) +#define PORT_PA19E_TC4_WO1 (1ul << 19) +#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC4_WO1 4L +#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) +#define PORT_PA15E_TC4_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for OPAMP peripheral ========== */ +#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ +#define MUX_PA02B_OPAMP_OANEG0 1L +#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) +#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) +#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ +#define MUX_PA07B_OPAMP_OAOUT0 1L +#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) +#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) +#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ +#define MUX_PA04B_OPAMP_OAOUT2 1L +#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) +#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) +#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ +#define MUX_PA06B_OPAMP_OAPOS0 1L +#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) +#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) +#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ +#define MUX_PA05B_OPAMP_OAPOS2 1L +#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) +#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) + +#endif /* _SAML21E17A_PIO_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g16a.h new file mode 100644 index 0000000000..d564312b22 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g16a.h @@ -0,0 +1,1060 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML21G16A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21G16A_PIO_ +#define _SAML21G16A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for RSTC peripheral ========== */ +#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ +#define MUX_PA00A_RSTC_EXTWAKE0 0L +#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) +#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) +#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ +#define MUX_PA01A_RSTC_EXTWAKE1 0L +#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) +#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) +#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ +#define MUX_PA02A_RSTC_EXTWAKE2 0L +#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) +#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) +#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ +#define MUX_PA03A_RSTC_EXTWAKE3 0L +#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) +#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) +#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ +#define MUX_PA04A_RSTC_EXTWAKE4 0L +#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) +#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) +#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ +#define MUX_PA05A_RSTC_EXTWAKE5 0L +#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) +#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) +#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ +#define MUX_PA06A_RSTC_EXTWAKE6 0L +#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) +#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) +#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ +#define MUX_PA07A_RSTC_EXTWAKE7 0L +#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) +#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ +#define MUX_PB10H_GCLK_IO4 7L +#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) +#define PORT_PB10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ +#define MUX_PA21H_GCLK_IO5 7L +#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) +#define PORT_PA21H_GCLK_IO5 (1ul << 21) +#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ +#define MUX_PB11H_GCLK_IO5 7L +#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) +#define PORT_PB11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 0L +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 2L +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 2L +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 3L +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 3L +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD0 3L +#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) +#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 3L +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD1 3L +#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) +#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 3L +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 3L +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 3L +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 3L +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 3L +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 5L +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (1ul << 10) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TCC2_WO0 4L +#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) +#define PORT_PA12E_TCC2_WO0 (1ul << 12) +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TCC2_WO1 4L +#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) +#define PORT_PA13E_TCC2_WO1 (1ul << 13) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC1_WO0 4L +#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) +#define PORT_PB10E_TC1_WO0 (1ul << 10) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 1L +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (1ul << 2) +#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 1L +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (1ul << 5) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD0 3L +#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) +#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD1 3L +#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) +#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 3L +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 2L +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) +#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 3L +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 2L +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC4_WO0 4L +#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) +#define PORT_PA18E_TC4_WO0 (1ul << 18) +#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC4_WO0 4L +#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) +#define PORT_PA14E_TC4_WO0 (1ul << 14) +#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC4_WO1 4L +#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) +#define PORT_PA19E_TC4_WO1 (1ul << 19) +#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC4_WO1 4L +#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) +#define PORT_PA15E_TC4_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for OPAMP peripheral ========== */ +#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ +#define MUX_PA02B_OPAMP_OANEG0 1L +#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) +#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) +#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ +#define MUX_PB08B_OPAMP_OANEG2 1L +#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) +#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) +#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ +#define MUX_PA07B_OPAMP_OAOUT0 1L +#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) +#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) +#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ +#define MUX_PA04B_OPAMP_OAOUT2 1L +#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) +#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) +#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ +#define MUX_PA06B_OPAMP_OAPOS0 1L +#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) +#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) +#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ +#define MUX_PB09B_OPAMP_OAPOS1 1L +#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) +#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) +#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ +#define MUX_PA05B_OPAMP_OAPOS2 1L +#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) +#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ +#define MUX_PB10I_CCL_IN5 8L +#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) +#define PORT_PB10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) + +#endif /* _SAML21G16A_PIO_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g17a.h new file mode 100644 index 0000000000..a6e1db3050 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g17a.h @@ -0,0 +1,1060 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML21G17A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21G17A_PIO_ +#define _SAML21G17A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for RSTC peripheral ========== */ +#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ +#define MUX_PA00A_RSTC_EXTWAKE0 0L +#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) +#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) +#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ +#define MUX_PA01A_RSTC_EXTWAKE1 0L +#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) +#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) +#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ +#define MUX_PA02A_RSTC_EXTWAKE2 0L +#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) +#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) +#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ +#define MUX_PA03A_RSTC_EXTWAKE3 0L +#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) +#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) +#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ +#define MUX_PA04A_RSTC_EXTWAKE4 0L +#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) +#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) +#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ +#define MUX_PA05A_RSTC_EXTWAKE5 0L +#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) +#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) +#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ +#define MUX_PA06A_RSTC_EXTWAKE6 0L +#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) +#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) +#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ +#define MUX_PA07A_RSTC_EXTWAKE7 0L +#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) +#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ +#define MUX_PB10H_GCLK_IO4 7L +#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) +#define PORT_PB10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ +#define MUX_PA21H_GCLK_IO5 7L +#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) +#define PORT_PA21H_GCLK_IO5 (1ul << 21) +#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ +#define MUX_PB11H_GCLK_IO5 7L +#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) +#define PORT_PB11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 0L +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 2L +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 2L +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 3L +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 3L +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD0 3L +#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) +#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 3L +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD1 3L +#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) +#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 3L +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 3L +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 3L +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 3L +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 3L +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 5L +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (1ul << 10) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TCC2_WO0 4L +#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) +#define PORT_PA12E_TCC2_WO0 (1ul << 12) +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TCC2_WO1 4L +#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) +#define PORT_PA13E_TCC2_WO1 (1ul << 13) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC1_WO0 4L +#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) +#define PORT_PB10E_TC1_WO0 (1ul << 10) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 1L +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (1ul << 2) +#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 1L +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (1ul << 5) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD0 3L +#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) +#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD1 3L +#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) +#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 3L +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 2L +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) +#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 3L +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 2L +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC4_WO0 4L +#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) +#define PORT_PA18E_TC4_WO0 (1ul << 18) +#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC4_WO0 4L +#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) +#define PORT_PA14E_TC4_WO0 (1ul << 14) +#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC4_WO1 4L +#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) +#define PORT_PA19E_TC4_WO1 (1ul << 19) +#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC4_WO1 4L +#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) +#define PORT_PA15E_TC4_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for OPAMP peripheral ========== */ +#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ +#define MUX_PA02B_OPAMP_OANEG0 1L +#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) +#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) +#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ +#define MUX_PB08B_OPAMP_OANEG2 1L +#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) +#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) +#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ +#define MUX_PA07B_OPAMP_OAOUT0 1L +#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) +#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) +#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ +#define MUX_PA04B_OPAMP_OAOUT2 1L +#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) +#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) +#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ +#define MUX_PA06B_OPAMP_OAPOS0 1L +#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) +#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) +#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ +#define MUX_PB09B_OPAMP_OAPOS1 1L +#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) +#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) +#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ +#define MUX_PA05B_OPAMP_OAPOS2 1L +#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) +#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ +#define MUX_PB10I_CCL_IN5 8L +#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) +#define PORT_PB10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) + +#endif /* _SAML21G17A_PIO_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g18a.h new file mode 100644 index 0000000000..444d98abb1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21g18a.h @@ -0,0 +1,1060 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML21G18A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21G18A_PIO_ +#define _SAML21G18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for RSTC peripheral ========== */ +#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ +#define MUX_PA00A_RSTC_EXTWAKE0 0L +#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) +#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) +#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ +#define MUX_PA01A_RSTC_EXTWAKE1 0L +#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) +#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) +#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ +#define MUX_PA02A_RSTC_EXTWAKE2 0L +#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) +#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) +#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ +#define MUX_PA03A_RSTC_EXTWAKE3 0L +#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) +#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) +#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ +#define MUX_PA04A_RSTC_EXTWAKE4 0L +#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) +#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) +#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ +#define MUX_PA05A_RSTC_EXTWAKE5 0L +#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) +#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) +#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ +#define MUX_PA06A_RSTC_EXTWAKE6 0L +#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) +#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) +#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ +#define MUX_PA07A_RSTC_EXTWAKE7 0L +#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) +#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ +#define MUX_PB10H_GCLK_IO4 7L +#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) +#define PORT_PB10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ +#define MUX_PA21H_GCLK_IO5 7L +#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) +#define PORT_PA21H_GCLK_IO5 (1ul << 21) +#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ +#define MUX_PB11H_GCLK_IO5 7L +#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) +#define PORT_PB11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 0L +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 2L +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 2L +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 3L +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 3L +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD0 3L +#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) +#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 3L +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD1 3L +#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) +#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 3L +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 3L +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 3L +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 3L +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 3L +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 5L +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (1ul << 10) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TCC2_WO0 4L +#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) +#define PORT_PA12E_TCC2_WO0 (1ul << 12) +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TCC2_WO1 4L +#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) +#define PORT_PA13E_TCC2_WO1 (1ul << 13) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC1_WO0 4L +#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) +#define PORT_PB10E_TC1_WO0 (1ul << 10) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 1L +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (1ul << 2) +#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 1L +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (1ul << 5) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD0 3L +#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) +#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD1 3L +#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) +#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 3L +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 2L +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) +#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 3L +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 2L +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC4_WO0 4L +#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) +#define PORT_PA18E_TC4_WO0 (1ul << 18) +#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC4_WO0 4L +#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) +#define PORT_PA14E_TC4_WO0 (1ul << 14) +#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC4_WO1 4L +#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) +#define PORT_PA19E_TC4_WO1 (1ul << 19) +#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC4_WO1 4L +#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) +#define PORT_PA15E_TC4_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for OPAMP peripheral ========== */ +#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ +#define MUX_PA02B_OPAMP_OANEG0 1L +#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) +#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) +#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ +#define MUX_PB08B_OPAMP_OANEG2 1L +#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) +#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) +#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ +#define MUX_PA07B_OPAMP_OAOUT0 1L +#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) +#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) +#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ +#define MUX_PA04B_OPAMP_OAOUT2 1L +#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) +#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) +#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ +#define MUX_PA06B_OPAMP_OAPOS0 1L +#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) +#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) +#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ +#define MUX_PB09B_OPAMP_OAPOS1 1L +#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) +#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) +#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ +#define MUX_PA05B_OPAMP_OAPOS2 1L +#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) +#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ +#define MUX_PB10I_CCL_IN5 8L +#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) +#define PORT_PB10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) + +#endif /* _SAML21G18A_PIO_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j16a.h new file mode 100644 index 0000000000..d3ca7de05d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j16a.h @@ -0,0 +1,1378 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML21J16A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21J16A_PIO_ +#define _SAML21J16A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for RSTC peripheral ========== */ +#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ +#define MUX_PA00A_RSTC_EXTWAKE0 0L +#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) +#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) +#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ +#define MUX_PA01A_RSTC_EXTWAKE1 0L +#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) +#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) +#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ +#define MUX_PA02A_RSTC_EXTWAKE2 0L +#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) +#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) +#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ +#define MUX_PA03A_RSTC_EXTWAKE3 0L +#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) +#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) +#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ +#define MUX_PA04A_RSTC_EXTWAKE4 0L +#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) +#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) +#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ +#define MUX_PA05A_RSTC_EXTWAKE5 0L +#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) +#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) +#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ +#define MUX_PA06A_RSTC_EXTWAKE6 0L +#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) +#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) +#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ +#define MUX_PA07A_RSTC_EXTWAKE7 0L +#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) +#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 7L +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (1ul << 1) +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK 7L +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (1ul << 0) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ +#define MUX_PB10H_GCLK_IO4 7L +#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) +#define PORT_PB10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ +#define MUX_PA21H_GCLK_IO5 7L +#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) +#define PORT_PA21H_GCLK_IO5 (1ul << 21) +#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ +#define MUX_PB11H_GCLK_IO5 7L +#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) +#define PORT_PB11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ +#define MUX_PB12H_GCLK_IO6 7L +#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) +#define PORT_PB12H_GCLK_IO6 (1ul << 12) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ +#define MUX_PB13H_GCLK_IO7 7L +#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) +#define PORT_PB13H_GCLK_IO7 (1ul << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 0L +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 2L +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 2L +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 3L +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 3L +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD0 3L +#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) +#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 3L +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 2L +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) +#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD1 3L +#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) +#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 3L +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 2L +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ +#define MUX_PB31F_SERCOM4_PAD1 5L +#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) +#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) +#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 3L +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 3L +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 2L +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ +#define MUX_PB30F_SERCOM4_PAD2 5L +#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) +#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) +#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 3L +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 3L +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) +#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 2L +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 5L +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (1ul << 10) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ +#define MUX_PB30F_TCC1_WO2 5L +#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) +#define PORT_PB30F_TCC1_WO2 (1ul << 30) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ +#define MUX_PB31F_TCC1_WO3 5L +#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) +#define PORT_PB31F_TCC1_WO3 (1ul << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TCC2_WO0 4L +#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) +#define PORT_PA12E_TCC2_WO0 (1ul << 12) +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TCC2_WO1 4L +#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) +#define PORT_PA13E_TCC2_WO1 (1ul << 13) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 4L +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (1ul << 12) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 4L +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (1ul << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC1_WO0 4L +#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) +#define PORT_PB10E_TC1_WO0 (1ul << 10) +#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 4L +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (1ul << 14) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 4L +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (1ul << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 4L +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (1ul << 16) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 4L +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (1ul << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 4L +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (1ul << 0) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 4L +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (1ul << 1) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 1L +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (1ul << 2) +#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 1L +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (1ul << 5) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD0 3L +#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) +#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 3L +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) +#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 2L +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD1 3L +#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) +#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 3L +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) +#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 2L +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) +#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 3L +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) +#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 3L +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 2L +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) +#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 3L +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) +#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 3L +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 2L +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC4_WO0 4L +#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) +#define PORT_PA18E_TC4_WO0 (1ul << 18) +#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC4_WO0 4L +#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) +#define PORT_PA14E_TC4_WO0 (1ul << 14) +#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC4_WO1 4L +#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) +#define PORT_PA19E_TC4_WO1 (1ul << 19) +#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC4_WO1 4L +#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) +#define PORT_PA15E_TC4_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for OPAMP peripheral ========== */ +#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ +#define MUX_PA02B_OPAMP_OANEG0 1L +#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) +#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) +#define PIN_PB05B_OPAMP_OANEG1 37L /**< \brief OPAMP signal: OANEG1 on PB05 mux B */ +#define MUX_PB05B_OPAMP_OANEG1 1L +#define PINMUX_PB05B_OPAMP_OANEG1 ((PIN_PB05B_OPAMP_OANEG1 << 16) | MUX_PB05B_OPAMP_OANEG1) +#define PORT_PB05B_OPAMP_OANEG1 (1ul << 5) +#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ +#define MUX_PB08B_OPAMP_OANEG2 1L +#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) +#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) +#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ +#define MUX_PA07B_OPAMP_OAOUT0 1L +#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) +#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) +#define PIN_PB06B_OPAMP_OAOUT1 38L /**< \brief OPAMP signal: OAOUT1 on PB06 mux B */ +#define MUX_PB06B_OPAMP_OAOUT1 1L +#define PINMUX_PB06B_OPAMP_OAOUT1 ((PIN_PB06B_OPAMP_OAOUT1 << 16) | MUX_PB06B_OPAMP_OAOUT1) +#define PORT_PB06B_OPAMP_OAOUT1 (1ul << 6) +#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ +#define MUX_PA04B_OPAMP_OAOUT2 1L +#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) +#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) +#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ +#define MUX_PA06B_OPAMP_OAPOS0 1L +#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) +#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) +#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ +#define MUX_PB09B_OPAMP_OAPOS1 1L +#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) +#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) +#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ +#define MUX_PA05B_OPAMP_OAPOS2 1L +#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) +#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 8L +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (1ul << 0) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 8L +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (1ul << 1) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ +#define MUX_PB10I_CCL_IN5 8L +#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) +#define PORT_PB10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 8L +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (1ul << 6) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 8L +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (1ul << 7) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 8L +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (1ul << 14) +#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 8L +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (1ul << 15) +#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 8L +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (1ul << 16) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) +#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 8L +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (1ul << 17) + +#endif /* _SAML21J16A_PIO_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j17a.h new file mode 100644 index 0000000000..64ae420b02 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j17a.h @@ -0,0 +1,1378 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML21J17A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21J17A_PIO_ +#define _SAML21J17A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for RSTC peripheral ========== */ +#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ +#define MUX_PA00A_RSTC_EXTWAKE0 0L +#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) +#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) +#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ +#define MUX_PA01A_RSTC_EXTWAKE1 0L +#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) +#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) +#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ +#define MUX_PA02A_RSTC_EXTWAKE2 0L +#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) +#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) +#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ +#define MUX_PA03A_RSTC_EXTWAKE3 0L +#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) +#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) +#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ +#define MUX_PA04A_RSTC_EXTWAKE4 0L +#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) +#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) +#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ +#define MUX_PA05A_RSTC_EXTWAKE5 0L +#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) +#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) +#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ +#define MUX_PA06A_RSTC_EXTWAKE6 0L +#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) +#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) +#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ +#define MUX_PA07A_RSTC_EXTWAKE7 0L +#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) +#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 7L +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (1ul << 1) +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK 7L +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (1ul << 0) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ +#define MUX_PB10H_GCLK_IO4 7L +#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) +#define PORT_PB10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ +#define MUX_PA21H_GCLK_IO5 7L +#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) +#define PORT_PA21H_GCLK_IO5 (1ul << 21) +#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ +#define MUX_PB11H_GCLK_IO5 7L +#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) +#define PORT_PB11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ +#define MUX_PB12H_GCLK_IO6 7L +#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) +#define PORT_PB12H_GCLK_IO6 (1ul << 12) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ +#define MUX_PB13H_GCLK_IO7 7L +#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) +#define PORT_PB13H_GCLK_IO7 (1ul << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 0L +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 2L +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 2L +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 3L +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 3L +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD0 3L +#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) +#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 3L +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 2L +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) +#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD1 3L +#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) +#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 3L +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 2L +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ +#define MUX_PB31F_SERCOM4_PAD1 5L +#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) +#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) +#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 3L +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 3L +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 2L +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ +#define MUX_PB30F_SERCOM4_PAD2 5L +#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) +#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) +#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 3L +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 3L +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) +#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 2L +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 5L +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (1ul << 10) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ +#define MUX_PB30F_TCC1_WO2 5L +#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) +#define PORT_PB30F_TCC1_WO2 (1ul << 30) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ +#define MUX_PB31F_TCC1_WO3 5L +#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) +#define PORT_PB31F_TCC1_WO3 (1ul << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TCC2_WO0 4L +#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) +#define PORT_PA12E_TCC2_WO0 (1ul << 12) +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TCC2_WO1 4L +#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) +#define PORT_PA13E_TCC2_WO1 (1ul << 13) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 4L +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (1ul << 12) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 4L +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (1ul << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC1_WO0 4L +#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) +#define PORT_PB10E_TC1_WO0 (1ul << 10) +#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 4L +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (1ul << 14) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 4L +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (1ul << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 4L +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (1ul << 16) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 4L +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (1ul << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 4L +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (1ul << 0) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 4L +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (1ul << 1) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 1L +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (1ul << 2) +#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 1L +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (1ul << 5) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD0 3L +#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) +#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 3L +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) +#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 2L +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD1 3L +#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) +#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 3L +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) +#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 2L +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) +#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 3L +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) +#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 3L +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 2L +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) +#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 3L +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) +#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 3L +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 2L +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC4_WO0 4L +#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) +#define PORT_PA18E_TC4_WO0 (1ul << 18) +#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC4_WO0 4L +#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) +#define PORT_PA14E_TC4_WO0 (1ul << 14) +#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC4_WO1 4L +#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) +#define PORT_PA19E_TC4_WO1 (1ul << 19) +#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC4_WO1 4L +#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) +#define PORT_PA15E_TC4_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for OPAMP peripheral ========== */ +#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ +#define MUX_PA02B_OPAMP_OANEG0 1L +#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) +#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) +#define PIN_PB05B_OPAMP_OANEG1 37L /**< \brief OPAMP signal: OANEG1 on PB05 mux B */ +#define MUX_PB05B_OPAMP_OANEG1 1L +#define PINMUX_PB05B_OPAMP_OANEG1 ((PIN_PB05B_OPAMP_OANEG1 << 16) | MUX_PB05B_OPAMP_OANEG1) +#define PORT_PB05B_OPAMP_OANEG1 (1ul << 5) +#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ +#define MUX_PB08B_OPAMP_OANEG2 1L +#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) +#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) +#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ +#define MUX_PA07B_OPAMP_OAOUT0 1L +#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) +#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) +#define PIN_PB06B_OPAMP_OAOUT1 38L /**< \brief OPAMP signal: OAOUT1 on PB06 mux B */ +#define MUX_PB06B_OPAMP_OAOUT1 1L +#define PINMUX_PB06B_OPAMP_OAOUT1 ((PIN_PB06B_OPAMP_OAOUT1 << 16) | MUX_PB06B_OPAMP_OAOUT1) +#define PORT_PB06B_OPAMP_OAOUT1 (1ul << 6) +#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ +#define MUX_PA04B_OPAMP_OAOUT2 1L +#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) +#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) +#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ +#define MUX_PA06B_OPAMP_OAPOS0 1L +#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) +#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) +#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ +#define MUX_PB09B_OPAMP_OAPOS1 1L +#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) +#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) +#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ +#define MUX_PA05B_OPAMP_OAPOS2 1L +#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) +#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 8L +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (1ul << 0) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 8L +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (1ul << 1) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ +#define MUX_PB10I_CCL_IN5 8L +#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) +#define PORT_PB10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 8L +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (1ul << 6) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 8L +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (1ul << 7) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 8L +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (1ul << 14) +#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 8L +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (1ul << 15) +#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 8L +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (1ul << 16) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) +#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 8L +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (1ul << 17) + +#endif /* _SAML21J17A_PIO_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j18a.h new file mode 100644 index 0000000000..2464b89737 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/pio/pio_saml21j18a.h @@ -0,0 +1,1378 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAML21J18A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21J18A_PIO_ +#define _SAML21J18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for RSTC peripheral ========== */ +#define PIN_PA00A_RSTC_EXTWAKE0 0L /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ +#define MUX_PA00A_RSTC_EXTWAKE0 0L +#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) +#define PORT_PA00A_RSTC_EXTWAKE0 (1ul << 0) +#define PIN_PA01A_RSTC_EXTWAKE1 1L /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ +#define MUX_PA01A_RSTC_EXTWAKE1 0L +#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) +#define PORT_PA01A_RSTC_EXTWAKE1 (1ul << 1) +#define PIN_PA02A_RSTC_EXTWAKE2 2L /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ +#define MUX_PA02A_RSTC_EXTWAKE2 0L +#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) +#define PORT_PA02A_RSTC_EXTWAKE2 (1ul << 2) +#define PIN_PA03A_RSTC_EXTWAKE3 3L /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ +#define MUX_PA03A_RSTC_EXTWAKE3 0L +#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) +#define PORT_PA03A_RSTC_EXTWAKE3 (1ul << 3) +#define PIN_PA04A_RSTC_EXTWAKE4 4L /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ +#define MUX_PA04A_RSTC_EXTWAKE4 0L +#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) +#define PORT_PA04A_RSTC_EXTWAKE4 (1ul << 4) +#define PIN_PA05A_RSTC_EXTWAKE5 5L /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ +#define MUX_PA05A_RSTC_EXTWAKE5 0L +#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) +#define PORT_PA05A_RSTC_EXTWAKE5 (1ul << 5) +#define PIN_PA06A_RSTC_EXTWAKE6 6L /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ +#define MUX_PA06A_RSTC_EXTWAKE6 0L +#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) +#define PORT_PA06A_RSTC_EXTWAKE6 (1ul << 6) +#define PIN_PA07A_RSTC_EXTWAKE7 7L /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ +#define MUX_PA07A_RSTC_EXTWAKE7 0L +#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) +#define PORT_PA07A_RSTC_EXTWAKE7 (1ul << 7) +/* ========== PORT definition for SUPC peripheral ========== */ +#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */ +#define MUX_PB01H_SUPC_OUT0 7L +#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0) +#define PORT_PB01H_SUPC_OUT0 (1ul << 1) +#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */ +#define MUX_PB02H_SUPC_OUT1 7L +#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) +#define PORT_PB02H_SUPC_OUT1 (1ul << 2) +#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */ +#define MUX_PB00H_SUPC_PSOK 7L +#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) +#define PORT_PB00H_SUPC_PSOK (1ul << 0) +#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */ +#define MUX_PB03H_SUPC_VBAT 7L +#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) +#define PORT_PB03H_SUPC_VBAT (1ul << 3) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ +#define MUX_PB10H_GCLK_IO4 7L +#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) +#define PORT_PB10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ +#define MUX_PA21H_GCLK_IO5 7L +#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) +#define PORT_PA21H_GCLK_IO5 (1ul << 21) +#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ +#define MUX_PB11H_GCLK_IO5 7L +#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) +#define PORT_PB11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ +#define MUX_PB12H_GCLK_IO6 7L +#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) +#define PORT_PB12H_GCLK_IO6 (1ul << 12) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ +#define MUX_PB13H_GCLK_IO7 7L +#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) +#define PORT_PB13H_GCLK_IO7 (1ul << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 0L +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */ +#define MUX_PA27G_TAL_BRK 6L +#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) +#define PORT_PA27G_TAL_BRK (1ul << 27) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 2L +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 2L +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA27F_SERCOM3_PAD0 27L /**< \brief SERCOM3 signal: PAD0 on PA27 mux F */ +#define MUX_PA27F_SERCOM3_PAD0 5L +#define PINMUX_PA27F_SERCOM3_PAD0 ((PIN_PA27F_SERCOM3_PAD0 << 16) | MUX_PA27F_SERCOM3_PAD0) +#define PORT_PA27F_SERCOM3_PAD0 (1ul << 27) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 3L +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 3L +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD0 3L +#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) +#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 3L +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 2L +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) +#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD1 3L +#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) +#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 3L +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 2L +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB31F_SERCOM4_PAD1 63L /**< \brief SERCOM4 signal: PAD1 on PB31 mux F */ +#define MUX_PB31F_SERCOM4_PAD1 5L +#define PINMUX_PB31F_SERCOM4_PAD1 ((PIN_PB31F_SERCOM4_PAD1 << 16) | MUX_PB31F_SERCOM4_PAD1) +#define PORT_PB31F_SERCOM4_PAD1 (1ul << 31) +#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 3L +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 3L +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 2L +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB30F_SERCOM4_PAD2 62L /**< \brief SERCOM4 signal: PAD2 on PB30 mux F */ +#define MUX_PB30F_SERCOM4_PAD2 5L +#define PINMUX_PB30F_SERCOM4_PAD2 ((PIN_PB30F_SERCOM4_PAD2 << 16) | MUX_PB30F_SERCOM4_PAD2) +#define PORT_PB30F_SERCOM4_PAD2 (1ul << 30) +#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 3L +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 3L +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) +#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 2L +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA16F_TCC0_WO0 16L /**< \brief TCC0 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO0 5L +#define PINMUX_PA16F_TCC0_WO0 ((PIN_PA16F_TCC0_WO0 << 16) | MUX_PA16F_TCC0_WO0) +#define PORT_PA16F_TCC0_WO0 (1ul << 16) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA17F_TCC0_WO1 17L /**< \brief TCC0 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO1 5L +#define PINMUX_PA17F_TCC0_WO1 ((PIN_PA17F_TCC0_WO1 << 16) | MUX_PA17F_TCC0_WO1) +#define PORT_PA17F_TCC0_WO1 (1ul << 17) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 5L +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (1ul << 10) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ +#define MUX_PB30F_TCC1_WO2 5L +#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) +#define PORT_PB30F_TCC1_WO2 (1ul << 30) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ +#define MUX_PB31F_TCC1_WO3 5L +#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) +#define PORT_PB31F_TCC1_WO3 (1ul << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TCC2_WO0 4L +#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) +#define PORT_PA12E_TCC2_WO0 (1ul << 12) +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TCC2_WO1 4L +#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) +#define PORT_PA13E_TCC2_WO1 (1ul << 13) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC0_WO0 4L +#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) +#define PORT_PA22E_TC0_WO0 (1ul << 22) +#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC0_WO0 4L +#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) +#define PORT_PB08E_TC0_WO0 (1ul << 8) +#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC0_WO0 4L +#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) +#define PORT_PB12E_TC0_WO0 (1ul << 12) +#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC0_WO1 4L +#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) +#define PORT_PA23E_TC0_WO1 (1ul << 23) +#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC0_WO1 4L +#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) +#define PORT_PB09E_TC0_WO1 (1ul << 9) +#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC0_WO1 4L +#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) +#define PORT_PB13E_TC0_WO1 (1ul << 13) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC1_WO0 4L +#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) +#define PORT_PA24E_TC1_WO0 (1ul << 24) +#define PIN_PB10E_TC1_WO0 42L /**< \brief TC1 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC1_WO0 4L +#define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) +#define PORT_PB10E_TC1_WO0 (1ul << 10) +#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC1_WO0 4L +#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) +#define PORT_PB14E_TC1_WO0 (1ul << 14) +#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC1_WO1 4L +#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) +#define PORT_PA25E_TC1_WO1 (1ul << 25) +#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC1_WO1 4L +#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) +#define PORT_PB11E_TC1_WO1 (1ul << 11) +#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC1_WO1 4L +#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) +#define PORT_PB15E_TC1_WO1 (1ul << 15) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC2_WO0 4L +#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) +#define PORT_PB02E_TC2_WO0 (1ul << 2) +#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC2_WO0 4L +#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) +#define PORT_PB16E_TC2_WO0 (1ul << 16) +#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC2_WO1 4L +#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) +#define PORT_PB03E_TC2_WO1 (1ul << 3) +#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC2_WO1 4L +#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) +#define PORT_PB17E_TC2_WO1 (1ul << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC3_WO0 4L +#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) +#define PORT_PA20E_TC3_WO0 (1ul << 20) +#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC3_WO0 4L +#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) +#define PORT_PB00E_TC3_WO0 (1ul << 0) +#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC3_WO0 4L +#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) +#define PORT_PB22E_TC3_WO0 (1ul << 22) +#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC3_WO1 4L +#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) +#define PORT_PA21E_TC3_WO1 (1ul << 21) +#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC3_WO1 4L +#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) +#define PORT_PB01E_TC3_WO1 (1ul << 1) +#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC3_WO1 4L +#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) +#define PORT_PB23E_TC3_WO1 (1ul << 23) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 2L /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 1L +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (1ul << 2) +#define PIN_PA05B_DAC_VOUT1 5L /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 1L +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (1ul << 5) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD0 3L +#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) +#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 3L +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) +#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 2L +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) +#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD1 3L +#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) +#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 3L +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) +#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 2L +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) +#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 3L +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) +#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 3L +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 2L +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) +#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 3L +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) +#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 3L +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 2L +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA18E_TC4_WO0 18L /**< \brief TC4 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC4_WO0 4L +#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) +#define PORT_PA18E_TC4_WO0 (1ul << 18) +#define PIN_PA14E_TC4_WO0 14L /**< \brief TC4 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC4_WO0 4L +#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) +#define PORT_PA14E_TC4_WO0 (1ul << 14) +#define PIN_PA19E_TC4_WO1 19L /**< \brief TC4 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC4_WO1 4L +#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) +#define PORT_PA19E_TC4_WO1 (1ul << 19) +#define PIN_PA15E_TC4_WO1 15L /**< \brief TC4 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC4_WO1 4L +#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) +#define PORT_PA15E_TC4_WO1 (1ul << 15) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for OPAMP peripheral ========== */ +#define PIN_PA02B_OPAMP_OANEG0 2L /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ +#define MUX_PA02B_OPAMP_OANEG0 1L +#define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) +#define PORT_PA02B_OPAMP_OANEG0 (1ul << 2) +#define PIN_PB05B_OPAMP_OANEG1 37L /**< \brief OPAMP signal: OANEG1 on PB05 mux B */ +#define MUX_PB05B_OPAMP_OANEG1 1L +#define PINMUX_PB05B_OPAMP_OANEG1 ((PIN_PB05B_OPAMP_OANEG1 << 16) | MUX_PB05B_OPAMP_OANEG1) +#define PORT_PB05B_OPAMP_OANEG1 (1ul << 5) +#define PIN_PB08B_OPAMP_OANEG2 40L /**< \brief OPAMP signal: OANEG2 on PB08 mux B */ +#define MUX_PB08B_OPAMP_OANEG2 1L +#define PINMUX_PB08B_OPAMP_OANEG2 ((PIN_PB08B_OPAMP_OANEG2 << 16) | MUX_PB08B_OPAMP_OANEG2) +#define PORT_PB08B_OPAMP_OANEG2 (1ul << 8) +#define PIN_PA07B_OPAMP_OAOUT0 7L /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ +#define MUX_PA07B_OPAMP_OAOUT0 1L +#define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) +#define PORT_PA07B_OPAMP_OAOUT0 (1ul << 7) +#define PIN_PB06B_OPAMP_OAOUT1 38L /**< \brief OPAMP signal: OAOUT1 on PB06 mux B */ +#define MUX_PB06B_OPAMP_OAOUT1 1L +#define PINMUX_PB06B_OPAMP_OAOUT1 ((PIN_PB06B_OPAMP_OAOUT1 << 16) | MUX_PB06B_OPAMP_OAOUT1) +#define PORT_PB06B_OPAMP_OAOUT1 (1ul << 6) +#define PIN_PA04B_OPAMP_OAOUT2 4L /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ +#define MUX_PA04B_OPAMP_OAOUT2 1L +#define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) +#define PORT_PA04B_OPAMP_OAOUT2 (1ul << 4) +#define PIN_PA06B_OPAMP_OAPOS0 6L /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ +#define MUX_PA06B_OPAMP_OAPOS0 1L +#define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) +#define PORT_PA06B_OPAMP_OAPOS0 (1ul << 6) +#define PIN_PB09B_OPAMP_OAPOS1 41L /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ +#define MUX_PB09B_OPAMP_OAPOS1 1L +#define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) +#define PORT_PB09B_OPAMP_OAPOS1 (1ul << 9) +#define PIN_PA05B_OPAMP_OAPOS2 5L /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ +#define MUX_PA05B_OPAMP_OAPOS2 1L +#define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) +#define PORT_PA05B_OPAMP_OAPOS2 (1ul << 5) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */ +#define MUX_PA04I_CCL_IN0 8L +#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) +#define PORT_PA04I_CCL_IN0 (1ul << 4) +#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */ +#define MUX_PA16I_CCL_IN0 8L +#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) +#define PORT_PA16I_CCL_IN0 (1ul << 16) +#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */ +#define MUX_PB22I_CCL_IN0 8L +#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) +#define PORT_PB22I_CCL_IN0 (1ul << 22) +#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */ +#define MUX_PA05I_CCL_IN1 8L +#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) +#define PORT_PA05I_CCL_IN1 (1ul << 5) +#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */ +#define MUX_PA17I_CCL_IN1 8L +#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) +#define PORT_PA17I_CCL_IN1 (1ul << 17) +#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */ +#define MUX_PB00I_CCL_IN1 8L +#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) +#define PORT_PB00I_CCL_IN1 (1ul << 0) +#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */ +#define MUX_PA06I_CCL_IN2 8L +#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) +#define PORT_PA06I_CCL_IN2 (1ul << 6) +#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */ +#define MUX_PA18I_CCL_IN2 8L +#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) +#define PORT_PA18I_CCL_IN2 (1ul << 18) +#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */ +#define MUX_PB01I_CCL_IN2 8L +#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) +#define PORT_PB01I_CCL_IN2 (1ul << 1) +#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */ +#define MUX_PA08I_CCL_IN3 8L +#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) +#define PORT_PA08I_CCL_IN3 (1ul << 8) +#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */ +#define MUX_PA30I_CCL_IN3 8L +#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) +#define PORT_PA30I_CCL_IN3 (1ul << 30) +#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */ +#define MUX_PA09I_CCL_IN4 8L +#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) +#define PORT_PA09I_CCL_IN4 (1ul << 9) +#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */ +#define MUX_PA10I_CCL_IN5 8L +#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) +#define PORT_PA10I_CCL_IN5 (1ul << 10) +#define PIN_PB10I_CCL_IN5 42L /**< \brief CCL signal: IN5 on PB10 mux I */ +#define MUX_PB10I_CCL_IN5 8L +#define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) +#define PORT_PB10I_CCL_IN5 (1ul << 10) +#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */ +#define MUX_PA22I_CCL_IN6 8L +#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) +#define PORT_PA22I_CCL_IN6 (1ul << 22) +#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */ +#define MUX_PB06I_CCL_IN6 8L +#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) +#define PORT_PB06I_CCL_IN6 (1ul << 6) +#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */ +#define MUX_PA23I_CCL_IN7 8L +#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) +#define PORT_PA23I_CCL_IN7 (1ul << 23) +#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */ +#define MUX_PB07I_CCL_IN7 8L +#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) +#define PORT_PB07I_CCL_IN7 (1ul << 7) +#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */ +#define MUX_PA24I_CCL_IN8 8L +#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) +#define PORT_PA24I_CCL_IN8 (1ul << 24) +#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */ +#define MUX_PB08I_CCL_IN8 8L +#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) +#define PORT_PB08I_CCL_IN8 (1ul << 8) +#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */ +#define MUX_PB14I_CCL_IN9 8L +#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) +#define PORT_PB14I_CCL_IN9 (1ul << 14) +#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */ +#define MUX_PB15I_CCL_IN10 8L +#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) +#define PORT_PB15I_CCL_IN10 (1ul << 15) +#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */ +#define MUX_PB16I_CCL_IN11 8L +#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) +#define PORT_PB16I_CCL_IN11 (1ul << 16) +#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */ +#define MUX_PA07I_CCL_OUT0 8L +#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) +#define PORT_PA07I_CCL_OUT0 (1ul << 7) +#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */ +#define MUX_PA19I_CCL_OUT0 8L +#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) +#define PORT_PA19I_CCL_OUT0 (1ul << 19) +#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */ +#define MUX_PB02I_CCL_OUT0 8L +#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) +#define PORT_PB02I_CCL_OUT0 (1ul << 2) +#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */ +#define MUX_PB23I_CCL_OUT0 8L +#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) +#define PORT_PB23I_CCL_OUT0 (1ul << 23) +#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */ +#define MUX_PA11I_CCL_OUT1 8L +#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) +#define PORT_PA11I_CCL_OUT1 (1ul << 11) +#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */ +#define MUX_PA31I_CCL_OUT1 8L +#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) +#define PORT_PA31I_CCL_OUT1 (1ul << 31) +#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */ +#define MUX_PB11I_CCL_OUT1 8L +#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) +#define PORT_PB11I_CCL_OUT1 (1ul << 11) +#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */ +#define MUX_PA25I_CCL_OUT2 8L +#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) +#define PORT_PA25I_CCL_OUT2 (1ul << 25) +#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */ +#define MUX_PB09I_CCL_OUT2 8L +#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) +#define PORT_PB09I_CCL_OUT2 (1ul << 9) +#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */ +#define MUX_PB17I_CCL_OUT3 8L +#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) +#define PORT_PB17I_CCL_OUT3 (1ul << 17) + +#endif /* _SAML21J18A_PIO_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21.h new file mode 100644 index 0000000000..06b72f3364 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21.h @@ -0,0 +1,77 @@ +/** + * \file + * + * \brief Top header file for SAML21 + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21_ +#define _SAML21_ + +/** + * \defgroup SAML21_definitions SAML21 Device Definitions + * \brief SAML21 CMSIS Definitions. + */ + +#if defined(__SAML21E15A__) || defined(__ATSAML21E15A__) +#include "saml21e15a.h" +#elif defined(__SAML21E16A__) || defined(__ATSAML21E16A__) +#include "saml21e16a.h" +#elif defined(__SAML21E17A__) || defined(__ATSAML21E17A__) +#include "saml21e17a.h" +#elif defined(__SAML21G16A__) || defined(__ATSAML21G16A__) +#include "saml21g16a.h" +#elif defined(__SAML21G17A__) || defined(__ATSAML21G17A__) +#include "saml21g17a.h" +#elif defined(__SAML21G18A__) || defined(__ATSAML21G18A__) +#include "saml21g18a.h" +#elif defined(__SAML21J16A__) || defined(__ATSAML21J16A__) +#include "saml21j16a.h" +#elif defined(__SAML21J17A__) || defined(__ATSAML21J17A__) +#include "saml21j17a.h" +#elif defined(__SAML21J18A__) || defined(__ATSAML21J18A__) +#include "saml21j18a.h" +#else +#error Library does not support the specified device. +#endif + +#endif /* _SAML21_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e15a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e15a.h new file mode 100644 index 0000000000..506a3a573c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e15a.h @@ -0,0 +1,623 @@ +/** + * \file + * + * \brief Header file for SAML21E15A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21E15A_ +#define _SAML21E15A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21E15A_definitions SAML21E15A definitions + * This file defines all structures and symbols for SAML21E15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21E15A */ +/* ************************************************************************** */ +/** \defgroup SAML21E15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML21E15A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21E15A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML21E15A Main Clock (MCLK) */ + OSCCTRL_IRQn = 0, /**< 0 SAML21E15A Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML21E15A 32k Oscillators Control (OSC32KCTRL) */ + PAC_IRQn = 0, /**< 0 SAML21E15A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML21E15A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML21E15A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML21E15A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML21E15A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21E15A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21E15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21E15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21E15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21E15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21E15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21E15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21E15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21E15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21E15A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 14, /**< 14 SAML21E15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21E15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21E15A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21E15A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21E15A Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21E15A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21E15A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21E15A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21E15A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21E15A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21E15A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21E15A True Random Generator (TRNG) */ + PICOP_IRQn = 28, /**< 28 SAML21E15A PicoProcessor (PICOP) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnReserved12; + void* pfnReserved13; + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnReserved19; + void* pfnReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pfnPICOP_Handler; /* 28 PicoProcessor */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void PICOP_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E15A */ +/* ************************************************************************** */ +/** \defgroup SAML21E15A_api Peripheral Software API */ +/*@{*/ + +#include "comp_ac.h" +#include "comp_adc.h" +#include "comp_aes.h" +#include "comp_ccl.h" +#include "comp_dac.h" +#include "comp_dmac.h" +#include "comp_dsu.h" +#include "comp_eic.h" +#include "comp_evsys.h" +#include "comp_gclk.h" +#include "comp_mclk.h" +#include "comp_mtb.h" +#include "comp_nvmctrl.h" +#include "comp_opamp.h" +#include "comp_oscctrl.h" +#include "comp_osc32kctrl.h" +#include "comp_pac.h" +#include "comp_pm.h" +#include "comp_port.h" +#include "comp_rstc.h" +#include "comp_rtc.h" +#include "comp_sercom.h" +#include "comp_supc.h" +#include "comp_tal.h" +#include "comp_tc.h" +#include "comp_tcc.h" +#include "comp_trng.h" +#include "comp_usb.h" +#include "comp_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21E15A */ +/* ************************************************************************** */ +/** \defgroup SAML21E15A_reg Registers Access Definitions */ +/*@{*/ + +#include "ins_ac.h" +#include "ins_adc.h" +#include "ins_aes.h" +#include "ins_ccl.h" +#include "ins_dac.h" +#include "ins_dmac.h" +#include "ins_dsu.h" +#include "ins_eic.h" +#include "ins_evsys.h" +#include "ins_gclk.h" +#include "ins_mclk.h" +#include "ins_mtb.h" +#include "ins_nvmctrl.h" +#include "ins_opamp.h" +#include "ins_oscctrl.h" +#include "ins_osc32kctrl.h" +#include "ins_pac.h" +#include "ins_pm.h" +#include "ins_port.h" +#include "ins_rstc.h" +#include "ins_rtc.h" +#include "ins_sercom0.h" +#include "ins_sercom1.h" +#include "ins_sercom2.h" +#include "ins_sercom3.h" +#include "ins_supc.h" +#include "ins_tal.h" +#include "ins_tc0.h" +#include "ins_tc1.h" +#include "ins_tc4.h" +#include "ins_tcc0.h" +#include "ins_tcc1.h" +#include "ins_tcc2.h" +#include "ins_trng.h" +#include "ins_usb.h" +#include "ins_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21E15A */ +/* ************************************************************************** */ +/** \defgroup SAML21E15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ +#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21E15A */ +/* ************************************************************************** */ +/** \defgroup SAML21E15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21E15A */ +/* ************************************************************************** */ +/** \defgroup SAML21E15A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21e15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21E15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x8000UL /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x1000UL /* 4 kB */ +#define LPRAM_SIZE 0x800UL /* 2 kB */ +#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ +#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ +#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ +#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ + +#define DSU_DID_RESETVALUE 0x1081000DUL +#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ +#define PORT_GROUPS 1 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21E15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21E15A_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e16a.h new file mode 100644 index 0000000000..cedbfa696a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e16a.h @@ -0,0 +1,623 @@ +/** + * \file + * + * \brief Header file for SAML21E16A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21E16A_ +#define _SAML21E16A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21E16A_definitions SAML21E16A definitions + * This file defines all structures and symbols for SAML21E16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21E16A */ +/* ************************************************************************** */ +/** \defgroup SAML21E16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML21E16A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21E16A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML21E16A Main Clock (MCLK) */ + OSCCTRL_IRQn = 0, /**< 0 SAML21E16A Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML21E16A 32k Oscillators Control (OSC32KCTRL) */ + PAC_IRQn = 0, /**< 0 SAML21E16A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML21E16A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML21E16A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML21E16A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML21E16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21E16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21E16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21E16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21E16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21E16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21E16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21E16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21E16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21E16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21E16A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 14, /**< 14 SAML21E16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21E16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21E16A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21E16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21E16A Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21E16A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21E16A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21E16A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21E16A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21E16A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21E16A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21E16A True Random Generator (TRNG) */ + PICOP_IRQn = 28, /**< 28 SAML21E16A PicoProcessor (PICOP) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnReserved12; + void* pfnReserved13; + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnReserved19; + void* pfnReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pfnPICOP_Handler; /* 28 PicoProcessor */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void PICOP_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E16A */ +/* ************************************************************************** */ +/** \defgroup SAML21E16A_api Peripheral Software API */ +/*@{*/ + +#include "comp_ac.h" +#include "comp_adc.h" +#include "comp_aes.h" +#include "comp_ccl.h" +#include "comp_dac.h" +#include "comp_dmac.h" +#include "comp_dsu.h" +#include "comp_eic.h" +#include "comp_evsys.h" +#include "comp_gclk.h" +#include "comp_mclk.h" +#include "comp_mtb.h" +#include "comp_nvmctrl.h" +#include "comp_opamp.h" +#include "comp_oscctrl.h" +#include "comp_osc32kctrl.h" +#include "comp_pac.h" +#include "comp_pm.h" +#include "comp_port.h" +#include "comp_rstc.h" +#include "comp_rtc.h" +#include "comp_sercom.h" +#include "comp_supc.h" +#include "comp_tal.h" +#include "comp_tc.h" +#include "comp_tcc.h" +#include "comp_trng.h" +#include "comp_usb.h" +#include "comp_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21E16A */ +/* ************************************************************************** */ +/** \defgroup SAML21E16A_reg Registers Access Definitions */ +/*@{*/ + +#include "ins_ac.h" +#include "ins_adc.h" +#include "ins_aes.h" +#include "ins_ccl.h" +#include "ins_dac.h" +#include "ins_dmac.h" +#include "ins_dsu.h" +#include "ins_eic.h" +#include "ins_evsys.h" +#include "ins_gclk.h" +#include "ins_mclk.h" +#include "ins_mtb.h" +#include "ins_nvmctrl.h" +#include "ins_opamp.h" +#include "ins_oscctrl.h" +#include "ins_osc32kctrl.h" +#include "ins_pac.h" +#include "ins_pm.h" +#include "ins_port.h" +#include "ins_rstc.h" +#include "ins_rtc.h" +#include "ins_sercom0.h" +#include "ins_sercom1.h" +#include "ins_sercom2.h" +#include "ins_sercom3.h" +#include "ins_supc.h" +#include "ins_tal.h" +#include "ins_tc0.h" +#include "ins_tc1.h" +#include "ins_tc4.h" +#include "ins_tcc0.h" +#include "ins_tcc1.h" +#include "ins_tcc2.h" +#include "ins_trng.h" +#include "ins_usb.h" +#include "ins_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21E16A */ +/* ************************************************************************** */ +/** \defgroup SAML21E16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ +#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21E16A */ +/* ************************************************************************** */ +/** \defgroup SAML21E16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21E16A */ +/* ************************************************************************** */ +/** \defgroup SAML21E16A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21e16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21E16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x10000UL /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x2000UL /* 8 kB */ +#define LPRAM_SIZE 0x1000UL /* 4 kB */ +#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ +#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ +#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ +#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ + +#define DSU_DID_RESETVALUE 0x1081000CUL +#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ +#define PORT_GROUPS 1 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21E16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21E16A_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e17a.h new file mode 100644 index 0000000000..93464bb325 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21e17a.h @@ -0,0 +1,623 @@ +/** + * \file + * + * \brief Header file for SAML21E17A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21E17A_ +#define _SAML21E17A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21E17A_definitions SAML21E17A definitions + * This file defines all structures and symbols for SAML21E17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21E17A */ +/* ************************************************************************** */ +/** \defgroup SAML21E17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML21E17A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21E17A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML21E17A Main Clock (MCLK) */ + OSCCTRL_IRQn = 0, /**< 0 SAML21E17A Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML21E17A 32k Oscillators Control (OSC32KCTRL) */ + PAC_IRQn = 0, /**< 0 SAML21E17A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML21E17A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML21E17A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML21E17A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML21E17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21E17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21E17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21E17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21E17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21E17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21E17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21E17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21E17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21E17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21E17A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 14, /**< 14 SAML21E17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21E17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21E17A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21E17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21E17A Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21E17A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21E17A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21E17A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21E17A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21E17A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21E17A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21E17A True Random Generator (TRNG) */ + PICOP_IRQn = 28, /**< 28 SAML21E17A PicoProcessor (PICOP) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnReserved12; + void* pfnReserved13; + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnReserved19; + void* pfnReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pfnPICOP_Handler; /* 28 PicoProcessor */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void PICOP_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E17A */ +/* ************************************************************************** */ +/** \defgroup SAML21E17A_api Peripheral Software API */ +/*@{*/ + +#include "comp_ac.h" +#include "comp_adc.h" +#include "comp_aes.h" +#include "comp_ccl.h" +#include "comp_dac.h" +#include "comp_dmac.h" +#include "comp_dsu.h" +#include "comp_eic.h" +#include "comp_evsys.h" +#include "comp_gclk.h" +#include "comp_mclk.h" +#include "comp_mtb.h" +#include "comp_nvmctrl.h" +#include "comp_opamp.h" +#include "comp_oscctrl.h" +#include "comp_osc32kctrl.h" +#include "comp_pac.h" +#include "comp_pm.h" +#include "comp_port.h" +#include "comp_rstc.h" +#include "comp_rtc.h" +#include "comp_sercom.h" +#include "comp_supc.h" +#include "comp_tal.h" +#include "comp_tc.h" +#include "comp_tcc.h" +#include "comp_trng.h" +#include "comp_usb.h" +#include "comp_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21E17A */ +/* ************************************************************************** */ +/** \defgroup SAML21E17A_reg Registers Access Definitions */ +/*@{*/ + +#include "ins_ac.h" +#include "ins_adc.h" +#include "ins_aes.h" +#include "ins_ccl.h" +#include "ins_dac.h" +#include "ins_dmac.h" +#include "ins_dsu.h" +#include "ins_eic.h" +#include "ins_evsys.h" +#include "ins_gclk.h" +#include "ins_mclk.h" +#include "ins_mtb.h" +#include "ins_nvmctrl.h" +#include "ins_opamp.h" +#include "ins_oscctrl.h" +#include "ins_osc32kctrl.h" +#include "ins_pac.h" +#include "ins_pm.h" +#include "ins_port.h" +#include "ins_rstc.h" +#include "ins_rtc.h" +#include "ins_sercom0.h" +#include "ins_sercom1.h" +#include "ins_sercom2.h" +#include "ins_sercom3.h" +#include "ins_supc.h" +#include "ins_tal.h" +#include "ins_tc0.h" +#include "ins_tc1.h" +#include "ins_tc4.h" +#include "ins_tcc0.h" +#include "ins_tcc1.h" +#include "ins_tcc2.h" +#include "ins_trng.h" +#include "ins_usb.h" +#include "ins_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21E17A */ +/* ************************************************************************** */ +/** \defgroup SAML21E17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ +#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21E17A */ +/* ************************************************************************** */ +/** \defgroup SAML21E17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21E17A */ +/* ************************************************************************** */ +/** \defgroup SAML21E17A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21e17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21E17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x20000UL /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x4000UL /* 16 kB */ +#define LPRAM_SIZE 0x1800UL /* 6 kB */ +#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ +#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ +#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ +#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ + +#define DSU_DID_RESETVALUE 0x1081000BUL +#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ +#define PORT_GROUPS 1 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21E17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21E17A_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g16a.h new file mode 100644 index 0000000000..1c9e7f826a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g16a.h @@ -0,0 +1,635 @@ +/** + * \file + * + * \brief Header file for SAML21G16A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21G16A_ +#define _SAML21G16A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21G16A_definitions SAML21G16A definitions + * This file defines all structures and symbols for SAML21G16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21G16A */ +/* ************************************************************************** */ +/** \defgroup SAML21G16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML21G16A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21G16A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML21G16A Main Clock (MCLK) */ + OSCCTRL_IRQn = 0, /**< 0 SAML21G16A Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML21G16A 32k Oscillators Control (OSC32KCTRL) */ + PAC_IRQn = 0, /**< 0 SAML21G16A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML21G16A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML21G16A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML21G16A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML21G16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21G16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21G16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21G16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21G16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21G16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21G16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21G16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21G16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21G16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21G16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21G16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21G16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21G16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21G16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21G16A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21G16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21G16A Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21G16A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21G16A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21G16A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21G16A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21G16A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21G16A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21G16A True Random Generator (TRNG) */ + PICOP_IRQn = 28, /**< 28 SAML21G16A PicoProcessor (PICOP) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnReserved19; + void* pfnReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pfnPICOP_Handler; /* 28 PicoProcessor */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void PICOP_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G16A */ +/* ************************************************************************** */ +/** \defgroup SAML21G16A_api Peripheral Software API */ +/*@{*/ + +#include "comp_ac.h" +#include "comp_adc.h" +#include "comp_aes.h" +#include "comp_ccl.h" +#include "comp_dac.h" +#include "comp_dmac.h" +#include "comp_dsu.h" +#include "comp_eic.h" +#include "comp_evsys.h" +#include "comp_gclk.h" +#include "comp_mclk.h" +#include "comp_mtb.h" +#include "comp_nvmctrl.h" +#include "comp_opamp.h" +#include "comp_oscctrl.h" +#include "comp_osc32kctrl.h" +#include "comp_pac.h" +#include "comp_pm.h" +#include "comp_port.h" +#include "comp_rstc.h" +#include "comp_rtc.h" +#include "comp_sercom.h" +#include "comp_supc.h" +#include "comp_tal.h" +#include "comp_tc.h" +#include "comp_tcc.h" +#include "comp_trng.h" +#include "comp_usb.h" +#include "comp_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21G16A */ +/* ************************************************************************** */ +/** \defgroup SAML21G16A_reg Registers Access Definitions */ +/*@{*/ + +#include "ins_ac.h" +#include "ins_adc.h" +#include "ins_aes.h" +#include "ins_ccl.h" +#include "ins_dac.h" +#include "ins_dmac.h" +#include "ins_dsu.h" +#include "ins_eic.h" +#include "ins_evsys.h" +#include "ins_gclk.h" +#include "ins_mclk.h" +#include "ins_mtb.h" +#include "ins_nvmctrl.h" +#include "ins_opamp.h" +#include "ins_oscctrl.h" +#include "ins_osc32kctrl.h" +#include "ins_pac.h" +#include "ins_pm.h" +#include "ins_port.h" +#include "ins_rstc.h" +#include "ins_rtc.h" +#include "ins_sercom0.h" +#include "ins_sercom1.h" +#include "ins_sercom2.h" +#include "ins_sercom3.h" +#include "ins_sercom4.h" +#include "ins_sercom5.h" +#include "ins_supc.h" +#include "ins_tal.h" +#include "ins_tc0.h" +#include "ins_tc1.h" +#include "ins_tc4.h" +#include "ins_tcc0.h" +#include "ins_tcc1.h" +#include "ins_tcc2.h" +#include "ins_trng.h" +#include "ins_usb.h" +#include "ins_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21G16A */ +/* ************************************************************************** */ +/** \defgroup SAML21G16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ +#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21G16A */ +/* ************************************************************************** */ +/** \defgroup SAML21G16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21G16A */ +/* ************************************************************************** */ +/** \defgroup SAML21G16A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21g16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21G16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x10000UL /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x2000UL /* 8 kB */ +#define LPRAM_SIZE 0x1000UL /* 4 kB */ +#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ +#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ +#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ +#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ + +#define DSU_DID_RESETVALUE 0x10810007UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21G16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21G16A_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g17a.h new file mode 100644 index 0000000000..634c0d32bc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g17a.h @@ -0,0 +1,635 @@ +/** + * \file + * + * \brief Header file for SAML21G17A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21G17A_ +#define _SAML21G17A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21G17A_definitions SAML21G17A definitions + * This file defines all structures and symbols for SAML21G17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21G17A */ +/* ************************************************************************** */ +/** \defgroup SAML21G17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML21G17A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21G17A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML21G17A Main Clock (MCLK) */ + OSCCTRL_IRQn = 0, /**< 0 SAML21G17A Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML21G17A 32k Oscillators Control (OSC32KCTRL) */ + PAC_IRQn = 0, /**< 0 SAML21G17A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML21G17A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML21G17A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML21G17A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML21G17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21G17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21G17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21G17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21G17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21G17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21G17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21G17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21G17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21G17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21G17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21G17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21G17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21G17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21G17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21G17A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21G17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21G17A Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21G17A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21G17A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21G17A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21G17A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21G17A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21G17A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21G17A True Random Generator (TRNG) */ + PICOP_IRQn = 28, /**< 28 SAML21G17A PicoProcessor (PICOP) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnReserved19; + void* pfnReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pfnPICOP_Handler; /* 28 PicoProcessor */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void PICOP_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G17A */ +/* ************************************************************************** */ +/** \defgroup SAML21G17A_api Peripheral Software API */ +/*@{*/ + +#include "comp_ac.h" +#include "comp_adc.h" +#include "comp_aes.h" +#include "comp_ccl.h" +#include "comp_dac.h" +#include "comp_dmac.h" +#include "comp_dsu.h" +#include "comp_eic.h" +#include "comp_evsys.h" +#include "comp_gclk.h" +#include "comp_mclk.h" +#include "comp_mtb.h" +#include "comp_nvmctrl.h" +#include "comp_opamp.h" +#include "comp_oscctrl.h" +#include "comp_osc32kctrl.h" +#include "comp_pac.h" +#include "comp_pm.h" +#include "comp_port.h" +#include "comp_rstc.h" +#include "comp_rtc.h" +#include "comp_sercom.h" +#include "comp_supc.h" +#include "comp_tal.h" +#include "comp_tc.h" +#include "comp_tcc.h" +#include "comp_trng.h" +#include "comp_usb.h" +#include "comp_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21G17A */ +/* ************************************************************************** */ +/** \defgroup SAML21G17A_reg Registers Access Definitions */ +/*@{*/ + +#include "ins_ac.h" +#include "ins_adc.h" +#include "ins_aes.h" +#include "ins_ccl.h" +#include "ins_dac.h" +#include "ins_dmac.h" +#include "ins_dsu.h" +#include "ins_eic.h" +#include "ins_evsys.h" +#include "ins_gclk.h" +#include "ins_mclk.h" +#include "ins_mtb.h" +#include "ins_nvmctrl.h" +#include "ins_opamp.h" +#include "ins_oscctrl.h" +#include "ins_osc32kctrl.h" +#include "ins_pac.h" +#include "ins_pm.h" +#include "ins_port.h" +#include "ins_rstc.h" +#include "ins_rtc.h" +#include "ins_sercom0.h" +#include "ins_sercom1.h" +#include "ins_sercom2.h" +#include "ins_sercom3.h" +#include "ins_sercom4.h" +#include "ins_sercom5.h" +#include "ins_supc.h" +#include "ins_tal.h" +#include "ins_tc0.h" +#include "ins_tc1.h" +#include "ins_tc4.h" +#include "ins_tcc0.h" +#include "ins_tcc1.h" +#include "ins_tcc2.h" +#include "ins_trng.h" +#include "ins_usb.h" +#include "ins_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21G17A */ +/* ************************************************************************** */ +/** \defgroup SAML21G17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ +#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21G17A */ +/* ************************************************************************** */ +/** \defgroup SAML21G17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21G17A */ +/* ************************************************************************** */ +/** \defgroup SAML21G17A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21g17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21G17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x20000UL /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x4000UL /* 16 kB */ +#define LPRAM_SIZE 0x1800UL /* 6 kB */ +#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ +#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ +#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ +#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ + +#define DSU_DID_RESETVALUE 0x10810006UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21G17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21G17A_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g18a.h new file mode 100644 index 0000000000..0b108ae74c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21g18a.h @@ -0,0 +1,635 @@ +/** + * \file + * + * \brief Header file for SAML21G18A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21G18A_ +#define _SAML21G18A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21G18A_definitions SAML21G18A definitions + * This file defines all structures and symbols for SAML21G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML21G18A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21G18A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML21G18A Main Clock (MCLK) */ + OSCCTRL_IRQn = 0, /**< 0 SAML21G18A Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML21G18A 32k Oscillators Control (OSC32KCTRL) */ + PAC_IRQn = 0, /**< 0 SAML21G18A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML21G18A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML21G18A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML21G18A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML21G18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21G18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21G18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21G18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21G18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21G18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21G18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21G18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21G18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21G18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21G18A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21G18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21G18A Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21G18A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21G18A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21G18A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21G18A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21G18A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21G18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21G18A True Random Generator (TRNG) */ + PICOP_IRQn = 28, /**< 28 SAML21G18A PicoProcessor (PICOP) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnReserved19; + void* pfnReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pfnPICOP_Handler; /* 28 PicoProcessor */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void PICOP_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_api Peripheral Software API */ +/*@{*/ + +#include "comp_ac.h" +#include "comp_adc.h" +#include "comp_aes.h" +#include "comp_ccl.h" +#include "comp_dac.h" +#include "comp_dmac.h" +#include "comp_dsu.h" +#include "comp_eic.h" +#include "comp_evsys.h" +#include "comp_gclk.h" +#include "comp_mclk.h" +#include "comp_mtb.h" +#include "comp_nvmctrl.h" +#include "comp_opamp.h" +#include "comp_oscctrl.h" +#include "comp_osc32kctrl.h" +#include "comp_pac.h" +#include "comp_pm.h" +#include "comp_port.h" +#include "comp_rstc.h" +#include "comp_rtc.h" +#include "comp_sercom.h" +#include "comp_supc.h" +#include "comp_tal.h" +#include "comp_tc.h" +#include "comp_tcc.h" +#include "comp_trng.h" +#include "comp_usb.h" +#include "comp_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "ins_ac.h" +#include "ins_adc.h" +#include "ins_aes.h" +#include "ins_ccl.h" +#include "ins_dac.h" +#include "ins_dmac.h" +#include "ins_dsu.h" +#include "ins_eic.h" +#include "ins_evsys.h" +#include "ins_gclk.h" +#include "ins_mclk.h" +#include "ins_mtb.h" +#include "ins_nvmctrl.h" +#include "ins_opamp.h" +#include "ins_oscctrl.h" +#include "ins_osc32kctrl.h" +#include "ins_pac.h" +#include "ins_pm.h" +#include "ins_port.h" +#include "ins_rstc.h" +#include "ins_rtc.h" +#include "ins_sercom0.h" +#include "ins_sercom1.h" +#include "ins_sercom2.h" +#include "ins_sercom3.h" +#include "ins_sercom4.h" +#include "ins_sercom5.h" +#include "ins_supc.h" +#include "ins_tal.h" +#include "ins_tc0.h" +#include "ins_tc1.h" +#include "ins_tc4.h" +#include "ins_tcc0.h" +#include "ins_tcc1.h" +#include "ins_tcc2.h" +#include "ins_trng.h" +#include "ins_usb.h" +#include "ins_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ +#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x40000UL /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x8000UL /* 32 kB */ +#define LPRAM_SIZE 0x2000UL /* 8 kB */ +#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ +#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ +#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ +#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ + +#define DSU_DID_RESETVALUE 0x10810005UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21G18A_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j16a.h new file mode 100644 index 0000000000..e5ac8baa65 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j16a.h @@ -0,0 +1,647 @@ +/** + * \file + * + * \brief Header file for SAML21J16A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21J16A_ +#define _SAML21J16A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21J16A_definitions SAML21J16A definitions + * This file defines all structures and symbols for SAML21J16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21J16A */ +/* ************************************************************************** */ +/** \defgroup SAML21J16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML21J16A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21J16A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML21J16A Main Clock (MCLK) */ + OSCCTRL_IRQn = 0, /**< 0 SAML21J16A Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML21J16A 32k Oscillators Control (OSC32KCTRL) */ + PAC_IRQn = 0, /**< 0 SAML21J16A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML21J16A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML21J16A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML21J16A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML21J16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21J16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21J16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21J16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21J16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21J16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21J16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21J16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21J16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21J16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21J16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21J16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21J16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21J16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21J16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21J16A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21J16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21J16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 19, /**< 19 SAML21J16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 20, /**< 20 SAML21J16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 21, /**< 21 SAML21J16A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21J16A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21J16A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21J16A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21J16A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21J16A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21J16A True Random Generator (TRNG) */ + PICOP_IRQn = 28, /**< 28 SAML21J16A PicoProcessor (PICOP) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pfnPICOP_Handler; /* 28 PicoProcessor */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void PICOP_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J16A */ +/* ************************************************************************** */ +/** \defgroup SAML21J16A_api Peripheral Software API */ +/*@{*/ + +#include "comp_ac.h" +#include "comp_adc.h" +#include "comp_aes.h" +#include "comp_ccl.h" +#include "comp_dac.h" +#include "comp_dmac.h" +#include "comp_dsu.h" +#include "comp_eic.h" +#include "comp_evsys.h" +#include "comp_gclk.h" +#include "comp_mclk.h" +#include "comp_mtb.h" +#include "comp_nvmctrl.h" +#include "comp_opamp.h" +#include "comp_oscctrl.h" +#include "comp_osc32kctrl.h" +#include "comp_pac.h" +#include "comp_pm.h" +#include "comp_port.h" +#include "comp_rstc.h" +#include "comp_rtc.h" +#include "comp_sercom.h" +#include "comp_supc.h" +#include "comp_tal.h" +#include "comp_tc.h" +#include "comp_tcc.h" +#include "comp_trng.h" +#include "comp_usb.h" +#include "comp_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21J16A */ +/* ************************************************************************** */ +/** \defgroup SAML21J16A_reg Registers Access Definitions */ +/*@{*/ + +#include "ins_ac.h" +#include "ins_adc.h" +#include "ins_aes.h" +#include "ins_ccl.h" +#include "ins_dac.h" +#include "ins_dmac.h" +#include "ins_dsu.h" +#include "ins_eic.h" +#include "ins_evsys.h" +#include "ins_gclk.h" +#include "ins_mclk.h" +#include "ins_mtb.h" +#include "ins_nvmctrl.h" +#include "ins_opamp.h" +#include "ins_oscctrl.h" +#include "ins_osc32kctrl.h" +#include "ins_pac.h" +#include "ins_pm.h" +#include "ins_port.h" +#include "ins_rstc.h" +#include "ins_rtc.h" +#include "ins_sercom0.h" +#include "ins_sercom1.h" +#include "ins_sercom2.h" +#include "ins_sercom3.h" +#include "ins_sercom4.h" +#include "ins_sercom5.h" +#include "ins_supc.h" +#include "ins_tal.h" +#include "ins_tc0.h" +#include "ins_tc1.h" +#include "ins_tc2.h" +#include "ins_tc3.h" +#include "ins_tc4.h" +#include "ins_tcc0.h" +#include "ins_tcc1.h" +#include "ins_tcc2.h" +#include "ins_trng.h" +#include "ins_usb.h" +#include "ins_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21J16A */ +/* ************************************************************************** */ +/** \defgroup SAML21J16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ +#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21J16A */ +/* ************************************************************************** */ +/** \defgroup SAML21J16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21J16A */ +/* ************************************************************************** */ +/** \defgroup SAML21J16A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21j16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21J16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x10000UL /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x2000UL /* 8 kB */ +#define LPRAM_SIZE 0x1000UL /* 4 kB */ +#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ +#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ +#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ +#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ + +#define DSU_DID_RESETVALUE 0x10810002UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21J16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21J16A_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j17a.h new file mode 100644 index 0000000000..ea00c47a2f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j17a.h @@ -0,0 +1,647 @@ +/** + * \file + * + * \brief Header file for SAML21J17A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21J17A_ +#define _SAML21J17A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21J17A_definitions SAML21J17A definitions + * This file defines all structures and symbols for SAML21J17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21J17A */ +/* ************************************************************************** */ +/** \defgroup SAML21J17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML21J17A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21J17A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML21J17A Main Clock (MCLK) */ + OSCCTRL_IRQn = 0, /**< 0 SAML21J17A Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML21J17A 32k Oscillators Control (OSC32KCTRL) */ + PAC_IRQn = 0, /**< 0 SAML21J17A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML21J17A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML21J17A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML21J17A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML21J17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21J17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21J17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21J17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21J17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21J17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21J17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21J17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21J17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21J17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21J17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21J17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21J17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21J17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21J17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21J17A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21J17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21J17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 19, /**< 19 SAML21J17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 20, /**< 20 SAML21J17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 21, /**< 21 SAML21J17A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21J17A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21J17A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21J17A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21J17A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21J17A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21J17A True Random Generator (TRNG) */ + PICOP_IRQn = 28, /**< 28 SAML21J17A PicoProcessor (PICOP) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pfnPICOP_Handler; /* 28 PicoProcessor */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void PICOP_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J17A */ +/* ************************************************************************** */ +/** \defgroup SAML21J17A_api Peripheral Software API */ +/*@{*/ + +#include "comp_ac.h" +#include "comp_adc.h" +#include "comp_aes.h" +#include "comp_ccl.h" +#include "comp_dac.h" +#include "comp_dmac.h" +#include "comp_dsu.h" +#include "comp_eic.h" +#include "comp_evsys.h" +#include "comp_gclk.h" +#include "comp_mclk.h" +#include "comp_mtb.h" +#include "comp_nvmctrl.h" +#include "comp_opamp.h" +#include "comp_oscctrl.h" +#include "comp_osc32kctrl.h" +#include "comp_pac.h" +#include "comp_pm.h" +#include "comp_port.h" +#include "comp_rstc.h" +#include "comp_rtc.h" +#include "comp_sercom.h" +#include "comp_supc.h" +#include "comp_tal.h" +#include "comp_tc.h" +#include "comp_tcc.h" +#include "comp_trng.h" +#include "comp_usb.h" +#include "comp_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21J17A */ +/* ************************************************************************** */ +/** \defgroup SAML21J17A_reg Registers Access Definitions */ +/*@{*/ + +#include "ins_ac.h" +#include "ins_adc.h" +#include "ins_aes.h" +#include "ins_ccl.h" +#include "ins_dac.h" +#include "ins_dmac.h" +#include "ins_dsu.h" +#include "ins_eic.h" +#include "ins_evsys.h" +#include "ins_gclk.h" +#include "ins_mclk.h" +#include "ins_mtb.h" +#include "ins_nvmctrl.h" +#include "ins_opamp.h" +#include "ins_oscctrl.h" +#include "ins_osc32kctrl.h" +#include "ins_pac.h" +#include "ins_pm.h" +#include "ins_port.h" +#include "ins_rstc.h" +#include "ins_rtc.h" +#include "ins_sercom0.h" +#include "ins_sercom1.h" +#include "ins_sercom2.h" +#include "ins_sercom3.h" +#include "ins_sercom4.h" +#include "ins_sercom5.h" +#include "ins_supc.h" +#include "ins_tal.h" +#include "ins_tc0.h" +#include "ins_tc1.h" +#include "ins_tc2.h" +#include "ins_tc3.h" +#include "ins_tc4.h" +#include "ins_tcc0.h" +#include "ins_tcc1.h" +#include "ins_tcc2.h" +#include "ins_trng.h" +#include "ins_usb.h" +#include "ins_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21J17A */ +/* ************************************************************************** */ +/** \defgroup SAML21J17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ +#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21J17A */ +/* ************************************************************************** */ +/** \defgroup SAML21J17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21J17A */ +/* ************************************************************************** */ +/** \defgroup SAML21J17A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21j17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21J17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x20000UL /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x4000UL /* 16 kB */ +#define LPRAM_SIZE 0x1800UL /* 6 kB */ +#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ +#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ +#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ +#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ + +#define DSU_DID_RESETVALUE 0x10810001UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21J17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21J17A_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j18a.h new file mode 100644 index 0000000000..51bb0f554f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/saml21j18a.h @@ -0,0 +1,647 @@ +/** + * \file + * + * \brief Header file for SAML21J18A + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAML21J18A_ +#define _SAML21J18A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21J18A_definitions SAML21J18A definitions + * This file defines all structures and symbols for SAML21J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAML21J18A-specific Interrupt Numbers ***********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21J18A System Interrupts */ + MCLK_IRQn = 0, /**< 0 SAML21J18A Main Clock (MCLK) */ + OSCCTRL_IRQn = 0, /**< 0 SAML21J18A Oscillators Control (OSCCTRL) */ + OSC32KCTRL_IRQn = 0, /**< 0 SAML21J18A 32k Oscillators Control (OSC32KCTRL) */ + PAC_IRQn = 0, /**< 0 SAML21J18A Peripheral Access Controller (PAC) */ + PM_IRQn = 0, /**< 0 SAML21J18A Power Manager (PM) */ + SUPC_IRQn = 0, /**< 0 SAML21J18A Supply Controller (SUPC) */ + TAL_IRQn = 0, /**< 0 SAML21J18A Trigger Allocator (TAL) */ + WDT_IRQn = 1, /**< 1 SAML21J18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21J18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21J18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21J18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21J18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21J18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21J18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21J18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21J18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21J18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21J18A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21J18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21J18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 19, /**< 19 SAML21J18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 20, /**< 20 SAML21J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 21, /**< 21 SAML21J18A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21J18A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21J18A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21J18A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21J18A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21J18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21J18A True Random Generator (TRNG) */ + PICOP_IRQn = 28, /**< 28 SAML21J18A PicoProcessor (PICOP) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pfnPICOP_Handler; /* 28 PicoProcessor */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void PICOP_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_api Peripheral Software API */ +/*@{*/ + +#include "comp_ac.h" +#include "comp_adc.h" +#include "comp_aes.h" +#include "comp_ccl.h" +#include "comp_dac.h" +#include "comp_dmac.h" +#include "comp_dsu.h" +#include "comp_eic.h" +#include "comp_evsys.h" +#include "comp_gclk.h" +#include "comp_mclk.h" +#include "comp_mtb.h" +#include "comp_nvmctrl.h" +#include "comp_opamp.h" +#include "comp_oscctrl.h" +#include "comp_osc32kctrl.h" +#include "comp_pac.h" +#include "comp_pm.h" +#include "comp_port.h" +#include "comp_rstc.h" +#include "comp_rtc.h" +#include "comp_sercom.h" +#include "comp_supc.h" +#include "comp_tal.h" +#include "comp_tc.h" +#include "comp_tcc.h" +#include "comp_trng.h" +#include "comp_usb.h" +#include "comp_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "ins_ac.h" +#include "ins_adc.h" +#include "ins_aes.h" +#include "ins_ccl.h" +#include "ins_dac.h" +#include "ins_dmac.h" +#include "ins_dsu.h" +#include "ins_eic.h" +#include "ins_evsys.h" +#include "ins_gclk.h" +#include "ins_mclk.h" +#include "ins_mtb.h" +#include "ins_nvmctrl.h" +#include "ins_opamp.h" +#include "ins_oscctrl.h" +#include "ins_osc32kctrl.h" +#include "ins_pac.h" +#include "ins_pm.h" +#include "ins_port.h" +#include "ins_rstc.h" +#include "ins_rtc.h" +#include "ins_sercom0.h" +#include "ins_sercom1.h" +#include "ins_sercom2.h" +#include "ins_sercom3.h" +#include "ins_sercom4.h" +#include "ins_sercom5.h" +#include "ins_supc.h" +#include "ins_tal.h" +#include "ins_tc0.h" +#include "ins_tc1.h" +#include "ins_tc2.h" +#include "ins_tc3.h" +#include "ins_tc4.h" +#include "ins_tcc0.h" +#include "ins_tcc1.h" +#include "ins_tcc2.h" +#include "ins_trng.h" +#include "ins_usb.h" +#include "ins_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ +#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_port PORT Definitions */ +/*@{*/ + +#include "pio_saml21j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE 0x40000UL /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE 0x8000UL /* 32 kB */ +#define LPRAM_SIZE 0x2000UL /* 8 kB */ +#define PICOPRAM_SIZE 0x1000UL /* 4 kB */ +#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR (0x20000000UL) /**< HSRAM base address */ +#define LPRAM_ADDR (0x30000000UL) /**< LPRAM base address */ +#define PICOPRAM_ADDR (0x50000000UL) /**< PICOPRAM base address */ + +#define DSU_DID_RESETVALUE 0x10810000UL +#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21J18A_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.c new file mode 100644 index 0000000000..74727a166f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.c @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "saml21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (4000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.h new file mode 100644 index 0000000000..65285ac3f4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/source/system_saml21.h @@ -0,0 +1,65 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SYSTEM_SAML21_H_INCLUDED_ +#define _SYSTEM_SAML21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAML21_H_INCLUDED */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h similarity index 68% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h index c375dd16b2..1973b025f6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h @@ -56,14 +56,14 @@ /* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } AC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -84,16 +84,16 @@ typedef union { /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -112,25 +112,25 @@ typedef union { /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } AC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -161,20 +161,20 @@ typedef union { /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -198,20 +198,20 @@ typedef union { /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -235,20 +235,20 @@ typedef union { /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -272,18 +272,18 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_STATUSA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -311,17 +311,17 @@ typedef union { /* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_STATUSB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -342,18 +342,18 @@ typedef union { /* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } AC_STATUSC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -381,12 +381,12 @@ typedef union { /* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } AC_WINCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -411,26 +411,26 @@ typedef union { /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ENABLE:1; /*!< bit: 0 Enable */ - uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ - uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 14 Reserved */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t OUT:2; /*!< bit: 16..17 Output */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ENABLE:1; /*!< bit: 0 Enable */ + uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ + uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ + uint32_t :1; /*!< bit: 4 Reserved */ + uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ + uint32_t :1; /*!< bit: 14 Reserved */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t OUT:2; /*!< bit: 16..17 Output */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } AC_COMPCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -516,11 +516,11 @@ typedef union { /* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } AC_SCALER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -535,22 +535,22 @@ typedef union { /** \brief AC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ - __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ - RoReg8 Reserved2[0x1]; - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ - RoReg8 Reserved3[0x3]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved4[0x8]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ + __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ + RoReg8 Reserved2[0x1]; + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ + RoReg8 Reserved3[0x3]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved4[0x8]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ } Ac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h similarity index 75% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h index 256d4f2b4d..871f0bff69 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h @@ -56,13 +56,13 @@ /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -80,12 +80,12 @@ typedef union { /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_REFCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -112,12 +112,12 @@ typedef union { /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_AVGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -157,11 +157,11 @@ typedef union { /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_SAMPCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -176,17 +176,17 @@ typedef union { /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -236,11 +236,11 @@ typedef union { /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_WINCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -265,12 +265,12 @@ typedef union { /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_SWTRIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -286,17 +286,17 @@ typedef union { /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ - uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ - uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ + uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ + uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } ADC_INPUTCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -405,15 +405,15 @@ typedef union { /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ - uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ + uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -433,14 +433,14 @@ typedef union { /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -460,14 +460,14 @@ typedef union { /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -487,14 +487,14 @@ typedef union { /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ - __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ + __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -514,11 +514,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -532,10 +532,10 @@ typedef union { /* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_RESULT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -550,10 +550,10 @@ typedef union { /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_WINLT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -568,10 +568,10 @@ typedef union { /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_WINUT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -586,11 +586,11 @@ typedef union { /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_GAINCORR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -605,11 +605,11 @@ typedef union { /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_OFFSETCORR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -624,12 +624,12 @@ typedef union { /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ - uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ + uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } ADC_CALIB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -647,11 +647,11 @@ typedef union { /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } ADC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -665,32 +665,32 @@ typedef union { /** \brief ADC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ - RoReg8 Reserved1[0x2]; - __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ - RoReg8 Reserved2[0x3]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ - RoReg8 Reserved3[0x3]; - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ - RoReg8 Reserved4[0x1]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ - RoReg8 Reserved5[0x2]; - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ - RoReg8 Reserved6[0x2]; - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ + RoReg8 Reserved1[0x2]; + __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ + RoReg8 Reserved2[0x3]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ + RoReg8 Reserved3[0x3]; + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ + RoReg8 Reserved4[0x1]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ + RoReg8 Reserved5[0x2]; + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ + RoReg8 Reserved6[0x2]; + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ } Adc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h similarity index 69% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h index 18d086f946..8ddc41bb5d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h @@ -56,23 +56,23 @@ /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -101,14 +101,14 @@ typedef union { /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_CRCCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -143,10 +143,10 @@ typedef union { /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_CRCDATAIN_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -161,10 +161,10 @@ typedef union { /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_CRCCHKSUM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -179,12 +179,12 @@ typedef union { /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CRCSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -200,11 +200,11 @@ typedef union { /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -218,13 +218,13 @@ typedef union { /* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ + uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ + uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_QOSCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -269,26 +269,26 @@ typedef union { /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_SWTRIGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -327,21 +327,21 @@ typedef union { /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_PRICTRL0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -373,18 +373,18 @@ typedef union { /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_INTPEND_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -411,26 +411,26 @@ typedef union { /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_INTSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -469,26 +469,26 @@ typedef union { /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_BUSYCH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -527,26 +527,26 @@ typedef union { /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_PENDCH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -585,22 +585,22 @@ typedef union { /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_ACTIVE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -631,10 +631,10 @@ typedef union { /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_BASEADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -649,10 +649,10 @@ typedef union { /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_WRBADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -667,11 +667,11 @@ typedef union { /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHID_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -686,12 +686,12 @@ typedef union { /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -707,19 +707,19 @@ typedef union { /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_CHCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -786,13 +786,13 @@ typedef union { /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHINTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -810,13 +810,13 @@ typedef union { /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHINTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -834,13 +834,13 @@ typedef union { /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHINTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -858,13 +858,13 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DMAC_CHSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -882,18 +882,18 @@ typedef union { /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_BTCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -965,10 +965,10 @@ typedef union { /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } DMAC_BTCNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -982,10 +982,10 @@ typedef union { /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_SRCADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -999,10 +999,10 @@ typedef union { /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_DSTADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1016,10 +1016,10 @@ typedef union { /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DMAC_DESCADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1033,49 +1033,49 @@ typedef union { /** \brief DMAC APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ - __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ - __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ - __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ - __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ - __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ - __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ - RoReg8 Reserved1[0x1]; - __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ - __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ - RoReg8 Reserved2[0x8]; - __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ - RoReg8 Reserved3[0x2]; - __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ - __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ - __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ - __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ - __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ - __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ - RoReg8 Reserved4[0x3]; - __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ - __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ - RoReg8 Reserved5[0x3]; - __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ - RoReg8 Reserved6[0x4]; - __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ - __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ - __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ - __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ + __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ + __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ + __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ + __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ + __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ + __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ + __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ + RoReg8 Reserved1[0x1]; + __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ + __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ + RoReg8 Reserved2[0x8]; + __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ + RoReg8 Reserved3[0x2]; + __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ + __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ + __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ + __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ + __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ + __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ + RoReg8 Reserved4[0x3]; + __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ + __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ + RoReg8 Reserved5[0x3]; + __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ + RoReg8 Reserved6[0x4]; + __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ + __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ + __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ + __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ } Dmac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief DMAC Descriptor SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ - __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ - __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ - __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ - __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ + __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ + __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ + __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ + __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ + __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ } DmacDescriptor #ifdef __GNUC__ - __attribute__ ((aligned (8))) +__attribute__ ((aligned (8))) #endif ; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h similarity index 65% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h index 8a9ab9840e..6fc3b83714 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h @@ -56,15 +56,15 @@ /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */ - uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */ - uint8_t CE:1; /*!< bit: 4 Chip Erase */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */ + uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */ + uint8_t CE:1; /*!< bit: 4 Chip Erase */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DSU_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -84,15 +84,15 @@ typedef union { /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DONE:1; /*!< bit: 0 Done */ - uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ - uint8_t BERR:1; /*!< bit: 2 Bus Error */ - uint8_t FAIL:1; /*!< bit: 3 Failure */ - uint8_t PERR:1; /*!< bit: 4 Protection Error */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DONE:1; /*!< bit: 0 Done */ + uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ + uint8_t BERR:1; /*!< bit: 2 Bus Error */ + uint8_t FAIL:1; /*!< bit: 3 Failure */ + uint8_t PERR:1; /*!< bit: 4 Protection Error */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } DSU_STATUSA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -114,20 +114,20 @@ typedef union { /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PROT:1; /*!< bit: 0 Protected */ - uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ - uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ - uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ - uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PROT:1; /*!< bit: 0 Protected */ + uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ + uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ + uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ + uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } DSU_STATUSB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -152,11 +152,11 @@ typedef union { /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t ADDR:30; /*!< bit: 2..31 Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t ADDR:30; /*!< bit: 2..31 Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -171,11 +171,11 @@ typedef union { /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t LENGTH:30; /*!< bit: 2..31 Length */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t LENGTH:30; /*!< bit: 2..31 Length */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_LENGTH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -190,10 +190,10 @@ typedef union { /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -208,10 +208,10 @@ typedef union { /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_DCC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -226,16 +226,16 @@ typedef union { /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ - uint32_t REVISION:4; /*!< bit: 8..11 Revision */ - uint32_t DIE:4; /*!< bit: 12..15 Die Identification */ - uint32_t SERIES:6; /*!< bit: 16..21 Product Series */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */ - uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ + uint32_t REVISION:4; /*!< bit: 8..11 Revision */ + uint32_t DIE:4; /*!< bit: 12..15 Die Identification */ + uint32_t SERIES:6; /*!< bit: 16..21 Product Series */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */ + uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_DID_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -264,13 +264,13 @@ typedef union { /* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EPRES:1; /*!< bit: 0 Entry Present */ - uint32_t FMT:1; /*!< bit: 1 Format */ - uint32_t :10; /*!< bit: 2..11 Reserved */ - uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EPRES:1; /*!< bit: 0 Entry Present */ + uint32_t FMT:1; /*!< bit: 1 Format */ + uint32_t :10; /*!< bit: 2..11 Reserved */ + uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_ENTRY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -289,10 +289,10 @@ typedef union { /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t END:32; /*!< bit: 0..31 End Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t END:32; /*!< bit: 0..31 End Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_END_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -307,11 +307,11 @@ typedef union { /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_MEMTYPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -325,12 +325,12 @@ typedef union { /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ - uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ + uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID4_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -348,11 +348,11 @@ typedef union { /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -367,12 +367,12 @@ typedef union { /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ - uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ + uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -390,13 +390,13 @@ typedef union { /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ - uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ - uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ + uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ + uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -416,12 +416,12 @@ typedef union { /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ - uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ + uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_PID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -439,11 +439,11 @@ typedef union { /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -458,12 +458,12 @@ typedef union { /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ - uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ + uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -481,11 +481,11 @@ typedef union { /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -500,11 +500,11 @@ typedef union { /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } DSU_CID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -519,30 +519,30 @@ typedef union { /** \brief DSU hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ - __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ - __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ - RoReg8 Reserved1[0x1]; - __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ - __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ - __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ - __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ - __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ - RoReg8 Reserved2[0xFE4]; - __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ - __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ - RoReg8 Reserved3[0xFC0]; - __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ - __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ - RoReg8 Reserved4[0xC]; - __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ - __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ - __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ - __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ - __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ - __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ - __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ - __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ + __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ + __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ + __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ + RoReg8 Reserved1[0x1]; + __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ + __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ + __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ + __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ + __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ + RoReg8 Reserved2[0xFE4]; + __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ + __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ + RoReg8 Reserved3[0xFC0]; + __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ + __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ + RoReg8 Reserved4[0xC]; + __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ + __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ + __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ + __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ + __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ + __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ + __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ + __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ } Dsu; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h similarity index 72% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h index bd6444328b..1f7322d85a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h @@ -56,12 +56,12 @@ /* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -77,11 +77,11 @@ typedef union { /* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -95,12 +95,12 @@ typedef union { /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ - uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ + uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_NMICTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -129,11 +129,11 @@ typedef union { /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EIC_NMIFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -147,30 +147,30 @@ typedef union { /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ - uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ - uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ - uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ - uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ - uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ - uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ - uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ - uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ - uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ - uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ - uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ - uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ - uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ - uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ - uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ + uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ + uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ + uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ + uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ + uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ + uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ + uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ + uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ + uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ + uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ + uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ + uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ + uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ + uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ + uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -217,30 +217,30 @@ typedef union { /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ + uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ + uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ + uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ + uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ + uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ + uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ + uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ + uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ + uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ + uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ + uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ + uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ + uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ + uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ + uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -287,30 +287,30 @@ typedef union { /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ - uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ - uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ - uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ - uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ - uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ - uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ - uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ - uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ - uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ - uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ - uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ - uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ - uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ - uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ - uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ + uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ + uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ + uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ + uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ + uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ + uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ + uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ + uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ + uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ + uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ + uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ + uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ + uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ + uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ + uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -357,30 +357,30 @@ typedef union { /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ - __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ - __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ - __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ - __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ - __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ - __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ - __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ - __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ - __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ - __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ - __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ - __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ - __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ - __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ - __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ - __I uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ - __I uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ + __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ + __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ + __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ + __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ + __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ + __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ + __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ + __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ + __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ + __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ + __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ + __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ + __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ + __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ + __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ + __I uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ + __I uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -427,30 +427,30 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ - uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ - uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ - uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ - uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ - uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ - uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ - uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ - uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ - uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ - uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ - uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ - uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ - uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ - uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ - uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ + uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ + uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ + uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ + uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ + uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ + uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ + uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ + uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ + uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ + uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ + uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ + uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ + uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ + uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ + uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EIC_WAKEUP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -497,25 +497,25 @@ typedef union { /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ - uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ - uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ - uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ - uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ - uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ - uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ - uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ - uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ - uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ - uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ - uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ - uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ - uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ - uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ - uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ + uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ + uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ + uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ + uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ + uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ + uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ + uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ + uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ + uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ + uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ + uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ + uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ + uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ + uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ + uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } EIC_CONFIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -663,16 +663,16 @@ typedef union { /** \brief EIC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ - __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ - __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ - __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ - __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ - __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ - __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ - __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ - __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ + __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ + __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ + __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ + __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ + __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ + __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ + __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ + __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ + __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ + __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ } Eic; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h similarity index 66% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h index b665bc29b4..32d12f2316 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h @@ -56,13 +56,13 @@ /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :3; /*!< bit: 1.. 3 Reserved */ - uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :3; /*!< bit: 1.. 3 Reserved */ + uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } EVSYS_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -78,18 +78,18 @@ typedef union { /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SWEVT:1; /*!< bit: 8 Software Event */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ - uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t SWEVT:1; /*!< bit: 8 Software Event */ + uint32_t :7; /*!< bit: 9..15 Reserved */ + uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ + uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_CHANNEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -129,13 +129,13 @@ typedef union { /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } EVSYS_USER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -155,43 +155,43 @@ typedef union { /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ - uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ - uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ - uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ - uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ - uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ - uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ - uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ - uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ - uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ - uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ - uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ - uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ - uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ - uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ - uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ - uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */ - uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */ - uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */ - uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ - uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ - uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ - uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ - uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ - uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ + uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ + uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ + uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ + uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ + uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ + uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ + uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ + uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ + uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ + uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ + uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ + uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ + uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ + uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ + uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ + uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */ + uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */ + uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */ + uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ + uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ + uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ + uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ + uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ + uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_CHSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -263,43 +263,43 @@ typedef union { /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ + uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ + uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ + uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ + uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ + uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ + uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ + uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ + uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ + uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ + uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ + uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ + uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ + uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ + uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -371,43 +371,43 @@ typedef union { /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ - uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ - uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ - uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ - uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ - uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ - uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ - uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ - uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ - uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ - uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ - uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ - uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ - uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ - uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ - uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ - uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ - uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ - uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ - uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ - uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ - uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ - uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ - uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ - uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ + uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ + uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ + uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ + uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ + uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ + uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ + uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ + uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ + uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ + uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ + uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ + uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ + uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ + uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ + uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ + uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */ + uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */ + uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */ + uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ + uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ + uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ + uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ + uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ + uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -479,43 +479,43 @@ typedef union { /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ - __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ - __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ - __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ - __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ - __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ - __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ - __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ - __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ - __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ - __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ - __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ - __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ - __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ - __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ - __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ - __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */ - __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */ - __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */ - __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */ - __I uint32_t :4; /*!< bit: 20..23 Reserved */ - __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ - __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ - __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ - __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ - __I uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ - __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ - __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */ - __I uint32_t :4; /*!< bit: 20..23 Reserved */ - __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */ - __I uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ + __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ + __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ + __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ + __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ + __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ + __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ + __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ + __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ + __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ + __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ + __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ + __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ + __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ + __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ + __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ + __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */ + __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */ + __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */ + __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */ + __I uint32_t :4; /*!< bit: 20..23 Reserved */ + __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ + __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ + __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ + __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ + __I uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ + __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ + __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */ + __I uint32_t :4; /*!< bit: 20..23 Reserved */ + __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */ + __I uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } EVSYS_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -587,15 +587,15 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /** \brief EVSYS hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ - __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ - RoReg8 Reserved2[0x2]; - __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ - __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ - __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ - __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ + __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ + __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ + RoReg8 Reserved2[0x2]; + __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ + __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ + __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ + __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ } Evsys; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h similarity index 83% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h index f18ef047ac..86e97913db 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h @@ -56,11 +56,11 @@ /* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } GCLK_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -74,11 +74,11 @@ typedef union { /* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } GCLK_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -92,15 +92,15 @@ typedef union { /* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ - uint16_t :2; /*!< bit: 12..13 Reserved */ - uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ - uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ + uint16_t :2; /*!< bit: 12..13 Reserved */ + uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ + uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } GCLK_CLKCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -212,20 +212,20 @@ typedef union { /* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t SRC:5; /*!< bit: 8..12 Source Select */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ - uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ - uint32_t OOV:1; /*!< bit: 18 Output Off Value */ - uint32_t OE:1; /*!< bit: 19 Output Enable */ - uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ - uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t SRC:5; /*!< bit: 8..12 Source Select */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ + uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ + uint32_t OOV:1; /*!< bit: 18 Output Off Value */ + uint32_t OE:1; /*!< bit: 19 Output Enable */ + uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ + uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } GCLK_GENCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -273,13 +273,13 @@ typedef union { /* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } GCLK_GENDIV_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -297,11 +297,11 @@ typedef union { /** \brief GCLK hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ - __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ - __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ - __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ + __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ + __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ + __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ + __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ } Gclk; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h similarity index 82% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h index 0102cabd6b..465c605b7c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h @@ -56,7 +56,7 @@ /* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } HMATRIXB_PRAS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -68,7 +68,7 @@ typedef union { /* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } HMATRIXB_PRBS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -80,10 +80,10 @@ typedef union { /* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } HMATRIXB_SFR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -98,18 +98,18 @@ typedef union { /** \brief HmatrixbPrs hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ - __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ + __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ + __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ } HmatrixbPrs; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief HMATRIXB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - RoReg8 Reserved1[0x80]; - HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ - RoReg8 Reserved2[0x10]; - __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ + RoReg8 Reserved1[0x80]; + HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ + RoReg8 Reserved2[0x10]; + __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ } Hmatrixb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h similarity index 70% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h index 4da747bfe3..b180c85346 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h @@ -56,12 +56,12 @@ /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ - uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ + uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } MTB_POSITION_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -77,17 +77,17 @@ typedef union { /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ - uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ - uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ - uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ - uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ - uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ - uint32_t :21; /*!< bit: 10..30 Reserved */ - uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ + uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ + uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ + uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ + uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ + uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ + uint32_t :21; /*!< bit: 10..30 Reserved */ + uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } MTB_MASTER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -114,13 +114,13 @@ typedef union { /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ - uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ + uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } MTB_FLOW_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -139,7 +139,7 @@ typedef union { /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_BASE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -149,7 +149,7 @@ typedef union { /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_ITCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -159,7 +159,7 @@ typedef union { /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CLAIMSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -169,7 +169,7 @@ typedef union { /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CLAIMCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -179,7 +179,7 @@ typedef union { /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_LOCKACCESS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -189,7 +189,7 @@ typedef union { /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_LOCKSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -199,7 +199,7 @@ typedef union { /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_AUTHSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -209,7 +209,7 @@ typedef union { /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_DEVARCH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -219,7 +219,7 @@ typedef union { /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_DEVID_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -229,7 +229,7 @@ typedef union { /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_DEVTYPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -239,7 +239,7 @@ typedef union { /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID4_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -249,7 +249,7 @@ typedef union { /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID5_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -259,7 +259,7 @@ typedef union { /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID6_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -269,7 +269,7 @@ typedef union { /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID7_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -279,7 +279,7 @@ typedef union { /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -289,7 +289,7 @@ typedef union { /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -299,7 +299,7 @@ typedef union { /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -309,7 +309,7 @@ typedef union { /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_PID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -319,7 +319,7 @@ typedef union { /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID0_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -329,7 +329,7 @@ typedef union { /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID1_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -339,7 +339,7 @@ typedef union { /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID2_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -349,7 +349,7 @@ typedef union { /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint32_t reg; /*!< Type used for register access */ + uint32_t reg; /*!< Type used for register access */ } MTB_CID3_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -359,35 +359,35 @@ typedef union { /** \brief MTB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ - __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ - __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ - __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ - RoReg8 Reserved1[0xEF0]; - __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ - RoReg8 Reserved2[0x9C]; - __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ - __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ - RoReg8 Reserved3[0x8]; - __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ - __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ - __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ - __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ - RoReg8 Reserved4[0x8]; - __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ - __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ - __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */ - __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */ - __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */ - __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */ - __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */ - __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */ - __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */ - __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */ - __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */ - __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */ - __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */ - __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */ + __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ + __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ + __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ + __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ + RoReg8 Reserved1[0xEF0]; + __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ + RoReg8 Reserved2[0x9C]; + __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ + __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ + RoReg8 Reserved3[0x8]; + __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ + __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ + __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ + __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ + RoReg8 Reserved4[0x8]; + __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ + __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ + __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */ + __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */ + __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */ + __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */ + __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */ + __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */ + __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */ + __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */ + __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */ + __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */ + __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */ + __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */ } Mtb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h similarity index 83% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h index 3398fd9eef..e014da1069 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h @@ -56,12 +56,12 @@ /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t CMD:7; /*!< bit: 0.. 6 Command */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t CMD:7; /*!< bit: 0.. 6 Command */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } NVMCTRL_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -107,18 +107,18 @@ typedef union { /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t MANW:1; /*!< bit: 7 Manual Write */ - uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ - uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t MANW:1; /*!< bit: 7 Manual Write */ + uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ + uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } NVMCTRL_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -161,12 +161,12 @@ typedef union { /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ - uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ + uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } NVMCTRL_PARAM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -200,12 +200,12 @@ typedef union { /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ + uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } NVMCTRL_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -221,12 +221,12 @@ typedef union { /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ - uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ + uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } NVMCTRL_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -242,12 +242,12 @@ typedef union { /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t READY:1; /*!< bit: 0 NVM Ready */ - __I uint8_t ERROR:1; /*!< bit: 1 Error */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t READY:1; /*!< bit: 0 NVM Ready */ + __I uint8_t ERROR:1; /*!< bit: 1 Error */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } NVMCTRL_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -263,17 +263,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ - uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ - uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ - uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ - uint16_t NVME:1; /*!< bit: 4 NVM Error */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t SB:1; /*!< bit: 8 Security Bit Status */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ + uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ + uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ + uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ + uint16_t NVME:1; /*!< bit: 4 NVM Error */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t SB:1; /*!< bit: 8 Security Bit Status */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } NVMCTRL_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -297,11 +297,11 @@ typedef union { /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } NVMCTRL_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -316,10 +316,10 @@ typedef union { /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } NVMCTRL_LOCK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -333,20 +333,20 @@ typedef union { /** \brief NVMCTRL APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - RoReg8 Reserved1[0x2]; - __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ - __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ - __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - RoReg8 Reserved2[0x3]; - __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ - RoReg8 Reserved3[0x3]; - __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x3]; - __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ - RoReg8 Reserved5[0x2]; - __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ - __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ + __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + RoReg8 Reserved1[0x2]; + __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ + __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ + __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + RoReg8 Reserved2[0x3]; + __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ + RoReg8 Reserved3[0x3]; + __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x3]; + __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ + RoReg8 Reserved5[0x2]; + __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ + __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ } Nvmctrl; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define SECTION_NVMCTRL_CAL diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h similarity index 80% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h index a8f5274685..9a4bc89e6d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h @@ -56,11 +56,11 @@ /* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PAC_WPCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -75,11 +75,11 @@ typedef union { /* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PAC_WPSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -94,8 +94,8 @@ typedef union { /** \brief PAC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ - __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ + __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ + __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ } Pac; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h similarity index 71% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h index 4c837c5ba2..4832dc43a4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h @@ -56,7 +56,7 @@ /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - uint8_t reg; /*!< Type used for register access */ + uint8_t reg; /*!< Type used for register access */ } PM_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -68,11 +68,11 @@ typedef union { /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_SLEEP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -93,11 +93,11 @@ typedef union { /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_CPUSEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -128,11 +128,11 @@ typedef union { /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_APBASEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -163,11 +163,11 @@ typedef union { /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_APBBSEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -198,11 +198,11 @@ typedef union { /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_APBCSEL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -233,17 +233,17 @@ typedef union { /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ - uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ - uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ - uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ - uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ - uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ - uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ + uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ + uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ + uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ + uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ + uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ + uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_AHBMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -269,17 +269,17 @@ typedef union { /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ - uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ - uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ - uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ - uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ - uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ - uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ + uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ + uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ + uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ + uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ + uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ + uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_APBAMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -305,17 +305,17 @@ typedef union { /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ - uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ - uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ - uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ - uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ - uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ - uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ + uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ + uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ + uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ + uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ + uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ + uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_APBBMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -341,31 +341,31 @@ typedef union { /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ - uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ - uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ - uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ - uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ - uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ - uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ - uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ - uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ - uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ - uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ - uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ - uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ - uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ - uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ - uint32_t :1; /*!< bit: 20 Reserved */ - uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ + uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ + uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ + uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ + uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ + uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ + uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ + uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ + uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ + uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ + uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ + uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ + uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ + uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ + uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ + uint32_t :1; /*!< bit: 20 Reserved */ + uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PM_APBCMASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -413,11 +413,11 @@ typedef union { /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -431,11 +431,11 @@ typedef union { /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -449,11 +449,11 @@ typedef union { /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ - __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ + __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -467,17 +467,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t POR:1; /*!< bit: 0 Power On Reset */ - uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ - uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EXT:1; /*!< bit: 4 External Reset */ - uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ - uint8_t SYST:1; /*!< bit: 6 System Reset Request */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t POR:1; /*!< bit: 0 Power On Reset */ + uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ + uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EXT:1; /*!< bit: 4 External Reset */ + uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ + uint8_t SYST:1; /*!< bit: 6 System Reset Request */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PM_RCAUSE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -501,24 +501,24 @@ typedef union { /** \brief PM hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ - __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ - RoReg8 Reserved1[0x6]; - __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ - __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ - __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ - __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ - RoReg8 Reserved2[0x8]; - __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ - __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ - __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ - __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ - RoReg8 Reserved3[0x10]; - __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ - __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ - __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ + __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ + __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ + RoReg8 Reserved1[0x6]; + __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ + __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ + __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ + __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ + RoReg8 Reserved2[0x8]; + __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ + __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ + __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ + __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ + RoReg8 Reserved3[0x10]; + __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ + __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ + __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x1]; + __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ } Pm; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h similarity index 73% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h index 23187d9291..344e41bc75 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h @@ -56,10 +56,10 @@ /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -74,10 +74,10 @@ typedef union { /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIRCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -92,10 +92,10 @@ typedef union { /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIRSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -110,10 +110,10 @@ typedef union { /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_DIRTGL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -128,10 +128,10 @@ typedef union { /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -146,10 +146,10 @@ typedef union { /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUTCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -164,10 +164,10 @@ typedef union { /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUTSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -182,10 +182,10 @@ typedef union { /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_OUTTGL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -200,10 +200,10 @@ typedef union { /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_IN_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -218,10 +218,10 @@ typedef union { /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -236,21 +236,21 @@ typedef union { /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ - uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ - uint32_t INEN:1; /*!< bit: 17 Input Enable */ - uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ - uint32_t :3; /*!< bit: 19..21 Reserved */ - uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ - uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ - uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ + uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ + uint32_t INEN:1; /*!< bit: 17 Input Enable */ + uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ + uint32_t :3; /*!< bit: 19..21 Reserved */ + uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ + uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ + uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } PORT_WRCONFIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -282,11 +282,11 @@ typedef union { /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */ - uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */ + uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PORT_PMUX_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -336,15 +336,15 @@ typedef union { /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ - uint8_t INEN:1; /*!< bit: 1 Input Enable */ - uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ + uint8_t INEN:1; /*!< bit: 1 Input Enable */ + uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } PORT_PINCFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -364,28 +364,28 @@ typedef union { /** \brief PortGroup hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ - __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ - __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ - __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ - __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ - __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ - __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ - __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ - __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ - __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ - __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ - RoReg8 Reserved1[0x4]; - __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ - __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ - RoReg8 Reserved2[0x20]; + __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ + __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ + __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ + __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ + __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ + __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ + __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ + __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ + __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ + __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ + __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ + RoReg8 Reserved1[0x4]; + __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ + __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ + RoReg8 Reserved2[0x20]; } PortGroup; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief PORT hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ + PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ } Port; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define SECTION_PORT_IOBUS diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h similarity index 82% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h index c260bb52b6..d18226b389 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h @@ -56,16 +56,16 @@ /* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */ - uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */ - uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */ - uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */ - uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */ - uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */ + uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */ + uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */ + uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */ + uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */ + uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RFCTRL_FECFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -95,7 +95,7 @@ typedef union { /** \brief RFCTRL hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */ + __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */ } Rfctrl; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h similarity index 69% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h index 9e657ccd9b..6c1e8c48c1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h @@ -56,16 +56,16 @@ /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :3; /*!< bit: 4.. 6 Reserved */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :3; /*!< bit: 4.. 6 Reserved */ + uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE0_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -117,15 +117,15 @@ typedef union { /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -175,17 +175,17 @@ typedef union { /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ - uint16_t :2; /*!< bit: 4.. 5 Reserved */ - uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ - uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ - uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ + uint16_t :2; /*!< bit: 4.. 5 Reserved */ + uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ + uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ + uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE2_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -239,13 +239,13 @@ typedef union { /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ - uint16_t :8; /*!< bit: 6..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ + uint16_t :8; /*!< bit: 6..13 Reserved */ + uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ + uint16_t RREQ:1; /*!< bit: 15 Read Request */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_READREQ_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -264,25 +264,25 @@ typedef union { /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE0_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -320,26 +320,26 @@ typedef union { /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ - uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ - uint16_t :5; /*!< bit: 10..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ + uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ + uint16_t :5; /*!< bit: 10..14 Reserved */ + uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -379,25 +379,25 @@ typedef union { /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ - uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ - uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ - uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ - uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ - uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ - uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ - uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ - uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ - uint16_t :6; /*!< bit: 9..14 Reserved */ - uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ - uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ + uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ + uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ + uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ + uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ + uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ + uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ + uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ + uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ + uint16_t :6; /*!< bit: 9..14 Reserved */ + uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ + uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE2_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -435,17 +435,17 @@ typedef union { /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE0_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -466,18 +466,18 @@ typedef union { /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE1_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -500,17 +500,17 @@ typedef union { /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -531,17 +531,17 @@ typedef union { /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE0_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -562,18 +562,18 @@ typedef union { /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ - uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ + uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE1_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -596,17 +596,17 @@ typedef union { /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ - uint8_t :5; /*!< bit: 1.. 5 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ - uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ + uint8_t :5; /*!< bit: 1.. 5 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ + uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -627,17 +627,17 @@ typedef union { /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ - __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - __I uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t CMP:1; /*!< bit: 0 Compare x */ - __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ + __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ + __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ + __I uint8_t OVF:1; /*!< bit: 7 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t CMP:1; /*!< bit: 0 Compare x */ + __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE0_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -658,18 +658,18 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ - __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ - __I uint8_t :4; /*!< bit: 2.. 5 Reserved */ - __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - __I uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ + __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ + __I uint8_t :4; /*!< bit: 2.. 5 Reserved */ + __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ + __I uint8_t OVF:1; /*!< bit: 7 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE1_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -692,17 +692,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ - __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ - __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ - __I uint8_t OVF:1; /*!< bit: 7 Overflow */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */ - __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ + __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ + __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ + __I uint8_t OVF:1; /*!< bit: 7 Overflow */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */ + __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -723,11 +723,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -741,11 +741,11 @@ typedef union { /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -759,11 +759,11 @@ typedef union { /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ - uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ + uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_FREQCORR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -780,10 +780,10 @@ typedef union { /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE0_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -798,10 +798,10 @@ typedef union { /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -816,15 +816,15 @@ typedef union { /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ + uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ + uint32_t HOUR:5; /*!< bit: 12..16 Hour */ + uint32_t DAY:5; /*!< bit: 17..21 Day */ + uint32_t MONTH:4; /*!< bit: 22..25 Month */ + uint32_t YEAR:6; /*!< bit: 26..31 Year */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE2_CLOCK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -856,10 +856,10 @@ typedef union { /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PER:16; /*!< bit: 0..15 Counter Period */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PER:16; /*!< bit: 0..15 Counter Period */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -874,10 +874,10 @@ typedef union { /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE0_COMP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -892,10 +892,10 @@ typedef union { /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } RTC_MODE1_COMP_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -910,15 +910,15 @@ typedef union { /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ - uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ - uint32_t HOUR:5; /*!< bit: 12..16 Hour */ - uint32_t DAY:5; /*!< bit: 17..21 Day */ - uint32_t MONTH:4; /*!< bit: 22..25 Month */ - uint32_t YEAR:6; /*!< bit: 26..31 Year */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ + uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ + uint32_t HOUR:5; /*!< bit: 12..16 Hour */ + uint32_t DAY:5; /*!< bit: 17..21 Day */ + uint32_t MONTH:4; /*!< bit: 22..25 Month */ + uint32_t YEAR:6; /*!< bit: 26..31 Year */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } RTC_MODE2_ALARM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -948,11 +948,11 @@ typedef union { /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } RTC_MODE2_MASK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -981,79 +981,79 @@ typedef union { /** \brief RtcMode2Alarm hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ - __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ - RoReg8 Reserved1[0x3]; + __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ + __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ + RoReg8 Reserved1[0x3]; } RtcMode2Alarm; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief RTC_MODE0 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 32-bit Counter with Single 32-bit Compare */ - __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ - __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ - __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ - __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ + __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ + __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ + __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ + __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ + __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ + RoReg8 Reserved2[0x3]; + __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ + RoReg8 Reserved3[0x4]; + __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ } RtcMode0; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief RTC_MODE1 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 16-bit Counter with Two 16-bit Compares */ - __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ - __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ - __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ - __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ - RoReg8 Reserved3[0x2]; - __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ - RoReg8 Reserved4[0x2]; - __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ + __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ + __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ + __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ + __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ + __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ + RoReg8 Reserved2[0x3]; + __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ + RoReg8 Reserved3[0x2]; + __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ + RoReg8 Reserved4[0x2]; + __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ } RtcMode1; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief RTC_MODE2 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* Clock/Calendar with Alarm */ - __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ - __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ - __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ - __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ - __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ - __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ - __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ - RoReg8 Reserved2[0x3]; - __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ - RoReg8 Reserved3[0x4]; - RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ + __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ + __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ + __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ + __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ + __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ + __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ + __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ + RoReg8 Reserved2[0x3]; + __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ + RoReg8 Reserved3[0x4]; + RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ } RtcMode2; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ - RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ - RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ + RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ + RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ + RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ } Rtc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h similarity index 66% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h index f1271ff1ac..055938af59 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sercom.h @@ -56,26 +56,26 @@ /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -127,26 +127,26 @@ typedef union { /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ - uint32_t :3; /*!< bit: 17..19 Reserved */ - uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ - uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ - uint32_t :1; /*!< bit: 26 Reserved */ - uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t :2; /*!< bit: 28..29 Reserved */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -193,25 +193,25 @@ typedef union { /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :7; /*!< bit: 9..15 Reserved */ - uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :7; /*!< bit: 9..15 Reserved */ + uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -261,26 +261,26 @@ typedef union { /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ - uint32_t :2; /*!< bit: 5.. 6 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ - uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ - uint32_t :4; /*!< bit: 9..12 Reserved */ - uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ - uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ - uint32_t :2; /*!< bit: 18..19 Reserved */ - uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ - uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ - uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ - uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ - uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ - uint32_t DORD:1; /*!< bit: 30 Data Order */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :4; /*!< bit: 9..12 Reserved */ + uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ + uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ + uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_USART_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -336,16 +336,16 @@ typedef union { /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -366,18 +366,18 @@ typedef union { /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ - uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ - uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ - uint32_t :3; /*!< bit: 11..13 Reserved */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t CMD:2; /*!< bit: 16..17 Command */ - uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ - uint32_t :13; /*!< bit: 19..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ + uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ + uint32_t :3; /*!< bit: 11..13 Reserved */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -403,20 +403,20 @@ typedef union { /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ - uint32_t :2; /*!< bit: 7.. 8 Reserved */ - uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ - uint32_t :3; /*!< bit: 10..12 Reserved */ - uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ - uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ + uint32_t :2; /*!< bit: 7.. 8 Reserved */ + uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ + uint32_t :3; /*!< bit: 10..12 Reserved */ + uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -442,22 +442,22 @@ typedef union { /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ - uint32_t :3; /*!< bit: 3.. 5 Reserved */ - uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ - uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ - uint32_t ENC:1; /*!< bit: 10 Encoding Format */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ - uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ + uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ + uint32_t ENC:1; /*!< bit: 10 Encoding Format */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_USART_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -486,13 +486,13 @@ typedef union { /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ - uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ - uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ + uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ + uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_BAUD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -516,10 +516,10 @@ typedef union { /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_BAUD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -534,21 +534,21 @@ typedef union { /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } bit; /*!< Structure used for bit access */ - struct { // FRAC mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRAC; /*!< Structure used for FRAC */ - struct { // FRACFP mode - uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ - uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ - } FRACFP; /*!< Structure used for FRACFP */ - struct { // USARTFP mode - uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ - } USARTFP; /*!< Structure used for USARTFP */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + struct { // FRAC mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRAC; /*!< Structure used for FRAC */ + struct { // FRACFP mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRACFP; /*!< Structure used for FRACFP */ + struct { // USARTFP mode + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } USARTFP; /*!< Structure used for USARTFP */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_USART_BAUD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -587,10 +587,10 @@ typedef union { /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_RXPL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -605,13 +605,13 @@ typedef union { /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -629,14 +629,14 @@ typedef union { /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -656,15 +656,15 @@ typedef union { /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -686,17 +686,17 @@ typedef union { /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -722,13 +722,13 @@ typedef union { /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ - uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -746,14 +746,14 @@ typedef union { /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ - uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ - uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -773,15 +773,15 @@ typedef union { /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -803,17 +803,17 @@ typedef union { /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ - uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ - uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ - uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ - uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ - uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -839,13 +839,13 @@ typedef union { /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ - __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ - __I uint8_t :5; /*!< bit: 2.. 6 Reserved */ - __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ + __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ + __I uint8_t :5; /*!< bit: 2.. 6 Reserved */ + __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -863,14 +863,14 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ - __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ - __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ - __I uint8_t :4; /*!< bit: 3.. 6 Reserved */ - __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ + __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ + __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ + __I uint8_t :4; /*!< bit: 3.. 6 Reserved */ + __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -890,15 +890,15 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ - __I uint8_t :3; /*!< bit: 4.. 6 Reserved */ - __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ + __I uint8_t :3; /*!< bit: 4.. 6 Reserved */ + __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -920,17 +920,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ - __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ - __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ - __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ - __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ - __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ - __I uint8_t :1; /*!< bit: 6 Reserved */ - __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ + __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ + __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ + __I uint8_t :1; /*!< bit: 6 Reserved */ + __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -956,20 +956,20 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t LENERR:1; /*!< bit: 10 Length Error */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t LENERR:1; /*!< bit: 10 Length Error */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_I2CM_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1000,21 +1000,21 @@ typedef union { /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ - uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ - uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ - uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ - uint16_t SR:1; /*!< bit: 4 Repeated Start */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ - uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ - uint16_t :1; /*!< bit: 8 Reserved */ - uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ - uint16_t HS:1; /*!< bit: 10 High Speed */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ + uint16_t SR:1; /*!< bit: 4 Repeated Start */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t :1; /*!< bit: 8 Reserved */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t HS:1; /*!< bit: 10 High Speed */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_I2CS_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1044,12 +1044,12 @@ typedef union { /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t :13; /*!< bit: 3..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t :13; /*!< bit: 3..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_SPI_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1063,16 +1063,16 @@ typedef union { /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PERR:1; /*!< bit: 0 Parity Error */ - uint16_t FERR:1; /*!< bit: 1 Frame Error */ - uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ - uint16_t CTS:1; /*!< bit: 3 Clear To Send */ - uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ - uint16_t COLL:1; /*!< bit: 5 Collision Detected */ - uint16_t :10; /*!< bit: 6..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PERR:1; /*!< bit: 0 Parity Error */ + uint16_t FERR:1; /*!< bit: 1 Frame Error */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t CTS:1; /*!< bit: 3 Clear To Send */ + uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ + uint16_t COLL:1; /*!< bit: 5 Collision Detected */ + uint16_t :10; /*!< bit: 6..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_USART_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1096,13 +1096,13 @@ typedef union { /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1120,12 +1120,12 @@ typedef union { /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1141,13 +1141,13 @@ typedef union { /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1165,13 +1165,13 @@ typedef union { /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_USART_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1189,16 +1189,16 @@ typedef union { /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ - uint32_t :2; /*!< bit: 11..12 Reserved */ - uint32_t LENEN:1; /*!< bit: 13 Length Enable */ - uint32_t HS:1; /*!< bit: 14 High Speed Mode */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t LEN:8; /*!< bit: 16..23 Length */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t LENEN:1; /*!< bit: 13 Length Enable */ + uint32_t HS:1; /*!< bit: 14 High Speed Mode */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t LEN:8; /*!< bit: 16..23 Length */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CM_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1222,16 +1222,16 @@ typedef union { /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ - uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ - uint32_t :4; /*!< bit: 11..14 Reserved */ - uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ - uint32_t :1; /*!< bit: 16 Reserved */ - uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ + uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ + uint32_t :4; /*!< bit: 11..14 Reserved */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_I2CS_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1253,13 +1253,13 @@ typedef union { /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ - uint32_t :8; /*!< bit: 8..15 Reserved */ - uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1277,10 +1277,10 @@ typedef union { /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1295,10 +1295,10 @@ typedef union { /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CS_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1313,11 +1313,11 @@ typedef union { /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint32_t :23; /*!< bit: 9..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint32_t :23; /*!< bit: 9..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1332,11 +1332,11 @@ typedef union { /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ - uint16_t :7; /*!< bit: 9..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SERCOM_USART_DATA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1351,11 +1351,11 @@ typedef union { /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_I2CM_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1369,11 +1369,11 @@ typedef union { /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_SPI_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1387,11 +1387,11 @@ typedef union { /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SERCOM_USART_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1405,101 +1405,101 @@ typedef union { /** \brief SERCOM_I2CM hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* I2C Master Mode */ - __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ - __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ - RoReg8 Reserved2[0x4]; - __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ - __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ - __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ - RoReg8 Reserved7[0x7]; - __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ + __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ + __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ + RoReg8 Reserved2[0x4]; + __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ + __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ + __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ + RoReg8 Reserved7[0x7]; + __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ } SercomI2cm; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief SERCOM_I2CS hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* I2C Slave Mode */ - __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ - __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ - RoReg8 Reserved1[0xC]; - __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ - RoReg8 Reserved2[0x1]; - __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ - __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ - RoReg8 Reserved5[0x4]; - __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ - __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ + __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ + __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ + RoReg8 Reserved1[0xC]; + __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ + RoReg8 Reserved2[0x1]; + __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ + __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ + RoReg8 Reserved5[0x4]; + __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ + __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ } SercomI2cs; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief SERCOM_SPI hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* SPI Mode */ - __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ - __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ - RoReg8 Reserved2[0x7]; - __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ - __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ - RoReg8 Reserved6[0x4]; - __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ - __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ - RoReg8 Reserved7[0x4]; - __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ + __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ + __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ + RoReg8 Reserved2[0x7]; + __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ + __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ + __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ + RoReg8 Reserved7[0x4]; + __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ } SercomSpi; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief SERCOM_USART hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USART Mode */ - __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ - __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ - RoReg8 Reserved1[0x4]; - __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ - __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ - RoReg8 Reserved2[0x5]; - __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ - RoReg8 Reserved3[0x1]; - __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ - RoReg8 Reserved4[0x1]; - __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ - RoReg8 Reserved5[0x1]; - __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ - __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ - RoReg8 Reserved6[0x8]; - __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ - RoReg8 Reserved7[0x6]; - __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ + __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ + __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ + __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ + RoReg8 Reserved2[0x5]; + __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ + __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ + RoReg8 Reserved6[0x8]; + __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ + RoReg8 Reserved7[0x6]; + __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ } SercomUsart; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ - SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ - SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ - SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ + SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ + SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ + SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ + SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ } Sercom; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h similarity index 69% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h index 92791c6481..52eb8bddd1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_sysctrl.h @@ -56,26 +56,26 @@ /* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -117,26 +117,26 @@ typedef union { /* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -178,26 +178,26 @@ typedef union { /* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - __I uint32_t :3; /*!< bit: 12..14 Reserved */ - __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - __I uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ + __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ + __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ + __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ + __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ + __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ + __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ + __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ + __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ + __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ + __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ + __I uint32_t :3; /*!< bit: 12..14 Reserved */ + __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ + __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ + __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ + __I uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -239,26 +239,26 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ - uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ - uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ - uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ - uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ - uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ - uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ - uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ - uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ - uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ - uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ - uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ - uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ - uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ - uint32_t :14; /*!< bit: 18..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_PCLKSR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -300,18 +300,18 @@ typedef union { /* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t :3; /*!< bit: 3.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ - uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ - uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint16_t :3; /*!< bit: 3.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ + uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ + uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_XOSC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -349,21 +349,21 @@ typedef union { /* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ - uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ - uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ - uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ + uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ + uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_XOSC32K_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -394,22 +394,22 @@ typedef union { /* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ - uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ - uint32_t :2; /*!< bit: 4.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ + uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ + uint32_t :2; /*!< bit: 4.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_OSC32K_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -439,12 +439,12 @@ typedef union { /* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_OSCULP32K_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -461,19 +461,19 @@ typedef union { /* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ - uint32_t :4; /*!< bit: 2.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ - uint32_t :6; /*!< bit: 10..15 Reserved */ - uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ - uint32_t :2; /*!< bit: 28..29 Reserved */ - uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t :4; /*!< bit: 2.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ + uint32_t :2; /*!< bit: 28..29 Reserved */ + uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_OSC8M_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -516,22 +516,22 @@ typedef union { /* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ - uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ - uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ - uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ - uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ - uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ - uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ - uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ + uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ + uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ + uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ + uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ + uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ + uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ + uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -565,12 +565,12 @@ typedef union { /* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ - uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ - uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ + uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ + uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLVAL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -591,12 +591,12 @@ typedef union { /* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ - uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ - uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ + uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ + uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLMUL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -617,11 +617,11 @@ typedef union { /* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t READREQ:1; /*!< bit: 7 Read Request */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t READREQ:1; /*!< bit: 7 Read Request */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_DFLLSYNC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -635,22 +635,22 @@ typedef union { /* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t HYST:1; /*!< bit: 2 Hysteresis */ - uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MODE:1; /*!< bit: 8 Operation Mode */ - uint32_t CEN:1; /*!< bit: 9 Clock Enable */ - uint32_t :2; /*!< bit: 10..11 Reserved */ - uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ - uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t HYST:1; /*!< bit: 2 Hysteresis */ + uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MODE:1; /*!< bit: 8 Operation Mode */ + uint32_t CEN:1; /*!< bit: 9 Clock Enable */ + uint32_t :2; /*!< bit: 10..11 Reserved */ + uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ + uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_BOD33_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -719,14 +719,14 @@ typedef union { /* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :6; /*!< bit: 0.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t :6; /*!< bit: 7..12 Reserved */ - uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :6; /*!< bit: 0.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t :6; /*!< bit: 7..12 Reserved */ + uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } SYSCTRL_VREG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -742,15 +742,15 @@ typedef union { /* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ - uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ - uint32_t :13; /*!< bit: 3..15 Reserved */ - uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ + uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ + uint32_t :13; /*!< bit: 3..15 Reserved */ + uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_VREF_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -769,14 +769,14 @@ typedef union { /* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -794,13 +794,13 @@ typedef union { /* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLRATIO_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -818,20 +818,20 @@ typedef union { /* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ - uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ - uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ - uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ + uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ + uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ + uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -885,14 +885,14 @@ typedef union { /* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ - uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ - uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ - uint8_t DIV:1; /*!< bit: 3 Divider Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ + uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ + uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ + uint8_t DIV:1; /*!< bit: 3 Divider Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } SYSCTRL_DPLLSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -912,34 +912,34 @@ typedef union { /** \brief SYSCTRL hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ - __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ - __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ - __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ - __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ - RoReg8 Reserved1[0x2]; - __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ - RoReg8 Reserved2[0x2]; - __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ - __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ - RoReg8 Reserved3[0x3]; - __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ - __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ - RoReg8 Reserved4[0x2]; - __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ - __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ - __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ - RoReg8 Reserved5[0x3]; - __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ - RoReg8 Reserved6[0x4]; - __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ - RoReg8 Reserved7[0x2]; - __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ - __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ - RoReg8 Reserved8[0x3]; - __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ - __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ - __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ + __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ + __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ + __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ + __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ + __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ + RoReg8 Reserved1[0x2]; + __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ + RoReg8 Reserved2[0x2]; + __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ + __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ + RoReg8 Reserved3[0x3]; + __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ + __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ + RoReg8 Reserved4[0x2]; + __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ + __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ + __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ + RoReg8 Reserved5[0x3]; + __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ + RoReg8 Reserved6[0x4]; + __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ + RoReg8 Reserved7[0x2]; + __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ + __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ + RoReg8 Reserved8[0x3]; + __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ + __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ + __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ } Sysctrl; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h similarity index 64% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h index e2e3700f95..44f2f706e2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tc.h @@ -56,19 +56,19 @@ /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -134,13 +134,13 @@ typedef union { /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ - uint16_t :9; /*!< bit: 5..13 Reserved */ - uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ - uint16_t RREQ:1; /*!< bit: 15 Read Request */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ + uint16_t :9; /*!< bit: 5..13 Reserved */ + uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ + uint16_t RREQ:1; /*!< bit: 15 Read Request */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_READREQ_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -159,14 +159,14 @@ typedef union { /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t CMD:2; /*!< bit: 6.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_CTRLBCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -191,14 +191,14 @@ typedef union { /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t :3; /*!< bit: 3.. 5 Reserved */ - uint8_t CMD:2; /*!< bit: 6.. 7 Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t CMD:2; /*!< bit: 6.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_CTRLBSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -223,21 +223,21 @@ typedef union { /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ - uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ - uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ + uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ + uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_CTRLC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -263,11 +263,11 @@ typedef union { /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -281,24 +281,24 @@ typedef union { /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ - uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ - uint16_t :3; /*!< bit: 9..11 Reserved */ - uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ - uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :12; /*!< bit: 0..11 Reserved */ - uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ + uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ + uint16_t :3; /*!< bit: 9..11 Reserved */ + uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ + uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :12; /*!< bit: 0..11 Reserved */ + uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -338,21 +338,21 @@ typedef union { /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -377,21 +377,21 @@ typedef union { /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ - uint8_t :1; /*!< bit: 2 Reserved */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ - uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -416,21 +416,21 @@ typedef union { /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t OVF:1; /*!< bit: 0 Overflow */ - __I uint8_t ERR:1; /*!< bit: 1 Error */ - __I uint8_t :1; /*!< bit: 2 Reserved */ - __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ - __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ - __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t :4; /*!< bit: 0.. 3 Reserved */ - __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ - __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t OVF:1; /*!< bit: 0 Overflow */ + __I uint8_t ERR:1; /*!< bit: 1 Error */ + __I uint8_t :1; /*!< bit: 2 Reserved */ + __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ + __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ + __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t :4; /*!< bit: 0.. 3 Reserved */ + __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ + __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } TC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -455,14 +455,14 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :3; /*!< bit: 0.. 2 Reserved */ - uint8_t STOP:1; /*!< bit: 3 Stop */ - uint8_t SLAVE:1; /*!< bit: 4 Slave */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :3; /*!< bit: 0.. 2 Reserved */ + uint8_t STOP:1; /*!< bit: 3 Stop */ + uint8_t SLAVE:1; /*!< bit: 4 Slave */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -480,10 +480,10 @@ typedef union { /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_COUNT16_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -498,10 +498,10 @@ typedef union { /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TC_COUNT32_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -516,10 +516,10 @@ typedef union { /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_COUNT8_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -534,10 +534,10 @@ typedef union { /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_COUNT8_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -552,10 +552,10 @@ typedef union { /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } TC_COUNT16_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -570,10 +570,10 @@ typedef union { /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TC_COUNT32_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -588,10 +588,10 @@ typedef union { /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TC_COUNT8_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -606,76 +606,76 @@ typedef union { /** \brief TC_COUNT8 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 8-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ - RoReg8 Reserved3[0x3]; - __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ - RoReg8 Reserved4[0x3]; - __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ + RoReg8 Reserved3[0x3]; + __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ + RoReg8 Reserved4[0x3]; + __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ } TcCount8; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief TC_COUNT16 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 16-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ - RoReg8 Reserved3[0x6]; - __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ + RoReg8 Reserved3[0x6]; + __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ } TcCount16; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief TC_COUNT32 hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* 32-bit Counter Mode */ - __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ - __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ - RoReg8 Reserved1[0x1]; - __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x1]; - __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ - __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ - __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ - __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ - __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ - __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ - RoReg8 Reserved3[0x4]; - __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ + RoReg8 Reserved3[0x4]; + __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ } TcCount32; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ - TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ - TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ + TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ + TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ + TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ } Tc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h similarity index 68% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h index 2a8ecd3c57..8274702497 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_tcc.h @@ -56,29 +56,29 @@ /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t :3; /*!< bit: 2.. 4 Reserved */ - uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ - uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ - uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ - uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ - uint32_t :9; /*!< bit: 15..23 Reserved */ - uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ - uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ - uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ - uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :24; /*!< bit: 0..23 Reserved */ - uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t :3; /*!< bit: 2.. 4 Reserved */ + uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ + uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ + uint32_t :9; /*!< bit: 15..23 Reserved */ + uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ + uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ + uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ + uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :24; /*!< bit: 0..23 Reserved */ + uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -148,14 +148,14 @@ typedef union { /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_CTRLBCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -197,14 +197,14 @@ typedef union { /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DIR:1; /*!< bit: 0 Counter Direction */ - uint8_t LUPD:1; /*!< bit: 1 Lock Update */ - uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ - uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ - uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_CTRLBSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -246,37 +246,37 @@ typedef union { /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ - uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ - uint32_t STATUS:1; /*!< bit: 3 Status Busy */ - uint32_t COUNT:1; /*!< bit: 4 Count Busy */ - uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ - uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ - uint32_t PER:1; /*!< bit: 7 Period busy */ - uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ - uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ - uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ - uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ - uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ - uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ - uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ - uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ - uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ - uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ - uint32_t :7; /*!< bit: 12..18 Reserved */ - uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ + uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ + uint32_t STATUS:1; /*!< bit: 3 Status Busy */ + uint32_t COUNT:1; /*!< bit: 4 Count Busy */ + uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ + uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ + uint32_t PER:1; /*!< bit: 7 Period busy */ + uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ + uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ + uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ + uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ + uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ + uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ + uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ + uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ + uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ + uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ + uint32_t :7; /*!< bit: 12..18 Reserved */ + uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -332,22 +332,22 @@ typedef union { /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_FCTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -432,22 +432,22 @@ typedef union { /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ - uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ - uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ - uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ - uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ - uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ - uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ - uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_FCTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -532,23 +532,23 @@ typedef union { /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ - uint32_t :6; /*!< bit: 2.. 7 Reserved */ - uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ - uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ - uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ - uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ - uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ + uint32_t :6; /*!< bit: 2.. 7 Reserved */ + uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ + uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ + uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ + uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ + uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WEXCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -580,41 +580,41 @@ typedef union { /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ - uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ - uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ - uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ - uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ - uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ - uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ - uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ - uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ - uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ - uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ - uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ - uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ - uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ - uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ - uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ - uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ - uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ - uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ - uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ - uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ - uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ - uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ - uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ - uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ - uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ - uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ - uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ + uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ + uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ + uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ + uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ + uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ + uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ + uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ + uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ + uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ + uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ + uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ + uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ + uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ + uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ + uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ + uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ + uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ + uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ + uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ + uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ + uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ + uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ + uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ + uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ + uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ + uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ + uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_DRVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -689,13 +689,13 @@ typedef union { /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } TCC_DBGCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -711,39 +711,39 @@ typedef union { /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ - uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ - uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ - uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ - uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ - uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ - uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ - uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ - uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ - uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ - uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ - uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ - uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ - uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ - uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ - uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :12; /*!< bit: 0..11 Reserved */ - uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ - uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ - uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ + uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ + uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ + uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ + uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ + uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ + uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ + uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ + uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ + uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ + uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ + uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ + uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ + uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ + uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ + uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :12; /*!< bit: 0..11 Reserved */ + uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ + uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ + uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_EVCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -844,29 +844,29 @@ typedef union { /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -907,29 +907,29 @@ typedef union { /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ - uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ - uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ - uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ - uint32_t :7; /*!< bit: 4..10 Reserved */ - uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ - uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ - uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ - uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ - uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -970,29 +970,29 @@ typedef union { /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint32_t OVF:1; /*!< bit: 0 Overflow */ - __I uint32_t TRG:1; /*!< bit: 1 Retrigger */ - __I uint32_t CNT:1; /*!< bit: 2 Counter */ - __I uint32_t ERR:1; /*!< bit: 3 Error */ - __I uint32_t :7; /*!< bit: 4..10 Reserved */ - __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ - __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ - __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ - __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ - __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ - __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ - __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ - __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ - __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ - __I uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint32_t :16; /*!< bit: 0..15 Reserved */ - __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ - __I uint32_t :12; /*!< bit: 20..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + __I uint32_t OVF:1; /*!< bit: 0 Overflow */ + __I uint32_t TRG:1; /*!< bit: 1 Retrigger */ + __I uint32_t CNT:1; /*!< bit: 2 Counter */ + __I uint32_t ERR:1; /*!< bit: 3 Error */ + __I uint32_t :7; /*!< bit: 4..10 Reserved */ + __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ + __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ + __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ + __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ + __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ + __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ + __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ + __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ + __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ + __I uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint32_t :16; /*!< bit: 0..15 Reserved */ + __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ + __I uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1033,42 +1033,42 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t STOP:1; /*!< bit: 0 Stop */ - uint32_t IDX:1; /*!< bit: 1 Ramp */ - uint32_t :1; /*!< bit: 2 Reserved */ - uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ - uint32_t SLAVE:1; /*!< bit: 4 Slave */ - uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ - uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ - uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ - uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ - uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ - uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ - uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ - uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ - uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ - uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ - uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ - uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ - uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ - uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ - uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ - uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ - uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ - uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t STOP:1; /*!< bit: 0 Stop */ + uint32_t IDX:1; /*!< bit: 1 Ramp */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ + uint32_t SLAVE:1; /*!< bit: 4 Slave */ + uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ + uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ + uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ + uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ + uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ + uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ + uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ + uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ + uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ + uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ + uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ + uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ + uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ + uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1132,26 +1132,26 @@ typedef union { /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t :5; /*!< bit: 0.. 4 Reserved */ - uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t :6; /*!< bit: 0.. 5 Reserved */ - uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t :6; /*!< bit: 0.. 5 Reserved */ + uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_COUNT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1184,29 +1184,29 @@ typedef union { /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ - uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ - uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ - uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ - uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ - uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ - uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ - uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ - uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ - uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ - uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ - uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ - uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ - uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ - uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ - uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ - uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ + uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ + uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ + uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ + uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ + uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ + uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ + uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ + uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ + uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ + uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ + uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ + uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ + uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ + uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ + uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ + uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TCC_PATT_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1256,38 +1256,38 @@ typedef union { /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ - uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ - uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ - uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ - uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ - uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ - uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ - uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ - uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ - uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ - uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ + uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ + uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ + uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ + uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ + uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ + uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ + uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ + uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ + uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ + uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WAVE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1360,26 +1360,26 @@ typedef union { /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t PER:20; /*!< bit: 4..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t PER:19; /*!< bit: 5..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t PER:18; /*!< bit: 6..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PER:24; /*!< bit: 0..23 Period Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t PER:20; /*!< bit: 4..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t PER:19; /*!< bit: 5..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t PER:18; /*!< bit: 6..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PER:24; /*!< bit: 0..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_PER_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1421,26 +1421,26 @@ typedef union { /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ - uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ - uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ - uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1482,29 +1482,29 @@ typedef union { /* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ - uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ - uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ - uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ - uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ - uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ - uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ - uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ - uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ - uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ - uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ - uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ - uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ - uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ - uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ - uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ - uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ + uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ + uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ + uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ + uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ + uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ + uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ + uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ + uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ + uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ + uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ + uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ + uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ + uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ + uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ + uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ + uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } TCC_PATTB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1554,38 +1554,38 @@ typedef union { /* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ - uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ - uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ - uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ - uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ - uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ - uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ - uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ - uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ - uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ - uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :8; /*!< bit: 0.. 7 Reserved */ - uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ - uint32_t :4; /*!< bit: 12..15 Reserved */ - uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ + uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ + uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ + uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ + uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ + uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ + uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ + uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ + uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ + uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ + uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ } TCC_WAVEB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1658,26 +1658,26 @@ typedef union { /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_PERB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1719,26 +1719,26 @@ typedef union { /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { // DITH4 mode - uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ - uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH4; /*!< Structure used for DITH4 */ - struct { // DITH5 mode - uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ - uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH5; /*!< Structure used for DITH5 */ - struct { // DITH6 mode - uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ - uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } DITH6; /*!< Structure used for DITH6 */ - struct { - uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } TCC_CCB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1780,35 +1780,35 @@ typedef union { /** \brief TCC hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ - __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ - RoReg8 Reserved1[0x2]; - __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ - __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ - __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ - __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ - RoReg8 Reserved2[0x2]; - __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ - RoReg8 Reserved3[0x1]; - __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ - __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ - __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ - __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ - __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ - __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ - __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ - RoReg8 Reserved4[0x2]; - __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ - __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ - __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ - RoReg8 Reserved5[0x10]; - __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ - RoReg8 Reserved6[0x2]; - __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ - __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ - __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ + __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + RoReg8 Reserved1[0x2]; + __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ + __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ + __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ + __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ + RoReg8 Reserved2[0x2]; + __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ + RoReg8 Reserved3[0x1]; + __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ + __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ + __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ + __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ + __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ + __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ + __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ + RoReg8 Reserved4[0x2]; + __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ + __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ + __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ + RoReg8 Reserved5[0x10]; + __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ + RoReg8 Reserved6[0x2]; + __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ + __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ + __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ } Tcc; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h similarity index 66% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h index da019a8cc1..6c9ee67435 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_usb.h @@ -56,14 +56,14 @@ /* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t MODE:1; /*!< bit: 7 Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t MODE:1; /*!< bit: 7 Operating Mode */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_CTRLA_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -87,12 +87,12 @@ typedef union { /* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_SYNCBUSY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -108,12 +108,12 @@ typedef union { /* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ - uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ + uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_QOSCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -147,20 +147,20 @@ typedef union { /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DETACH:1; /*!< bit: 0 Detach */ - uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ - uint16_t NREPLY:1; /*!< bit: 4 No Reply */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ - uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ - uint16_t GNAK:1; /*!< bit: 9 Global NAK */ - uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DETACH:1; /*!< bit: 0 Detach */ + uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ + uint16_t NREPLY:1; /*!< bit: 4 No Reply */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ + uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ + uint16_t GNAK:1; /*!< bit: 9 Global NAK */ + uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -210,21 +210,21 @@ typedef union { /* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :1; /*!< bit: 0 Reserved */ - uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ - uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ - uint16_t TSTK:1; /*!< bit: 6 Test mode K */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ - uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ - uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ - uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ + uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ + uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ + uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_CTRLB_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -257,11 +257,11 @@ typedef union { /* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ - uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ + uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_DADD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -278,12 +278,12 @@ typedef union { /* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_HSOFC_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -300,13 +300,13 @@ typedef union { /* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -336,13 +336,13 @@ typedef union { /* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :2; /*!< bit: 0.. 1 Reserved */ - uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ - uint8_t :2; /*!< bit: 4.. 5 Reserved */ - uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -360,11 +360,11 @@ typedef union { /* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_FSMSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -393,13 +393,13 @@ typedef union { /* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :1; /*!< bit: 14 Reserved */ - uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :1; /*!< bit: 14 Reserved */ + uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_FNUM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -419,12 +419,12 @@ typedef union { /* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ - uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_FNUM_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -442,10 +442,10 @@ typedef union { /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_FLENHIGH_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -460,20 +460,20 @@ typedef union { /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -505,19 +505,19 @@ typedef union { /* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ - uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ - uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ + uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ + uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -545,20 +545,20 @@ typedef union { /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ - uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ - uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ - uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ - uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -590,19 +590,19 @@ typedef union { /* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t :2; /*!< bit: 0.. 1 Reserved */ - uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ - uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ - uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ - uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ - uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ - uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ - uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ - uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ + uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -630,20 +630,20 @@ typedef union { /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ - __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ - __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ - __I uint16_t EORST:1; /*!< bit: 3 End of Reset */ - __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ - __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ - __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ - __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ - __I uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ + __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ + __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ + __I uint16_t EORST:1; /*!< bit: 3 End of Reset */ + __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ + __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ + __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ + __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ + __I uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -675,19 +675,19 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint16_t :2; /*!< bit: 0.. 1 Reserved */ - __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ - __I uint16_t RST:1; /*!< bit: 3 Bus Reset */ - __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ - __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */ - __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ - __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ - __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */ - __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ - __I uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + __I uint16_t :2; /*!< bit: 0.. 1 Reserved */ + __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ + __I uint16_t RST:1; /*!< bit: 3 Bus Reset */ + __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */ + __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ + __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */ + __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ + __I uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -715,22 +715,22 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTSMRY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -761,22 +761,22 @@ typedef union { /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ - uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ - uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ - uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ - uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ - uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ - uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ - uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_PINTSMRY_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -807,10 +807,10 @@ typedef union { /* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_DESCADD_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -825,15 +825,15 @@ typedef union { /* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ - uint16_t :1; /*!< bit: 5 Reserved */ - uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_PADCAL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -854,13 +854,13 @@ typedef union { /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ - uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ + uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPCFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -880,13 +880,13 @@ typedef union { /* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ - uint8_t BK:1; /*!< bit: 2 Pipe Bank */ - uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ + uint8_t BK:1; /*!< bit: 2 Pipe Bank */ + uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PCFG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -906,10 +906,10 @@ typedef union { /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_BINTERVAL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -924,22 +924,22 @@ typedef union { /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ + uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPSTATUSCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -968,17 +968,17 @@ typedef union { /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PSTATUSCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1000,22 +1000,22 @@ typedef union { /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPSTATUSSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1044,17 +1044,17 @@ typedef union { /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PSTATUSSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1076,22 +1076,22 @@ typedef union { /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ - uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ - uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t :4; /*!< bit: 0.. 3 Reserved */ - uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1120,17 +1120,17 @@ typedef union { /* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t CURBK:1; /*!< bit: 2 Current Bank */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ - uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PSTATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1152,24 +1152,24 @@ typedef union { /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ - __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ - __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ - __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ - __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ - __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ - __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ - __I uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ - __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ - __I uint8_t :1; /*!< bit: 4 Reserved */ - __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ - __I uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ + __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ + __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ + __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ + __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ + __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ + __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ + __I uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ + __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ + __I uint8_t :1; /*!< bit: 4 Reserved */ + __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ + __I uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1204,20 +1204,20 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ - __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ - __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ - __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ - __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ - __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ - __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ + __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ + __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ + __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ + __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ + __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ + __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PINTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1244,24 +1244,24 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1296,20 +1296,20 @@ typedef union { /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ - uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ + uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PINTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1336,24 +1336,24 @@ typedef union { /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ - uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ - uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ - uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ - uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ - uint8_t :1; /*!< bit: 4 Reserved */ - uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ - uint8_t :1; /*!< bit: 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_EPINTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1388,20 +1388,20 @@ typedef union { /* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ - uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ - uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ - uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ - uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ - uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_PINTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1428,10 +1428,10 @@ typedef union { /* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_DEVICE_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1445,10 +1445,10 @@ typedef union { /* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_HOST_ADDR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1462,13 +1462,13 @@ typedef union { /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_DEVICE_PCKSIZE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1490,13 +1490,13 @@ typedef union { /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ - uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ - uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ - uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ } USB_HOST_PCKSIZE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1518,12 +1518,12 @@ typedef union { /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_DEVICE_EXTREG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1540,12 +1540,12 @@ typedef union { /* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ - uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ - uint16_t :1; /*!< bit: 15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_EXTREG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1562,12 +1562,12 @@ typedef union { /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_DEVICE_STATUS_BK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1582,12 +1582,12 @@ typedef union { /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ - uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } USB_HOST_STATUS_BK_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1602,13 +1602,13 @@ typedef union { /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ - uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ + uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_CTRL_PIPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1629,16 +1629,16 @@ typedef union { /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ - uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ - uint16_t PIDER:1; /*!< bit: 2 PID Error */ - uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ - uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ - uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ - uint16_t :8; /*!< bit: 8..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ + struct { + uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ + uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ + uint16_t PIDER:1; /*!< bit: 2 PID Error */ + uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ + uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ + uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ } USB_HOST_STATUS_PIPE_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -1662,140 +1662,140 @@ typedef union { /** \brief UsbDeviceDescBank SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ - __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ - __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ - __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ - RoReg8 Reserved1[0x5]; + __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ + __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ + __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ + __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ + RoReg8 Reserved1[0x5]; } UsbDeviceDescBank; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief UsbHostDescBank SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ - __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ - __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ - __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ - RoReg8 Reserved1[0x1]; - __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ - __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ + __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ + __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ + __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ + __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ + RoReg8 Reserved1[0x1]; + __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ + __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ } UsbHostDescBank; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief UsbDeviceEndpoint hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ - RoReg8 Reserved1[0x3]; - __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ - __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ - __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ - __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ - __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ - __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ - RoReg8 Reserved2[0x16]; + __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ + RoReg8 Reserved1[0x3]; + __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ + __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ + __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ + __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ + __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ + __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ + RoReg8 Reserved2[0x16]; } UsbDeviceEndpoint; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief UsbHostPipe hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ - RoReg8 Reserved1[0x2]; - __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ - __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ - __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ - __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ - __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ - __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ - __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ - RoReg8 Reserved2[0x16]; + __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ + RoReg8 Reserved1[0x2]; + __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ + __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ + __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ + __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ + __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ + __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ + __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ + RoReg8 Reserved2[0x16]; } UsbHostPipe; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_DEVICE APB hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Device */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ - __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ - RoReg8 Reserved3[0x1]; - __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ - RoReg8 Reserved5[0x2]; - __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ + RoReg8 Reserved2[0x4]; + __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ + __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ + RoReg8 Reserved3[0x1]; + __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ + RoReg8 Reserved5[0x2]; + __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ } UsbDevice; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_HOST hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Host */ - __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ - RoReg8 Reserved1[0x1]; - __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ - __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ - RoReg8 Reserved2[0x4]; - __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ - __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ - RoReg8 Reserved3[0x1]; - __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ - __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ - RoReg8 Reserved4[0x2]; - __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ - __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ - RoReg8 Reserved5[0x1]; - __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ - RoReg8 Reserved6[0x2]; - __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ - RoReg8 Reserved7[0x2]; - __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ - RoReg8 Reserved8[0x2]; - __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ - RoReg8 Reserved9[0x2]; - __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ - __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ - RoReg8 Reserved10[0xD6]; - UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ + RoReg8 Reserved2[0x4]; + __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ + __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ + RoReg8 Reserved3[0x1]; + __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ + __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ + RoReg8 Reserved5[0x1]; + __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ } UsbHost; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_DEVICE Descriptor SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Device */ - UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ + UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ } UsbDeviceDescriptor; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /** \brief USB_HOST Descriptor SRAM registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { /* USB is Host */ - UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ + UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ } UsbHostDescriptor; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ #define SECTION_USB_DESCRIPTOR #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ - UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ + UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ + UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ } Usb; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h similarity index 79% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h index 9f53b7670c..bb4f410719 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/component/comp_wdt.h @@ -56,14 +56,14 @@ /* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :1; /*!< bit: 0 Reserved */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_CTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -81,11 +81,11 @@ typedef union { /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ - uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ + uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_CONFIG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -151,11 +151,11 @@ typedef union { /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_EWCTRL_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -194,11 +194,11 @@ typedef union { /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_INTENCLR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -212,11 +212,11 @@ typedef union { /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_INTENSET_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -230,11 +230,11 @@ typedef union { /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t EW:1; /*!< bit: 0 Early Warning */ - __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + __I uint8_t EW:1; /*!< bit: 0 Early Warning */ + __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_INTFLAG_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -248,11 +248,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register /* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_STATUS_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -266,10 +266,10 @@ typedef union { /* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef union { - struct { - uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ + struct { + uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ } WDT_CLEAR_Type; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ @@ -286,15 +286,15 @@ typedef union { /** \brief WDT hardware registers */ #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) typedef struct { - __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ - __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ - RoReg8 Reserved1[0x1]; - __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ + __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ + __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ + RoReg8 Reserved1[0x1]; + __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ } Wdt; #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h index ca428877ea..18d441ec3a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_ac.h @@ -81,7 +81,7 @@ #define AC_CMP_NUM 2 // Number of comparators #define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog #define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital -#define AC_NUM_CMP 2 +#define AC_NUM_CMP 2 #define AC_PAIRS 1 // Number of pairs of comparators #endif /* _SAMR21_AC_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_adc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_adc.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_adc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_adc.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_dmac.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dmac.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_dmac.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dmac.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_dsu.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dsu.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_dsu.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_dsu.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_eic.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_eic.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_eic.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_eic.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_evsys.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_evsys.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_evsys.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_evsys.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h similarity index 88% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h index 41bc085297..96fd76c35f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_gclk.h @@ -60,20 +60,20 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 +#define GCLK_GENDIV_BITS 16 #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 #define GCLK_NUM 37 // Number of Generic Clock Users -#define GCLK_SOURCE_DFLL48M 7 -#define GCLK_SOURCE_FDPLL 8 -#define GCLK_SOURCE_GCLKGEN1 2 -#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_DFLL48M 7 +#define GCLK_SOURCE_FDPLL 8 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 -#define GCLK_SOURCE_OSC8M 6 -#define GCLK_SOURCE_OSC32K 4 -#define GCLK_SOURCE_XOSC 0 -#define GCLK_SOURCE_XOSC32K 5 +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC8M 6 +#define GCLK_SOURCE_OSC32K 4 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 5 #endif /* _SAMR21_GCLK_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_mtb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_mtb.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_mtb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_mtb.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h similarity index 91% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h index ca040fdc63..4f95860e73 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_nvmctrl.h @@ -74,16 +74,16 @@ #define NVMCTRL_AUX3_ADDRESS 0x0080A000 #define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 262144 +#define NVMCTRL_FLASH_SIZE 262144 #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGES 4096 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 +#define NVMCTRL_PAGES 4096 +#define NVMCTRL_PAGE_HW 32 +#define NVMCTRL_PAGE_SIZE 64 +#define NVMCTRL_PAGE_W 16 +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES 4 +#define NVMCTRL_ROW_SIZE 256 #define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030 #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac0.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac0.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac0.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac1.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac1.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac1.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac2.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac2.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pac2.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h similarity index 95% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h index 489baa2e6c..c7d06c6c62 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_pm.h @@ -78,10 +78,10 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for PM peripheral ========== */ -#define PM_CTRL_MCSEL_DFLL48M 3 -#define PM_CTRL_MCSEL_GCLK 0 -#define PM_CTRL_MCSEL_OSC8M 1 -#define PM_CTRL_MCSEL_XOSC 2 -#define PM_PM_CLK_APB_NUM 2 +#define PM_CTRL_MCSEL_DFLL48M 3 +#define PM_CTRL_MCSEL_GCLK 0 +#define PM_CTRL_MCSEL_OSC8M 1 +#define PM_CTRL_MCSEL_XOSC 2 +#define PM_PM_CLK_APB_NUM 2 #endif /* _SAMR21_PM_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_port.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_port.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_port.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_port.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h similarity index 98% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h index cab774174d..60cdb6b2e4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rfctrl.h @@ -52,6 +52,6 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for RFCTRL peripheral ========== */ -#define RFCTRL_FBUSMSB 5 +#define RFCTRL_FBUSMSB 5 #endif /* _SAMR21_RFCTRL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rtc.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rtc.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_rtc.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_rtc.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h index 840931954e..f8dd7396cc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sbmatrix.h @@ -146,7 +146,7 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SBMATRIX peripheral ========== */ -#define SBMATRIX_DEFINED +#define SBMATRIX_DEFINED /* ========== Instance parameters for SBMATRIX ========== */ #define SBMATRIX_SLAVE_FLASH 0 #define SBMATRIX_SLAVE_HPB0 1 diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h index ac8bd1b779..1849d43531 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom0.h @@ -138,6 +138,6 @@ #define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger #define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core #define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM0_INT_MSB 6 +#define SERCOM0_INT_MSB 6 #endif /* _SAMR21_SERCOM0_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h index 4e732a52e6..6c0674bc2e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom1.h @@ -138,6 +138,6 @@ #define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger #define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core #define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM1_INT_MSB 6 +#define SERCOM1_INT_MSB 6 #endif /* _SAMR21_SERCOM1_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h index 3f588f005c..517225b90c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom2.h @@ -138,6 +138,6 @@ #define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger #define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core #define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM2_INT_MSB 6 +#define SERCOM2_INT_MSB 6 #endif /* _SAMR21_SERCOM2_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h index 7eb3429c8d..8f69e39808 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom3.h @@ -138,6 +138,6 @@ #define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger #define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core #define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM3_INT_MSB 6 +#define SERCOM3_INT_MSB 6 #endif /* _SAMR21_SERCOM3_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h index f498aaecb7..52497513df 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom4.h @@ -138,6 +138,6 @@ #define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger #define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core #define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM4_INT_MSB 6 +#define SERCOM4_INT_MSB 6 #endif /* _SAMR21_SERCOM4_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h index c0dff13035..12f9a88983 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sercom5.h @@ -138,6 +138,6 @@ #define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger #define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core #define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout -#define SERCOM5_INT_MSB 6 +#define SERCOM5_INT_MSB 6 #endif /* _SAMR21_SERCOM5_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h similarity index 86% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h index 278eb5debe..d7757ad16c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_sysctrl.h @@ -90,31 +90,31 @@ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for SYSCTRL peripheral ========== */ -#define SYSCTRL_BGAP_CALIB_MSB 11 -#define SYSCTRL_BOD33_CALIB_MSB 5 -#define SYSCTRL_DFLL48M_COARSE_MSB 5 -#define SYSCTRL_DFLL48M_FINE_MSB 9 +#define SYSCTRL_BGAP_CALIB_MSB 11 +#define SYSCTRL_BOD33_CALIB_MSB 5 +#define SYSCTRL_DFLL48M_COARSE_MSB 5 +#define SYSCTRL_DFLL48M_FINE_MSB 9 #define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 #define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL #define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 -#define SYSCTRL_POR33_ENTEST_MSB 1 -#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 -#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 -#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 -#define SYSCTRL_VREF_CONTROL_MSB 48 -#define SYSCTRL_VREF_STATUS_MSB 7 -#define SYSCTRL_VREG_LEVEL_MSB 2 -#define SYSCTRL_BOD12_VERSION 0x111 -#define SYSCTRL_BOD33_VERSION 0x111 -#define SYSCTRL_DFLL48M_VERSION 0x301 -#define SYSCTRL_FDPLL_VERSION 0x111 -#define SYSCTRL_OSCULP32K_VERSION 0x111 -#define SYSCTRL_OSC8M_VERSION 0x120 -#define SYSCTRL_OSC32K_VERSION 0x1101 -#define SYSCTRL_VREF_VERSION 0x200 -#define SYSCTRL_VREG_VERSION 0x201 -#define SYSCTRL_XOSC_VERSION 0x1111 -#define SYSCTRL_XOSC32K_VERSION 0x1111 +#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define SYSCTRL_POR33_ENTEST_MSB 1 +#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 +#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 +#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 +#define SYSCTRL_VREF_CONTROL_MSB 48 +#define SYSCTRL_VREF_STATUS_MSB 7 +#define SYSCTRL_VREG_LEVEL_MSB 2 +#define SYSCTRL_BOD12_VERSION 0x111 +#define SYSCTRL_BOD33_VERSION 0x111 +#define SYSCTRL_DFLL48M_VERSION 0x301 +#define SYSCTRL_FDPLL_VERSION 0x111 +#define SYSCTRL_OSCULP32K_VERSION 0x111 +#define SYSCTRL_OSC8M_VERSION 0x120 +#define SYSCTRL_OSC32K_VERSION 0x1101 +#define SYSCTRL_VREF_VERSION 0x200 +#define SYSCTRL_VREG_VERSION 0x201 +#define SYSCTRL_XOSC_VERSION 0x1111 +#define SYSCTRL_XOSC32K_VERSION 0x1111 #endif /* _SAMR21_SYSCTRL_INSTANCE_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h index c3a57f3b4f..987f85240b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc3.h @@ -103,7 +103,7 @@ #define TC3_DMAC_ID_MC_SIZE 2 #define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger #define TC3_GCLK_ID 27 // Index of Generic Clock -#define TC3_MASTER 0 +#define TC3_MASTER 0 #define TC3_OW_NUM 2 // Number of Output Waveforms #define TC3_PERIOD_EXT 0 // Period feature implemented #define TC3_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h index 382c71c45c..598dc7b900 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc4.h @@ -103,7 +103,7 @@ #define TC4_DMAC_ID_MC_SIZE 2 #define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger #define TC4_GCLK_ID 28 // Index of Generic Clock -#define TC4_MASTER 1 +#define TC4_MASTER 1 #define TC4_OW_NUM 2 // Number of Output Waveforms #define TC4_PERIOD_EXT 0 // Period feature implemented #define TC4_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h index f7f98af2cd..3d0518800b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tc5.h @@ -103,7 +103,7 @@ #define TC5_DMAC_ID_MC_SIZE 2 #define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger #define TC5_GCLK_ID 28 // Index of Generic Clock -#define TC5_MASTER 0 +#define TC5_MASTER 0 #define TC5_OW_NUM 2 // Number of Output Waveforms #define TC5_PERIOD_EXT 0 // Period feature implemented #define TC5_SHADOW_EXT 0 // Shadow feature implemented diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h index 8d7371ae4c..5912bfbc8d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc0.h @@ -124,7 +124,7 @@ #define TCC0_OTMX 1 // Output Matrix feature implemented #define TCC0_OW_NUM 8 // Number of Output Waveforms #define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 +#define TCC0_SIZE 24 #define TCC0_SWAP 1 // DTI outputs swap feature implemented #define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h index 441fdbbc74..da2ff09f44 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc1.h @@ -112,7 +112,7 @@ #define TCC1_OTMX 0 // Output Matrix feature implemented #define TCC1_OW_NUM 4 // Number of Output Waveforms #define TCC1_PG 1 // Pattern Generation feature implemented -#define TCC1_SIZE 24 +#define TCC1_SIZE 24 #define TCC1_SWAP 0 // DTI outputs swap feature implemented #define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h similarity index 99% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h index 559a82bf9b..6090fc6296 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_tcc2.h @@ -108,7 +108,7 @@ #define TCC2_OTMX 0 // Output Matrix feature implemented #define TCC2_OW_NUM 2 // Number of Output Waveforms #define TCC2_PG 0 // Pattern Generation feature implemented -#define TCC2_SIZE 16 +#define TCC2_SIZE 16 #define TCC2_SWAP 0 // DTI outputs swap feature implemented #define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_usb.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_usb.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_usb.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_usb.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_wdt.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_wdt.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/instance/ins_wdt.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/instance/ins_wdt.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e16a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e16a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e17a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e17a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e18a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21e18a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g16a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g16a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g17a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g17a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g18a.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/pio/pio_samr21g18a.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21.h similarity index 91% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21.h index 90a489d30d..769e7004d0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21.h @@ -50,19 +50,19 @@ */ #if defined(__SAMR21E16A__) || defined(__ATSAMR21E16A__) - #include "samr21e16a.h" +#include "samr21e16a.h" #elif defined(__SAMR21E17A__) || defined(__ATSAMR21E17A__) - #include "samr21e17a.h" +#include "samr21e17a.h" #elif defined(__SAMR21E18A__) || defined(__ATSAMR21E18A__) - #include "samr21e18a.h" +#include "samr21e18a.h" #elif defined(__SAMR21G16A__) || defined(__ATSAMR21G16A__) - #include "samr21g16a.h" +#include "samr21g16a.h" #elif defined(__SAMR21G17A__) || defined(__ATSAMR21G17A__) - #include "samr21g17a.h" +#include "samr21g17a.h" #elif defined(__SAMR21G18A__) || defined(__ATSAMR21G18A__) - #include "samr21g18a.h" +#include "samr21g18a.h" #else - #error Library does not support the specified device. +#error Library does not support the specified device. #endif #endif /* _SAMR21_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h similarity index 80% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h index 6bb342d500..2208878819 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21E16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21E16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21E16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21E16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21E16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21E16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21E16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21E16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21E16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21E16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21E16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21E16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21E16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21E16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21E16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21E16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21E16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21E16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21E16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21E16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21E16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21E16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21E16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21E16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21E16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21E16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21E16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21E16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21E16A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMR21E16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMR21E16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMR21E16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMR21E16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMR21E16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMR21E16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMR21E16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMR21E16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMR21E16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMR21E16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMR21E16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMR21E16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMR21E16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMR21E16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMR21E16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMR21E16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMR21E16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMR21E16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMR21E16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMR21E16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMR21E16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMR21E16A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMR21E16A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMR21E16A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMR21E16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMR21E16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMR21E16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMR21E16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMR21E16A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -227,7 +225,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h similarity index 80% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h index 7931cbe4d2..e4c3c23319 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21E17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21E17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21E17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21E17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21E17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21E17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21E17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21E17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21E17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21E17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21E17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21E17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21E17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21E17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21E17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21E17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21E17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21E17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21E17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21E17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21E17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21E17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21E17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21E17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21E17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21E17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21E17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21E17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21E17A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMR21E17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMR21E17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMR21E17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMR21E17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMR21E17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMR21E17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMR21E17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMR21E17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMR21E17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMR21E17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMR21E17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMR21E17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMR21E17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMR21E17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMR21E17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMR21E17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMR21E17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMR21E17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMR21E17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMR21E17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMR21E17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMR21E17A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMR21E17A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMR21E17A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMR21E17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMR21E17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMR21E17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMR21E17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMR21E17A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -227,7 +225,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h similarity index 80% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h index 8c9dcbb27b..2e4e3dd90a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21E18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21E18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21E18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21E18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21E18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21E18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21E18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21E18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21E18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21E18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21E18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21E18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21E18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21E18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21E18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21E18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21E18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21E18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21E18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21E18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21E18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21E18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21E18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21E18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21E18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21E18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21E18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21E18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21E18A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMR21E18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMR21E18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMR21E18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMR21E18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMR21E18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMR21E18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMR21E18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMR21E18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMR21E18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMR21E18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMR21E18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMR21E18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMR21E18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMR21E18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMR21E18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMR21E18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMR21E18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMR21E18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMR21E18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMR21E18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMR21E18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMR21E18A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMR21E18A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMR21E18A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMR21E18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMR21E18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMR21E18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMR21E18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMR21E18A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -227,7 +225,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h similarity index 80% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h index 6ceab69a84..42d7c79af5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21G16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21G16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21G16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21G16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21G16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21G16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21G16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21G16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21G16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21G16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21G16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21G16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21G16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21G16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21G16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21G16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21G16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21G16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21G16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21G16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21G16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21G16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21G16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21G16A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMR21G16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMR21G16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMR21G16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMR21G16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMR21G16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMR21G16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMR21G16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMR21G16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMR21G16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMR21G16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMR21G16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMR21G16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMR21G16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMR21G16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMR21G16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMR21G16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMR21G16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMR21G16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMR21G16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMR21G16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMR21G16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMR21G16A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMR21G16A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMR21G16A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMR21G16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMR21G16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMR21G16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMR21G16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMR21G16A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -227,7 +225,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h similarity index 80% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h index 6f2e69f224..44ba21d89b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21G17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21G17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21G17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21G17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21G17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21G17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21G17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21G17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21G17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21G17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21G17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21G17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21G17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21G17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21G17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21G17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21G17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21G17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21G17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21G17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21G17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21G17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21G17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21G17A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMR21G17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMR21G17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMR21G17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMR21G17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMR21G17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMR21G17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMR21G17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMR21G17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMR21G17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMR21G17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMR21G17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMR21G17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMR21G17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMR21G17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMR21G17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMR21G17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMR21G17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMR21G17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMR21G17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMR21G17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMR21G17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMR21G17A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMR21G17A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMR21G17A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMR21G17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMR21G17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMR21G17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMR21G17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMR21G17A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -227,7 +225,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h similarity index 80% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h index 99009a892c..49123bb959 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h @@ -56,7 +56,7 @@ /*@{*/ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) @@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati /*@{*/ /** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMR21G18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */ +typedef enum IRQn { + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMR21G18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMR21G18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMR21G18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMR21G18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMR21G18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMR21G18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMR21G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMR21G18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMR21G18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMR21G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMR21G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMR21G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMR21G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMR21G18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMR21G18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMR21G18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMR21G18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMR21G18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMR21G18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMR21G18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMR21G18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMR21G18A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMR21G18A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMR21G18A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMR21G18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMR21G18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMR21G18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMR21G18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMR21G18A Inter-IC Sound Interface (I2S) */ - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ } IRQn_Type; -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; +typedef struct _DeviceVectors { + /* Stack pointer */ + void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnReservedM12; + void* pfnReservedM11; + void* pfnReservedM10; + void* pfnReservedM9; + void* pfnReservedM8; + void* pfnReservedM7; + void* pfnReservedM6; + void* pfnSVC_Handler; + void* pfnReservedM4; + void* pfnReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pfnReserved28; + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pfnReserved28; } DeviceVectors; /* Cortex-M0+ processor handlers */ @@ -227,7 +225,7 @@ void I2S_Handler ( void ); * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define LITTLE_ENDIAN 1 +#define LITTLE_ENDIAN 1 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/source/system_samr21.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.c similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/source/system_samr21.c rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.c diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/source/system_samr21.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/source/system_samr21.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMR21/source/system_samr21.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/compiler.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/compiler.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/compiler.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/compiler.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/header_files/io.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/header_files/io.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/header_files/io.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/header_files/io.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/mrecursion.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrecursion.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/mrecursion.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrecursion.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/mrepeat.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrepeat.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/mrepeat.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/mrepeat.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/preprocessor.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/preprocessor.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/preprocessor.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/preprocessor.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/stringz.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/stringz.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/stringz.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/stringz.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/tpaste.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/tpaste.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/preprocessor/tpaste.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/preprocessor/tpaste.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/status_codes.h b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/status_codes.h similarity index 100% rename from libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/status_codes.h rename to libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/status_codes.h diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h index 041f997824..82bb6fd929 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h @@ -3530,6 +3530,8 @@ typedef struct { #define PIT_TCTRL_TEN_SHIFT 0 #define PIT_TCTRL_TIE_MASK 0x2u #define PIT_TCTRL_TIE_SHIFT 1 +#define PIT_TCTRL_CHN_MASK 0x4u +#define PIT_TCTRL_CHN_SHIFT 2 /* TFLG Bit Fields */ #define PIT_TFLG_TIF_MASK 0x1u #define PIT_TFLG_TIF_SHIFT 0 diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c index 4f34cc76c1..9b851b44df 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c @@ -42,22 +42,20 @@ #define DISABLE_WDOG 1 -#define CLOCK_SETUP 3 +#define CLOCK_SETUP 1 /* Predefined clock setups 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode Reference clock source for MCG module is the slow internal clock source 32.768kHz Core clock = 41.94MHz, BusClock = 41.94MHz - This works on Teensy3.1 + Works on Teensy3.1 but no USB support 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode - Reference clock source for MCG module is an external crystal 8MHz - Core clock = 48MHz, BusClock = 48MHz - 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode - Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication - Core clock = 8MHz, BusClock = 8MHz - 3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode Reference clock source for MCG module is an external crystal 16MHz - Core clock = 72MHz, BusClock = 48MHz - This is the default Teensy3.1 72Mhz set up + Core clock = 96MHz, BusClock = 48MHz + Default high speed Teensy3.1 96Mhz set up + 2 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode + Reference clock source for MCG module is an external crystal 16MHz + Core clock = 72MHz, BusClock = 36MHz + Alternative standard 'slower' Teensy3.1 72Mhz set up */ /*---------------------------------------------------------------------------- @@ -70,23 +68,17 @@ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ #elif (CLOCK_SETUP == 1) - #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ -#elif (CLOCK_SETUP == 2) - #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ - #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ - #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ - #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ -#elif (CLOCK_SETUP == 3) #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ - #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */ + #define DEFAULT_SYSTEM_CLOCK 96000000u /* Default System clock value */ +#elif (CLOCK_SETUP == 2) + #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */ + #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ + #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ + #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ + #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */ #endif /* (CLOCK_SETUP == 2) */ @@ -130,65 +122,44 @@ void SystemInit (void) { while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */ #elif (CLOCK_SETUP == 1) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 48MHz cpu, 48MHz system, 24MHz flash*/ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 Set Prescalers 96MHz cpu, 48MHz bus, 24MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3); + /* SIM->CLKDIV2: USBDIV=2, Divide 96MHz system clock for USB 48MHz */ + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1); + /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/ + OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK; /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC0->CR = (uint8_t)0x00u; /* MCG->C7: OSCSEL=0 */ MCG->C7 = (uint8_t)0x00u; /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = MCG_C2_RANGE0(2); + MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; + //MCG->C2 = (uint8_t)0x24u; /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = MCG_C5_PRDIV0(3); + /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */ + MCG->C5 = MCG_C5_PRDIV0(7); /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ MCG->C6 = (uint8_t)0x00u; while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ /* Switch to PBE Mode */ - /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = MCG_C5_PRDIV0(3); - /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ - MCG->C6 = MCG_C6_PLLS_MASK; + /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */ + MCG->C5 = MCG_C5_PRDIV0(3); // config PLL input for 16 MHz Crystal / 4 = 4 MHz + /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */ + MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0);// config PLL for 96 MHz output while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ /* Switch to PEE Mode */ - /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; + /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK; while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ #elif (CLOCK_SETUP == 2) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 8MHz cpu, 8MHz system, 8MHz flash*/ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); - /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC0->CR = (uint8_t)0x00u; - /* MCG->C7: OSCSEL=0 */ - MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; - /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ - MCG->C5 = (uint8_t)0x00u; - /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ - while((MCG->S & 0x0CU) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ - /* Switch to BLPE Mode */ - /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; - -#elif (CLOCK_SETUP == 3) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 72MHz system, 36MHz flash*/ - SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 36MHz bus, 24MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2); /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK; /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/ @@ -220,7 +191,7 @@ void SystemInit (void) { /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK; while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ #endif /* (CLOCK_SETUP) */ } @@ -306,4 +277,4 @@ void SystemCoreClockUpdate (void) { return; } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); -} +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c index fc13c884fc..784193b664 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c @@ -31,14 +31,13 @@ #include "cmsis_nvic.h" #define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t*)SCB->VTOR; uint32_t i; // Copy and switch to dynamic vectors if the first time called - if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + if (SCB->VTOR < NVIC_RAM_VECTOR_ADDRESS) { uint32_t *old_vectors = vectors; vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; for (i=0; i RamAHB32 AT>MFlash512 + } > RamAHB_USB AT>MFlash512 /* MAIN DATA SECTION */ - .uninit_RESERVED : ALIGN(4) + .uninit_RESERVED(NOLOAD) : ALIGN(4) { KEEP(*(.bss.$RESERVED*)) } > RamLoc32 @@ -130,15 +131,21 @@ SECTIONS } > RamLoc32 AT>MFlash512 - .bss_RAM2 : ALIGN(4) + .bss_RAM2(NOLOAD) : ALIGN(4) { *(.bss.$RAM2*) *(.bss.$RamAHB32*) + *(AHBSRAM0) . = ALIGN(4) ; - } > RamAHB32 + } > RamAHB_USB + .bss_RAM3(NOLOAD) : ALIGN(4) + { + *(AHBSRAM1) + . = ALIGN(4) ; + } > RamAHB_Eth /* MAIN BSS SECTION */ - .bss : ALIGN(4) + .bss(NOLOAD) : ALIGN(4) { _bss = .; *(.bss*) diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c index 9e67970b0b..723ec247c8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c @@ -1,8 +1,8 @@ /**************************************************************************//** * @file pl310.c - * @brief Implementation of pl310 functions + * @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions * @version - * @date 11 June 2013 + * @date 3 December 2014 * * @note * @@ -80,7 +80,7 @@ void PL310_CleanInvAllByWay (void) assoc = 8; PL310->CLEAN_INV_WAY = (1 << assoc) - 1; - while(PL310->CLEAN_INV_WAY && ((1 << assoc) - 1)); //poll invalidate + while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate PL310_Sync(); } diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c index 3a37c602c0..37fc9196c9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c @@ -1,14 +1,14 @@ /**************************************************************************//** * @file system_MBRZA1H.c * @brief CMSIS Device System Source File for - * ARMCA9 Device Series + * ARM Cortex-A9 Device Series * @version V1.00 - * @date 19 Sept 2013 + * @date 09 January 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED +/* Copyright (c) 2011 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -50,9 +50,9 @@ void FPUEnable(void); #endif uint32_t IRQNestLevel; +unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 -#if defined(__ARMCC_VERSION) /** * Initialize the cache. * @@ -61,6 +61,7 @@ uint32_t IRQNestLevel; * * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode. */ +#if defined(__ARMCC_VERSION) #pragma push #pragma arm @@ -189,7 +190,7 @@ void SystemInit (void) //Fault Status Register (IFSR/DFSR) definitions #define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup -#define FSR_INSTRUCTION_CACHE_MAINTAINANCE 0x04 //DFSR only - async/external +#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external #define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external #define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external #define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external @@ -223,7 +224,7 @@ void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { //Your code here. Value in DFAR is invalid for some fault statuses. case FSR_ALIGNMENT_FAULT: - case FSR_INSTRUCTION_CACHE_MAINTAINANCE: + case FSR_INSTRUCTION_CACHE_MAINTENANCE: case FSR_SYNC_EXT_TTB_WALK_FIRST: case FSR_SYNC_EXT_TTB_WALK_SECOND: case FSR_TRANSLATION_FAULT_FIRST: @@ -278,21 +279,36 @@ void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { } //returns amount to decrement lr by -//this will be 0 when we have emulated the instruction and simply want to execute the next instruction -//this will be 2 when we have performed some maintenance and want to retry the instruction in thumb (state == 2) -//this will be 4 when we have performed some maintenance and want to retry the instruction in arm (state == 4) +//this will be 0 when we have emulated the instruction and want to execute the next instruction +//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) +//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4) uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { const unsigned int THUMB = 2; const unsigned int ARM = 4; //Lazy VFP/NEON initialisation and switching - if ((state == ARM && ((opcode & 0x0C000000)) >> 26 == 0x03) || - (state == THUMB && ((opcode & 0xEC000000)) >> 26 == 0x3B)) { - if (((opcode & 0x00000E00) >> 9) == 5) { //fp instruction? + + // (ARM ARM section A7.5) VFP data processing instruction? + // (ARM ARM section A7.6) VFP/NEON register load/store instruction? + // (ARM ARM section A7.8) VFP/NEON register data transfer instruction? + // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction? + if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) || + (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) { + if (((opcode & 0x00000E00) >> 9) == 5) { FPUEnable(); return state; } } + // (ARM ARM section A7.4) NEON data processing instruction? + if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) || + (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) || + // (ARM ARM section A7.7) NEON load/store instruction? + (state == ARM && ((opcode >> 24) == 0xF4)) || + (state == THUMB && ((opcode >> 24) == 0xF9))) { + FPUEnable(); + return state; + } + //Add code here for other Undef cases while(1); } @@ -304,18 +320,22 @@ uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { __asm void FPUEnable(void) { ARM - //Permit access to VFP registers by modifying CPACR + //Permit access to VFP/NEON, registers by modifying CPACR MRC p15,0,R1,c1,c0,2 ORR R1,R1,#0x00F00000 MCR p15,0,R1,c1,c0,2 - //Enable VFP + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + ISB + + //Enable VFP/NEON VMRS R1,FPEXC ORR R1,R1,#0x40000000 VMSR FPEXC,R1 - //Initialise VFP registers to 0 + //Initialise VFP/NEON registers to 0 MOV R2,#0 + //Initialise D16 registers to 0 VMOV D0, R2,R2 VMOV D1, R2,R2 VMOV D2, R2,R2 @@ -332,7 +352,23 @@ __asm void FPUEnable(void) { VMOV D13,R2,R2 VMOV D14,R2,R2 VMOV D15,R2,R2 - + //Initialise D32 registers to 0 + VMOV D16,R2,R2 + VMOV D17,R2,R2 + VMOV D18,R2,R2 + VMOV D19,R2,R2 + VMOV D20,R2,R2 + VMOV D21,R2,R2 + VMOV D22,R2,R2 + VMOV D23,R2,R2 + VMOV D24,R2,R2 + VMOV D25,R2,R2 + VMOV D26,R2,R2 + VMOV D27,R2,R2 + VMOV D28,R2,R2 + VMOV D29,R2,R2 + VMOV D30,R2,R2 + VMOV D31,R2,R2 //Initialise FPSCR to a known state VMRS R2,FPSCR LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. @@ -344,40 +380,71 @@ __asm void FPUEnable(void) { #pragma pop #elif defined(__GNUC__) -void FPUEnable(void) -{ - __asm__ __volatile__ ( - ".align 2 \n\t" - ".arm \n\t" - "mrc p15,0,r1,c1,c0,2 \n\t" - "orr r1,r1,#0x00f00000 \n\t" - "mcr p15,0,r1,c1,c0,2 \n\t" - "vmrs r1,fpexc \n\t" - "orr r1,r1,#0x40000000 \n\t" - "vmsr fpexc,r1 \n\t" - "mov r2,#0 \n\t" - "vmov d0, r2,r2 \n\t" - "vmov d1, r2,r2 \n\t" - "vmov d2, r2,r2 \n\t" - "vmov d3, r2,r2 \n\t" - "vmov d4, r2,r2 \n\t" - "vmov d5, r2,r2 \n\t" - "vmov d6, r2,r2 \n\t" - "vmov d7, r2,r2 \n\t" - "vmov d8, r2,r2 \n\t" - "vmov d9, r2,r2 \n\t" - "vmov d10,r2,r2 \n\t" - "vmov d11,r2,r2 \n\t" - "vmov d12,r2,r2 \n\t" - "vmov d13,r2,r2 \n\t" - "vmov d14,r2,r2 \n\t" - "vmov d15,r2,r2 \n\t" - "vmrs r2,fpscr \n\t" - "ldr r3,=0x00086060 \n\t" - "and r2,r2,r3 \n\t" - "vmsr fpscr,r2 \n\t" - "bx lr \n\t" - ); +void FPUEnable(void) { + __asm__ ( + ".ARM;" + + //Permit access to VFP/NEON, registers by modifying CPACR + "MRC p15,0,R1,c1,c0,2;" + "ORR R1,R1,#0x00F00000;" + "MCR p15,0,R1,c1,c0,2;" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + "ISB;" + + //Enable VFP/NEON + "VMRS R1,FPEXC;" + "ORR R1,R1,#0x40000000;" + "VMSR FPEXC,R1;" + + //Initialise VFP/NEON registers to 0 + "MOV R2,#0;" + //Initialise D16 registers to 0 + "VMOV D0, R2,R2;" + "VMOV D1, R2,R2;" + "VMOV D2, R2,R2;" + "VMOV D3, R2,R2;" + "VMOV D4, R2,R2;" + "VMOV D5, R2,R2;" + "VMOV D6, R2,R2;" + "VMOV D7, R2,R2;" + "VMOV D8, R2,R2;" + "VMOV D9, R2,R2;" + "VMOV D10,R2,R2;" + "VMOV D11,R2,R2;" + "VMOV D12,R2,R2;" + "VMOV D13,R2,R2;" + "VMOV D14,R2,R2;" + "VMOV D15,R2,R2;" + //Initialise D32 registers to 0 + "VMOV D16,R2,R2;" + "VMOV D17,R2,R2;" + "VMOV D18,R2,R2;" + "VMOV D19,R2,R2;" + "VMOV D20,R2,R2;" + "VMOV D21,R2,R2;" + "VMOV D22,R2,R2;" + "VMOV D23,R2,R2;" + "VMOV D24,R2,R2;" + "VMOV D25,R2,R2;" + "VMOV D26,R2,R2;" + "VMOV D27,R2,R2;" + "VMOV D28,R2,R2;" + "VMOV D29,R2,R2;" + "VMOV D30,R2,R2;" + "VMOV D31,R2,R2;" + + //Initialise FPSCR to a known state + "VMRS R2,FPSCR;" + "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + "AND R2,R2,R3;" + "VMSR FPSCR,R2;" + + //"BX LR;" + : + : + :"r1", "r2", "r3"); + return; } #else #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html index 2b50515c1c..185f5d2c67 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html @@ -653,7 +653,7 @@ ul

Release Notes for STM32F0xx HAL Drivers

Copyright -2014 STMicroelectronics

+2015 STMicroelectronics

@@ -665,8 +665,39 @@ Notes for STM32F0xx HAL Drivers

Update History

-

V1.2.0 -/ 11-December-2014

Main +

V1.3.0 +/ 26-June-2015

Main +Changes

  • Maintenance release to fix known defects and +enhancements implementation
  • Complete HAL API alignment (macro/function renaming)
  • HAL Generic
    • Update HAL drivers to be MISRA/C++ compliant.
    • Initialized handle lock in HAL_PPP_Init().
    • Add SYSCFG define macros to manage FM+ on GPIOs.
    • Use uint32_t instead of uint8_t/uint_16.
  • HAL ADC
    • Update ADC state machine. Missing state in function "HAL_ADCEx_Calibration_Start().
    • Align ADC_SOFTWARE_START literal on STM32L0xx.
    • HAL_ADC_PollForConversion(): update to return error status in case of ADC-DMA mode.
    • HAL_ADC_Init(): ADC resolution must be changed only when ADC is disabled.
    • ADC_ConversionStop(): correct wrong timeout value.
    • HAL_ADC_AnalogWDGConfig(): Add missing assert param.
    • Remove channel for monitoring VBAT power supply pin on F0 Value line devices.
    • Move +sampling time setting into ADC init stucture (keep setting into ADC +channel init stucture with comments of obsolete setting).
    • Move +__HAL_UNLOCK() before peripheral activation because if an interruption +occurs between ADC enable & __HAL_UNLOCK(), IRQ handler will be +executed while HAL still locked.
    • ADC_DMAConvCplt(): Add call to ADC error callback in case of error.
    • Rename local variables for compliancy with coding rules (tmpHALstatus ==> tmp_hal_status).
    • Simplify __HAL_ADC_GET_IT_SOURCE().
    • Add use of POSITION_VAL.
    • Add optimization of ADC stabilization delays.
  • HAL CAN 
    • Add management of CAN Slave start bank in HAL_CAN_ConfigFilter().
    • Unlock the CAN process when communication error occurred.
    • Replace uint32_t Data[8] by uint8_t Data[8] in structures  CanTxMsgTypeDef and CanRxMsgTypeDef.
  • HAL CEC 
    • Add new API HAL_CEC_GetReceivedFrameSize() to get size of received frame
  • HAL CORTEX 
    • Add new macro IS_NVIC_DEVICE_IRQ() to +check on negative values of IRQn parameter
  • HAL CRC 
    • Add new macros __HAL_CRC_GET_IDR() and __HAL_CRC_SET_IDR().
    • Update __HAL_CRC_SET_IDR macro in resorting to WRITE_REG instead of MODIFY_REG (cycles gain at execution).
  • HAL DAC 
    • HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and +DAC_FLAG_DMAUDR2.
  • HAL DMA
    • Correct __HAL_DMA_GET_IT_SOURCE brief comments.
  • HAL FLASH
    • FLASH_OB_GetRDP(): update function to return the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • FLASH_OB_RDP_LevelConfig(): update function to set the FLASH Read Protection level (OB_RDP_LEVEL_x).
    • Add missing macro __HAL_FLASH_GET_LATENCY.
    • Disable WRP not compliant with other family.
    • Add FLASH_BANK1_END defines.
    • Remove WRP defines for few defines under devices swicthes.
    • Add switch to handle option bits BOOT_SEL & nBOOT1 not present on STM32F030xC & STM32F070x6.
  • HAL GPIO 
    • stm32f0xx_hal_gpio_ex.h: add IR as possible GPIO alternate function 1 for STM32F030x6.
  • HAL I2C
    • HAL_I2C_ER_IRQHandler(): handle NACK test during wait on flag treatment.
  • HAL I2S
    • HAL_I2S_DMAStop(): Correctt DMA Stop function which stops both Rx and Tx channels regardless which one was set-up.
  • HAL IRDA
    • HAL_IRDA_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL PWR
    • Add macros __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() and __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE.
    • Update HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() comments.
  • HAL RCC
    • Implement workaround to cover RCC limitation regarding Peripheral enable delay.
    • HAL_RCC_OscConfig(): correct test on LSEState.
    • Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.
    • Add defines for RCC_System_Clock_Source_Status.
    • Follow specific procedure to enable HSE.
    • Add macros to get the enable or disable status of peripheral clock.
    • HAL_RCCEx_PeriphCLKConfig(): reset backup domain only if RTC clock source has been changed.
    • Add interface HAL_RCCEx_GetPeriphCLKFreq.
  • HAL RTC
    • Add missing RTC_FLAG_INIT in flag list.
    • HAL_RTC_DeInit(): add switch products condition around WakeUp timer registers (WUTWF,WUTR).
    • Remove RTC_FLAG_INIT as currently unused.
  • HAL SMARTCARD
    • Add missing IDLE flag management.
    • Align SMARTCARD_Last_Bit defines.
  • HAL SPI 
    • Fix issue related to missing reset of the Dma Tx callback inside the function HAL_SPI_TransmitReceive_DMA().
      In +that case only RX callback are used and the call of TX callback can +close the communication before the end of the RX processing.
    • SPI_2linesRxISR_8BIT(): +correct issue on RX 2lines with DataSize8bit, even buffer size and CRC +8bit (SPI_RXFIFO_THRESHOLD is not set).
    • Fit bit update add BSY flag check for all the process.
    • Add +__IO (volatile) to the "State" member of the SPI_HandleTypeDef +struct. to missing reset of the Dma Tx callback inside the +function +HAL_SPI_TransmitReceive_DMA().
  • HAL TIM
    • Add __HAL_TIM_SET_CAPTUREPOLARITY, TIM_SET_CAPTUREPOLARITY, TIM_RESET_CAPTUREPOLARITY macros.
  • HAL UART
    • Add macro to control CTS and RTS from the customer applications.
    • UART_DMATransmitCplt(): change implementation to remove WaitOnFlag in ISR.
    • Change DMA TX management to remove WaitOnFlag in ISR.
    • Add DMA circular mode support for the communication peripherals.
    • Add UART NVIC configuration in the HAL_UART_MspInit().
    • Add the UARTx_IRQHandler() in the stm32fxxx_it.c and the prototype in the stm32fxxx_it.h.
    • Modify UART DMA implementation issue (missed clear the TC bit in the SR).
    • Add a OVR flag clear prior resuming DMA RX transfer.
    • HAL_UART_DMAResume(): Remove UART_CheckIdleState() call and replace it by unlock + return(HAL_OK).
    • HAL_UART_DMAStop(): remove LOCK/UNLOCK calls.
    • HAL_UART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.
  • HAL USART
    • HAL_USART_IRQHandler(): Correct parameters values of __HAL_USART_CLEAR_IT().
    • Replace xxxITxxx defines by xxxCLEARxxxF defines in __HAL_USART_CLEAR_IT calls.
    • HAL_USART_Init(): update to reach max frequencies (enable oversampling by 8).
    • HAL_USART_DMAPause()/HAL_USART_DMAResume(): add of a OVR flag clear prior resuming DMA RX transfer.
    • HAL_USART_DMAResume(): Remove UART_CheckIdleState() call and replace it by just an Unlock + ret(HAL_OK).
    • HAL_USART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.

V1.2.1 +/ 09-January-2015

  • HAL 
    • stm32f0xx_hal.h: add missing define for USART3_RX/TX DMA remap on channel3 & channel2 for STM32F070xB only
  • HAL GPIO
    • stm32f0xx_hal_gpio_ex.h: add I2C1 as possible GPIO alternate function 3 for STM32F070xB
  • HAL RCC
    • stm32f0xx_hal_rcc_ex.h: add missing USART2_CLK_ENABLE/DISABLE() macros for STM32F070x6
  • HAL RTC +
    • stm32f0xx_hal_rtc_ex.h/.c: +Enable RTC periodic Wakeup timer feature on STM32F070xB +& STM32F030xC +
    • stm32f0xx_hal_rtc_ex.c: +remove HAL_RTCEx_Tamper3EventCallback() +API for STM32F070xB +& STM32F030xC, since +there is no TAMPER3 on those products.
    +
  • HAL UART +
    • stm32f0xx_hal_uart_ex.c/.h: +add HAL_RS485Ex_Init() API for STM32F0xx Value +Line devices

V1.2.0 +/ 05-December-2014

Main Changes

  • HAL generic 
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • HandleTypeDef.ErrorCode must be typed uint32_t
    • Update HAL drivers to ensure compliancy w/ C++
    • Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h
    • Case mismatch between #include typo and effective file name generating compiler errors under Linux
    • Correct various issues for documentation generation (group name, doxygen tags, etc..)
    • Missing support of I2C_PAx_FMP of F04xx devices

  • HAL ADC 

    • Improve HAL ADC comments
    • Correct issue observed with ADC start simultaneous commands
    • Remove macro __HAL_ADC_OFR_CHANNEL() since OFRx register is not available on F0 devices.
  • HAL CAN 
    • ErrorCode field is now declared as __IO uint32 instead of enum HAL_CAN_ErrorTypeDef to fix C++ compilation issue

  • HAL CEC 

    • change ErrorCode field declaration from uint32_t  to __IO uint32_t

    • correct CEC state: Ready to Receive state lost upon Transmission end

  • HAL COMP 
    • State field is now declared as uint32_t instead of enum HAL_COMP_StateTypeDef to fix C++ compilation issue
    • change HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t to fix C++ compilation issue

  • HAL CRC 

    • Wrong @ref in CRCLength field description for documentation generation 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.

  • HAL DAC 

    • HAL_DAC_Stop_DMA() code clean up

    • Use of internal macro MODIFY_REG() to update CR register

  • HAL DMA 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • DMA channel remap register renamed for compatibility with other STM32 devices.
    • Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description
  • HAL FLASH 
    • Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected
    • ErrorCode field is now declared as uint32 instead of enum FLASH_ErrorTypeDef to fix C++ compilation issue
    • change HAL_FLASH_GetError() type declaration from FLASH_ErrorTypeDef to uint32_t to fix C++ compilation issue
    • Clean the error context to FLASH_ERROR_NONE before starting new Flash operation
    • Put all the clear flags in the FLASH_SetSerrorCode()
    • Stop the programming procedure in case of error detected in HAL_FLASH_Program()
    • Check error before doing new procedure in HAL_FLASH_IRQhandler()

  • HAL GPIO 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • correct Typo in 'How to use this driver' section & update comments
    • Add assert on GPIO PIN in HAL_GPIO_DeInit()
    • Add assert on GPIO AF instance to protect HAL_GPIO_Init() from impossible AF configuration
    • Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX()
    • Reset Interrupt mode registers only in HAL_GPIO_DeInit()
  • HAL I2C
    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • ErrorCode field is now declared as uint32 instead of enum HAL_I2C_ErrorTypeDef to fix C++ compilation issue

  • HAL I2S 

    • ErrorCode field is now declared as uint32 instead of enum HAL_I2S_ErrorTypeDef to fix C++ compilation issue.
    • Change HAL_I2S_GetError() type declaration from HAL_I2S_ErrorTypeDef to uint32_t to fix C++ compilation issue.
    • Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() & __HAL_I2S_CLEAR_UDRFLAG to fix Unused variable" warning w/ TrueSTUDIO.
    • Typo in 'I2S HAL driver macros list' section of stm32f0xx_hal_i2s.c
    • Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation)

  • HAL IRDA 

    • ErrorCode field is now declared as uint32 instead of enum HAL_IRDA_ErrorTypeDef to fix C++ compilation issue
    • Missing doxygen tags for IRDA_HandleTypeDef fields description

  • HAL PWR 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register:
  • HAL_PWR_DisableSleepOnExit()
  • HAL_PWR_EnableSleepOnExit()
  • HAL_PWR_EnableSEVOnPend()
  • HAL_PWR_DisableSEVOnPend()
    • Removed useless regulator parameter setting for F0 family in core of HAL_PWR_EnterSLEEPMode()

  • HAL RCC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Add a comment in the 'How to use this driver' section to mention the Peripheral enable delay
    • Move __HAL_RCC_USART2_CONFIG() & __HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to stm32f0xx_hal_rcc_ex.h since this feature is not supported on all F0 devices
    • Change HAL_RCCEx_CRSWaitSynchronization() type declaration from RCC_CRSStatusTypeDef to uint32_t to fix C++ compilation issue

  • HAL RTC 

    • Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.
    • Enhance @note describing the use of HAL RTC APIs 
  • HAL SMARTCARD
    • ErrorCode field is now declared as uint32 instead of enum HAL_SMARTCARD_ErrorTypeDef to fix C++ compilation issue
  • HAL SMBUS
    • ErrorCode & PreviousState fields are now declared as uint32 instead of enum HAL_SMBUS_ErrorTypeDef & HAL_SMBUS_StateTypeDef to fix C++ compilation issue
    • Change HAL_SMBUS_GetState() type declaration from HAL_SMBUS_StateTypeDef to uint32_t to fix C++ compilation issue

  • HAL SPI 

    • ErrorCode field is now declared as uint32 instead of enum HAL_SPI_ErrorTypeDef to fix C++ compilation issue
    • Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix "Unused variable" warning w/ TrueSTUDIO.
    • Add DMA circular mode support on SPI HAL driver.
    • Internal fucntion renaming: HAL_SPI_DMATransmitCplt(), diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h index be4a7706f3..9fc73d11ef 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * A generic CMSIS include header ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c index 3a0d329f0b..d445227af3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -33,10 +33,10 @@ #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash -static unsigned char vtor_remap = 0; // To keep track that the vectors remap is done - void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { int i; + // To keep track that the vectors remap is done + static volatile uint32_t vtor_remap = 0; // Space for dynamic vectors, initialised to allocate in R/W static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h index ce6b91f7fb..570550abfd 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h index 3b3687105a..ebcd9cbaa5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f051x8.h * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS STM32F051x4/STM32F051x6/STM32F051x8 devices Peripheral Access * Layer Header File. * @@ -15,7 +15,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -60,7 +60,6 @@ /** @addtogroup Configuration_section_for_CMSIS * @{ */ - /** * @brief Configuration of the Cortex-M0 Processor and Core Peripherals */ @@ -284,14 +283,12 @@ typedef struct */ typedef struct { - __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ - __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ - __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ - __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ - __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ - __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ - __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */ - __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */ + __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ + __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ + __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ + __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ + __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ + __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ }OB_TypeDef; /** @@ -369,6 +366,7 @@ typedef struct /** * @brief Reset and Clock Control */ + typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ @@ -390,7 +388,6 @@ typedef struct /** * @brief Real-Time Clock */ - typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ @@ -426,24 +423,15 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ }SPI_TypeDef; /** @@ -535,6 +523,7 @@ typedef struct */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0800FFFF) /*!< FLASH END address of bank1 */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ @@ -556,6 +545,7 @@ typedef struct #define I2C2_BASE (APBPERIPH_BASE + 0x00005800) #define PWR_BASE (APBPERIPH_BASE + 0x00007000) #define DAC_BASE (APBPERIPH_BASE + 0x00007400) + #define CEC_BASE (APBPERIPH_BASE + 0x00007800) #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) @@ -642,7 +632,6 @@ typedef struct #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) - /** * @} */ @@ -782,7 +771,6 @@ typedef struct #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */ #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */ - /******************************************************************************/ /* */ /* HDMI-CEC (CEC) */ @@ -841,7 +829,6 @@ typedef struct #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */ #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */ - /******************************************************************************/ /* */ /* Analog Comparators (COMP) */ @@ -889,24 +876,24 @@ typedef struct #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ /* COMPx bits definition */ -#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */ -#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */ -#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */ -#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */ -#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */ -#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */ -#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */ -#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */ -#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */ -#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */ -#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */ -#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */ -#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */ -#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */ -#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */ -#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */ +#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */ +#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */ +#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */ +#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */ +#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */ +#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */ +#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */ +#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */ +#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */ +#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */ +#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */ +#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */ +#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */ +#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */ +#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */ +#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */ /******************************************************************************/ /* */ @@ -929,7 +916,6 @@ typedef struct /******************* Bit definition for CRC_INIT register *******************/ #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */ - /******************************************************************************/ /* */ /* Digital to Analog Converter (DAC) */ @@ -1266,8 +1252,8 @@ typedef struct #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ /****************** FLASH Keys **********************************************/ -#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ -#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 +#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 to unlock the write access to the FPEC. */ #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */ @@ -1302,12 +1288,13 @@ typedef struct #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */ -#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */ +#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */ #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */ +#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */ /* Old BOOT1 bit definition, maintained for legacy purpose */ #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 @@ -2181,16 +2168,6 @@ typedef struct #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */ -/*!< USART2 Clock source selection */ -#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */ -#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */ -#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */ -#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */ -#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */ - /******************* Bit definition for RCC_CR2 register *******************/ #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */ #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */ @@ -2566,6 +2543,7 @@ typedef struct #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */ #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */ + #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */ #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */ #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */ @@ -2578,173 +2556,174 @@ typedef struct #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */ #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */ + /***************** Bit definition for SYSCFG_EXTICR1 register **************/ -#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ +#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register **************/ -#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ +#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register **************/ -#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ +#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register **************/ -#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ +#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */ /***************** Bit definition for SYSCFG_CFGR2 register ****************/ #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ @@ -3497,13 +3476,15 @@ typedef struct ((INSTANCE) == DMA1_Channel5)) /****************************** GPIO Instances ********************************/ -#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ - ((INSTANCE) == GPIOB) || \ - ((INSTANCE) == GPIOC) || \ - ((INSTANCE) == GPIOD) || \ - ((INSTANCE) == GPIOF)) +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOF)) + +#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB)) -/****************************** GPIO Lock Instances ****************************/ #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ ((INSTANCE) == GPIOB)) @@ -3767,7 +3748,6 @@ typedef struct /****************** UART Instances : Driver enable detection ********************/ #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) - /****************************** WWDG Instances ********************************/ #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h index 8dee1e5415..e54731d4ff 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h @@ -2,10 +2,10 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. - * + * * The file is the unique include file that the application programmer * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: @@ -14,11 +14,11 @@ * code will be based on direct access to peripherals registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" - * + * ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,21 +59,28 @@ #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ - + /** @addtogroup Library_configuration_section * @{ */ +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ + /* Uncomment the line below according to the target STM32 device used in your application */ #if !defined (STM32F030x6) && !defined (STM32F030x8) && \ !defined (STM32F031x6) && !defined (STM32F038xx) && \ - !defined (STM32F042x6) && !defined (STM32F048xx) && \ + !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ !defined (STM32F051x8) && !defined (STM32F058xx) && \ - !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \ - !defined (STM32F091xC) && !defined (STM32F098xx) + !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ + !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ @@ -82,13 +89,16 @@ /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */ #define STM32F051x8 /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ + /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */ /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ #endif - + /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ @@ -102,11 +112,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.1.0 - */ + * @brief CMSIS Device version number V2.2.2 + */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ -#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ @@ -137,6 +147,10 @@ #include "stm32f051x8.h" #elif defined(STM32F058xx) #include "stm32f058xx.h" +#elif defined(STM32F070x6) + #include "stm32f070x6.h" +#elif defined(STM32F070xB) + #include "stm32f070xb.h" #elif defined(STM32F071xB) #include "stm32f071xb.h" #elif defined(STM32F072xB) @@ -146,7 +160,9 @@ #elif defined(STM32F091xC) #include "stm32f091xc.h" #elif defined(STM32F098xx) - #include "stm32f098xx.h" + #include "stm32f098xx.h" +#elif defined(STM32F030xC) + #include "stm32f030xc.h" #else #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" #endif @@ -157,7 +173,7 @@ /** @addtogroup Exported_types * @{ - */ + */ typedef enum { RESET = 0, @@ -177,7 +193,7 @@ typedef enum SUCCESS = !ERROR } ErrorStatus; -/** +/** * @} */ @@ -186,13 +202,13 @@ typedef enum * @{ */ #define SET_BIT(REG, BIT) ((REG) |= (BIT)) - + #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) #define READ_BIT(REG, BIT) ((REG) & (BIT)) #define CLEAR_REG(REG) ((REG) = (0x0)) - + #define WRITE_REG(REG, VAL) ((REG) = (VAL)) #define READ_REG(REG) ((REG)) @@ -203,7 +219,7 @@ typedef enum /** * @} */ - + #if defined (USE_HAL_DRIVER) #include "stm32f0xx_hal.h" #endif /* USE_HAL_DRIVER */ @@ -217,11 +233,11 @@ typedef enum /** * @} */ - + /** * @} */ - + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c index 164d05f195..20d2cced2e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c @@ -2,18 +2,18 @@ ****************************************************************************** * @file system_stm32f0xx.c * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. * - * 1. This file provides two functions and one global variable to be called from - * user application: + * 1. This file provides two functions and one global variable to be called from + * user application: * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f0xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must @@ -42,7 +42,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -75,8 +75,8 @@ /** @addtogroup stm32f0xx_system * @{ - */ - + */ + /** @addtogroup STM32F0xx_System_Private_Includes * @{ */ @@ -107,6 +107,7 @@ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ + /** * @} */ @@ -134,7 +135,8 @@ call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ -uint32_t SystemCoreClock = 48000000; +uint32_t SystemCoreClock = 48000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** @@ -166,7 +168,7 @@ uint8_t SetSysClock_PLL_HSI(void); * @retval None */ void SystemInit(void) -{ +{ /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; @@ -191,15 +193,31 @@ void SystemInit(void) /* Reset PREDIV[3:0] bits */ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB) - /* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ +#if defined (STM32F072xB) || defined (STM32F078xx) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; +#elif defined (STM32F071xB) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFCEAC; #elif defined (STM32F091xC) || defined (STM32F098xx) - /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFF0FFAC; -#else - /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; +#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) + /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEEC; +#elif defined (STM32F051x8) || defined (STM32F058xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; +#elif defined (STM32F042x6) || defined (STM32F048xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ RCC->CFGR3 &= (uint32_t)0xFFFFFE2C; +#elif defined (STM32F070x6) || defined (STM32F070xB) + /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE6C; + /* Set default USB clock to PLLCLK, since there is no HSI48 */ + RCC->CFGR3 |= (uint32_t)0x00000080; +#else + #warning "No target selected" #endif /* Reset HSI14 bit */ @@ -207,14 +225,6 @@ void SystemInit(void) /* Disable all interrupts */ RCC->CIR = 0x00000000; - - /* Configure the Cube driver */ - SystemCoreClock = 8000000; // At this stage the HSI is used as system clock - HAL_Init(); - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings */ - SetSysClock(); } /** @@ -225,16 +235,16 @@ void SystemInit(void) * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. + * based on this variable will be incorrect. * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * + * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @@ -259,7 +269,7 @@ void SystemCoreClockUpdate (void) /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; - + switch (tmp) { case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ @@ -274,7 +284,7 @@ void SystemCoreClockUpdate (void) pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; pllmull = ( pllmull >> 18) + 2; predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; - + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) { /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ @@ -289,14 +299,18 @@ void SystemCoreClockUpdate (void) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ else { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; #else /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; -#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ - } +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } break; default: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; @@ -306,7 +320,7 @@ void SystemCoreClockUpdate (void) /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK clock frequency */ - SystemCoreClock >>= tmp; + SystemCoreClock >>= tmp; } /** @@ -339,7 +353,7 @@ void SetSysClock(void) } } } - + // Output clock on MCO pin(PA8) for debugging purpose //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz } @@ -350,25 +364,32 @@ void SetSysClock(void) /******************************************************************************/ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + //Select HSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + // Select HSE oscillator as PLL source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT } else { RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only } - RCC_OscInitStruct.HSI48State = 0; // not used RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL - } - + } + // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz @@ -376,9 +397,11 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { return 0; // FAIL - } - - return 1; // OK + } + +// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz + + return 1; // OK } #endif @@ -389,10 +412,10 @@ uint8_t SetSysClock_PLL_HSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; - + // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; @@ -400,7 +423,7 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - + // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz @@ -410,6 +433,8 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz + return 1; // OK } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h index 00f7ba2efd..73912666f9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf index ba742ac296..1c5f98b6f3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf @@ -1,31 +1,34 @@ -/* [ROM = 64kb = 0x10000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x0800FFFF; - +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; /* [RAM = 8kb = 0x2000] Vector table dynamic copy: 45 vectors = 180 bytes (0xB4) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200000B7; /* Add 4 more bytes to be aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x200000B8; -define symbol __region_RAM_end__ = 0x20001FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000B8; /* Add 4 more bytes after NVIC section to be aligned on 8 bytes */ +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ -/* Memory regions */ define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -/* Stack and Heap */ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __size_cstack__ = 0x400; -define symbol __size_heap__ = 0x800; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -initialize by copy with packing = zeros { readwrite }; +initialize by copy { readwrite }; do not initialize { section .noinit }; -place at address mem:__intvec_start__ { readonly section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h index 8cab6e21c4..30d7413c01 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f030x8.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS STM32F030x8 devices Peripheral Access Layer Header File. * * This file contains: @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,7 +59,6 @@ /** @addtogroup Configuration_section_for_CMSIS * @{ */ - /** * @brief Configuration of the Cortex-M0 Processor and Core Peripherals */ @@ -236,14 +235,12 @@ typedef struct */ typedef struct { - __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ - __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ - __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ - __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ - __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ - __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ - __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */ - __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */ + __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ + __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ + __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ + __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ + __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ + __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ }OB_TypeDef; /** @@ -321,6 +318,7 @@ typedef struct /** * @brief Reset and Clock Control */ + typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ @@ -342,7 +340,6 @@ typedef struct /** * @brief Real-Time Clock */ - typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ @@ -410,7 +407,6 @@ typedef struct __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ }TIM_TypeDef; - /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ @@ -451,6 +447,7 @@ typedef struct */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0800FFFF) /*!< FLASH END address of bank1 */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ @@ -545,7 +542,6 @@ typedef struct #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) - /** * @} */ @@ -681,7 +677,6 @@ typedef struct #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */ #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */ #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */ @@ -994,8 +989,8 @@ typedef struct #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ /****************** FLASH Keys **********************************************/ -#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ -#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 +#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 to unlock the write access to the FPEC. */ #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */ @@ -1030,12 +1025,13 @@ typedef struct #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */ -#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */ +#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */ #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */ +#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */ /* Old BOOT1 bit definition, maintained for legacy purpose */ #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 @@ -1560,6 +1556,7 @@ typedef struct /******************* Bit definition for PWR_CSR register *******************/ #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */ #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */ + #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */ #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */ @@ -1873,16 +1870,6 @@ typedef struct #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */ #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */ -/*!< USART2 Clock source selection */ -#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */ -#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */ -#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */ -#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */ -#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */ - /******************* Bit definition for RCC_CR2 register *******************/ #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */ #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */ @@ -2240,6 +2227,7 @@ typedef struct #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */ #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */ + #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */ #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */ #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */ @@ -2252,173 +2240,174 @@ typedef struct #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */ #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */ + /***************** Bit definition for SYSCFG_EXTICR1 register **************/ -#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ +#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register **************/ -#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ +#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register **************/ -#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ +#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register **************/ -#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ +#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */ /***************** Bit definition for SYSCFG_CFGR2 register ****************/ #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ @@ -2724,7 +2713,6 @@ typedef struct #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!
      © COPYRIGHT(c) 2014 STMicroelectronics
      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,6 +63,13 @@ /** @addtogroup Library_configuration_section * @{ */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ /* Uncomment the line below according to the target STM32 device used in your application @@ -105,11 +112,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.2.0 + * @brief CMSIS Device version number V2.2.2 */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c index dd37dffd05..bc1f5e0eab 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f0xx.c * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from @@ -42,7 +42,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -107,6 +107,7 @@ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ + /** * @} */ @@ -192,7 +193,7 @@ void SystemInit(void) /* Reset PREDIV[3:0] bits */ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; -#if defined (STM32F072xB) || defined (STM32F078xB) +#if defined (STM32F072xB) || defined (STM32F078xx) /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; #elif defined (STM32F071xB) @@ -224,14 +225,6 @@ void SystemInit(void) /* Disable all interrupts */ RCC->CIR = 0x00000000; - - /* Configure the Cube driver */ - SystemCoreClock = 8000000; // At this stage the HSI is used as system clock - HAL_Init(); - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings */ - SetSysClock(); } /** @@ -306,9 +299,9 @@ void SystemCoreClockUpdate (void) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ else { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; #else @@ -362,7 +355,7 @@ void SetSysClock(void) } // Output clock on MCO pin(PA8) for debugging purpose - //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz } #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) @@ -371,17 +364,24 @@ void SetSysClock(void) /******************************************************************************/ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + //Select HSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + // Select HSE oscillator as PLL source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT } else { RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only } - RCC_OscInitStruct.HSI48State = 0; // not used RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; @@ -399,6 +399,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz + return 1; // OK } #endif @@ -413,7 +415,7 @@ uint8_t SetSysClock_PLL_HSI(void) // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; @@ -431,6 +433,8 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz + return 1; // OK } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h index 7647daf2c2..73912666f9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s new file mode 100644 index 0000000000..a6eea51afd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s @@ -0,0 +1,226 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20001000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct new file mode 100644 index 0000000000..e8afe05f15 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 32KB FLASH (0x8000) + 4KB RAM (0x1000) + + LR_IROM1 0x08000000 0x8000 { ; load region size_region + ER_IROM1 0x08000000 0x8000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + +; 44 vectors = 176 bytes (0xB0) to be reserved in RAM + RW_IRAM1 (0x20000000+0xB0) (0x1000-0xB0) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s new file mode 100644 index 0000000000..757a90de99 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s @@ -0,0 +1,199 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20001000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/stm32f0xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/stm32f0xx.sct new file mode 100644 index 0000000000..e8afe05f15 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/stm32f0xx.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 32KB FLASH (0x8000) + 4KB RAM (0x1000) + + LR_IROM1 0x08000000 0x8000 { ; load region size_region + ER_IROM1 0x08000000 0x8000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + +; 44 vectors = 176 bytes (0xB0) to be reserved in RAM + RW_IRAM1 (0x20000000+0xB0) (0x1000-0xB0) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/STM32F031X6.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/STM32F031X6.ld new file mode 100644 index 0000000000..25bdcb5a63 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/STM32F031X6.ld @@ -0,0 +1,153 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32k + RAM (xrw) : ORIGIN = 0x200000B0, LENGTH = 4k - 0x0B0 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s new file mode 100644 index 0000000000..5984c47c93 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s @@ -0,0 +1,279 @@ +/** + ****************************************************************************** + * @file startup_stm32f031x6.s + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief STM32F031x4/STM32F031x6 devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ +// bl main + bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* Reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word 0 /* Reserved */ + .word USART1_IRQHandler /* USART1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_IAR/startup_stm32f031x6.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_IAR/startup_stm32f031x6.s new file mode 100644 index 0000000000..c02773e1ac --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_IAR/startup_stm32f031x6.s @@ -0,0 +1,272 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address, +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;*

      © COPYRIGHT(c) 2015 STMicroelectronics

      +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_IAR/stm32f031x6.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_IAR/stm32f031x6.icf new file mode 100644 index 0000000000..c0345cf3e8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_IAR/stm32f031x6.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x08007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000B0; +define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis.h new file mode 100644 index 0000000000..9fc73d11ef --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f0xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis_nvic.c new file mode 100644 index 0000000000..634d04d8cd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis_nvic.c @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + int i; + // To keep track that the vectors remap is done + static volatile uint32_t vtor_remap = 0; + // Space for dynamic vectors, initialised to allocate in R/W + static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; + + // Copy and switch to dynamic vectors if first time called + if (vtor_remap == 0) { + uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; + for (i = 0; i < NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000 + vtor_remap = 1; // The vectors remap is done + } + + // Set the vector + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + // Return the vector + return vectors[IRQn + 16]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis_nvic.h new file mode 100644 index 0000000000..5f887e1eb6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis_nvic.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F031K6 +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 28 vectors = 112 bytes from 0x40 to 0xAF +// Total: 44 vectors = 176 bytes (0xB0) to be reserved in RAM +#define NVIC_NUM_VECTORS 44 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/hal_tick.c new file mode 100644 index 0000000000..3512124dbd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/hal_tick.c @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Update the SystemCoreClock variable + SystemCoreClockUpdate(); + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 s tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/hal_tick.h new file mode 100644 index 0000000000..3c5285a9e3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stm32f0xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __TIM2_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f031x6.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f031x6.h new file mode 100644 index 0000000000..17852205f1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f031x6.h @@ -0,0 +1,3248 @@ +/** + ****************************************************************************** + * @file stm32f031x6.h + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief CMSIS STM32F031x4/STM32F031x6 devices Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f031x6 + * @{ + */ + +#ifndef __STM32F031x6_H +#define __STM32F031x6_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F031x4/STM32F031x6 device Interrupt Number Definition + */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** STM32F031x4/STM32F031x6 specific Interrupt Numbers **************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD Interrupts through EXTI Lines 16 */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 global Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + USART1_IRQn = 27 /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_stm32f0xx.h" /* STM32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ + __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ + __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ +}ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; +}ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +}CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +}DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +}DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
      © COPYRIGHT(c) 2015 STMicroelectronics
      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0xx_H +#define __STM32F0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ + !defined (STM32F031x6) && !defined (STM32F038xx) && \ + !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ + !defined (STM32F051x8) && !defined (STM32F058xx) && \ + !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ + !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) + /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ + #define STM32F031x6 /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ + /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ + /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ + /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */ + /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.2.2 + */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ + |(__CMSIS_DEVICE_HAL_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F030x6) + #include "stm32f030x6.h" +#elif defined(STM32F030x8) + #include "stm32f030x8.h" +#elif defined(STM32F031x6) + #include "stm32f031x6.h" +#elif defined(STM32F038xx) + #include "stm32f038xx.h" +#elif defined(STM32F042x6) + #include "stm32f042x6.h" +#elif defined(STM32F048xx) + #include "stm32f048xx.h" +#elif defined(STM32F051x8) + #include "stm32f051x8.h" +#elif defined(STM32F058xx) + #include "stm32f058xx.h" +#elif defined(STM32F070x6) + #include "stm32f070x6.h" +#elif defined(STM32F070xB) + #include "stm32f070xb.h" +#elif defined(STM32F071xB) + #include "stm32f071xb.h" +#elif defined(STM32F072xB) + #include "stm32f072xb.h" +#elif defined(STM32F078xx) + #include "stm32f078xx.h" +#elif defined(STM32F091xC) + #include "stm32f091xc.h" +#elif defined(STM32F098xx) + #include "stm32f098xx.h" +#elif defined(STM32F030xC) + #include "stm32f030xc.h" +#else + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c new file mode 100644 index 0000000000..7447a175d7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c @@ -0,0 +1,455 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. This file configures the system clock as follows: + *============================================================================= + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 48 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 48 | 48 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 48 | 48 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 48 | 48 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | YES | YES + *============================================================================= + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (1) /* Use external clock */ +#define USE_PLL_HSE_XTAL (0) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock there is no need to + call the 2 first functions listed above, since SystemCoreClock variable is + updated automatically. + */ +uint32_t SystemCoreClock = 48000000; + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + +#if defined (STM32F051x8) || defined (STM32F058x8) + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80C; +#else + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ + RCC->CFGR &= (uint32_t)0x08FFB80C; +#endif /* STM32F051x8 or STM32F058x8 */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFF; + + /* Reset PREDIV[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + +#if defined (STM32F072xB) || defined (STM32F078xx) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; +#elif defined (STM32F071xB) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFCEAC; +#elif defined (STM32F091xC) || defined (STM32F098xx) + /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; +#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) + /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEEC; +#elif defined (STM32F051x8) || defined (STM32F058xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; +#elif defined (STM32F042x6) || defined (STM32F048xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE2C; +#elif defined (STM32F070x6) || defined (STM32F070xB) + /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE6C; + /* Set default USB clock to PLLCLK, since there is no HSI48 */ + RCC->CFGR3 |= (uint32_t)0x00000080; +#else + #warning "No target selected" +#endif + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFE; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ + SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + // Output clock on MCO pin(PA8) for debugging purpose + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + //Select HSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + + + // Select HSE oscillator as PLL source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + return 0; // FAIL + } + +// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + return 0; // FAIL + } + + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.h new file mode 100644 index 0000000000..73912666f9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.h @@ -0,0 +1,123 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.h + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.s new file mode 100644 index 0000000000..25c8f93530 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.s @@ -0,0 +1,267 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f042x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20001800 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + + + + LDR R0, =__initial_sp ; set stack pointer + MSR MSP, R0 + +;;Check if boot space corresponds to test memory + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + +;; SYSCFG clock enable + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +;; Set CFGR1 register with flash memory remap at address 0 + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_CAN_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct new file mode 100644 index 0000000000..1a52debd8a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 32KB FLASH (0x8000) + 6KB RAM (0x1800) + + LR_IROM1 0x08000000 0x8000 { ; load region size_region + ER_IROM1 0x08000000 0x8000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + +; 48 vectors = 192 bytes (0xC0) to be reserved in RAM + RW_IRAM1 (0x20000000+0xC0) (0x1800-0xC0) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_STD/startup_stm32f042x6.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_STD/startup_stm32f042x6.s new file mode 100644 index 0000000000..0144877486 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_STD/startup_stm32f042x6.s @@ -0,0 +1,240 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f042x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20001800 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + + + + LDR R0, =__initial_sp ; set stack pointer + MSR MSP, R0 + +;;Check if boot space corresponds to test memory + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + +;; SYSCFG clock enable + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +;; Set CFGR1 register with flash memory remap at address 0 + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_CAN_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_STD/stm32f0xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_STD/stm32f0xx.sct new file mode 100644 index 0000000000..1a52debd8a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_STD/stm32f0xx.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 32KB FLASH (0x8000) + 6KB RAM (0x1800) + + LR_IROM1 0x08000000 0x8000 { ; load region size_region + ER_IROM1 0x08000000 0x8000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + +; 48 vectors = 192 bytes (0xC0) to be reserved in RAM + RW_IRAM1 (0x20000000+0xC0) (0x1800-0xC0) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_GCC_ARM/STM32F042X6.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_GCC_ARM/STM32F042X6.ld new file mode 100644 index 0000000000..c3372ab4a3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_GCC_ARM/STM32F042X6.ld @@ -0,0 +1,153 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32k + RAM (xrw) : ORIGIN = 0x200000C0, LENGTH = 6k - 0x0C0 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s new file mode 100644 index 0000000000..caf8f926d8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s @@ -0,0 +1,326 @@ +/** + ****************************************************************************** + * @file startup_stm32f042x6.s + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief STM32F042x4/STM32F042x6 devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/*Check if boot space corresponds to test memory*/ + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + MOVS R1, #0 + MOVS R2, #1 + CMP R1, R2 + BNE ApplicationStart + + /*SYSCFG clock enable*/ + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +/*Set CFGR1 register with flash memory remap at address 0*/ + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] + +ApplicationStart: +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ +// bl main + bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC and CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word TSC_IRQHandler /* TSC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word CEC_CAN_IRQHandler /* CEC and CAN */ + .word USB_IRQHandler /* USB */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_IAR/startup_stm32f042x6.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_IAR/startup_stm32f042x6.s new file mode 100644 index 0000000000..8cde7360b8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_IAR/startup_stm32f042x6.s @@ -0,0 +1,323 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f042x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address, +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;*

      © COPYRIGHT(c) 2015 STMicroelectronics

      +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =sfe(CSTACK) ; set stack pointer + MSR MSP, R0 + +;;Check if boot space corresponds to test memory + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart +;; SYSCFG clock enable + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +;; Set CFGR1 register with flash memory remap at address 0 + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK CEC_CAN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_CAN_IRQHandler + B CEC_CAN_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_IAR/stm32f042x6.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_IAR/stm32f042x6.icf new file mode 100644 index 0000000000..fc9e00ca52 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/TOOLCHAIN_IAR/stm32f042x6.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x08007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0; +define symbol __ICFEDIT_region_RAM_end__ = 0x200017FF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/cmsis.h new file mode 100644 index 0000000000..9fc73d11ef --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f0xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/cmsis_nvic.c new file mode 100644 index 0000000000..634d04d8cd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/cmsis_nvic.c @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + int i; + // To keep track that the vectors remap is done + static volatile uint32_t vtor_remap = 0; + // Space for dynamic vectors, initialised to allocate in R/W + static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; + + // Copy and switch to dynamic vectors if first time called + if (vtor_remap == 0) { + uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; + for (i = 0; i < NVIC_NUM_VECTORS; i++) { + vectors[i] = old_vectors[i]; + } + SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000 + vtor_remap = 1; // The vectors remap is done + } + + // Set the vector + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + // Return the vector + return vectors[IRQn + 16]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/cmsis_nvic.h new file mode 100644 index 0000000000..75bb632dba --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/cmsis_nvic.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F042K6 +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF +// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM +#define NVIC_NUM_VECTORS 48 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/hal_tick.c new file mode 100644 index 0000000000..3512124dbd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/hal_tick.c @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Update the SystemCoreClock variable + SystemCoreClockUpdate(); + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 s tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/hal_tick.h new file mode 100644 index 0000000000..3c5285a9e3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stm32f0xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __TIM2_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f042x6.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f042x6.h new file mode 100644 index 0000000000..3a4853f45d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/stm32f042x6.h @@ -0,0 +1,5307 @@ +/** + ****************************************************************************** + * @file stm32f042x6.h + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief CMSIS STM32F042x4/STM32F042x6 Devices Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f042x6 + * @{ + */ + +#ifndef __STM32F042x6_H +#define __STM32F042x6_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0 Processor and Core Peripherals + */ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ +#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F042x4/STM32F042x6 device Interrupt Number Definition + */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** STM32F042x4/STM32F042x6 specific Interrupt Numbers **************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */ + RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC & CRS Global Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupt */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ + USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_stm32f0xx.h" /* STM32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ + __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ + __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ +}ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; +}ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +}CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +}CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +}CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +}CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +}CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +}CRS_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +}DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +}DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
      © COPYRIGHT(c) 2015 STMicroelectronics
      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx + * @{ + */ + +#ifndef __STM32F0xx_H +#define __STM32F0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F030x6) && !defined (STM32F030x8) && \ + !defined (STM32F031x6) && !defined (STM32F038xx) && \ + !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \ + !defined (STM32F051x8) && !defined (STM32F058xx) && \ + !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \ + !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC) + /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */ + #define STM32F042x6 /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */ + /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */ + /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */ + /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */ + /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */ + /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */ + /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */ + /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */ + /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.2.2 + */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ + |(__CMSIS_DEVICE_HAL_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F030x6) + #include "stm32f030x6.h" +#elif defined(STM32F030x8) + #include "stm32f030x8.h" +#elif defined(STM32F031x6) + #include "stm32f031x6.h" +#elif defined(STM32F038xx) + #include "stm32f038xx.h" +#elif defined(STM32F042x6) + #include "stm32f042x6.h" +#elif defined(STM32F048xx) + #include "stm32f048xx.h" +#elif defined(STM32F051x8) + #include "stm32f051x8.h" +#elif defined(STM32F058xx) + #include "stm32f058xx.h" +#elif defined(STM32F070x6) + #include "stm32f070x6.h" +#elif defined(STM32F070xB) + #include "stm32f070xb.h" +#elif defined(STM32F071xB) + #include "stm32f071xb.h" +#elif defined(STM32F072xB) + #include "stm32f072xb.h" +#elif defined(STM32F078xx) + #include "stm32f078xx.h" +#elif defined(STM32F091xC) + #include "stm32f091xc.h" +#elif defined(STM32F098xx) + #include "stm32f098xx.h" +#elif defined(STM32F030xC) + #include "stm32f030xc.h" +#else + #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c new file mode 100644 index 0000000000..32d79092f4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c @@ -0,0 +1,455 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. This file configures the system clock as follows: + *============================================================================= + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 48 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 48 | 48 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 48 | 48 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 48 | 48 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | YES | YES + *============================================================================= + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "stm32f0xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (1) /* Use external clock */ +#define USE_PLL_HSE_XTAL (0) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock there is no need to + call the 2 first functions listed above, since SystemCoreClock variable is + updated automatically. + */ +uint32_t SystemCoreClock = 48000000; + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + +#if defined (STM32F051x8) || defined (STM32F058x8) + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80C; +#else + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ + RCC->CFGR &= (uint32_t)0x08FFB80C; +#endif /* STM32F051x8 or STM32F058x8 */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFF; + + /* Reset PREDIV[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + +#if defined (STM32F072xB) || defined (STM32F078xx) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; +#elif defined (STM32F071xB) + /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFCEAC; +#elif defined (STM32F091xC) || defined (STM32F098xx) + /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; +#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) + /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEEC; +#elif defined (STM32F051x8) || defined (STM32F058xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; +#elif defined (STM32F042x6) || defined (STM32F048xx) + /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE2C; +#elif defined (STM32F070x6) || defined (STM32F070xB) + /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFE6C; + /* Set default USB clock to PLLCLK, since there is no HSI48 */ + RCC->CFGR3 |= (uint32_t)0x00000080; +#else + #warning "No target selected" +#endif + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFE; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ + SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; + } +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + // Output clock on MCO pin(PA8) for debugging purpose + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + //Select HSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + + + // Select HSE oscillator as PLL source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + return 0; // FAIL + } + +// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + // Select PLLCLK = 48 MHz ((HSI 8 MHz) * 6) + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + return 0; // FAIL + } + + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.h new file mode 100644 index 0000000000..73912666f9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.h @@ -0,0 +1,123 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.h + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F0XX_H +#define __SYSTEM_STM32F0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf index 2a2b853d40..b7bf91b562 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf @@ -1,31 +1,33 @@ -/* [ROM = 128kb = 0x20000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x0801FFFF; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ -/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x200000C0; -define symbol __region_RAM_end__ = 0x20003FFF; - -/* Memory regions */ define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -/* Stack and Heap */ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __size_cstack__ = 0x800; -define symbol __size_heap__ = 0x1000; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -initialize by copy with packing = zeros { readwrite }; +initialize by copy { readwrite }; do not initialize { section .noinit }; -place at address mem:__intvec_start__ { readonly section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h index be4a7706f3..9fc73d11ef 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * A generic CMSIS include header ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c index 1253c2d50b..6b3ce72fd3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -33,21 +33,21 @@ #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash -int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done - void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { int i; + // To keep track that the vectors remap is done + static volatile uint32_t vtor_remap = 0; // Space for dynamic vectors, initialised to allocate in R/W - uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; + static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; // Copy and switch to dynamic vectors if first time called - if (NVIC_vtor_remap == 0) { + if (vtor_remap == 0) { uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; for (i = 0; i < NVIC_NUM_VECTORS; i++) { vectors[i] = old_vectors[i]; } SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000 - NVIC_vtor_remap = 1; // The vectors remap is done + vtor_remap = 1; // The vectors remap is done } // Set the vector diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h index 027dd9f78a..63246b8025 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h index 5313b9d71d..fc1384025f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f070xb.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS STM32F070xB devices Peripheral Access Layer Header File. * * This file contains: @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,7 +59,6 @@ /** @addtogroup Configuration_section_for_CMSIS * @{ */ - /** * @brief Configuration of the Cortex-M0 Processor and Core Peripherals */ @@ -324,6 +323,7 @@ typedef struct /** * @brief Reset and Clock Control */ + typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ @@ -345,7 +345,6 @@ typedef struct /** * @brief Real-Time Clock */ - typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ @@ -353,10 +352,10 @@ typedef struct __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ @@ -492,6 +491,7 @@ typedef struct */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ @@ -730,7 +730,6 @@ typedef struct #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ /******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */ #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */ #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */ @@ -1050,8 +1049,8 @@ typedef struct #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ /****************** FLASH Keys **********************************************/ -#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ -#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 +#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 to unlock the write access to the FPEC. */ #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */ @@ -1086,12 +1085,13 @@ typedef struct #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */ -#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */ +#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */ #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */ +#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */ /* Old BOOT1 bit definition, maintained for legacy purpose */ #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 @@ -2053,11 +2053,16 @@ typedef struct #define RTC_CR_TSIE ((uint32_t)0x00008000) #define RTC_CR_ALRAIE ((uint32_t)0x00001000) #define RTC_CR_TSE ((uint32_t)0x00000800) +#define RTC_CR_WUTE ((uint32_t)0x00000400) #define RTC_CR_ALRAE ((uint32_t)0x00000100) #define RTC_CR_FMT ((uint32_t)0x00000040) #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) #define RTC_CR_REFCKON ((uint32_t)0x00000010) #define RTC_CR_TSEDGE ((uint32_t)0x00000008) +#define RTC_CR_WUCKSEL ((uint32_t)0x00000007) +#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) +#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) +#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) /******************** Bits definition for RTC_ISR register *****************/ #define RTC_ISR_RECALPF ((uint32_t)0x00010000) @@ -2065,18 +2070,23 @@ typedef struct #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) #define RTC_ISR_TSOVF ((uint32_t)0x00001000) #define RTC_ISR_TSF ((uint32_t)0x00000800) +#define RTC_ISR_WUTF ((uint32_t)0x00000400) #define RTC_ISR_ALRAF ((uint32_t)0x00000100) #define RTC_ISR_INIT ((uint32_t)0x00000080) #define RTC_ISR_INITF ((uint32_t)0x00000040) #define RTC_ISR_RSF ((uint32_t)0x00000020) #define RTC_ISR_INITS ((uint32_t)0x00000010) #define RTC_ISR_SHPF ((uint32_t)0x00000008) +#define RTC_ISR_WUTWF ((uint32_t)0x00000004) #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /******************** Bits definition for RTC_PRER register ****************/ #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) +/******************** Bits definition for RTC_WUTR register ****************/ +#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) + /******************** Bits definition for RTC_ALRMAR register **************/ #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) @@ -2306,187 +2316,189 @@ typedef struct #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */ #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */ -#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */ + +#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x04001F00) /*!< DMA remap mask */ #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */ #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */ #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */ #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */ #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */ +#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */ #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */ #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */ #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */ #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */ #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ -#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */ + /***************** Bit definition for SYSCFG_EXTICR1 register **************/ -#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ +#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register **************/ -#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ +#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register **************/ -#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ +#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register **************/ -#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ +#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */ /***************** Bit definition for SYSCFG_CFGR2 register ****************/ #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ @@ -3140,6 +3152,7 @@ typedef struct #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ ((INSTANCE) == I2C2)) + /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) @@ -3361,6 +3374,11 @@ typedef struct #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2)) +/****************** UART Instances : Driver enable detection ********************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3) || \ + ((INSTANCE) == USART4)) /****************************** USB Instances ********************************/ #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h index 7c60f8808b..e36efab33f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File. * * The file is the unique include file that the application programmer @@ -18,7 +18,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,6 +63,13 @@ /** @addtogroup Library_configuration_section * @{ */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ /* Uncomment the line below according to the target STM32 device used in your application @@ -105,11 +112,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.2.0 + * @brief CMSIS Device version number V2.2.2 */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c index fe0f8d4ba0..45731b6b75 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f0xx.c * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from @@ -42,7 +42,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -82,7 +82,6 @@ */ #include "stm32f0xx.h" -#include "hal_tick.h" /** * @} @@ -108,6 +107,7 @@ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ + /** * @} */ @@ -161,8 +161,6 @@ uint8_t SetSysClock_PLL_HSI(void); * @{ */ -extern int NVIC_vtor_remap; - /** * @brief Setup the microcontroller system. * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. @@ -195,7 +193,7 @@ void SystemInit(void) /* Reset PREDIV[3:0] bits */ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; -#if defined (STM32F072xB) || defined (STM32F078xB) +#if defined (STM32F072xB) || defined (STM32F078xx) /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; #elif defined (STM32F071xB) @@ -227,19 +225,6 @@ void SystemInit(void) /* Disable all interrupts */ RCC->CIR = 0x00000000; - - /* Configure the Cube driver */ - SystemCoreClock = 8000000; // At this stage the HSI is used as system clock - NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector() - HAL_Init(); - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings */ - SetSysClock(); - - /* Reset the timer to avoid issues after the RAM initialization */ - TIM_MST_RESET_ON; - TIM_MST_RESET_OFF; } /** @@ -314,9 +299,9 @@ void SystemCoreClockUpdate (void) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ else { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; #else @@ -379,17 +364,24 @@ void SetSysClock(void) /******************************************************************************/ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + //Select HSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + // Select HSE oscillator as PLL source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT } else { RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only } - RCC_OscInitStruct.HSI48State = 0; // not used RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h index 7647daf2c2..73912666f9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf index 585592331d..44b77e7ac3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf @@ -1,30 +1,34 @@ -/* [ROM = 128kb = 0x20000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x0801FFFF; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ -/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x200000C0; -define symbol __region_RAM_end__ = 0x20003FFF; - -/* Memory regions */ define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -/* Stack and Heap */ -define symbol __size_cstack__ = 0x800; -define symbol __size_heap__ = 0x1000; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -initialize by copy with packing = zeros { readwrite }; +initialize by copy { readwrite }; do not initialize { section .noinit }; -place at address mem:__intvec_start__ { readonly section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h index be4a7706f3..9fc73d11ef 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * A generic CMSIS include header ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c index 1253c2d50b..6b3ce72fd3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -33,21 +33,21 @@ #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash -int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done - void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { int i; + // To keep track that the vectors remap is done + static volatile uint32_t vtor_remap = 0; // Space for dynamic vectors, initialised to allocate in R/W - uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; + static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; // Copy and switch to dynamic vectors if first time called - if (NVIC_vtor_remap == 0) { + if (vtor_remap == 0) { uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; for (i = 0; i < NVIC_NUM_VECTORS; i++) { vectors[i] = old_vectors[i]; } SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000 - NVIC_vtor_remap = 1; // The vectors remap is done + vtor_remap = 1; // The vectors remap is done } // Set the vector diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h index 2ba1800050..5296fd4a2f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h index baba8b4d64..653c19eca3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f072xb.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File. * * This file contains: @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,7 +59,6 @@ /** @addtogroup Configuration_section_for_CMSIS * @{ */ - /** * @brief Configuration of the Cortex-M0 Processor and Core Peripherals */ @@ -449,6 +448,7 @@ typedef struct /** * @brief Reset and Clock Control */ + typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ @@ -470,7 +470,6 @@ typedef struct /** * @brief Real-Time Clock */ - typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ @@ -644,6 +643,7 @@ typedef struct */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ @@ -672,6 +672,7 @@ typedef struct #define CRS_BASE (APBPERIPH_BASE + 0x00006C00) #define PWR_BASE (APBPERIPH_BASE + 0x00007000) #define DAC_BASE (APBPERIPH_BASE + 0x00007400) + #define CEC_BASE (APBPERIPH_BASE + 0x00007800) #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) @@ -1145,9 +1146,10 @@ typedef struct /*!
      © COPYRIGHT(c) 2014 STMicroelectronics
      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,6 +63,13 @@ /** @addtogroup Library_configuration_section * @{ */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ /* Uncomment the line below according to the target STM32 device used in your application @@ -105,11 +112,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.2.0 + * @brief CMSIS Device version number V2.2.2 */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c index b203ab80e7..6229b987b0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f0xx.c * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from @@ -42,7 +42,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -82,7 +82,6 @@ */ #include "stm32f0xx.h" -#include "hal_tick.h" /** * @} @@ -108,6 +107,7 @@ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ + /** * @} */ @@ -161,8 +161,6 @@ uint8_t SetSysClock_PLL_HSI(void); * @{ */ -extern int NVIC_vtor_remap; - /** * @brief Setup the microcontroller system. * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. @@ -195,7 +193,7 @@ void SystemInit(void) /* Reset PREDIV[3:0] bits */ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; -#if defined (STM32F072xB) || defined (STM32F078xB) +#if defined (STM32F072xB) || defined (STM32F078xx) /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; #elif defined (STM32F071xB) @@ -227,19 +225,6 @@ void SystemInit(void) /* Disable all interrupts */ RCC->CIR = 0x00000000; - - /* Configure the Cube driver */ - SystemCoreClock = 8000000; // At this stage the HSI is used as system clock - NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector() - HAL_Init(); - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings */ - SetSysClock(); - - /* Reset the timer to avoid issues after the RAM initialization */ - TIM_MST_RESET_ON; - TIM_MST_RESET_OFF; } /** @@ -314,9 +299,9 @@ void SystemCoreClockUpdate (void) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ else { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; #else @@ -370,7 +355,7 @@ void SetSysClock(void) } // Output clock on MCO pin(PA8) for debugging purpose - //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz } #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) @@ -379,17 +364,24 @@ void SetSysClock(void) /******************************************************************************/ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + //Select HSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + // Select HSE oscillator as PLL source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT } else { RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only } - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; @@ -425,13 +417,13 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; - // Select HSI48 oscillator as PLL source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48; - RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -446,7 +438,7 @@ uint8_t SetSysClock_PLL_HSI(void) } // Output clock on MCO1 pin(PA8) for debugging purpose - //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 48 MHz return 1; // OK } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h index 7647daf2c2..73912666f9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf index f7a77ff5d9..2f8c627c70 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf @@ -1,31 +1,33 @@ -/* [ROM = 256kb = 0x40000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x0803FFFF; +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ -/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x200000C0; -define symbol __region_RAM_end__ = 0x20007FFF; - -/* Memory regions */ define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -/* Stack and Heap */ -/*Heap 1/4 of ram and stack 1/8*/ -define symbol __size_cstack__ = 0x1000; -define symbol __size_heap__ = 0x2000; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -initialize by copy with packing = zeros { readwrite }; +initialize by copy { readwrite }; do not initialize { section .noinit }; -place at address mem:__intvec_start__ { readonly section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h index be4a7706f3..9fc73d11ef 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * A generic CMSIS include header ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c index 1253c2d50b..6b3ce72fd3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -33,21 +33,21 @@ #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash -int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done - void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { int i; + // To keep track that the vectors remap is done + static volatile uint32_t vtor_remap = 0; // Space for dynamic vectors, initialised to allocate in R/W - uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; + static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; // Copy and switch to dynamic vectors if first time called - if (NVIC_vtor_remap == 0) { + if (vtor_remap == 0) { uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; for (i = 0; i < NVIC_NUM_VECTORS; i++) { vectors[i] = old_vectors[i]; } SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000 - NVIC_vtor_remap = 1; // The vectors remap is done + vtor_remap = 1; // The vectors remap is done } // Set the vector diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h index 4cc9ad6763..3b7329585d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h index 2ba1800050..5296fd4a2f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h index 79a4f7d6dc..d507e9948c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f091xc.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS STM32F091xC devices Peripheral Access Layer Header File. * * This file contains: @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,7 +59,6 @@ /** @addtogroup Configuration_section_for_CMSIS * @{ */ - /** * @brief Configuration of the Cortex-M0 Processor and Core Peripherals */ @@ -453,6 +452,7 @@ typedef struct /** * @brief Reset and Clock Control */ + typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ @@ -474,7 +474,6 @@ typedef struct /** * @brief Real-Time Clock */ - typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ @@ -610,6 +609,7 @@ typedef struct */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ @@ -637,6 +637,7 @@ typedef struct #define CRS_BASE (APBPERIPH_BASE + 0x00006C00) #define PWR_BASE (APBPERIPH_BASE + 0x00007000) #define DAC_BASE (APBPERIPH_BASE + 0x00007400) + #define CEC_BASE (APBPERIPH_BASE + 0x00007800) #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) @@ -754,7 +755,6 @@ typedef struct #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) - /** * @} */ @@ -1130,9 +1130,10 @@ typedef struct /*!
      © COPYRIGHT(c) 2014 STMicroelectronics
      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,6 +63,13 @@ /** @addtogroup Library_configuration_section * @{ */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F0) +#define STM32F0 +#endif /* STM32F0 */ /* Uncomment the line below according to the target STM32 device used in your application @@ -105,11 +112,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.2.0 + * @brief CMSIS Device version number V2.2.2 */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c index b203ab80e7..fee5efa7ef 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f0xx.c * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from @@ -42,7 +42,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -82,7 +82,6 @@ */ #include "stm32f0xx.h" -#include "hal_tick.h" /** * @} @@ -108,6 +107,7 @@ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ + /** * @} */ @@ -161,8 +161,6 @@ uint8_t SetSysClock_PLL_HSI(void); * @{ */ -extern int NVIC_vtor_remap; - /** * @brief Setup the microcontroller system. * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. @@ -195,7 +193,7 @@ void SystemInit(void) /* Reset PREDIV[3:0] bits */ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; -#if defined (STM32F072xB) || defined (STM32F078xB) +#if defined (STM32F072xB) || defined (STM32F078xx) /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; #elif defined (STM32F071xB) @@ -227,19 +225,6 @@ void SystemInit(void) /* Disable all interrupts */ RCC->CIR = 0x00000000; - - /* Configure the Cube driver */ - SystemCoreClock = 8000000; // At this stage the HSI is used as system clock - NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector() - HAL_Init(); - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings */ - SetSysClock(); - - /* Reset the timer to avoid issues after the RAM initialization */ - TIM_MST_RESET_ON; - TIM_MST_RESET_OFF; } /** @@ -314,9 +299,9 @@ void SystemCoreClockUpdate (void) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ else { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; #else @@ -370,7 +355,7 @@ void SetSysClock(void) } // Output clock on MCO pin(PA8) for debugging purpose - //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz } #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) @@ -379,17 +364,24 @@ void SetSysClock(void) /******************************************************************************/ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + //Select HSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + // Select HSE oscillator as PLL source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT } else { RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only } - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; @@ -425,13 +417,13 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; - // Select HSI48 oscillator as PLL source - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48; - RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } @@ -446,7 +438,7 @@ uint8_t SetSysClock_PLL_HSI(void) } // Output clock on MCO1 pin(PA8) for debugging purpose - //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 48 MHz return 1; // OK } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h index 7647daf2c2..73912666f9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32_hal_legacy.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32_hal_legacy.h new file mode 100644 index 0000000000..77685271f1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32_hal_legacy.h @@ -0,0 +1,2500 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @version V1.3.0 + * @date 26-June-2015 + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_HAL_LEGACY +#define __STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR + +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 + +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE ((uint32_t)0x00000000) +#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) +#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + + + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#else +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSISTIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSISTIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSISTIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) +#define CAN_TXSTATUS_OK ((uint8_t)0x01) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR ((uint32_t)0x00000100) +#define ETH_MMCRIR ((uint32_t)0x00000104) +#define ETH_MMCTIR ((uint32_t)0x00000108) +#define ETH_MMCRIMR ((uint32_t)0x0000010C) +#define ETH_MMCTIMR ((uint32_t)0x00000110) +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) +#define ETH_MMCTGFCR ((uint32_t)0x00000168) +#define ETH_MMCRFCECR ((uint32_t)0x00000194) +#define ETH_MMCRFAECR ((uint32_t)0x00000198) +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) + +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ + +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +/** + * @} + */ + + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4() +#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4() +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER + +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_TS_ITR0 ((uint32_t)0x0000) +#define TIM_TS_ITR1 ((uint32_t)0x0010) +#define TIM_TS_ITR2 ((uint32_t)0x0020) +#define TIM_TS_ITR3 ((uint32_t)0x0030) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) + +#define TIM_CHANNEL_1 ((uint32_t)0x0000) +#define TIM_CHANNEL_2 ((uint32_t)0x0004) +#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) + +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ + ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) + +#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) + +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ + ((STATE) == TIM_OUTPUTSTATE_ENABLE)) +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE + +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c index aba3a02ebd..b3fbacddbc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -23,7 +23,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -57,7 +57,7 @@ * @{ */ -/** @defgroup HAL HAL module driver +/** @defgroup HAL HAL * @brief HAL module driver. * @{ */ @@ -66,14 +66,14 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup HAL_Private Constants +/** @defgroup HAL_Private_Constants HAL Private Constants * @{ */ /** - * @brief STM32F0xx HAL Driver version number V1.2.0 + * @brief STM32F0xx HAL Driver version number V1.3.0 */ #define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F0xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F0xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24)\ @@ -87,6 +87,13 @@ */ /* Private macro -------------------------------------------------------------*/ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /** @defgroup HAL_Private_Variables HAL Private Variables * @{ @@ -174,14 +181,14 @@ HAL_StatusTypeDef HAL_Init(void) HAL_StatusTypeDef HAL_DeInit(void) { /* Reset of all peripherals */ - __APB1_FORCE_RESET(); - __APB1_RELEASE_RESET(); + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); - __APB2_FORCE_RESET(); - __APB2_RELEASE_RESET(); + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); - __AHB_FORCE_RESET(); - __AHB_RELEASE_RESET(); + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); /* De-Init the low level hardware */ HAL_MspDeInit(); @@ -282,8 +289,8 @@ __weak void HAL_IncTick(void) } /** - * @brief Povides a tick value in millisecond. - * @note The function is declared as __Weak to be overwritten in case of other + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ @@ -292,41 +299,6 @@ __weak uint32_t HAL_GetTick(void) return uwTick; } -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) - -{ - /* Disable SysTick Interrupt */ - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; - -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * The function is declared as __Weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; - -} - /** * @brief This function provides accurate delay (in milliseconds) based * on variable incremented. @@ -347,6 +319,39 @@ __weak void HAL_Delay(__IO uint32_t Delay) } } +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) + +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + /** * @brief This method returns the HAL revision * @retval version : 0xXYZR (8bits for each decimal, R for RC) @@ -378,7 +383,7 @@ uint32_t HAL_GetDEVID(void) * @brief Enable the Debug Module during STOP mode * @retval None */ -void HAL_EnableDBGStopMode(void) +void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } @@ -387,7 +392,7 @@ void HAL_EnableDBGStopMode(void) * @brief Disable the Debug Module during STOP mode * @retval None */ -void HAL_DisableDBGStopMode(void) +void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } @@ -396,7 +401,7 @@ void HAL_DisableDBGStopMode(void) * @brief Enable the Debug Module during STANDBY mode * @retval None */ -void HAL_EnableDBGStandbyMode(void) +void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } @@ -405,7 +410,7 @@ void HAL_EnableDBGStandbyMode(void) * @brief Disable the Debug Module during STANDBY mode * @retval None */ -void HAL_DisableDBGStandbyMode(void) +void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h index 8417f64162..b1a707768b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f0xx_hal.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,91 +55,43 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Macros + * @{ */ - -#if defined(SYSCFG_CFGR1_DMA_RMP) -/** @defgroup HAL_DMA_remapping HAL DMA remapping - * Elements values convention: 0xYYYYYYYY - * - YYYYYYYY : Position in the SYSCFG register CFGR1 - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap - 0: No remap (ADC DMA requests mapped on DMA channel 1 - 1: Remap (ADC DMA requests mapped on DMA channel 2 */ -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap - 0: No remap (USART1_TX DMA request mapped on DMA channel 2 - 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap - 0: No remap (USART1_RX DMA request mapped on DMA channel 3 - 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ -#define HAL_REMAPDMA_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap - 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) - 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ -#define HAL_REMAPDMA_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap - 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 - 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ - -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) -#define HAL_REMAPDMA_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only - 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) - 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ -#define HAL_REMAPDMA_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only - 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) - 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ -#define HAL_REMAPDMA_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) - 1: 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ -#define HAL_REMAPDMA_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) - 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ -#define HAL_REMAPDMA_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) - 1: 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ -#define HAL_REMAPDMA_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) - 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ -#define HAL_REMAPDMA_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) - 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ -#define HAL_REMAPDMA_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) - 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ -#define HAL_REMAPDMA_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. - 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) - 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ -#endif - -#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) -#define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \ - ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \ - ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \ - ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \ - ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2) || \ - ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH6) || \ - ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH7) || \ - ((RMP) == HAL_REMAPDMA_SPI2_DMA_CH67) || \ - ((RMP) == HAL_REMAPDMA_USART2_DMA_CH67) || \ - ((RMP) == HAL_REMAPDMA_USART3_DMA_CH32) || \ - ((RMP) == HAL_REMAPDMA_I2C1_DMA_CH76) || \ - ((RMP) == HAL_REMAPDMA_TIM1_DMA_CH6) || \ - ((RMP) == HAL_REMAPDMA_TIM2_DMA_CH7) || \ - ((RMP) == HAL_REMAPDMA_TIM3_DMA_CH6)) +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ + defined(STM32F070xB) || defined(STM32F030x6) +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) #else -#define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \ - ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \ - ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \ - ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \ - ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2)) +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) #endif +#if defined(SYSCFG_CFGR1_PA11_PA12_RMP) +#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) +#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ +#if defined(STM32F091xC) || defined(STM32F098xx) +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) +#endif /* STM32F091xC || STM32F098xx */ /** * @} */ -#endif /* SYSCFG_CFGR1_DMA_RMP */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) /** @defgroup HAL_Pin_remapping HAL Pin remapping * @{ @@ -148,7 +100,6 @@ 0: No remap (pin pair PA9/10 mapped on the pins) 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ -#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) /** * @} */ @@ -163,100 +114,33 @@ #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */ #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */ -#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ - ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ - ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) /** * @} */ #endif /* STM32F091xC || STM32F098xx */ -/** @defgroup HAL_FastModePlus_I2C HAL FastModePlus I2C +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO * @{ */ -#if defined(SYSCFG_CFGR1_I2C_FMP_PB6) -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 (SYSCFG_CFGR1_I2C_FMP_PB6) /*!< Fast Mode Plus (FM+) driving capability activation on the pad - 0: PB6 pin operates in standard mode - 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */ -#endif /* SYSCFG_CFGR1_I2C_FMP_PB6 */ -#if defined(SYSCFG_CFGR1_I2C_FMP_PB7) -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 (SYSCFG_CFGR1_I2C_FMP_PB7) /*!< Fast Mode Plus (FM+) driving capability activation on the pad - 0: PB7 pin operates in standard mode - 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */ -#endif /* SYSCFG_CFGR1_I2C_FMP_PB7 */ - -#if defined(SYSCFG_CFGR1_I2C_FMP_PB8) -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 (SYSCFG_CFGR1_I2C_FMP_PB8) /*!< Fast Mode Plus (FM+) driving capability activation on the pad - 0: PB8 pin operates in standard mode - 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */ -#endif /* SYSCFG_CFGR1_I2C_FMP_PB8 */ - -#if defined(SYSCFG_CFGR1_I2C_FMP_PB9) -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 (SYSCFG_CFGR1_I2C_FMP_PB9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad - 0: PB9 pin operates in standard mode - 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */ -#endif /* SYSCFG_CFGR1_I2C_FMP_PB9 */ - -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 (SYSCFG_CFGR1_I2C_FMP_I2C1) /*!< I2C1 fast mode Plus driving capability activation - 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits - 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */ -#endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */ - -#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 (SYSCFG_CFGR1_I2C_FMP_I2C2) /*!< I2C2 fast mode Plus driving capability activation - 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits - 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */ -#endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */ - -#if defined(SYSCFG_CFGR1_I2C_FMP_PA9) -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 (SYSCFG_CFGR1_I2C_FMP_PA9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad - 0: PA9 pin operates in standard mode - 1: FM+ mode is enabled on PA9 pin, and the Speed control is bypassed */ -#endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */ - -#if defined(SYSCFG_CFGR1_I2C_FMP_PA10) -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 (SYSCFG_CFGR1_I2C_FMP_PA10) /*!< Fast Mode Plus (FM+) driving capability activation on the pad - 0: PA10 pin operates in standard mode - 1: FM+ mode is enabled on PA10 pin, and the Speed control is bypassed */ -#endif /* SYSCFG_CFGR1_I2C_FMP_PA10 */ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) -#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) -#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) -#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) -#elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030x6) -#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) -#else -#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ - ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ + defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ + defined(STM32F070xB) || defined(STM32F030x6) +#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */ +#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */ #endif +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */ /** - * @} - */ + * @} + */ + #if defined(STM32F091xC) || defined (STM32F098xx) /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper @@ -394,68 +278,68 @@ #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) -#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) -#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) -#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) -#define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) -#define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) -#define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) -#define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) -#define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) -#define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ /** @@ -468,13 +352,13 @@ #if defined(SYSCFG_CFGR1_MEM_MODE) /** @brief Main Flash memory mapped at 0x00000000 */ -#define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) #endif /* SYSCFG_CFGR1_MEM_MODE */ #if defined(SYSCFG_CFGR1_MEM_MODE_0) /** @brief System Flash memory mapped at 0x00000000 */ -#define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ }while(0) #endif /* SYSCFG_CFGR1_MEM_MODE_0 */ @@ -482,7 +366,7 @@ #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) /** @brief Embedded SRAM mapped at 0x00000000 */ -#define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ }while(0) #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ @@ -490,22 +374,6 @@ * @} */ -#if defined(SYSCFG_CFGR1_DMA_RMP) -/** @defgroup HAL_DMA_remap HAL DMA remap - * @brief DMA remapping enable/disable macros - * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping - * @{ - */ -#define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ - SYSCFG->CFGR1 |= (__DMA_REMAP__); \ - }while(0) -#define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ - SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ - }while(0) -/** - * @} - */ -#endif /* SYSCFG_CFGR1_DMA_RMP */ #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) /** @defgroup HAL_Pin_remap HAL Pin remap @@ -524,22 +392,17 @@ */ #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ -/** @defgroup HAL_Fast_mode_plus_driving_cap HAL Fast mode plus driving cap - * @brief Fast mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C - * @{ +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. + * That you can find above these macros. */ -#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ - SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ }while(0) -#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ - SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \ +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ }while(0) -/** - * @} - */ - #if defined(SYSCFG_CFGR2_LOCKUP_LOCK) /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable * @{ @@ -635,14 +498,15 @@ /** * @} - */ + */ + /* Exported functions --------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Functions HAL Exported Functions + +/** @addtogroup HAL_Exported_Functions * @{ */ -/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions +/** @addtogroup HAL_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ******************************/ @@ -655,11 +519,11 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); * @} */ -/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions +/** @addtogroup HAL_Exported_Functions_Group2 * @{ */ -/* Peripheral Control functions **********************************************/ + +/* Peripheral Control functions ************************************************/ void HAL_IncTick(void); void HAL_Delay(__IO uint32_t Delay); uint32_t HAL_GetTick(void); @@ -668,26 +532,26 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); -void HAL_EnableDBGStopMode(void); -void HAL_DisableDBGStopMode(void); -void HAL_EnableDBGStandbyMode(void); -void HAL_DisableDBGStandbyMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} */ +/** + * @} + */ + /** * @} */ /** * @} - */ + */ -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c index b6f04aee87..9166f69fe6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c @@ -2,53 +2,55 @@ ****************************************************************************** * @file stm32f0xx_hal_adc.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Initialization and de-initialization functions * ++ Initialization and Configuration of ADC * + Operation functions - * ++ Start, stop, get result of conversions of regular group, - * using 3 possible modes: polling, interruption or DMA. + * ++ Start, stop, get result of conversions of regular + * group, using 3 possible modes: polling, interruption or DMA. * + Control functions - * ++ Analog Watchdog configuration * ++ Channels configuration on regular group + * ++ Analog Watchdog configuration * + State functions * ++ ADC state machine management * ++ Interrupts and flags management - * + * Other functions (extended functions) are available in file + * "stm32f0xx_hal_adc_ex.c". + * @verbatim ============================================================================== - ##### ADC specific features ##### + ##### ADC peripheral features ##### ============================================================================== - [..] - (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution + [..] + (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution - (#) Interrupt generation at the end of regular conversion and in case of + (+) Interrupt generation at the end of regular conversion and in case of analog watchdog or overrun events. - (#) Single and continuous conversion modes. + (+) Single and continuous conversion modes. - (#) Scan mode for automatic conversion of channel 0 to channel 'n'. + (+) Scan mode for conversion of several channels sequentially. - (#) Data alignment with in-built data coherency. + (+) Data alignment with in-built data coherency. - (#) Programmable sampling time. + (+) Programmable sampling time (common for all channels) - (#) ADC conversion group Regular. + (+) ADC conversion of regular group. - (#) External trigger (timer or EXTI) with configurable polarity. + (+) External trigger (timer or EXTI) with configurable polarity - (#) DMA request generation for transfer of conversions data of regular group. + (+) DMA request generation for transfer of conversions data of regular group. - (#) ADC calibration + (+) ADC calibration - (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed. - (#) ADC input range: from Vref minus (connected to Vssa) to Vref plus (connected to + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). @@ -56,64 +58,176 @@ ============================================================================== [..] - (#) Enable the ADC interface - (++) As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured - at RCC top level: clock source and clock prescaler. - (++)Two possible clock sources: synchronous clock derived from APB clock - or asynchronous clock derived from ADC dedicated HSI RC oscillator - 14MHz. - (++)Example: - __ADC1_CLK_ENABLE(); (mandatory) - - HI14 enable or let under control of ADC: (optional) + *** Configuration of top level parameters related to ADC *** + ============================================================ + [..] - RCC_OscInitTypeDef RCC_OscInitStructure; - RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; - RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; - RCC_OscInitStructure.PLL... (optional if used for system clock) - HAL_RCC_OscConfig(&RCC_OscInitStructure); - - Parameter "HSI14State" must be set either: - - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control - the HSI14 oscillator enable/disable (if not used to supply the main - system clock): feature used if ADC mode LowPowerAutoPowerOff is - enabled. - - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator - always enabled: can be used to supply the main system clock. + (#) Enable the ADC interface + (++) As prerequisite, ADC clock must be configured at RCC top level. + Caution: On STM32F0, ADC clock frequency max is 14MHz (refer + to device datasheet). + Therefore, ADC clock prescaler must be configured in + function of ADC clock source frequency to remain below + this maximum frequency. + + (++) Two clock settings are mandatory: + (+++) ADC clock (core clock, also possibly conversion clock). + + (+++) ADC clock (conversions clock). + Two possible clock sources: synchronous clock derived from APB clock + or asynchronous clock derived from ADC dedicated HSI RC oscillator + 14MHz. + If asynchronous clock is selected, parameter "HSI14State" must be set either: + - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control + the HSI14 oscillator enable/disable (if not used to supply the main + system clock): feature used if ADC mode LowPowerAutoPowerOff is + enabled. + - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator + always enabled: can be used to supply the main system clock. + + (+++) Example: + Into HAL_ADC_MspInit() (recommended code location) or with + other device clock parameters configuration: + (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory) + + HI14 enable or let under control of ADC: (optional: if asynchronous clock selected) + (+++) RCC_OscInitTypeDef RCC_OscInitStructure; + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + (+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; + (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; + (+++) RCC_OscInitStructure.PLL... (optional if used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (++) ADC clock source and clock prescaler are configured at ADC level with + parameter "ClockPrescaler" using function HAL_ADC_Init(). (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (++) Configure these ADC pins in analog mode using HAL_GPIO_Init(); - - (#) Configure the ADC parameters (conversion resolution, data alignment, - continuous mode, ...) using the HAL_ADC_Init() function. + (++) Enable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_ENABLE() + (++) Configure these ADC pins in analog mode + using function HAL_GPIO_Init() - (#) Activate the ADC peripheral using one of the start functions: - HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(). + (#) Optionally, in case of usage of ADC with interruptions: + (++) Configure the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector + ADCx_IRQHandler(). + + (#) Optionally, in case of usage of DMA: + (++) Configure the DMA (DMA channel, mode normal or circular, ...) + using function HAL_DMA_Init(). + (++) Configure the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector + DMAx_Channelx_IRQHandler(). - *** Channels configuration to regular group *** - ================================================ - [..] - (+) To configure the ADC regular group features, use - HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. - (+) To activate the continuous mode, use the HAL_ADC_Init() function. - (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. - - *** DMA for regular configuration *** - ============================================================= + *** Configuration of ADC, group regular, channels parameters *** + ================================================================ [..] - (+) To enable the DMA mode for regular group, use the - HAL_ADC_Start_DMA() function. - (+) To enable the generation of DMA requests continuously at the end of - the last DMA transfer, use the HAL_ADC_Init() function. + + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) + using function HAL_ADC_AnalogWDGConfig(). + + *** Execution of ADC conversions *** + ==================================== + [..] + + (#) Optionally, perform an automatic ADC calibration to improve the + conversion accuracy + using function HAL_ADCEx_Calibration_Start(). + + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + (++) ADC conversion by polling: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start() + (+++) Wait for ADC conversion completion + using function HAL_ADC_PollForConversion() + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop() + + (++) ADC conversion by interruption: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_IT() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() + (this function must be implemented in user program) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_IT() + + (++) ADC conversion with transfer by DMA: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_DMA() + + [..] + + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + + *** Deinitialization of ADC *** + ============================================================ + [..] + + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + (++) ADC clock disable + using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA + using function HAL_DMA_Init(). + (++) Disable the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + + [..] @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -147,7 +261,7 @@ * @{ */ -/** @defgroup ADC ADC HAL module driver +/** @defgroup ADC ADC * @brief ADC HAL module driver * @{ */ @@ -171,17 +285,16 @@ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 2) - /* Delay for temperature sensor stabilization time. */ - /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ - /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */ - /* have the minimum number of CPU cycles to fulfill this delay. */ - #define ADC_TEMPSENSOR_DELAY_CPU_CYCLES ((uint32_t) 480) - /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ - /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */ - /* have the minimum number of CPU cycles to fulfill this delay. */ - #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)48) + /* Unit: us */ + #define ADC_STAB_DELAY_US ((uint32_t) 1) + + /* Delay for temperature sensor stabilization time. */ + /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ + /* Unit: us */ + #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) + /** * @} */ @@ -247,7 +360,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma); */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpCFGR1 = 0; /* Check ADC handle */ @@ -282,9 +395,14 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) { + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_ADC_MspInit(hadc); - } /* Configuration of ADC parameters if previous preliminary actions are */ @@ -292,17 +410,21 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* and if there is no conversion on going on regular group (ADC can be */ /* enabled anyway, in case of call of this function to update a parameter */ /* on the fly). */ - if ((hadc->State != HAL_ADC_STATE_ERROR) && - (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && + (tmp_hal_status == HAL_OK) && + (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) { - /* Initialize the ADC state */ - hadc->State = HAL_ADC_STATE_BUSY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - ADC clock mode */ /* - ADC clock prescaler */ - if (__HAL_ADC_IS_ENABLED(hadc) == RESET) + /* - ADC resolution */ + if (ADC_IS_ENABLE(hadc) == RESET) { /* Some parameters of this register are not reset, since they are set */ /* by other functions and must be kept in case of usage of this */ @@ -312,13 +434,16 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() ) */ - /* Reset configuration of ADC configuration register CFGR2: */ - /* - ADC clock mode: CKMODE */ - hadc->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); + /* Configuration of ADC resolution */ + MODIFY_REG(hadc->Instance->CFGR1, + ADC_CFGR1_RES , + hadc->Init.Resolution ); /* Configuration of ADC clock mode: clock source AHB or HSI with */ /* selectable prescaler */ - hadc->Instance->CFGR2 |= hadc->Init.ClockPrescaler; + MODIFY_REG(hadc->Instance->CFGR2 , + ADC_CFGR2_CKMODE , + hadc->Init.ClockPrescaler ); } /* Configuration of ADC: */ @@ -341,18 +466,16 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN | ADC_CFGR1_ALIGN | - ADC_CFGR1_RES | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG ); - tmpCFGR1 |= (__HAL_ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) | - __HAL_ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) | - __HAL_ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) | - __HAL_ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | - hadc->Init.DataAlign | - hadc->Init.Resolution | - __HAL_ADC_CFGR1_SCANDIR(hadc->Init.ScanConvMode) | - __HAL_ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); + tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) | + ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) | + ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) | + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + hadc->Init.DataAlign | + ADC_SCANDIR(hadc->Init.ScanConvMode) | + ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); /* Enable discontinuous mode only if continuous mode is disabled */ if ((hadc->Init.DiscontinuousConvMode == ENABLE) && @@ -364,7 +487,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Enable external trigger if trigger selection is different of software */ /* start. */ - /* @Note: This configuration keeps the hardware feature of parameter */ + /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) @@ -376,41 +499,62 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Update ADC configuration register with previous settings */ hadc->Instance->CFGR1 |= tmpCFGR1; + /* Channel sampling time configuration */ + /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ + /* (obsolete): sampling time set in this function if parameter */ + /* "SamplingTimeCommon" has been set to a valid sampling time. */ + /* Otherwise, sampling time is set into ADC channel initialization */ + /* structure with parameter "SamplingTime" (obsolete). */ + if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) + { + /* Channel sampling time configuration */ + /* Clear the old sample time */ + hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); + + /* Set the new sample time */ + hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); + } + /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CFGR1 (excluding analog watchdog configuration: */ - /* set into separate dedicated function). */ - if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)) + /* set into separate dedicated function, and bits of ADC resolution set */ + /* out of temporary variable 'tmpCFGR1'). */ + if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) == tmpCFGR1) { /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); - /* Initialize the ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } } else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } @@ -428,7 +572,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ if(hadc == NULL) @@ -439,20 +583,20 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going, on regular group */ - tmpHALStatus = ADC_ConversionStop(hadc); + tmp_hal_status = ADC_ConversionStop(hadc); /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { /* Disable the ADC peripheral */ - tmpHALStatus = ADC_Disable(hadc); + tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status != HAL_ERROR) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_READY; @@ -462,7 +606,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status != HAL_ERROR) { /* ========== Reset ADC registers ========== */ @@ -487,7 +631,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ); /* Reset register CFGR2 */ - /* @Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ /* already done above. */ hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; @@ -508,9 +652,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* bits in access mode read only, no direct reset applicable*/ /* Reset register CCR */ - ADC->CCR &= ~( ADC_CCR_VBATEN | - ADC_CCR_TSEN | - ADC_CCR_VREFEN ); + ADC->CCR &= ~(ADC_CCR_ALL); /* ========== Hard reset ADC peripheral ========== */ /* Performs a global reset of the entire ADC peripheral: ADC state is */ @@ -518,16 +660,16 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* If needed, copy-paste and uncomment the following reset code into */ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ /* */ - /* __ADC1_FORCE_RESET() */ - /* __ADC1_RELEASE_RESET() */ + /* __HAL_RCC_ADC1_FORCE_RESET() */ + /* __HAL_RCC_ADC1_RELEASE_RESET() */ /* DeInit the low level hardware */ HAL_ADC_MspDeInit(hadc); /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); - /* Change ADC state */ + /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; } @@ -535,7 +677,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } @@ -597,13 +739,13 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ - if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); @@ -613,17 +755,26 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* performed automatically by hardware. */ if (hadc->Init.LowPowerAutoPowerOff != ENABLE) { - tmpHALStatus = ADC_Enable(hadc); + tmp_hal_status = ADC_Enable(hadc); } /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { - /* State machine update: Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ @@ -636,17 +787,14 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* trigger event. */ hadc->Instance->CR |= ADC_CR_ADSTART; } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); } else { - tmpHALStatus = HAL_BUSY; + tmp_hal_status = HAL_BUSY; } /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** @@ -656,7 +804,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -665,19 +813,21 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on regular group */ - tmpHALStatus = ADC_ConversionStop(hadc); + tmp_hal_status = ADC_ConversionStop(hadc); /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { /* 2. Disable the ADC peripheral */ - tmpHALStatus = ADC_Disable(hadc); + tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); } } @@ -685,11 +835,23 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** * @brief Wait for regular group conversion to be completed. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence (ADC init + * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status @@ -703,19 +865,38 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence */ - if (hadc->Init.EOCSelection == EOC_SEQ_CONV) + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { tmp_Flag_EOC = ADC_FLAG_EOS; } /* If end of conversion selected to end of each conversion */ - else /* EOC_SINGLE_CONV */ + else /* ADC_EOC_SINGLE_CONV */ { - tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ + if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + else + { + tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); + } } - - /* Get timeout */ - tickstart = HAL_GetTick(); - + + /* Get tick count */ + tickstart = HAL_GetTick(); + /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) { @@ -725,12 +906,49 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_TIMEOUT; + } + } + } + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } @@ -744,13 +962,6 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; - } - /* Return ADC state */ return HAL_OK; } @@ -760,8 +971,8 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * @param hadc: ADC handle * @param EventType: the ADC event type. * This parameter can be one of the following values: - * @arg AWD_EVENT: ADC Analog watchdog event - * @arg OVR_EVENT: ADC Overrun event + * @arg ADC_AWD_EVENT: ADC Analog watchdog event + * @arg ADC_OVR_EVENT: ADC Overrun event * @param Timeout: Timeout value in millisecond. * @retval HAL status */ @@ -773,6 +984,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); + /* Get tick count */ tickstart = HAL_GetTick(); /* Check selected event flag */ @@ -784,7 +996,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Update ADC state machine to timeout */ - hadc->State = HAL_ADC_STATE_TIMEOUT; + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -797,27 +1009,27 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy switch(EventType) { /* Analog watchdog (level out of window) event */ - case AWD_EVENT: - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_AWD; + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); break; /* Overrun event */ - default: /* Case OVR_EVENT */ + default: /* Case ADC_OVR_EVENT */ /* If overrun is set to overwrite previous data, overrun event is not */ /* considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and without */ /* overrun ") */ - if (hadc->Init.Overrun == OVR_DATA_PRESERVED) + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_ERROR; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); /* Set ADC error code to overrun */ - hadc->ErrorCode |= HAL_ADC_ERROR_OVR; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); } /* Clear ADC Overrun flag */ @@ -842,13 +1054,13 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ - if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); @@ -858,17 +1070,26 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* performed automatically by hardware. */ if (hadc->Init.LowPowerAutoPowerOff != ENABLE) { - tmpHALStatus = ADC_Enable(hadc); + tmp_hal_status = ADC_Enable(hadc); } /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { - /* State machine update: Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ @@ -879,11 +1100,11 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Enable ADC overrun interrupt */ switch(hadc->Init.EOCSelection) { - case EOC_SEQ_CONV: + case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); break; - /* case EOC_SINGLE_CONV */ + /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); break; @@ -895,17 +1116,14 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* trigger event. */ hadc->Instance->CR |= ADC_CR_ADSTART; } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); } else { - tmpHALStatus = HAL_BUSY; + tmp_hal_status = HAL_BUSY; } /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } @@ -917,7 +1135,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -926,23 +1144,25 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on regular group */ - tmpHALStatus = ADC_ConversionStop(hadc); - + tmp_hal_status = ADC_ConversionStop(hadc); + /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* 2. Disable the ADC peripheral */ - tmpHALStatus = ADC_Disable(hadc); + tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); } } @@ -950,7 +1170,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** @@ -968,13 +1188,13 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ - if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); @@ -984,19 +1204,27 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* performed automatically by hardware. */ if (hadc->Init.LowPowerAutoPowerOff != ENABLE) { - tmpHALStatus = ADC_Enable(hadc); + tmp_hal_status = ADC_Enable(hadc); } /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { - /* State machine update: Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); - /* Set ADC error code to none */ - __HAL_ADC_CLEAR_ERRORCODE(hadc); - + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; @@ -1030,17 +1258,14 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* trigger event. */ hadc->Instance->CR |= ADC_CR_ADSTART; } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); } else { - tmpHALStatus = HAL_BUSY; + tmp_hal_status = HAL_BUSY; } /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** @@ -1052,7 +1277,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1061,34 +1286,34 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on regular group */ - tmpHALStatus = ADC_ConversionStop(hadc); + tmp_hal_status = ADC_ConversionStop(hadc); /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmpHALStatus != HAL_ERROR) + if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN; /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ - tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle); + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ - if (tmpHALStatus != HAL_OK) + if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripheral */ - /* Update "tmpHALStatus" only if DMA channel disabling passed, to keep in */ - /* memory a potential failing status. */ - if (tmpHALStatus == HAL_OK) + /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ + /* in memory a potential failing status. */ + if (tmp_hal_status == HAL_OK) { - tmpHALStatus = ADC_Disable(hadc); + tmp_hal_status = ADC_Disable(hadc); } else { @@ -1096,10 +1321,12 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) } /* Check if ADC is effectively disabled */ - if (tmpHALStatus == HAL_OK) + if (tmp_hal_status == HAL_OK) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); } } @@ -1108,7 +1335,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** @@ -1125,7 +1352,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* @Note: EOC flag is not cleared here by software because automatically */ + /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Clear regular group end of sequence flag */ @@ -1135,61 +1362,6 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) return hadc->Instance->DR; } -/** - * @brief DMA transfer complete callback. - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; - } - - /* Conversion complete callback */ - HAL_ADC_ConvCpltCallback(hadc); -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Half conversion callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void ADC_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_ERROR; - - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - - /* Error callback */ - HAL_ADC_ErrorCallback(hadc); -} - /** * @brief Handles ADC interrupt request. * @param hadc: ADC handle @@ -1207,52 +1379,56 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) { /* Update state machine on conversion status if not in error state */ - if(hadc->State != HAL_ADC_STATE_ERROR) + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC_REG; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } - /* Disable interruption if no further conversion upcoming by regular */ - /* external trigger or by continuous mode, */ - /* and if scan sequence if completed. */ - if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) { /* If End of Sequence is reached, disable interrupts */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ - if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { - /* Disable ADC end of sequence conversion interrupt */ - /* @Note: Overrun interrupt was enabled with EOC interrupt in */ + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); } else { /* Change ADC state to error state */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } /* Conversion complete callback */ - /* @Note: into callback, to determine if conversion has been triggered */ + /* Note: into callback, to determine if conversion has been triggered */ /* from EOC or EOS, possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ HAL_ADC_ConvCpltCallback(hadc); /* Clear regular group conversion flag */ - /* @Note: in case of overrun set to OVR_DATA_PRESERVED, end of conversion */ - /* flags clear induces the release of the preserved data. */ + /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ + /* conversion flags clear induces the release of the preserved data.*/ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); @@ -1261,8 +1437,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* ========== Check Analog watchdog flags ========== */ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_AWD; + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Level out of window callback */ HAL_ADC_LevelOutOfWindowCallback(hadc); @@ -1282,14 +1458,14 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ - if ((hadc->Init.Overrun == OVR_DATA_PRESERVED) || + if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) { - /* Change ADC state to error state */ - hadc->State = HAL_ADC_STATE_ERROR; - /* Set ADC error code to overrun */ - hadc->ErrorCode |= HAL_ADC_ERROR_OVR; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); /* Error callback */ HAL_ADC_ErrorCallback(hadc); @@ -1397,15 +1573,19 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; __IO uint32_t wait_loop_index = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_RANK(sConfig->Rank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - + + if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) + { + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + } + /* Process locked */ __HAL_LOCK(hadc); @@ -1414,8 +1594,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* conversion on going on regular group: */ /* - Channel number */ /* - Channel sampling time */ - /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */ - if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Configure channel: depending on rank setting, add it or remove it from */ /* ADC conversion sequencer. */ @@ -1423,97 +1603,90 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Regular sequence configuration */ /* Set the channel selection register from the selected channel */ - hadc->Instance->CHSELR |= __HAL_ADC_CHSELR_CHANNEL(sConfig->Channel); + hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); /* Channel sampling time configuration */ - /* Modify sampling time if needed (not needed in case of reoccurrence */ - /* for several channels programmed consecutively into the sequencer) */ - if (sConfig->SamplingTime != __HAL_ADC_GET_SAMPLINGTIME(hadc)) + /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ + /* (obsolete): sampling time set in this function with */ + /* parameter "SamplingTime" (obsolete) only if not already set into */ + /* ADC initialization structure with parameter "SamplingTimeCommon". */ + if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) { - /* Channel sampling time configuration */ - /* Clear the old sample time */ - hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); - - /* Set the new sample time */ - hadc->Instance->SMPR |= (sConfig->SamplingTime); - } - - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ - /* internal measurement paths enable: If internal channel selected, */ - /* enable dedicated internal buffers and path. */ - /* @Note: these internal measurement paths can be disabled using */ - /* HAL_ADC_DeInit() or removing the channel from sequencer with */ - /* channel configuration parameter "Rank". */ - - /* If Channel_16 is selected, enable Temp. sensor measurement path. */ - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - ADC->CCR |= ADC_CCR_TSEN; - - /* Delay for temperature sensor stabilization time */ - while(wait_loop_index < ADC_TEMPSENSOR_DELAY_CPU_CYCLES) + /* Modify sampling time if needed (not needed in case of reoccurrence */ + /* for several channels programmed consecutively into the sequencer) */ + if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) { - wait_loop_index++; + /* Channel sampling time configuration */ + /* Clear the old sample time */ + hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); + + /* Set the new sample time */ + hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); } } - /* If Channel_17 is selected, enable VBAT measurement path. */ - else if (sConfig->Channel == ADC_CHANNEL_VBAT) + + /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit() or removing the channel from sequencer with */ + /* channel configuration parameter "Rank". */ + if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) { - ADC->CCR |= ADC_CCR_VBATEN; + /* If Channel_16 is selected, enable Temp. sensor measurement path. */ + /* If Channel_17 is selected, enable VREFINT measurement path. */ + /* If Channel_18 is selected, enable VBAT measurement path. */ + ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); + + /* If Temp. sensor is selected, wait for stabilization delay */ + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); + while(wait_loop_index != 0) + { + wait_loop_index--; + } + } } - /* If Channel_18 is selected, enable VREFINT measurement path. */ - else if (sConfig->Channel == ADC_CHANNEL_VREFINT) - { - ADC->CCR |= ADC_CCR_VREFEN; - } - } else { /* Regular sequence configuration */ /* Reset the channel selection register from the selected channel */ - hadc->Instance->CHSELR &= ~__HAL_ADC_CHSELR_CHANNEL(sConfig->Channel); + hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ + /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths disable: If internal channel selected, */ /* disable dedicated internal buffers and path. */ - - /* If Channel_16 is selected, disable Temp. sensor measurement path. */ - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) { - ADC->CCR &= ~ADC_CCR_TSEN; - } - /* If Channel_17 is selected, disable VBAT measurement path. */ - else if (sConfig->Channel == ADC_CHANNEL_VBAT) - { - ADC->CCR &= ~ADC_CCR_VBATEN; - } - /* If Channel_18 is selected, disable VREFINT measurement path. */ - else if (sConfig->Channel == ADC_CHANNEL_VREFINT) - { - ADC->CCR &= ~ADC_CCR_VREFEN; + /* If Channel_16 is selected, disable Temp. sensor measurement path. */ + /* If Channel_17 is selected, disable VREFINT measurement path. */ + /* If Channel_18 is selected, disable VBAT measurement path. */ + ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); } } - + } - /* If a conversion is on going on regular group, no update on regular */ /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } @@ -1533,18 +1706,19 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpAWDHighThresholdShifted; uint32_t tmpAWDLowThresholdShifted; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); /* Verify if threshold is within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) { @@ -1559,7 +1733,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* conversion on going on regular group: */ /* - Analog watchdog channels */ /* - Analog watchdog thresholds */ - if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ @@ -1570,18 +1744,18 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG ADC_CFGR1_AWDEN | ADC_CFGR1_AWDCH ); - hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | - __HAL_ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) ); + hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | + ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) ); /* Shift the offset in function of the selected ADC resolution: Thresholds*/ /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpAWDHighThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); + tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); /* Set the high and low thresholds */ hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); - hadc->Instance->TR |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | - tmpAWDLowThresholdShifted ); + hadc->Instance->TR |= ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | + tmpAWDLowThresholdShifted ); /* Clear the ADC Analog watchdog flag (in case of left enabled by */ /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ @@ -1606,9 +1780,9 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - tmpHALStatus = HAL_ERROR; + tmp_hal_status = HAL_ERROR; } @@ -1616,7 +1790,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } @@ -1647,7 +1821,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * @param hadc: ADC handle * @retval HAL state */ -HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1682,6 +1856,12 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @note If low power mode AutoPowerOff is enabled, power-on/off phases are + * performed automatically by hardware. + * In this mode, this function is useless and must not be called because + * flag ADC_FLAG_RDY is not usable. + * Therefore, this function must be called under condition of + * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". * @param hadc: ADC handle * @retval HAL status. */ @@ -1694,16 +1874,16 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ - if (__HAL_ADC_IS_ENABLED(hadc) == RESET) + if (ADC_IS_ENABLE(hadc) == RESET) { /* Check if conditions to enable the ADC are fulfilled */ - if (__HAL_ADC_ENABLING_CONDITIONS(hadc) == RESET) + if (ADC_ENABLING_CONDITIONS(hadc) == RESET) { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } @@ -1711,14 +1891,15 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ __HAL_ADC_ENABLE(hadc); - /* Delay for ADC stabilization time. */ - /* Delay fixed to worst case: maximum CPU frequency */ - while(wait_loop_index < ADC_STAB_DELAY_CPU_CYCLES) + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(wait_loop_index != 0) { - wait_loop_index++; - } + wait_loop_index--; + } - /* Get timeout */ + /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively enabled */ @@ -1727,10 +1908,10 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } @@ -1754,12 +1935,12 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) uint32_t tickstart = 0; /* Verification if ADC is not already disabled: */ - /* @Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ - /* disabled. */ - if (__HAL_ADC_IS_ENABLED(hadc) != RESET ) + /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ + /* disabled. */ + if (ADC_IS_ENABLE(hadc) != RESET) { /* Check if conditions to disable the ADC are fulfilled */ - if (__HAL_ADC_DISABLING_CONDITIONS(hadc) != RESET) + if (ADC_DISABLING_CONDITIONS(hadc) != RESET) { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); @@ -1767,26 +1948,27 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } /* Wait for ADC effectively disabled */ + /* Get tick count */ tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) { - if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } @@ -1814,7 +1996,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) /* Verification if ADC is not already stopped on regular group to bypass */ /* this function if not needed. */ - if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) { /* Stop potential conversion on going on regular group */ @@ -1827,6 +2009,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) } /* Wait for conversion effectively stopped */ + /* Get tick count */ tickstart = HAL_GetTick(); while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) @@ -1834,10 +2017,10 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; - + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Set ADC error code to ADC IP internal error */ - hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } @@ -1849,6 +2032,102 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) return HAL_OK; } + +/** + * @brief DMA transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) + { + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } + +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Half conversion callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to DMA handle. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + + /* Set ADC error code to DMA error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); + + /* Error callback */ + HAL_ADC_ErrorCallback(hadc); +} + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h index ee6dd66a49..a553f12ffe 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_adc.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler') - * - For all parameters except 'ClockPrescaler': ADC enabled without conversion on going on regular group. + * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). */ @@ -88,8 +88,8 @@ typedef struct uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. This parameter can be a value of @ref ADC_EOCSelection. */ uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous - conversion (for regular group) or previous sequence (for injected group) has been treated by user software. - This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. + conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue(). + This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed @@ -119,6 +119,14 @@ typedef struct uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten This parameter has an effect on regular group only, including in DMA mode. This parameter can be a value of @ref ADC_Overrun */ + uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. + This parameter can be a value of @ref ADC_sampling_times + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ }ADC_InitTypeDef; /** @@ -135,7 +143,7 @@ typedef struct This parameter can be a value of @ref ADC_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. - On STM32F0 devices, rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).. Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. This parameter can be a value of @ref ADC_rank */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. @@ -143,6 +151,8 @@ typedef struct Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of @ref ADC_sampling_times Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set. + Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure. + If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ @@ -169,26 +179,40 @@ typedef struct }ADC_AnalogWDGConfTypeDef; /** - * @brief HAL ADC state machine: ADC States structure definition + * @brief HAL ADC state machine: ADC states definition (bitfields) */ -typedef enum -{ - HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ - HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ - HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ - HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ - HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ - HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ - HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ - HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ - HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ - HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ - HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */ - HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */ - HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */ -}HAL_ADC_StateTypeDef; +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on, multimode ADC master control) */ +#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F0 device: End Of Sampling flag raised */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on, multimode ADC master control) */ +#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on STM32F0 device: Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */ + /** * @brief ADC handle Structure definition @@ -199,13 +223,11 @@ typedef struct ADC_InitTypeDef Init; /*!< ADC required parameters */ - __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */ - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ HAL_LockTypeDef Lock; /*!< ADC locking object */ - __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t ErrorCode; /*!< ADC Error code */ }ADC_HandleTypeDef; @@ -237,18 +259,11 @@ typedef struct /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler * @{ */ -#define ADC_CLOCK_ASYNC ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ +#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /* Obsolete naming, kept for compatibility with some other devices */ -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /* Obsolete naming, kept for compatibility with some other devices */ - -#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC) || \ - ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ - ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) - /** * @} */ @@ -256,15 +271,10 @@ typedef struct /** @defgroup ADC_Resolution ADC Resolution * @{ */ -#define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ -#define ADC_RESOLUTION10b ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ -#define ADC_RESOLUTION8b ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ -#define ADC_RESOLUTION6b ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ - -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \ - ((RESOLUTION) == ADC_RESOLUTION10b) || \ - ((RESOLUTION) == ADC_RESOLUTION8b) || \ - ((RESOLUTION) == ADC_RESOLUTION6b) ) +#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ +#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ +#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ +#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ /** * @} */ @@ -274,9 +284,6 @@ typedef struct */ #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) - -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ - ((ALIGN) == ADC_DATAALIGN_LEFT) ) /** * @} */ @@ -300,8 +307,6 @@ typedef struct #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ -#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ - ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) /** * @} */ @@ -313,51 +318,6 @@ typedef struct #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) - -#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) -/** - * @} - */ - -/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular - * @{ - */ -/* List of external triggers with generic trigger name, sorted by trigger */ -/* name: */ - -/* External triggers of regular group for ADC1 */ -#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO -#define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4 -#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO -#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO -#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO -#define ADC_SOFTWARE_START ((uint32_t)0x00000010) - -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ - ((REGTRIG) == ADC_SOFTWARE_START) ) -/** - * @} - */ - -/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular - * @{ - */ - -/* List of external triggers of regular group for ADC1: */ -/* (used internally by HAL driver. To not use into HAL structure parameters) */ -#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)0x00000000) -#define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) -#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) -#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) -#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) - /** * @} */ @@ -365,13 +325,9 @@ typedef struct /** @defgroup ADC_EOCSelection ADC EOCSelection * @{ */ -#define EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) -#define EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) -#define EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ - -#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \ - ((EOC_SELECTION) == EOC_SEQ_CONV) || \ - ((EOC_SELECTION) == EOC_SINGLE_SEQ_CONV) ) +#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) +#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) +#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ /** * @} */ @@ -379,68 +335,8 @@ typedef struct /** @defgroup ADC_Overrun ADC Overrun * @{ */ -#define OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000) -#define OVR_DATA_PRESERVED ((uint32_t)0x00000001) - -#define IS_ADC_OVERRUN(OVR) (((OVR) == OVR_DATA_PRESERVED) || \ - ((OVR) == OVR_DATA_OVERWRITTEN) ) -/** - * @} - */ - -/** @defgroup ADC_channels ADC channels - * @{ - */ -/* Note: Depending on devices, some channels may not be available on package */ -/* pins. Refer to device datasheet for channels availability. */ -/* Note: Channels are used by bitfields for setting of channel selection */ -/* (register ADC_CHSELR) and used by number for setting of analog watchdog */ -/* channel (bits AWDCH in register ADC_CFGR1). */ -/* Channels are defined with decimal numbers and converted them to bitfields */ -/* when needed. */ -#define ADC_CHANNEL_0 ((uint32_t) 0x00000000) -#define ADC_CHANNEL_1 ((uint32_t) 0x00000001) -#define ADC_CHANNEL_2 ((uint32_t) 0x00000002) -#define ADC_CHANNEL_3 ((uint32_t) 0x00000003) -#define ADC_CHANNEL_4 ((uint32_t) 0x00000004) -#define ADC_CHANNEL_5 ((uint32_t) 0x00000005) -#define ADC_CHANNEL_6 ((uint32_t) 0x00000006) -#define ADC_CHANNEL_7 ((uint32_t) 0x00000007) -#define ADC_CHANNEL_8 ((uint32_t) 0x00000008) -#define ADC_CHANNEL_9 ((uint32_t) 0x00000009) -#define ADC_CHANNEL_10 ((uint32_t) 0x0000000A) -#define ADC_CHANNEL_11 ((uint32_t) 0x0000000B) -#define ADC_CHANNEL_12 ((uint32_t) 0x0000000C) -#define ADC_CHANNEL_13 ((uint32_t) 0x0000000D) -#define ADC_CHANNEL_14 ((uint32_t) 0x0000000E) -#define ADC_CHANNEL_15 ((uint32_t) 0x0000000F) -#define ADC_CHANNEL_16 ((uint32_t) 0x00000010) -#define ADC_CHANNEL_17 ((uint32_t) 0x00000011) -#define ADC_CHANNEL_18 ((uint32_t) 0x00000012) - -#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 -#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 -#define ADC_CHANNEL_VBAT ADC_CHANNEL_18 - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ - ((CHANNEL) == ADC_CHANNEL_1) || \ - ((CHANNEL) == ADC_CHANNEL_2) || \ - ((CHANNEL) == ADC_CHANNEL_3) || \ - ((CHANNEL) == ADC_CHANNEL_4) || \ - ((CHANNEL) == ADC_CHANNEL_5) || \ - ((CHANNEL) == ADC_CHANNEL_6) || \ - ((CHANNEL) == ADC_CHANNEL_7) || \ - ((CHANNEL) == ADC_CHANNEL_8) || \ - ((CHANNEL) == ADC_CHANNEL_9) || \ - ((CHANNEL) == ADC_CHANNEL_10) || \ - ((CHANNEL) == ADC_CHANNEL_11) || \ - ((CHANNEL) == ADC_CHANNEL_12) || \ - ((CHANNEL) == ADC_CHANNEL_13) || \ - ((CHANNEL) == ADC_CHANNEL_14) || \ - ((CHANNEL) == ADC_CHANNEL_15) || \ - ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ - ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ - ((CHANNEL) == ADC_CHANNEL_VBAT) ) +#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000) +#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000001) /** * @} */ @@ -448,19 +344,20 @@ typedef struct /** @defgroup ADC_rank ADC rank * @{ */ -#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ +#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ #define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */ - -#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ - ((WATCHDOG) == ADC_RANK_NONE) ) /** * @} */ /** @defgroup ADC_sampling_times ADC sampling times * @{ - */ -#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */ + */ +/* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */ +/* to distinguish this parameter versus reset value 0x00000000, */ +/* in the context of management of parameters "SamplingTimeCommon" */ +/* and "SamplingTime" (obsolete)). */ +#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x10000000) /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */ @@ -468,15 +365,6 @@ typedef struct #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */ #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */ #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */ - -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ - ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) /** * @} */ @@ -487,11 +375,6 @@ typedef struct #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) - - -#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) /** * @} */ @@ -499,11 +382,8 @@ typedef struct /** @defgroup ADC_Event_type ADC Event type * @{ */ -#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ -#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ - -#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \ - ((EVENT) == OVR_EVENT) ) +#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ +#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ /** * @} */ @@ -530,54 +410,192 @@ typedef struct #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ - -#define ADC_FLAG_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC | \ - ADC_FLAG_EOSMP | ADC_FLAG_RDY ) - -/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ -#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) /** * @} */ -/** @defgroup ADC_range_verification ADC range verification - * in function of ADC resolution selected (12, 10, 8 or 6 bits) - * @{ - */ -#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ - ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ - (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ - (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ - (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))) ) /** * @} */ -/** @defgroup ADC_regular_rank_verification ADC regular rank verification + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup ADC_Private_Constants ADC Private Constants * @{ - */ -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16))) + */ + +/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular + * @{ + */ + +/* List of external triggers of regular group for ADC1: */ +/* (used internally by HAL driver. To not use into HAL structure parameters) */ +#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)0x00000000) +#define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) +#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) +#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) +#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) /** * @} */ +/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) + /** * @} - */ - -/* Exported macros -----------------------------------------------------------*/ + */ + + +/* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Macros ADC Exported Macros * @{ */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** + * @brief Enable the ADC peripheral + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) + +/** + * @brief Disable the ADC peripheral + * @param __HANDLE__: ADC handle + * @retval None + */ +#define __HAL_ADC_DISABLE(__HANDLE__) \ + do{ \ + (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ + __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ + } while(0) + +/** + * @brief Enable the ADC end of conversion interrupt. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC Interrupt + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @arg ADC_IT_OVR: ADC overrun interrupt source + * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source + * @arg ADC_IT_RDY: ADC Ready interrupt source + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the ADC end of conversion interrupt. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC Interrupt + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @arg ADC_IT_OVR: ADC overrun interrupt source + * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source + * @arg ADC_IT_RDY: ADC Ready interrupt source + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__: ADC handle + * @param __INTERRUPT__: ADC interrupt source to check + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source + * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source + * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source + * @arg ADC_IT_OVR: ADC overrun interrupt source + * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source + * @arg ADC_IT_RDY: ADC Ready interrupt source + * @retval State ofinterruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Get the selected ADC's flag status. + * @param __HANDLE__: ADC handle + * @param __FLAG__: ADC flag + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag + * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag + * @arg ADC_FLAG_AWD: ADC Analog watchdog flag + * @arg ADC_FLAG_OVR: ADC overrun flag + * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag + * @arg ADC_FLAG_RDY: ADC Ready flag + * @retval None + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the ADC's pending flags + * @param __HANDLE__: ADC handle + * @param __FLAG__: ADC flag + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag + * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag + * @arg ADC_FLAG_AWD: ADC Analog watchdog flag + * @arg ADC_FLAG_OVR: ADC overrun flag + * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag + * @arg ADC_FLAG_RDY: ADC Ready flag + * @retval None + */ +/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance->ISR) = (__FLAG__)) + /** @brief Reset ADC handle state * @param __HANDLE__: ADC handle * @retval None */ -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) -/* Macro for internal HAL driver usage, and possibly can be used into code of */ -/* final user. */ +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + + +/** + * @brief Verification of hardware constraints before ADC can be enabled + * @param __HANDLE__: ADC handle + * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) + */ +#define ADC_ENABLING_CONDITIONS(__HANDLE__) \ + (( ( ((__HANDLE__)->Instance->CR) & \ + (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \ + ) == RESET \ + ) ? SET : RESET) + +/** + * @brief Verification of hardware constraints before ADC can be disabled + * @param __HANDLE__: ADC handle + * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) + */ +#define ADC_DISABLING_CONDITIONS(__HANDLE__) \ + (( ( ((__HANDLE__)->Instance->CR) & \ + (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ + ) ? SET : RESET) /** * @brief Verification of ADC state: enabled or disabled @@ -587,11 +605,11 @@ typedef struct /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ /* performed automatically by hardware and flag ADC_FLAG_RDY is not */ /* set. */ -#define __HAL_ADC_IS_ENABLED(__HANDLE__) \ - (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ - (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ - ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ - ) ? SET : RESET) +#define ADC_IS_ENABLE(__HANDLE__) \ + (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ + (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ + ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ + ) ? SET : RESET) /** * @brief Test if conversion trigger of regular group is software start @@ -599,17 +617,17 @@ typedef struct * @param __HANDLE__: ADC handle * @retval SET (software start) or RESET (external trigger) */ -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) /** * @brief Check if no conversion on going on regular group * @param __HANDLE__: ADC handle * @retval SET (conversion is on going) or RESET (no conversion is on going) */ -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ - (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ - ) ? RESET : SET) +#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ + (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ + ) ? RESET : SET) /** * @brief Returns resolution bits in CFGR1 register: RES[1:0]. @@ -617,7 +635,8 @@ typedef struct * @param __HANDLE__: ADC handle * @retval None */ -#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) +#define ADC_GET_RESOLUTION(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) /** * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. @@ -625,57 +644,25 @@ typedef struct * @param __HANDLE__: ADC handle * @retval None */ -#define __HAL_ADC_GET_SAMPLINGTIME(__HANDLE__) (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) - -/** @brief Checks if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC interrupt source to check - * @retval State ofinterruption (SET or RESET) - */ -#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \ - )? SET : RESET \ - ) +#define ADC_GET_SAMPLINGTIME(__HANDLE__) \ + (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) /** - * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt + * @brief Simultaneously clears and sets specific bits of the handle State + * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ -#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) - -/** - * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: ADC handle - * @param __INTERRUPT__: ADC Interrupt - * @retval None - */ -#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) - -/** - * @brief Get the selected ADC's flag status. - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag - * @retval None - */ -#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the ADC's pending flags - * @param __HANDLE__: ADC handle - * @param __FLAG__: ADC flag - * @retval None - */ -/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__)) +#define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Clear ADC error code (set it to error code: "no error") * @param __HANDLE__: ADC handle * @retval None */ -#define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) +#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ + ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** @@ -705,52 +692,61 @@ typedef struct ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17) ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18) */ -#define __HAL_ADC_CHSELR_CHANNEL(_CHANNEL_) ( 1U << (_CHANNEL_)) - -/** - * @} - */ +#define ADC_CHSELR_CHANNEL(_CHANNEL_) \ + ( 1U << (_CHANNEL_)) -/** @defgroup ADC_Exported_Macro_internal_HAL_driver ADC Exported Macro internal HAL driver - * @{ +/** + * @brief Set the ADC's sample time + * @param _SAMPLETIME_: Sample time parameter. + * @retval None */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ +/* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ +/* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */ +/* distinguish this parameter versus reset value 0x00000000, */ +/* in the context of management of parameters "SamplingTimeCommon" */ +/* and "SamplingTime" (obsolete)). */ +#define ADC_SMPR_SET(_SAMPLETIME_) \ + ((_SAMPLETIME_) & (ADC_SMPR_SMP)) /** * @brief Set the Analog Watchdog 1 channel. * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1. * @retval None */ -#define __HAL_ADC_CFGR_AWDCH(_CHANNEL_) ((_CHANNEL_) << 26) +#define ADC_CFGR_AWDCH(_CHANNEL_) \ + ((_CHANNEL_) << 26) /** * @brief Enable ADC discontinuous conversion mode for regular group * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. * @retval None */ -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16) +#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ + ((_REG_DISCONTINUOUS_MODE_) << 16) /** * @brief Enable the ADC auto off mode. * @param _AUTOOFF_: Auto off bit enable or disable. * @retval None */ -#define __HAL_ADC_CFGR1_AUTOOFF(_AUTOOFF_) ((_AUTOOFF_) << 15) +#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ + ((_AUTOOFF_) << 15) /** * @brief Enable the ADC auto delay mode. * @param _AUTOWAIT_: Auto delay bit enable or disable. * @retval None */ -#define __HAL_ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14) +#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ + ((_AUTOWAIT_) << 14) /** * @brief Enable ADC continuous conversion mode. * @param _CONTINUOUS_MODE_: Continuous mode. * @retval None */ -#define __HAL_ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13) +#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ + ((_CONTINUOUS_MODE_) << 13) /** * @brief Enable ADC overrun mode. @@ -758,10 +754,10 @@ typedef struct * @retval Overun bit setting to be programmed into CFGR register */ /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ -/* "OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it as the */ -/* default case to be compliant with other STM32 devices. */ -#define __HAL_ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ - ( ( (_OVERRUN_MODE_) != (OVR_DATA_PRESERVED) \ +/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ +/* as the default case to be compliant with other STM32 devices. */ +#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ + ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ )? (ADC_CFGR1_OVRMOD) : (0x00000000) \ ) @@ -770,65 +766,31 @@ typedef struct * @param _SCAN_MODE_: Scan conversion mode. * @retval None */ -#define __HAL_ADC_CFGR1_SCANDIR(_SCAN_MODE_) \ +/* Note: Scan mode set using this macro (instead of parameter direct set) */ +/* due to different modes on other STM32 devices: to avoid any */ +/* unwanted setting, the exact parameter corresponding to the device */ +/* must be passed to this macro. */ +#define ADC_SCANDIR(_SCAN_MODE_) \ ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ ) - + /** * @brief Enable the ADC DMA continuous request. * @param _DMACONTREQ_MODE_: DMA continuous request mode. * @retval None */ -#define __HAL_ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1) +#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ + ((_DMACONTREQ_MODE_) << 1) /** * @brief Configure the analog watchdog high threshold into register TR. * @param _Threshold_: Threshold value * @retval None */ -#define __HAL_ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16) - -/** - * @brief Enable the ADC peripheral - * @param __HANDLE__: ADC handle - * @retval None - */ -#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) - -/** - * @brief Verification of hardware constraints before ADC can be enabled - * @param __HANDLE__: ADC handle - * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) - */ -#define __HAL_ADC_ENABLING_CONDITIONS(__HANDLE__) \ - (( ( ((__HANDLE__)->Instance->CR) & \ - (ADC_CR_ADCAL | ADC_CR_ADSTP | \ - ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \ - ) == RESET \ - ) ? SET : RESET) - -/** - * @brief Disable the ADC peripheral - * @param __HANDLE__: ADC handle - * @retval None - */ -#define __HAL_ADC_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ - __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ - } while(0) - -/** - * @brief Verification of hardware constraints before ADC can be disabled - * @param __HANDLE__: ADC handle - * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) - */ -#define __HAL_ADC_DISABLING_CONDITIONS(__HANDLE__) \ - (( ( ((__HANDLE__)->Instance->CR) & \ - (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ - ) ? SET : RESET) - +#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ + ((_Threshold_) << 16) + /** * @brief Shift the AWD threshold in function of the selected ADC resolution. * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. @@ -841,8 +803,76 @@ typedef struct * @param _Threshold_: Value to be shifted * @retval None */ -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ - ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2)) +#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ + ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2)) + + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B) ) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT) ) + +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ + ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) + +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) + +#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ + ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \ + ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV) ) + +#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ + ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) + +#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ + ((WATCHDOG) == ADC_RANK_NONE) ) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ + ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) + +#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) + +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ + ((EVENT) == ADC_OVR_EVENT) ) + +/** @defgroup ADC_range_verification ADC range verification + * in function of ADC resolution selected (12, 10, 8 or 6 bits) + * @{ + */ +#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ + ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ + (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ + (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ + (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))) ) +/** + * @} + */ + +/** @defgroup ADC_regular_rank_verification ADC regular rank verification + * @{ + */ +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16))) +/** + * @} + */ /** * @} @@ -920,7 +950,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c index 99f6a0f72f..9fee413930 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c @@ -2,109 +2,26 @@ ****************************************************************************** * @file stm32f0xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions * ++ Calibration (ADC automatic self-calibration) - * + * Other functions (generic functions) are available in file + * "stm32l1xx_hal_adc.c". + * @verbatim - ============================================================================== - ##### ADC specific features ##### - ============================================================================== [..] - (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution - - (#) Interrupt generation at the end of regular conversion and in case of - analog watchdog or overrun events. - - (#) Single and continuous conversion modes. - - (#) Scan mode for automatic conversion of channel 0 to channel 'n'. - - (#) Data alignment with in-built data coherency. - - (#) Programmable sampling time. - - (#) ADC conversion group Regular. - - (#) External trigger (timer or EXTI) with configurable polarity. - - (#) DMA request generation for transfer of conversions data of regular group. - - (#) ADC calibration - - (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at - slower speed. - - (#) ADC input range: from Vref minud (connected to Vssa) to Vref plus(connected to - Vdda or to an external voltage reference). - - - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Enable the ADC interface - As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured - at RCC top level: clock source and clock prescaler. - Two possible clock sources: synchronous clock derived from APB clock - or asynchronous clock derived from ADC dedicated HSI RC oscillator - 14MHz. - Example: - __ADC1_CLK_ENABLE(); (mandatory) - - HI14 enable or let under control of ADC: (optional) - - RCC_OscInitTypeDef RCC_OscInitStructure; - RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; - RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; - RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; - RCC_OscInitStructure.PLL... (optional if used for system clock) - HAL_RCC_OscConfig(&RCC_OscInitStructure); - - Parameter "HSI14State" must be set either: - - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control - the HSI14 oscillator enable/disable (if not used to supply the main - system clock): feature used if ADC mode LowPowerAutoPowerOff is - enabled. - - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator - always enabled: can be used to supply the main system clock. - - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (++) Configure these ADC pins in analog mode using HAL_GPIO_Init(); - - (#) Configure the ADC parameters (conversion resolution, data alignment, - continuous mode, ...) using the HAL_ADC_Init() function. - - (#) Activate the ADC peripheral using one of the start functions: - HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(). - - *** Regular channels group configuration *** - ============================================ - [..] - (+) To configure the ADC regular channels group features, use - HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions. - (+) To activate the continuous mode, use the HAL_ADC_Init() function. - (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. - - *** DMA for Regular channels group features configuration *** - ============================================================= - [..] - (+) To enable the DMA mode for regular channels group, use the - HAL_ADC_Start_DMA() function. - (+) To enable the generation of DMA requests continuously at the end of - the last DMA transfer, use the HAL_ADC_Init() function. - - @endverbatim + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32l1xx_hal_adc.c". + [..] + @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -138,7 +55,7 @@ * @{ */ -/** @defgroup ADCEx ADCEx Extended HAL Module Driver +/** @defgroup ADCEx ADCEx * @brief ADC HAL module driver * @{ */ @@ -163,8 +80,8 @@ /** * @} */ - -/* Private macro -------------------------------------------------------------*/ + +/* Private macros -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ @@ -174,9 +91,9 @@ */ /** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions - * @brief Extended Initialization and Configuration functions + * @brief Extended Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -197,7 +114,7 @@ */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { - HAL_StatusTypeDef tmpHALStatus = HAL_OK; + HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart=0; /* Check the parameters */ @@ -205,12 +122,14 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) /* Process locked */ __HAL_LOCK(hadc); - - /* Calibration prerequisite: ADC must be disabled. */ - if (__HAL_ADC_IS_ENABLED(hadc) == RESET ) + + /* Calibration prerequisite: ADC must be disabled. */ + if (ADC_IS_ENABLE(hadc) == RESET) { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration */ hadc->Instance->CR |= ADC_CR_ADCAL; @@ -223,7 +142,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -231,18 +152,25 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) return HAL_ERROR; } } + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ - hadc->State = HAL_ADC_STATE_ERROR; + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ - return tmpHALStatus; + return tmp_hal_status; } /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h index 7e58010597..73b461e3e3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of ADC HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -56,7 +56,226 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_CCR_ALL (ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN) +#else +#define ADC_CCR_ALL (ADC_CCR_TSEN | ADC_CCR_VREFEN) +#endif + +/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular + * @{ + */ +/* List of external triggers with generic trigger name, sorted by trigger */ +/* name: */ + +/* External triggers of regular group for ADC1 */ +#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO +#define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4 +#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO +#define ADC_SOFTWARE_START (ADC_CFGR1_EXTSEL + (uint32_t)1) + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO +#endif + +#if !defined(STM32F030x6) && !defined(STM32F070x6) && !defined(STM32F042x6) +#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO +#endif + +/** + * @} + */ + + +/** @defgroup ADC_channels ADC channels + * @{ + */ +/* Note: Depending on devices, some channels may not be available on package */ +/* pins. Refer to device datasheet for channels availability. */ +/* Note: Channels are used by bitfields for setting of channel selection */ +/* (register ADC_CHSELR) and used by number for setting of analog */ +/* watchdog channel (bits AWDCH in register ADC_CFGR1). */ +/* Channels are defined with decimal numbers and converted them to */ +/* bitfields when needed. */ +#define ADC_CHANNEL_0 ((uint32_t) 0x00000000) +#define ADC_CHANNEL_1 ((uint32_t) 0x00000001) +#define ADC_CHANNEL_2 ((uint32_t) 0x00000002) +#define ADC_CHANNEL_3 ((uint32_t) 0x00000003) +#define ADC_CHANNEL_4 ((uint32_t) 0x00000004) +#define ADC_CHANNEL_5 ((uint32_t) 0x00000005) +#define ADC_CHANNEL_6 ((uint32_t) 0x00000006) +#define ADC_CHANNEL_7 ((uint32_t) 0x00000007) +#define ADC_CHANNEL_8 ((uint32_t) 0x00000008) +#define ADC_CHANNEL_9 ((uint32_t) 0x00000009) +#define ADC_CHANNEL_10 ((uint32_t) 0x0000000A) +#define ADC_CHANNEL_11 ((uint32_t) 0x0000000B) +#define ADC_CHANNEL_12 ((uint32_t) 0x0000000C) +#define ADC_CHANNEL_13 ((uint32_t) 0x0000000D) +#define ADC_CHANNEL_14 ((uint32_t) 0x0000000E) +#define ADC_CHANNEL_15 ((uint32_t) 0x0000000F) +#define ADC_CHANNEL_16 ((uint32_t) 0x00000010) +#define ADC_CHANNEL_17 ((uint32_t) 0x00000011) + +#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 +#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_CHANNEL_18 ((uint32_t) 0x00000012) +#define ADC_CHANNEL_VBAT ADC_CHANNEL_18 +#endif + +/** + * @} + */ + +/** + * @} + */ + /* Exported macro ------------------------------------------------------------*/ + + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Macros ADCEx Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Test if the selected ADC channel is an internal channel + * VrefInt/TempSensor/Vbat + * Note: On STM32F0, availability of internal channel Vbat depends on + * devices lines. + * @param __CHANNEL__: ADC channel + * @retval None + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT) \ + ) +#else +#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT) \ + ) +#endif + +/** + * @brief Select the internal measurement path to be enabled/disabled + * corresponding to the selected ADC internal channel + * VrefInt/TempSensor/Vbat. + * Note: On STM32F0, availability of internal channel Vbat depends on + * devices lines. + * @param __CHANNEL__: ADC channel + * @retval Bit of register ADC_CCR + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \ + (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \ + )? \ + (ADC_CCR_TSEN) \ + : \ + ( \ + ( (__CHANNEL__) == ADC_CHANNEL_VREFINT \ + )? \ + (ADC_CCR_VREFEN) \ + : \ + (ADC_CCR_VBATEN) \ + ) \ + ) +#else +#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \ + (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \ + )? \ + (ADC_CCR_TSEN) \ + : \ + (ADC_CHANNEL_VREFINT) \ + ) +#endif + + +#if defined (STM32F030x6) || defined (STM32F070x6) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#elif defined (STM32F042x6) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) + +#elif defined (STM32F030xC) || defined (STM32F070xB) || defined (STM32F030x8) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#else +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#endif + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ + ((CHANNEL) == ADC_CHANNEL_VBAT) ) +#else +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_CHANNEL_VREFINT) ) +#endif + +/** + * @} + */ + + /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions * @{ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c index 263c2f7308..2b0824c5b6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_can.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: @@ -17,11 +17,11 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Enable the CAN controller interface clock using __CAN_CLK_ENABLE(); + (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE(); (#) CAN pins configuration (++) Enable the clock for the CAN GPIOs using the following function: - __GPIOx_CLK_ENABLE(); + __HAL_RCC_GPIOx_CLK_ENABLE(); (++) Connect and configure the involved CAN pins to AF9 using the following function HAL_GPIO_Init(); @@ -71,7 +71,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -109,7 +109,7 @@ * @{ */ -/** @defgroup CAN CAN HAL Module Driver +/** @defgroup CAN CAN * @brief CAN driver modules * @{ */ @@ -119,7 +119,7 @@ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define HAL_CAN_DEFAULT_TIMEOUT 10 +#define CAN_TIMEOUT_VALUE 10 /** * @} */ @@ -190,6 +190,8 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) if(hcan->State == HAL_CAN_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hcan->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_CAN_MspInit(hcan); } @@ -203,15 +205,17 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) /* Request initialisation */ hcan->Instance->MCR |= CAN_MCR_INRQ ; - /* Get tickstart */ + /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { - if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT) + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); return HAL_TIMEOUT; } } @@ -289,15 +293,17 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) /* Request leave initialisation */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - /* Get timeout */ + /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { - if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT) + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); return HAL_TIMEOUT; } } @@ -355,6 +361,10 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /* Initialisation mode for the filter */ hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT; + + /* Select the start slave bank */ + hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); + hcan->Instance->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); /* Filter Deactivation */ hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos; @@ -493,8 +503,8 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) * @} */ -/** @defgroup CAN_Exported_Functions_Group2 I/O operation functions - * @brief I/O operation functions +/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions + * @brief IO operation functions * @verbatim ============================================================================== @@ -590,7 +600,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - /* Get timeout */ + /* Get tick */ tickstart = HAL_GetTick(); /* Check End of transmission flag */ @@ -782,7 +792,7 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u hcan->State = HAL_CAN_STATE_BUSY_RX; } - /* Get timeout */ + /* Get tick */ tickstart = HAL_GetTick(); /* Check pending message */ @@ -957,13 +967,13 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) return HAL_ERROR; } - /* Get timeout */ + /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) { - if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT) + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { hcan->State = HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -1002,13 +1012,13 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) /* Wake up request */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - /* Get timeout */ + /* Get tick */ tickstart = HAL_GetTick(); /* Sleep mode status */ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) { - if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT) + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ @@ -1245,7 +1255,6 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) * * @{ */ - /** * @brief Initiates and transmits a CAN frame message. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains @@ -1380,7 +1389,6 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum /* Return function status */ return HAL_OK; } - /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h index 6aec5253f8..a584fd6bad 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_can.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -52,7 +52,7 @@ * @{ */ -/** @addtogroup CAN CAN HAL Module Driver +/** @addtogroup CAN * @{ */ @@ -180,7 +180,7 @@ typedef struct uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint32_t Data[8]; /*!< Contains the data to be transmitted. + uint8_t Data[8]; /*!< Contains the data to be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ }CanTxMsgTypeDef; @@ -205,7 +205,7 @@ typedef struct uint32_t DLC; /*!< Specifies the length of the frame that will be received. This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint32_t Data[8]; /*!< Contains the data to be received. + uint8_t Data[8]; /*!< Contains the data to be received. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. @@ -234,7 +234,7 @@ typedef struct __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ __IO uint32_t ErrorCode; /*!< CAN Error code - This parameter can be a value of @ref CAN_Error */ + This parameter can be a value of @ref HAL_CAN_Error_Code */ }CAN_HandleTypeDef; /** @@ -247,7 +247,7 @@ typedef struct * @{ */ -/** @defgroup CAN_Error CAN Error +/** @defgroup HAL_CAN_Error_Code CAN Error Code * @{ */ #define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ @@ -280,11 +280,6 @@ typedef struct #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ - ((MODE) == CAN_MODE_LOOPBACK)|| \ - ((MODE) == CAN_MODE_SILENT) || \ - ((MODE) == CAN_MODE_SILENT_LOOPBACK)) /** * @} */ @@ -297,9 +292,6 @@ typedef struct #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ - ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) /** * @} */ @@ -324,7 +316,6 @@ typedef struct #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) /** * @} */ @@ -341,23 +332,6 @@ typedef struct #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler CAN clock prescaler - * @{ - */ -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -/** - * @} - */ - -/** @defgroup CAN_filter_number CAN filter number - * @{ - */ -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) /** * @} */ @@ -368,8 +342,6 @@ typedef struct #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ - ((MODE) == CAN_FILTERMODE_IDLIST)) /** * @} */ @@ -380,8 +352,6 @@ typedef struct #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ - ((SCALE) == CAN_FILTERSCALE_32BIT)) /** * @} */ @@ -392,31 +362,6 @@ typedef struct #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ - ((FIFO) == CAN_FILTER_FIFO1)) - -/* Legacy defines */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -/** - * @} - */ - -/** @defgroup CAN_Start_bank_filter_for_slave_CAN CAN Start bank filter for slave CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) -/** - * @} - */ - -/** @defgroup CAN_Tx CAN Tx - * @{ - */ -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) /** * @} */ @@ -426,8 +371,7 @@ typedef struct */ #define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ #define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ - ((IDTYPE) == CAN_ID_EXT)) + /** * @} */ @@ -437,19 +381,6 @@ typedef struct */ #define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ #define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) - -/** - * @} - */ - -/** @defgroup CAN_transmit_constants CAN transmit constants - * @{ - */ -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */ -#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ /** * @} @@ -461,7 +392,6 @@ typedef struct #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) /** * @} */ @@ -532,26 +462,10 @@ typedef struct #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME /** * @} */ -/** @defgroup CAN_Timeouts CAN Timeouts -* @{ -*/ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF) -/** - * @} - */ - /** @defgroup CAN_Mailboxes CAN Mailboxes * @{ */ @@ -630,7 +544,6 @@ typedef struct * @arg CAN_FLAG_BOF: Bus-Off Flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define CAN_FLAG_MASK ((uint32_t)0x000000FF) #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ @@ -751,7 +664,7 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); * @} */ -/** @addtogroup CAN_Exported_Functions_Group2 I/O operation functions +/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions * @brief I/O operation functions * @{ */ @@ -789,6 +702,79 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); * @} */ +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +#define CAN_FLAG_MASK ((uint32_t)0x000000FF) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ + +/** + * @} + */ + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c index fc05c35829..85ab65a9a2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_cec.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface @@ -47,7 +47,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -88,7 +88,7 @@ * @{ */ -/** @defgroup CEC CEC HAL Module Driver +/** @defgroup CEC CEC * @brief HAL CEC module driver * @{ */ @@ -161,7 +161,8 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) return HAL_ERROR; } - /* Check the parameters */ + /* Check the parameters */ + assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime)); assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop)); @@ -172,12 +173,13 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress)); assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode)); assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress)); - - + if(hcec->State == HAL_CEC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hcec->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK */ - HAL_CEC_MspInit(hcec); + HAL_CEC_MspInit(hcec); } hcec->State = HAL_CEC_STATE_BUSY; @@ -365,7 +367,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA hcec->TxXferCount--; tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_TXBR)) + while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR)) { if(Timeout != HAL_MAX_DELAY) { @@ -384,19 +386,19 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA * has Tx Missing Acknowledge error occurred ? * has Arbitration Loss error occurred ? */ tempisr = hcec->Instance->ISR; - if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)) != 0) + if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0) { /* copy ISR for error handling purposes */ hcec->ErrorCode = tempisr; /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)); + __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); hcec->State = HAL_CEC_STATE_ERROR; __HAL_UNLOCK(hcec); return HAL_ERROR; } } /* TXBR to clear BEFORE writing TXDR register */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); if (hcec->TxXferCount == 0) { /* if last byte transmission, set TX End of Message (TXEOM) bit */ @@ -406,12 +408,12 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA /* error check after TX byte write up */ tempisr = hcec->Instance->ISR; - if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)) != 0) + if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0) { /* copy ISR for error handling purposes */ hcec->ErrorCode = tempisr; /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)); + __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); hcec->State = HAL_CEC_STATE_ERROR; __HAL_UNLOCK(hcec); return HAL_ERROR; @@ -438,12 +440,12 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA /* Final error check once all bytes have been transmitted */ tempisr = hcec->Instance->ISR; - if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0) + if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0) { /* copy ISR for error handling purposes */ hcec->ErrorCode = tempisr; /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)); + __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)); hcec->State = HAL_CEC_STATE_ERROR; __HAL_UNLOCK(hcec); return HAL_ERROR; @@ -490,12 +492,12 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3 __HAL_LOCK(hcec); - /* Rx loop until CEC_ISR_RXEND is set */ - while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) + /* Rx loop until CEC_FLAG_RXEND is set */ + while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) { tickstart = HAL_GetTick(); /* Wait for next byte to be received */ - while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) + while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) { if(Timeout != HAL_MAX_DELAY) { @@ -513,46 +515,46 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3 * has Rx Bit Rising error occurred ? * has Rx Overrun error occurred ? */ temp = (uint32_t) (hcec->Instance->ISR); - if ((temp & (CEC_ISR_RXACKE|CEC_ISR_LBPE|CEC_ISR_SBPE|CEC_ISR_BRE|CEC_ISR_RXOVR)) != 0) + if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0) { /* copy ISR for error handling purposes */ hcec->ErrorCode = temp; /* clear all error flags by default */ - __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_RXACKE|CEC_ISR_LBPE|CEC_ISR_SBPE|CEC_ISR_BRE|CEC_ISR_RXOVR)); + __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)); hcec->State = HAL_CEC_STATE_ERROR; __HAL_UNLOCK(hcec); return HAL_ERROR; } - } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */ + } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) */ /* read received data */ *pData++ = hcec->Instance->RXDR; temp = (uint32_t) (hcec->Instance->ISR); /* end of message ? */ - if ((temp & CEC_ISR_RXEND) != 0) + if ((temp & CEC_FLAG_RXEND) != 0) { assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize)); - __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXEND); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND); hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); return HAL_OK; } /* clear Rx-Byte Received flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXBR); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR); /* increment payload byte counter */ hcec->RxXferSize++; - } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */ + } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) */ /* if the instructions below are executed, it means RXEND was set when RXBR was * set for the first time: - * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))" + * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))" * loop has not been executed and this means a single byte has been sent */ *pData++ = hcec->Instance->RXDR; /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */ hcec->RxXferSize = 0; - __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXEND); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND); hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); @@ -609,7 +611,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati * Tx-Error IT * Tx-Buffer Underrun IT * Tx arbitration lost */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE|CEC_IER_TX_ALL_ERR); + __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); /* Enable the Peripheral */ __HAL_CEC_ENABLE(hcec); @@ -656,14 +658,14 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati __HAL_CEC_DISABLE(hcec); /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE); + __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); /* Disable the CEC Transmission Error Interrupts */ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); /* Enable the Peripheral */ __HAL_CEC_ENABLE(hcec); - __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR|CEC_ISR_TXEND); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND); hcec->State = HAL_CEC_STATE_READY; /* Call the Process Unlocked before calling the Tx call back API to give the possibility to @@ -682,7 +684,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati __HAL_CEC_LAST_BYTE_TX_SET(hcec); } /* clear Tx-Byte request flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); hcec->Instance->TXDR = *hcec->pTxBuffPtr++; hcec->TxXferCount--; @@ -744,7 +746,7 @@ HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) /* Enable the following two CEC Reception interrupts: * Rx Byte Received IT * End of Reception IT */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RXBRIE|CEC_IER_RXENDIE); + __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND); __HAL_CEC_ENABLE(hcec); @@ -756,7 +758,15 @@ HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) } } - +/** + * @brief Get size of the received frame. + * @param hcec: CEC handle + * @retval Frame size + */ +uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec) +{ + return hcec->RxXferSize; +} /** * @brief This function handles CEC interrupt requests. @@ -768,65 +778,65 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* save interrupts register for further error or interrupts handling purposes */ hcec->ErrorCode = hcec->Instance->ISR; /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXACKEIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET)) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXACKE); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE); hcec->State = HAL_CEC_STATE_ERROR; } /* CEC transmit error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXERRIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET)) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXERR); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR); hcec->State = HAL_CEC_STATE_ERROR; } /* CEC TX underrun error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXUDRIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET)) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXUDR); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR); hcec->State = HAL_CEC_STATE_ERROR; } /* CEC TX arbitration error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_ARBLSTIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET)) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_ARBLST); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); hcec->State = HAL_CEC_STATE_ERROR; } /* CEC RX overrun error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXOVRIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET)) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXOVR); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR); hcec->State = HAL_CEC_STATE_ERROR; } /* CEC RX bit rising error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_BREIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET)) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_BRE); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE); hcec->State = HAL_CEC_STATE_ERROR; } /* CEC RX short bit period error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_SBPEIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET)) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_SBPE); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE); hcec->State = HAL_CEC_STATE_ERROR; } /* CEC RX long bit period error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_LBPEIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET)) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_LBPE); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE); hcec->State = HAL_CEC_STATE_ERROR; } /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXACKEIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET)) { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXACKE); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE); hcec->State = HAL_CEC_STATE_ERROR; } @@ -836,14 +846,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) } /* CEC RX byte received interrupt ---------------------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXBRIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET)) { /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ CEC_Receive_IT(hcec); } /* CEC RX end received interrupt ---------------------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXENDIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET)) { /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ CEC_Receive_IT(hcec); @@ -851,14 +861,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* CEC TX byte request interrupt ------------------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXBRIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET)) { /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */ CEC_Transmit_IT(hcec); } /* CEC TX end interrupt ------------------------------------------------*/ - if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXENDIE) != RESET)) + if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET)) { /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */ CEC_Transmit_IT(hcec); @@ -983,17 +993,17 @@ static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) __HAL_CEC_DISABLE(hcec); /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE); + __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); /* Disable the CEC Transmission Error Interrupts */ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); /* Enable the Peripheral */ __HAL_CEC_ENABLE(hcec); - __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR|CEC_ISR_TXEND); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND); /* If RX interruptions are enabled, return to HAL_CEC_STATE_STANDBY_RX state */ - if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IER_RXBRIE|CEC_IER_RXENDIE) ) != RESET) + if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IT_RXBR|CEC_IT_RXEND) ) != RESET) { hcec->State = HAL_CEC_STATE_STANDBY_RX; } @@ -1014,7 +1024,7 @@ static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) __HAL_CEC_LAST_BYTE_TX_SET(hcec); } /* clear Tx-Byte request flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR); hcec->Instance->TXDR = *hcec->pTxBuffPtr++; hcec->TxXferCount--; @@ -1055,15 +1065,15 @@ static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec) /* reception is starting */ hcec->State = HAL_CEC_STATE_BUSY_RX; tempisr = (uint32_t) (hcec->Instance->ISR); - if ((tempisr & CEC_ISR_RXBR) != 0) + if ((tempisr & CEC_FLAG_RXBR) != 0) { /* read received byte */ *hcec->pRxBuffPtr++ = hcec->Instance->RXDR; /* if last byte has been received */ - if ((tempisr & CEC_ISR_RXEND) != 0) + if ((tempisr & CEC_FLAG_RXEND) != 0) { /* clear IT */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXBR|CEC_ISR_RXEND); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND); /* RX interrupts are not disabled at this point. * Indeed, to disable the IT, the IP must be disabled first * which resets the TXSOM flag. In case of arbitration loss, @@ -1081,7 +1091,7 @@ static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec) return HAL_OK; } - __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXBR); + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); hcec->RxXferSize++; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h index 4c52b08771..fdad03745e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_cec.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,7 +54,7 @@ * @{ */ -/** @addtogroup CEC CEC HAL Module Driver +/** @addtogroup CEC CEC * @{ */ @@ -143,24 +143,6 @@ typedef enum HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */ }HAL_CEC_StateTypeDef; -/** - * @brief HAL Error structures definition - */ -typedef enum -{ - HAL_CEC_ERROR_NONE = (uint32_t) 0x0, /*!< no error */ - HAL_CEC_ERROR_RXOVR = CEC_ISR_RXOVR, /*!< CEC Rx-Overrun */ - HAL_CEC_ERROR_BRE = CEC_ISR_BRE, /*!< CEC Rx Bit Rising Error */ - HAL_CEC_ERROR_SBPE = CEC_ISR_SBPE, /*!< CEC Rx Short Bit period Error */ - HAL_CEC_ERROR_LBPE = CEC_ISR_LBPE, /*!< CEC Rx Long Bit period Error */ - HAL_CEC_ERROR_RXACKE = CEC_ISR_RXACKE, /*!< CEC Rx Missing Acknowledge */ - HAL_CEC_ERROR_ARBLST = CEC_ISR_ARBLST, /*!< CEC Arbitration Lost */ - HAL_CEC_ERROR_TXUDR = CEC_ISR_TXUDR, /*!< CEC Tx-Buffer Underrun */ - HAL_CEC_ERROR_TXERR = CEC_ISR_TXERR, /*!< CEC Tx-Error */ - HAL_CEC_ERROR_TXACKE = CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ -} -HAL_CEC_ErrorTypeDef; - /** * @brief CEC handle Structure definition */ @@ -178,7 +160,7 @@ typedef struct uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */ - __IO uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register + uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register in case error is reported */ HAL_LockTypeDef Lock; /* Locking object */ @@ -194,7 +176,24 @@ typedef struct /** @defgroup CEC_Exported_Constants CEC Exported Constants * @{ */ - + +/** @defgroup CEC_Error_Code CEC Error Code + * @{ + */ +#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */ +#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ +#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ +#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ +#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */ +#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */ +#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */ +#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */ +#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */ +#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ +/** + * @} + */ + /** @defgroup CEC_Signal_Free_Time Signal Free Time setting parameter * @{ */ @@ -206,7 +205,6 @@ typedef struct #define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005) #define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006) #define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007) -#define IS_CEC_SIGNALFREETIME(SFT) ((SFT) <= CEC_CFGR_SFT) /** * @} */ @@ -216,8 +214,6 @@ typedef struct */ #define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000) #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) -#define IS_CEC_TOLERANCE(RXTOL) (((RXTOL) == CEC_STANDARD_TOLERANCE) || \ - ((RXTOL) == CEC_EXTENDED_TOLERANCE)) /** * @} */ @@ -227,8 +223,6 @@ typedef struct */ #define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000) #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) -#define IS_CEC_BRERXSTOP(BRERXSTOP) (((BRERXSTOP) == CEC_NO_RX_STOP_ON_BRE) || \ - ((BRERXSTOP) == CEC_RX_STOP_ON_BRE)) /** * @} */ @@ -238,8 +232,6 @@ typedef struct */ #define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) -#define IS_CEC_BREERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ - ((ERRORBITGEN) == CEC_BRE_ERRORBIT_GENERATION)) /** * @} */ @@ -249,8 +241,6 @@ typedef struct */ #define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) -#define IS_CEC_LBPEERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ - ((ERRORBITGEN) == CEC_LBPE_ERRORBIT_GENERATION)) /** * @} */ @@ -260,8 +250,6 @@ typedef struct */ #define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000) #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) -#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(ERRORBITGEN) (((ERRORBITGEN) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ - ((ERRORBITGEN) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) /** * @} */ @@ -271,8 +259,6 @@ typedef struct */ #define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000) #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) -#define IS_CEC_SFTOP(SFTOP) (((SFTOP) == CEC_SFT_START_ON_TXSOM) || \ - ((SFTOP) == CEC_SFT_START_ON_TX_RX_END)) /** * @} */ @@ -282,11 +268,66 @@ typedef struct */ #define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000) #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) -#define IS_CEC_LISTENING_MODE(MODE) (((MODE) == CEC_REDUCED_LISTENING_MODE) || \ - ((MODE) == CEC_FULL_LISTENING_MODE)) /** * @} */ + +/** @defgroup CEC_OAR_Position Device Own Address position in CEC CFGR register + * @{ + */ +#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16) +/** + * @} + */ + +/** @defgroup CEC_Initiator_Position Initiator logical address position in message header + * @{ + */ +#define CEC_INITIATOR_LSB_POS ((uint32_t) 4) +/** + * @} + */ + +/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition + * @{ + */ +#define CEC_IT_TXACKE CEC_IER_TXACKEIE +#define CEC_IT_TXERR CEC_IER_TXERRIE +#define CEC_IT_TXUDR CEC_IER_TXUDRIE +#define CEC_IT_TXEND CEC_IER_TXENDIE +#define CEC_IT_TXBR CEC_IER_TXBRIE +#define CEC_IT_ARBLST CEC_IER_ARBLSTIE +#define CEC_IT_RXACKE CEC_IER_RXACKEIE +#define CEC_IT_LBPE CEC_IER_LBPEIE +#define CEC_IT_SBPE CEC_IER_SBPEIE +#define CEC_IT_BRE CEC_IER_BREIE +#define CEC_IT_RXOVR CEC_IER_RXOVRIE +#define CEC_IT_RXEND CEC_IER_RXENDIE +#define CEC_IT_RXBR CEC_IER_RXBRIE +/** + * @} + */ + +/** @defgroup CEC_Flags_Definitions CEC Flags definition + * @{ + */ +#define CEC_FLAG_TXACKE CEC_ISR_TXACKE +#define CEC_FLAG_TXERR CEC_ISR_TXERR +#define CEC_FLAG_TXUDR CEC_ISR_TXUDR +#define CEC_FLAG_TXEND CEC_ISR_TXEND +#define CEC_FLAG_TXBR CEC_ISR_TXBR +#define CEC_FLAG_ARBLST CEC_ISR_ARBLST +#define CEC_FLAG_RXACKE CEC_ISR_RXACKE +#define CEC_FLAG_LBPE CEC_ISR_LBPE +#define CEC_FLAG_SBPE CEC_ISR_SBPE +#define CEC_FLAG_BRE CEC_ISR_BRE +#define CEC_FLAG_RXOVR CEC_ISR_RXOVR +#define CEC_FLAG_RXEND CEC_ISR_RXEND +#define CEC_FLAG_RXBR CEC_ISR_RXBR +/** + * @} + */ + /** @defgroup CEC_ALL_ERROR all RX or TX errors flags in CEC ISR register * @{ @@ -311,23 +352,7 @@ typedef struct #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) /** * @} - */ - -/** @defgroup CEC_OAR_Position Device Own Address position in CEC CFGR register - * @{ - */ -#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16) -/** - * @} - */ - -/** @defgroup CEC_Initiator_Position Initiator logical address position in message header - * @{ - */ -#define CEC_INITIATOR_LSB_POS ((uint32_t) 4) -/** - * @} - */ + */ /** * @} @@ -346,63 +371,62 @@ typedef struct /** @brief Checks whether or not the specified CEC interrupt flag is set. * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the interrupt to check. - * This parameter can be one of the following values: - * @arg CEC_ISR_RXBR : Rx-Byte Received - * @arg CEC_ISR_RXEND : End of Reception - * @arg CEC_ISR_RXOVR : Rx Overrun - * @arg CEC_ISR_BRE : Rx Bit Rising Error - * @arg CEC_ISR_SBPE : Rx Short Bit Period Error - * @arg CEC_ISR_LBPE : Rx Long Bit Period Error - * @arg CEC_ISR_RXACKE : Rx Missing Acknowledge - * @arg CEC_ISR_ARBLST : Arbitration lost - * @arg CEC_ISR_TXBR : Tx-Byte Request - * @arg CEC_ISR_TXEND : End of Transmission - * @arg CEC_ISR_TXUDR : Tx-buffer Underrun - * @arg CEC_ISR_TXERR : Tx Error - * @arg CEC_ISR_TXACKE : Tx Missing Acknowledge - * @retval ITStatus + * @param __FLAG__: specifies the interrupt to check. + * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error + * @arg CEC_FLAG_TXERR: Tx Error. + * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. + * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_FLAG_TXBR: Tx-Byte Request. + * @arg CEC_FLAG_ARBLST: Arbitration Lost + * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge + * @arg CEC_FLAG_LBPE: Rx Long period Error + * @arg CEC_FLAG_SBPE: Rx Short period Error + * @arg CEC_FLAG_BRE: Rx Bit Rissing Error + * @arg CEC_FLAG_RXOVR: Rx Overrun. + * @arg CEC_FLAG_RXEND: End Of Reception. + * @arg CEC_FLAG_RXBR: Rx-Byte Received. + * @retval None */ -#define __HAL_CEC_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__)) +#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) /** @brief Clears the interrupt or status flag when raised (write at 1) * @param __HANDLE__: specifies the CEC Handle. * @param __FLAG__: specifies the interrupt/status flag to clear. * This parameter can be one of the following values: - * @arg CEC_ISR_RXBR : Rx-Byte Received - * @arg CEC_ISR_RXEND : End of Reception - * @arg CEC_ISR_RXOVR : Rx Overrun - * @arg CEC_ISR_BRE : Rx Bit Rising Error - * @arg CEC_ISR_SBPE : Rx Short Bit Period Error - * @arg CEC_ISR_LBPE : Rx Long Bit Period Error - * @arg CEC_ISR_RXACKE : Rx Missing Acknowledge - * @arg CEC_ISR_ARBLST : Arbitration lost - * @arg CEC_ISR_TXBR : Tx-Byte Request - * @arg CEC_ISR_TXEND : End of Transmission - * @arg CEC_ISR_TXUDR : Tx-buffer Underrun - * @arg CEC_ISR_TXERR : Tx Error - * @arg CEC_ISR_TXACKE : Tx Missing Acknowledge + * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error + * @arg CEC_FLAG_TXERR: Tx Error. + * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. + * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). + * @arg CEC_FLAG_TXBR: Tx-Byte Request. + * @arg CEC_FLAG_ARBLST: Arbitration Lost + * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge + * @arg CEC_FLAG_LBPE: Rx Long period Error + * @arg CEC_FLAG_SBPE: Rx Short period Error + * @arg CEC_FLAG_BRE: Rx Bit Rissing Error + * @arg CEC_FLAG_RXOVR: Rx Overrun. + * @arg CEC_FLAG_RXEND: End Of Reception. + * @arg CEC_FLAG_RXBR: Rx-Byte Received. * @retval none */ -#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (__FLAG__)) +#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) /** @brief Enables the specified CEC interrupt. * @param __HANDLE__: specifies the CEC Handle. * @param __INTERRUPT__: specifies the CEC interrupt to enable. * This parameter can be one of the following values: - * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable - * @arg CEC_IER_RXENDIE : End Of Reception IT Enable - * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable - * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable - * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable - * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable - * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable - * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable - * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable - * @arg CEC_IER_TXENDIE : End of Transmission IT Enable - * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable - * @arg CEC_IER_TXERRIE : Tx-Error IT Enable - * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable + * @arg CEC_IT_TXERR: Tx Error IT Enable + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable + * @arg CEC_IT_TXEND: End of transmission IT Enable + * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable + * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable + * @arg CEC_IT_LBPE: Rx Long period Error IT Enable + * @arg CEC_IT_SBPE: Rx Short period Error IT Enable + * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable + * @arg CEC_IT_RXOVR: Rx Overrun IT Enable + * @arg CEC_IT_RXEND: End Of Reception IT Enable + * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable * @retval none */ #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) @@ -411,19 +435,19 @@ typedef struct * @param __HANDLE__: specifies the CEC Handle. * @param __INTERRUPT__: specifies the CEC interrupt to disable. * This parameter can be one of the following values: - * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable - * @arg CEC_IER_RXENDIE : End Of Reception IT Enable - * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable - * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable - * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable - * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable - * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable - * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable - * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable - * @arg CEC_IER_TXENDIE : End of Transmission IT Enable - * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable - * @arg CEC_IER_TXERRIE : Tx-Error IT Enable - * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable + * @arg CEC_IT_TXERR: Tx Error IT Enable + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable + * @arg CEC_IT_TXEND: End of transmission IT Enable + * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable + * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable + * @arg CEC_IT_LBPE: Rx Long period Error IT Enable + * @arg CEC_IT_SBPE: Rx Short period Error IT Enable + * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable + * @arg CEC_IT_RXOVR: Rx Overrun IT Enable + * @arg CEC_IT_RXEND: End Of Reception IT Enable + * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable * @retval none */ #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) @@ -432,19 +456,19 @@ typedef struct * @param __HANDLE__: specifies the CEC Handle. * @param __INTERRUPT__: specifies the CEC interrupt to check. * This parameter can be one of the following values: - * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable - * @arg CEC_IER_RXENDIE : End Of Reception IT Enable - * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable - * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable - * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable - * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable - * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable - * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable - * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable - * @arg CEC_IER_TXENDIE : End of Transmission IT Enable - * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable - * @arg CEC_IER_TXERRIE : Tx-Error IT Enable - * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable + * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable + * @arg CEC_IT_TXERR: Tx Error IT Enable + * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable + * @arg CEC_IT_TXEND: End of transmission IT Enable + * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable + * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable + * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable + * @arg CEC_IT_LBPE: Rx Long period Error IT Enable + * @arg CEC_IT_SBPE: Rx Short period Error IT Enable + * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable + * @arg CEC_IT_RXOVR: Rx Overrun IT Enable + * @arg CEC_IT_RXEND: End Of Reception IT Enable + * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable * @retval FlagStatus */ #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) @@ -499,7 +523,112 @@ typedef struct * @retval none */ #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CEC_Exported_Functions + * @{ + */ +/** @addtogroup CEC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); +HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); +void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); +void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); +/** + * @} + */ + +/** @addtogroup CEC_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData); +uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec); +void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); +void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); +void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec); +void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); +/** + * @} + */ + +/** @addtogroup CEC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); +uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CEC_Private_Types CEC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Variables CEC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Constants CEC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CEC_Private_Macros CEC Private Macros + * @{ + */ + +#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) + +#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ + ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) + +#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ + ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) + +#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ + ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) + +#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ + ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) + +#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ + ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) + +#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ + ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) + +#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ + ((__MODE__) == CEC_FULL_LISTENING_MODE)) + /** @brief Check CEC device Own Address Register (OAR) setting. * OAR address is written in a 15-bit field within CEC_CFGR register. * @param __ADDRESS__: CEC own address. @@ -521,57 +650,17 @@ typedef struct * @param __SIZE__: CEC message size. * @retval Test result (TRUE or FALSE). */ -#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF) - +#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF) + /** * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CEC_Exported_Functions CEC Exported Functions - * @{ - */ -/** @addtogroup CEC_Exported_Functions_Group1 Initialization/de-initialization function - * @brief Initialization and Configuration functions - * @{ - */ -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); -HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); -void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); -void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); -/** - * @} - */ - -/** @addtogroup CEC_Exported_Functions_Group2 IO operation function - * @brief CEC Transmit/Receive functions - * @{ - */ -/* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); -HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData); -void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); -void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); -void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec); -void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); -/** - * @} - */ - -/** @addtogroup CEC_Exported_Functions_Group3 Peripheral Control function - * @brief CEC control functions - * @{ */ -/* Peripheral State functions ************************************************/ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); -/** - * @} - */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Functions CEC Private Functions + * @{ + */ + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c index 88e46e7778..1919abd851 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_comp.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief COMP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: @@ -19,25 +19,24 @@ [..] The STM32F0xx device family integrates up to 2 analog comparators COMP1 and COMP2: - (#) The non inverting input and inverting input can be set to GPIO pins + (+) The non inverting input and inverting input can be set to GPIO pins as shown in table1. COMP Inputs below. - (#) The COMP output is available using HAL_COMP_GetOutputLevel() + (+) The COMP output is available using HAL_COMP_GetOutputLevel() and can be set on GPIO pins. Refer to table 2. COMP Outputs below. - (#) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3) + (+) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3) Refer to table 3. COMP Outputs redirection to embedded timers below. - (#) The comparators COMP1 and COMP2 can be combined in window mode. + (+) The comparators COMP1 and COMP2 can be combined in window mode. - (#) The comparators have interrupt capability with wake-up + (+) The comparators have interrupt capability with wake-up from Sleep and Stop modes (through the EXTI controller): (++) COMP1 is internally connected to EXTI Line 21 (++) COMP2 is internally connected to EXTI Line 22 - From the corresponding IRQ handler, the right interrupt source can be retrieved with the - macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are: - (++) COMP_EXTI_LINE_COMP1_EVENT - (++) COMP_EXTI_LINE_COMP2_EVENT + + (+) From the corresponding IRQ handler, the right interrupt source can be retrieved with the + macros __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG(). [..] Table 1. COMP Inputs for the STM32F05x, STM32F07x and STM32F09x devices @@ -100,23 +99,36 @@ interrupt vector using HAL_NVIC_EnableIRQ() function. (#) Configure the comparator using HAL_COMP_Init() function: - (++) Select the inverting input - (++) Select the non inverting input + (++) Select the inverting input (input minus) + (++) Select the non inverting input (input plus) (++) Select the output polarity (++) Select the output redirection (++) Select the hysteresis level (++) Select the power mode (++) Select the event/interrupt mode + (++) Select the window mode - (#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode - - (#) Read the comparator output level with HAL_COMP_GetOutputLevel() + -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() in order + to access the comparator(s) registers. + + (#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode. + (#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions + to manage comparator outputs (event/interrupt triggered and output level). + + (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT() + function. + + (#) De-initialize the comparator using HAL_COMP_DeInit() function. + + (#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function. + Only a MCU reset can reset that protection. + @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -156,7 +168,7 @@ * @{ */ -/** @defgroup COMP COMP HAL Module Driver +/** @defgroup COMP COMP * @brief COMP HAL module driver * @{ */ @@ -235,19 +247,26 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_DAC1SWITCH_INSTANCE(hcomp->Instance)); } - if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED) + if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) { assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance)); } - + + /* Init SYSCFG and the low level hardware to access comparators */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Init the low level hardware : SYSCFG to access comparators */ + HAL_COMP_MspInit(hcomp); + if(hcomp->State == HAL_COMP_STATE_RESET) { - /* Init SYSCFG and the low level hardware to access comparators */ - __SYSCFG_CLK_ENABLE(); - - HAL_COMP_MspInit(hcomp); + /* Allocate lock resource and initialize it */ + hcomp->Lock = HAL_UNLOCKED; } - + + /* Change COMP peripheral state */ + hcomp->State = HAL_COMP_STATE_BUSY; + /* Set COMP parameters */ /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */ /* Set COMPxOUTSEL bits according to hcomp->Init.Output value */ @@ -259,7 +278,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) regshift = COMP_CSR_COMP2_SHIFT; } MODIFY_REG(COMP->CSR, - (uint32_t)(COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \ + (COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \ COMP_CSR_COMPxOUTSEL | COMP_CSR_COMPxPOL | \ COMP_CSR_COMPxHYST | COMP_CSR_COMPxMODE) << regshift, (hcomp->Init.InvertingInput | \ @@ -269,16 +288,13 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) hcomp->Init.Hysteresis | \ hcomp->Init.Mode) << regshift); - if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED) + if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) { COMP->CSR |= COMP_CSR_WNDWEN; } /* Initialize the COMP state*/ - if(hcomp->State == HAL_COMP_STATE_RESET) - { - hcomp->State = HAL_COMP_STATE_READY; - } + hcomp->State = HAL_COMP_STATE_READY; } return status; @@ -319,6 +335,9 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_COMP_MspDeInit(hcomp); hcomp->State = HAL_COMP_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcomp); } return status; @@ -394,7 +413,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { regshift = COMP_CSR_COMP2_SHIFT; } - SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); + SET_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift); hcomp->State = HAL_COMP_STATE_BUSY; } @@ -434,7 +453,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) { regshift = COMP_CSR_COMP2_SHIFT; } - CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); + CLEAR_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift); hcomp->State = HAL_COMP_STATE_READY; } @@ -464,29 +483,31 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) if(status == HAL_OK) { /* Check the Exti Line output configuration */ - extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); + extiline = COMP_GET_EXTI_LINE(hcomp->Instance); /* Configure the rising edge */ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET) { - __HAL_COMP_EXTI_RISING_IT_ENABLE(extiline); + SET_BIT(EXTI->RTSR, extiline); } else { - __HAL_COMP_EXTI_RISING_IT_DISABLE(extiline); + CLEAR_BIT(EXTI->RTSR, extiline); } /* Configure the falling edge */ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET) { - __HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline); + SET_BIT(EXTI->FTSR, extiline); } else { - __HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline); + CLEAR_BIT(EXTI->FTSR, extiline); } + + /* Clear COMP EXTI pending bit */ + WRITE_REG(EXTI->PR, extiline); + /* Enable Exti interrupt mode */ - __HAL_COMP_EXTI_ENABLE_IT(extiline); - /* Clear COMP Exti pending bit */ - __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + SET_BIT(EXTI->IMR, extiline); } return status; @@ -502,7 +523,7 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Disable the Exti Line interrupt mode */ - __HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance)); + CLEAR_BIT(EXTI->IMR, COMP_GET_EXTI_LINE(hcomp->Instance)); status = HAL_COMP_Stop(hcomp); @@ -516,17 +537,17 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) */ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) { - uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); + uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance); /* Check COMP Exti flag */ - if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET) + if(READ_BIT(EXTI->PR, extiline) != RESET) { /* Clear COMP Exti pending bit */ - __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + WRITE_REG(EXTI->PR, extiline); /* COMP trigger user callback */ HAL_COMP_TriggerCallback(hcomp); - } + } } /** @@ -576,7 +597,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) { regshift = COMP_CSR_COMP2_SHIFT; } - SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift); + SET_BIT(COMP->CSR, COMP_CSR_COMPxLOCK << regshift); } return status; @@ -611,7 +632,7 @@ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { regshift = COMP_CSR_COMP2_SHIFT; } - level = READ_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxOUT << regshift); + level = READ_BIT(COMP->CSR, COMP_CSR_COMPxOUT << regshift); if(level != 0) { diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h index 82cf797adc..9eed8fd793 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_comp.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,7 +54,7 @@ * @{ */ -/** @addtogroup COMP COMP HAL Module Driver +/** @addtogroup COMP COMP * @{ */ @@ -134,9 +134,6 @@ typedef struct */ #define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ #define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */ - -#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \ - ((POL) == COMP_OUTPUTPOL_INVERTED)) /** * @} */ @@ -148,11 +145,6 @@ typedef struct #define COMP_HYSTERESIS_LOW COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */ #define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */ #define COMP_HYSTERESIS_HIGH COMP_CSR_COMP1HYST /*!< Hysteresis level high */ - -#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \ - ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \ - ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \ - ((HYSTERESIS) == COMP_HYSTERESIS_HIGH)) /** * @} */ @@ -166,12 +158,6 @@ typedef struct #define COMP_MODE_MEDIUMSPEED COMP_CSR_COMP1MODE_0 /*!< Medium Speed */ #define COMP_MODE_LOWPOWER COMP_CSR_COMP1MODE_1 /*!< Low power mode */ #define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMP1MODE /*!< Ultra-low power mode */ - -#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \ - ((MODE) == COMP_MODE_MEDIUMSPEED) || \ - ((MODE) == COMP_MODE_LOWPOWER) || \ - ((MODE) == COMP_MODE_ULTRALOWPOWER)) - /** * @} */ @@ -189,15 +175,6 @@ typedef struct and close switch (PA0 for COMP1 only) */ #define COMP_INVERTINGINPUT_DAC2 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_0) /*!< DAC_OUT2 (PA5) connected to comparator inverting input */ #define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_1) /*!< IO (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */ - -#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \ - ((INPUT) == COMP_INVERTINGINPUT_DAC1) || \ - ((INPUT) == COMP_INVERTINGINPUT_DAC1SWITCHCLOSED) || \ - ((INPUT) == COMP_INVERTINGINPUT_DAC2) || \ - ((INPUT) == COMP_INVERTINGINPUT_IO1)) /** * @} */ @@ -208,9 +185,6 @@ typedef struct #define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA3 for COMP2) connected to comparator non inverting input */ #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */ - -#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \ - ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)) /** * @} */ @@ -228,16 +202,6 @@ typedef struct #define COMP_OUTPUT_TIM2OCREFCLR (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM2 OCREF Clear */ #define COMP_OUTPUT_TIM3IC1 (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 Input Capture 1 */ #define COMP_OUTPUT_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */ - -#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \ - ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \ - ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \ - ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \ - ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \ - ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \ - ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \ - ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)) - /** * @} */ @@ -262,11 +226,9 @@ typedef struct #define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */ #define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */ #define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_NONE) || \ - ((MODE) == COMP_TRIGGERMODE_IT_RISING) || \ - ((MODE) == COMP_TRIGGERMODE_IT_FALLING) || \ - ((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING)) +#define COMP_TRIGGERMODE_EVENT_RISING ((uint32_t)0x00000010) /*!< Event Mode with Rising edge trigger detection */ +#define COMP_TRIGGERMODE_EVENT_FALLING ((uint32_t)0x00000020) /*!< Event Mode with Falling edge trigger detection */ +#define COMP_TRIGGERMODE_EVENT_RISING_FALLING ((uint32_t)0x00000030) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -274,40 +236,22 @@ typedef struct /** @defgroup COMP_WindowMode COMP WindowMode * @{ */ -#define COMP_WINDOWMODE_DISABLED ((uint32_t)0x00000000) /*!< Window mode disabled */ -#define COMP_WINDOWMODE_ENABLED COMP_CSR_WNDWEN /*!< Window mode enabled: non inverting input of comparator 2 +#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */ +#define COMP_WINDOWMODE_ENABLE COMP_CSR_WNDWEN /*!< Window mode enabled: non inverting input of comparator 2 is connected to the non inverting input of comparator 1 (PA1) */ - -#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLED) || \ - ((WINDOWMODE) == COMP_WINDOWMODE_ENABLED)) /** * @} */ -/** @defgroup COMP_ExtiLineEvent COMP ExtiLineEvent - * Elements values convention: XXXX0000 - * - XXXX : Interrupt mask in the EMR/IMR/RTSR/FTSR register - * @{ - */ -#define COMP_EXTI_LINE_COMP1_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to COMP1 */ -#define COMP_EXTI_LINE_COMP2_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to COMP2 */ +/** @defgroup COMP_Flag COMP Flag + * @{ + */ +#define COMP_FLAG_LOCK ((uint32_t)COMP_CSR_COMPxLOCK) /*!< Lock flag */ /** * @} */ -/** @defgroup COMP_Lock COMP Lock - * @{ - */ -#define COMP_LOCK_DISABLE ((uint32_t)0x00000000) -#define COMP_LOCK_ENABLE COMP_CSR_COMP1LOCK - -#define COMP_STATE_BIT_LOCK ((uint32_t)0x10) -/** - * @} - */ - - /** * @} */ @@ -324,76 +268,209 @@ typedef struct #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) /** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param __FLAG__: specifies the COMP Exti sources to be checked. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval The state of __FLAG__ (SET or RESET). + * @brief Enable the specified comparator. + * @param __HANDLE__: COMP handle. + * @retval None */ -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (EXTI->PR & (__FLAG__)) +#define __HAL_COMP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ + SET_BIT(COMP->CSR, COMP_CSR_COMP1EN) : \ + SET_BIT(COMP->CSR, COMP_CSR_COMP2EN)) + +/** + * @brief Disable the specified comparator. + * @param __HANDLE__: COMP handle. + * @retval None + */ +#define __HAL_COMP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ + CLEAR_BIT(COMP->CSR, COMP_CSR_COMP1EN) : \ + CLEAR_BIT(COMP->CSR, COMP_CSR_COMP2EN)) + +/** + * @brief Lock the specified comparator configuration. + * @param __HANDLE__: COMP handle. + * @retval None + */ +#define __HAL_COMP_LOCK(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \ + SET_BIT(COMP->CSR, COMP_CSR_COMP1LOCK) : \ + SET_BIT(COMP->CSR, COMP_CSR_COMP2LOCK)) + +/** + * @brief Enable the COMP1 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the COMP1 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Enable the COMP1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Generate a software interrupt on the COMP1 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI Line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI Line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) + +/** + * @brief Check whether the COMP1 EXTI line flag is set or not. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1) /** - * @brief Clear the COMP Exti flags. - * @param __FLAG__: specifies the COMP Exti sources to be cleared. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Clear the COMP1 EXTI flag. + * @retval None */ -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) +#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1) /** - * @brief Enable the COMP Exti Line. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Enable the COMP2 EXTI line rising edge trigger. + * @retval None */ -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) - +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) + /** - * @brief Disable the COMP Exti Line. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. + * @brief Disable the COMP2 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Enable the COMP2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line in interrupt mode. + * @retval None */ -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) +#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) /** - * @brief Enable the Exti Line rising edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (EXTI->RTSR |= (__EXTILINE__)) - -/** - * @brief Disable the Exti Line rising edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (EXTI->RTSR &= ~(__EXTILINE__)) - -/** - * @brief Enable the Exti Line falling edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (EXTI->FTSR |= (__EXTILINE__)) - -/** - * @brief Disable the Exti Line falling edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent - * @retval None. - */ -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (EXTI->FTSR &= ~(__EXTILINE__)) - -/** - * @brief Get the specified EXTI line for a comparator instance - * @param __INSTANCE__: specifies the COMP instance. - * @retval value of @ref COMP_ExtiLineEvent + * @brief Generate a software interrupt on the COMP2 EXTI line. + * @retval None */ -#define __HAL_COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1_EVENT : \ - COMP_EXTI_LINE_COMP2_EVENT) +#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI Line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI Line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Check whether the COMP2 EXTI line flag is set or not. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Clear the COMP2 EXTI flag. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2) + +/** @brief Check whether the specified COMP flag is set or not. + * @param __HANDLE__: specifies the COMP Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg COMP_FLAG_LOCK: lock flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) + /** * @} */ @@ -457,6 +534,114 @@ uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup COMP_Private_Constants COMP Private Constants + * @{ + */ +/** @defgroup COMP_ExtiLine COMP EXTI Lines + * Elements values convention: XXXX0000 + * - XXXX : Interrupt mask in the EMR/IMR/RTSR/FTSR register + * @{ + */ +#define COMP_EXTI_LINE_COMP1 ((uint32_t)EXTI_IMR_MR21) /*!< EXTI line 21 connected to COMP1 output */ +#define COMP_EXTI_LINE_COMP2 ((uint32_t)EXTI_IMR_MR22) /*!< EXTI line 22 connected to COMP2 output */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup COMP_Private_Macros COMP Private Macros + * @{ + */ +/** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators + * @{ + */ +/** + * @brief Get the specified EXTI line for a comparator instance. + * @param __INSTANCE__: specifies the COMP instance. + * @retval value of @ref COMP_ExtiLine + */ +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \ + COMP_EXTI_LINE_COMP2) +/** + * @} + */ + +/** @defgroup COMP_IS_COMP_Definitions COMP Private macros to check input parameters + * @{ + */ + +#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \ + ((POL) == COMP_OUTPUTPOL_INVERTED)) + +#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \ + ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \ + ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \ + ((HYSTERESIS) == COMP_HYSTERESIS_HIGH)) + +#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \ + ((MODE) == COMP_MODE_MEDIUMSPEED) || \ + ((MODE) == COMP_MODE_LOWPOWER) || \ + ((MODE) == COMP_MODE_ULTRALOWPOWER)) + +#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \ + ((INPUT) == COMP_INVERTINGINPUT_DAC1) || \ + ((INPUT) == COMP_INVERTINGINPUT_DAC1SWITCHCLOSED) || \ + ((INPUT) == COMP_INVERTINGINPUT_DAC2) || \ + ((INPUT) == COMP_INVERTINGINPUT_IO1)) + +#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \ + ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED)) + +#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \ + ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \ + ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \ + ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \ + ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \ + ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \ + ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \ + ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR)) + +#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \ + ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE)) + +#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ + ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ + ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \ + ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \ + ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \ + ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \ + ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING)) +/** + * @} + */ + +/** @defgroup COMP_Lock COMP Lock + * @{ + */ +#define COMP_LOCK_DISABLE ((uint32_t)0x00000000) +#define COMP_LOCK_ENABLE COMP_CSR_COMP1LOCK + +#define COMP_STATE_BIT_LOCK ((uint32_t)0x10) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h index c39e929da1..b3f88818a5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h @@ -1,14 +1,14 @@ /** ****************************************************************************** - * @file stm32f0xx_hal_conf_template.h + * @file stm32f0xx_hal_conf.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief HAL configuration file. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -146,6 +146,10 @@ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c index 26af9a410a..76ac3713ed 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_cortex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -32,13 +32,15 @@ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + -@- Negative value of IRQn_Type are not allowed. [..] *** How to configure Systick using CORTEX HAL driver *** ======================================================== [..] - Setup SysTick Timer for time base + Setup SysTick Timer for time base. (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which is a CMSIS function that: @@ -68,7 +70,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -102,7 +104,7 @@ * @{ */ -/** @defgroup CORTEX CORTEX HAL module driver +/** @defgroup CORTEX CORTEX * @brief CORTEX CORTEX HAL module driver * @{ */ @@ -141,10 +143,10 @@ * @param IRQn: External interrupt number . * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) - * @param PreemptPriority: The pre-emption priority for the IRQn channel. + * @param PreemptPriority: The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 3. * A lower priority value indicates a higher priority - * @param SubPriority: The subpriority level for the IRQ channel. + * @param SubPriority: the subpriority level for the IRQ channel. * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0 based products. * @retval None @@ -160,26 +162,32 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub * @brief Enables a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. - * @param IRQn External interrupt number + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } /** * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } @@ -228,7 +236,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number + * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval None @@ -248,6 +256,9 @@ uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } @@ -255,7 +266,7 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) /** * @brief Gets Pending Interrupt (reads the pending register in the NVIC * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval status: - 0 Interrupt status is not pending. @@ -263,19 +274,25 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } /** * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h index 28f2be05d6..62715f5ce7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_cortex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,30 +50,22 @@ * @{ */ -/** @addtogroup CORTEX CORTEX HAL module driver +/** @addtogroup CORTEX CORTEX * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ + /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants * @{ */ -/** @defgroup CORTEX_Priority CORTEX Priority - * @{ - */ -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) -/** - * @} - */ - /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source * @{ */ #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + /** * @} */ @@ -147,6 +139,23 @@ void HAL_SYSTICK_Callback(void); * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +/** + * @} + */ + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c index ba5e364b15..3f6a3e25ec 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_crc.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -16,7 +16,7 @@ ##### How to use this driver ##### =============================================================================== [..] - (#) Enable CRC AHB clock using __CRC_CLK_ENABLE(); + (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); (#) Initialize CRC calculator (++)specify generating polynomial (IP default or non-default one) (++)specify initialization value (IP default or non-default one) @@ -33,7 +33,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,7 +67,7 @@ * @{ */ -/** @defgroup CRC CRC HAL module driver +/** @defgroup CRC CRC * @brief CRC HAL module driver. * @{ */ @@ -130,6 +130,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) if(hcrc->State == HAL_CRC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h index 7b13f58309..39836319ff 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_crc.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup CRC CRC HAL module driver +/** @addtogroup CRC CRC * @{ */ @@ -111,8 +111,8 @@ typedef struct uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. Can be either - CRC_OUTPUTDATA_INVERSION_DISABLED no CRC inversion, or - CRC_OUTPUTDATA_INVERSION_ENABLED CRC 0x11223344 is converted into 0x22CC4488 */ + CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or + CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ }CRC_InitTypeDef; @@ -238,6 +238,20 @@ typedef struct */ #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param __HANDLE__: CRC handle + * @param __VALUE__: 8-bit value to be stored in the ID register + * @retval None + */ +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * @param __HANDLE__: CRC handle + * @retval 8-bit value of the ID register + */ +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c index 807fe8ad80..6984dca3d9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Extended CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CRC peripheral: @@ -25,7 +25,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,7 +59,7 @@ * @{ */ -/** @defgroup CRCEx CRCEx Extended HAL Module Driver +/** @defgroup CRCEx CRCEx * @brief CRC Extended HAL module driver * @{ */ @@ -160,8 +160,8 @@ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t * @param hcrc: CRC handle * @param OutputReverseMode: Output Data inversion mode * This parameter can be one of the following values: - * @arg CRC_OUTPUTDATA_INVERSION_DISABLED: no CRC inversion (default value) - * @arg CRC_OUTPUTDATA_INVERSION_ENABLED: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) + * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value) + * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h index 9a49b6e41f..f38ce6b243 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup CRCEx CRCEx Extended HAL Module Driver +/** @addtogroup CRCEx CRCEx * @{ */ @@ -78,11 +78,11 @@ /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes * @{ */ -#define CRC_OUTPUTDATA_INVERSION_DISABLED ((uint32_t)0x00000000) -#define CRC_OUTPUTDATA_INVERSION_ENABLED ((uint32_t)CRC_CR_REV_OUT) +#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000) +#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) -#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLED) || \ - ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLED)) +#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ + ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c index 38f94f0e01..959641ebf9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_dac.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -33,17 +33,17 @@ *** DAC Triggers *** ==================== [..] - Digital to Analog conversion can be non-triggered using DAC_Trigger_None + Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. [..] Digital to Analog conversion can be triggered by: - (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. - The used pin (GPIOx_Pin9) must be configured in input mode. + (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9. + The used pin (GPIOx_PIN_9) must be configured in input mode. (#) Timers TRGO: TIM2, TIM3, TIM6, and TIM15 - (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...) + (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...) - (#) Software using DAC_Trigger_Software + (#) Software using DAC_TRIGGER_SOFTWARE *** DAC Buffer mode feature *** =============================== @@ -52,10 +52,21 @@ reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. To enable, the output buffer use - sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; [..] (@) Refer to the device datasheet for more details about output impedance value with and without output buffer. + + *** GPIO configurations guidelines *** + ===================== + [..] + When a DAC channel is used (ex channel1 on PA4) and the other is not + (ex channel1 on PA5 is configured in Analog and disabled). + Channel1 may disturb channel2 as coupling effect. + Note that there is no coupling on channel2 as soon as channel2 is turned on. + Coupling on adjacent channel could be avoided as follows: + when unused PA5 is configured as INPUT PULL-UP or DOWN. + PA5 is configured in ANALOG just before it is turned on. *** DAC wave generation feature *** =================================== @@ -72,16 +83,19 @@ (#) 12-bit left alignment using DAC_ALIGN_12B_L (#) 12-bit right alignment using DAC_ALIGN_12B_R - *** DAC data value to voltage correspondence *** + *** DAC data value to voltage correspondance *** ================================================ [..] The analog output voltage on each DAC channel pin is determined by the following equation: + [..] DAC_OUTx = VREF+ * DOR / 4095 - with DOR is the Data Output Register + (+) with DOR is the Data Output Register + [..] VEF+ is the input voltage reference (refer to the device datasheet) + [..] e.g. To set DAC_OUT1 to 0.7V, use - Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V *** DMA requests *** ===================== @@ -96,8 +110,8 @@ (#) DAC channel2 : mapped on DMA1 channel4 which must be already configured - -@- For Dual mode and specific signal (Triangle and noise) generation please - refer to Extension Features Driver description + (@) For Dual mode and specific signal (Triangle and noise) generation please + refer to Extended Features Driver description STM32F0 devices with one channel (one converting capability) does not support Dual mode and specific signal (Triangle and noise) generation. @@ -108,25 +122,33 @@ registers using HAL_DAC_Init() (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. - (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions + (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions. *** Polling mode IO operation *** ================================= [..] (+) Start the DAC peripheral using HAL_DAC_Start() - (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function. + (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. (+) Stop the DAC peripheral using HAL_DAC_Stop() *** DMA mode IO operation *** ============================== [..] (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length - of data to be transfered at each end of conversion - (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() + of data to be transferred at each end of conversion + (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() function is executed and user can add his own code by customization of function pointer - HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 + HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() *** DAC HAL driver macros list *** @@ -146,7 +168,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -177,17 +199,17 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + #ifdef HAL_DAC_MODULE_ENABLED #if defined(STM32F051x8) || defined(STM32F058xx) || \ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ defined(STM32F091xC) || defined (STM32F098xx) -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup DAC DAC HAL module driver +/** @defgroup DAC DAC * @brief DAC driver modules * @{ */ @@ -195,10 +217,23 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @defgroup DAC_Private_Functions DAC Private Functions + * @{ + */ +/** + * @} + */ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions -------------------------------------------------------*/ /** @defgroup DAC_Exported_Functions DAC Exported Functions * @{ @@ -220,8 +255,8 @@ */ /** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. + * @brief Initialize the DAC peripheral according to the specified parameters + * in the DAC_InitStruct and initialize the associated handle. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status @@ -238,6 +273,9 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) if(hdac->State == HAL_DAC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hdac->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_DAC_MspInit(hdac); } @@ -256,7 +294,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) } /** - * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @brief Deinitialize the DAC peripheral registers to their default reset values. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status @@ -292,27 +330,27 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) } /** - * @brief Initializes the DAC MSP. + * @brief Initialize the DAC MSP. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspInit could be implemented in the user file */ } /** - * @brief DeInitializes the DAC MSP. + * @brief DeInitialize the DAC MSP. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspDeInit could be implemented in the user file */ } @@ -333,7 +371,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) (+) Stop conversion. (+) Start conversion and enable DMA transfer. (+) Stop conversion and disable DMA transfer. - (+) Get result of conversion. + (+) Set the specified data holding register value for DAC channel. @endverbatim * @{ @@ -429,20 +467,35 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /* Disable the selected DAC channel DMA request */ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); - /* Disable the Peripharal */ + /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); - /* Disable the DMA Channel */ + /* Disable the DMA channel */ /* Channel1 is used */ if (Channel == DAC_CHANNEL_1) { + /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); - } - else /* Channel2 is used for */ - { - status = HAL_DMA_Abort(hdac->DMA_Handle2); + + /* Disable the DAC DMA underrun interrupt */ + __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined (STM32F098xx) + /* Does not apply to STM32F051x8 & STM32F058xx */ + + else /* Channel2 is used for */ + { + /* Disable the DMA channel */ + status = HAL_DMA_Abort(hdac->DMA_Handle2); + + /* Disable the DAC DMA underrun interrupt */ + __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); + } +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + /* Check if DMA Channel effectively disabled */ if (status != HAL_OK) { @@ -460,94 +513,15 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) } /** - * @brief Conversion complete callback in non blocking mode for Channel1 + * @brief Handles DAC interrupt request * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels. - (+) Set the specified data holding register value for DAC channel. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) { /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f0xx_hal_dac_ex.c */ - - /* Return error status as not implemented here */ - return HAL_ERROR; } /** @@ -578,11 +552,11 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui tmp = (uint32_t)hdac->Instance; if(Channel == DAC_CHANNEL_1) { - tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment); + tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } else { - tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment); + tmp += DAC_DHR12R2_ALIGNMENT(Alignment); } /* Set the DAC channel1 selected data holding register */ @@ -592,6 +566,77 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui return HAL_OK; } +/** + * @brief Conversion complete callback in non blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels. + (+) Get result of conversion. + +@endverbatim + * @{ + */ + /** * @brief Returns the last data output value of the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -611,6 +656,26 @@ __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) return HAL_ERROR; } +/** + * @brief Configures the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig: DAC configuration structure. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32f0xx_hal_dac_ex.c */ + + /* Return error status as not implemented here */ + return HAL_ERROR; +} + /** * @} */ @@ -632,14 +697,14 @@ __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) */ /** - * @brief return the DAC state + * @brief return the DAC handle state * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) { - /* Return DAC state */ + /* Return DAC handle state */ return hdac->State; } @@ -655,18 +720,6 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) return hdac->ErrorCode; } -/** - * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) -{ - /* Note : This function is defined into this file for library reference. */ - /* Function content is located into file stm32f0xx_hal_dac_ex.c */ -} - /** * @} */ @@ -679,15 +732,15 @@ __weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @} */ - -/** - * @} - */ - #endif /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ #endif /* HAL_DAC_MODULE_ENABLED */ +/** + * @} + */ + + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h index 5a0704556f..8e7602e04c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_dac.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,6 +43,10 @@ extern "C" { #endif +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + #if defined(STM32F051x8) || defined(STM32F058xx) || \ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ defined(STM32F091xC) || defined(STM32F098xx) @@ -50,10 +54,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal_def.h" -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - /** @addtogroup DAC * @{ */ @@ -123,8 +123,8 @@ typedef struct * @{ */ #define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */ #define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ /** * @} @@ -136,30 +136,17 @@ typedef struct #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ - ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) /** * @} */ -/** @defgroup DAC_data_alignement DAC data alignement +/** @defgroup DAC_data_alignment DAC data alignment * @{ */ #define DAC_ALIGN_12B_R ((uint32_t)0x00000000) #define DAC_ALIGN_12B_L ((uint32_t)0x00000004) #define DAC_ALIGN_8B_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ - ((ALIGN) == DAC_ALIGN_12B_L) || \ - ((ALIGN) == DAC_ALIGN_8B_R)) -/** - * @} - */ - -/** @defgroup DAC_data DAC data - * @{ - */ -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) /** * @} */ @@ -214,27 +201,12 @@ typedef struct #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) -/** @brief Set DHR12R1 alignment - * @param __ALIGNEMENT__: specifies the DAC alignement - * @retval None - */ -#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__)) - -/** @brief Set DHR12R2 alignment - * @param __ALIGNEMENT__: specifies the DAC alignement - * @retval None - */ -#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__)) - -/** @brief Set DHR12RD alignment - * @param __ALIGNEMENT__: specifies the DAC alignement - * @retval None - */ -#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__)) - /** @brief Enable the DAC interrupt * @param __HANDLE__: specifies the DAC handle * @param __INTERRUPT__: specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt * @retval None */ #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) @@ -242,20 +214,36 @@ typedef struct /** @brief Disable the DAC interrupt * @param __HANDLE__: specifies the DAC handle * @param __INTERRUPT__: specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @retval None */ #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) -/** @brief Get the selected DAC's flag status. +/** @brief Check whether the specified DAC interrupt source is enabled or not + * @param __HANDLE__: DAC handle + * @param __INTERRUPT__: DAC interrupt source to check + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt + * @retval State of interruption (SET or RESET) + */ +#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Get the selected DAC's flag status * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the FLAG. + * @param __FLAG__: specifies the DAC flag to get. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @retval None */ #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) -/** @brief Clear the DAC's flag. +/** @brief Clear the DAC's flag * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the FLAG. + * @param __FLAG__: specifies the DAC flag to clear. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @retval None */ #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) @@ -264,6 +252,58 @@ typedef struct * @} */ +/* Private macro -------------------------------------------------------------*/ + +/** @addtogroup DAC_Private_Macros + * @{ + */ +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ + ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) + + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1)) + +#endif /* STM32F051x8 || STM32F058xx */ + + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) + +/** @brief Set DHR12R1 alignment + * @param __ALIGNMENT__: specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) + +/** @brief Set DHR12R2 alignment + * @param __ALIGNMENT__: specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) + +/** @brief Set DHR12RD alignment + * @param __ALIGNMENT__: specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) + +/** + * @} + */ /* Include DAC HAL Extension module */ #include "stm32f0xx_hal_dac_ex.h" @@ -296,6 +336,10 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); + +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); + void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); @@ -308,9 +352,9 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); + +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); /** * @} */ @@ -320,7 +364,6 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); */ /* Peripheral State and Error functions ***************************************/ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); -void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); /** @@ -335,14 +378,14 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); * @} */ -/** - * @} - */ - #endif /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c index 8a4a993fc8..5312d621dc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c @@ -2,12 +2,11 @@ ****************************************************************************** * @file stm32f0xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief DAC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of DAC extension peripheral: - * + Extended features functions + * This file provides firmware functions to manage the extended + * functionalities of the DAC peripheral. * * @verbatim @@ -15,7 +14,7 @@ ##### How to use this driver ##### ============================================================================== [..] - (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) : + (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : Use HAL_DACEx_DualGetValue() to get digital data to be converted and use HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. @@ -25,7 +24,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -56,28 +55,21 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + #ifdef HAL_DAC_MODULE_ENABLED +/** @addtogroup DAC + * @{ + */ + #if defined(STM32F051x8) || defined(STM32F058xx) || \ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ defined(STM32F091xC) || defined(STM32F098xx) -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - -/** @defgroup DACEx DACEx Extended HAL module driver - * @brief DACEx driver module - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DACEx_Private_Functions DACEx Private Functions +/** @addtogroup DAC_Private_Functions * @{ */ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); @@ -87,29 +79,6 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); * @} */ -/** @defgroup DACEx_Exported_Functions DACEx Exported Functions - * @{ - */ - -/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - ============================================================================== - ##### Extended features functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion. - (+) Stop conversion. - (+) Start conversion and enable DMA transfer. - (+) Stop conversion and disable DMA transfer. - (+) Get result of conversion. - (+) Get result of dual mode conversion. - -@endverbatim - * @{ - */ - #endif /* STM32F051x8 STM32F058xx */ /* STM32F071xB STM32F072xB STM32F078xx */ /* STM32F091xC STM32F098xx */ @@ -117,6 +86,34 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ defined(STM32F091xC) || defined(STM32F098xx) +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */ +/* are set by HAL_DAC_Start_DMA */ + +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +#endif /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group3 + * @{ + */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + /** * @brief Configures the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -145,7 +142,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf hdac->State = HAL_DAC_STATE_BUSY; /* Get the DAC CR value */ - tmpreg1 = DAC->CR; + tmpreg1 = hdac->Instance->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); /* Configure for the selected DAC channel: buffer output, trigger */ @@ -155,9 +152,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC CR */ - DAC->CR = tmpreg1; - /* Disable wave generation */ - DAC->CR &= ~(DAC_CR_WAVE1 << Channel); + hdac->Instance->CR = tmpreg1; /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -201,9 +196,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf hdac->State = HAL_DAC_STATE_BUSY; /* Get the DAC CR value */ - tmpreg1 = DAC->CR; + tmpreg1 = hdac->Instance->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - // tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); tmpreg1 &= ~(((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); /* Configure for the selected DAC channel: buffer output, trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ @@ -212,9 +206,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC CR */ - DAC->CR = tmpreg1; - /* Disable wave generation */ - // DAC->CR &= ~(DAC_CR_WAVE1 << Channel); + hdac->Instance->CR = tmpreg1; /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -287,6 +279,14 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) #endif /* STM32F051x8 STM32F058xx */ +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ + #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ defined(STM32F091xC) || defined(STM32F098xx) @@ -302,8 +302,6 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { - uint32_t tmp1 = 0, tmp2 = 0; - /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -318,24 +316,20 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) if(Channel == DAC_CHANNEL_1) { - tmp1 = hdac->Instance->CR & DAC_CR_TEN1; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1)) { /* Enable the selected DAC software conversion */ - hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1; + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } } else { - tmp1 = hdac->Instance->CR & DAC_CR_TEN2; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) + if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2)) { /* Enable the selected DAC software conversion*/ - hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2; + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); } } @@ -392,7 +386,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; /* Enable the selected DAC channel1 DMA request */ - hdac->Instance->CR |= DAC_CR_DMAEN1; + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); /* Case of use of channel 1 */ switch(Alignment) @@ -425,7 +419,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; /* Enable the selected DAC channel2 DMA request */ - hdac->Instance->CR |= DAC_CR_DMAEN2; + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); /* Case of use of channel 2 */ switch(Alignment) @@ -484,8 +478,6 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { - uint32_t tmp1 = 0, tmp2 = 0; - /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -500,13 +492,11 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) if(Channel == DAC_CHANNEL_1) { - tmp1 = hdac->Instance->CR & DAC_CR_TEN1; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1)) { /* Enable the selected DAC software conversion */ - hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1; + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } } @@ -560,7 +550,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; /* Enable the selected DAC channel1 DMA request */ - hdac->Instance->CR |= DAC_CR_DMAEN1; + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); /* Case of use of channel 1 */ switch(Alignment) @@ -618,40 +608,47 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) { - /* Check Overrun flag */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) - { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; + if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + { + /* Check underrun channel 1 flag */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; - /* Set DAC error code to chanel1 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; + /* Set DAC error code to channel1 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN1; + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN1; - /* Error callback */ - HAL_DAC_DMAUnderrunCallbackCh1(hdac); + /* Error callback */ + HAL_DAC_DMAUnderrunCallbackCh1(hdac); + } } - else + if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; + /* Check underrun channel 2 flag */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; - /* Set DAC error code to channel2 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; + /* Set DAC error code to channel2 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN2; + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN2; - /* Error callback */ - HAL_DACEx_DMAUnderrunCallbackCh2(hdac); + /* Error callback */ + HAL_DACEx_DMAUnderrunCallbackCh2(hdac); + } } } @@ -669,28 +666,205 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) { + if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + { /* Check Overrun flag */ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) - { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; - /* Set DAC error code to chanel1 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; + /* Set DAC error code to chanel1 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN1; + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN1; - /* Error callback */ - HAL_DAC_DMAUnderrunCallbackCh1(hdac); + /* Error callback */ + HAL_DAC_DMAUnderrunCallbackCh1(hdac); + } } } #endif /* STM32F051x8 STM32F058xx */ +/** + * @} + */ + +/** + * @} + */ + +#if defined(STM32F051x8) || defined(STM32F058xx) || \ + defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_DAC_ConvCpltCallbackCh1(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + + HAL_DAC_ErrorCallbackCh1(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} +/** + * @} + */ +#endif /* STM32F051x8 STM32F058xx */ + /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_DACEx_ConvCpltCallbackCh2(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + + HAL_DACEx_ErrorCallbackCh2(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @} + */ + +#endif /* STM32F071xB STM32F072xB STM32F078xx */ + /* STM32F091xC STM32F098xx */ + +/** + * @} + */ + +/** @defgroup DACEx DACEx + * @brief DACEx driver module + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup DACEx_Private_Macros DACEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DACEx_Exported_Functions DACEx Exported Functions + * @{ + */ + +/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + ============================================================================== + ##### Extended features functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + (+) Get result of dual mode conversion. + +@endverbatim + * @{ + */ + #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ defined(STM32F091xC) || defined(STM32F098xx) @@ -775,7 +949,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 hdac->State = HAL_DAC_STATE_BUSY; /* Enable the selected wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY; @@ -823,7 +997,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t hdac->State = HAL_DAC_STATE_BUSY; /* Enable the selected wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY; @@ -838,10 +1012,27 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t #endif /* STM32F071xB STM32F072xB STM32F078xx */ /* STM32F091xC STM32F098xx */ +/** + * @} + */ + +/** + * @} + */ + #if defined(STM32F051x8) || defined(STM32F058xx) || \ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ defined(STM32F091xC) || defined(STM32F098xx) +/** @addtogroup DACEx_Exported_Functions + * @{ + */ + +/** @addtogroup DACEx_Exported_Functions_Group1 + * @brief Extended features functions + * @{ + */ + /** * @brief Set the specified data holding register value for dual DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -877,7 +1068,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align } tmp = (uint32_t)hdac->Instance; - tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment); + tmp += DAC_DHR12RD_ALIGNMENT(Alignment); /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; @@ -894,58 +1085,6 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align * @} */ -/** @addtogroup DACEx_Private_Functions - * @{ - */ - -/** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DAC_ConvCpltCallbackCh1(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DAC_ConvHalfCpltCallbackCh1(hdac); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DAC_ErrorCallbackCh1(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} -/** - * @} - */ #endif /* STM32F051x8 STM32F058xx */ /* STM32F071xB STM32F072xB STM32F078xx */ /* STM32F091xC STM32F098xx */ @@ -961,6 +1100,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) * @brief Extended features functions * @{ */ + /** * @brief Conversion complete callback in non blocking mode for Channel2 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains @@ -1013,60 +1153,6 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) */ } -/** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DACEx_ConvCpltCallbackCh2(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DACEx_ErrorCallbackCh2(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @} - */ - -/** - * @} - */ - /** * @} */ @@ -1078,6 +1164,14 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) #endif /* STM32F071xB STM32F072xB STM32F078xx */ /* STM32F091xC STM32F098xx */ +/** + * @} + */ + #endif /* HAL_DAC_MODULE_ENABLED */ +/** + * @} + */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h index b38d32f373..51e4a69658 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,6 +43,10 @@ extern "C" { #endif +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + #if defined(STM32F051x8) || defined(STM32F058xx) || \ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ defined(STM32F091xC) || defined(STM32F098xx) @@ -50,37 +54,17 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal_def.h" -/** @addtogroup STM32F0xx_HAL_Driver - * @{ - */ - /** @addtogroup DACEx * @{ */ /* Exported types ------------------------------------------------------------*/ -/** - * @brief HAL State structures definition - */ - /* Exported constants --------------------------------------------------------*/ + /** @defgroup DACEx_Exported_Constants DACEx Exported Constants * @{ */ -/** @defgroup DACEx_wave_generation DACEx wave generation - * @{ - */ -#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000) -#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) - -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \ - ((WAVE) == DAC_WAVEGENERATION_NOISE) || \ - ((WAVE) == DAC_WAVEGENERATION_TRIANGLE)) -/** - * @} - */ /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude * @{ @@ -110,6 +94,133 @@ #define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ #define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + + +/** @defgroup DACEx_Exported_Macros DACEx Exported Macros + * @{ + */ + +/** @defgroup DAC_trigger_selection DAC trigger selection + * @{ + */ +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ + +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** @defgroup DAC_Channel_selection DAC Channel selection + * @{ + */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define DAC_CHANNEL_1 ((uint32_t)0x00000000) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define DAC_CHANNEL_1 ((uint32_t)0x00000000) + +#endif /* STM32F051x8 || STM32F058xx */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @addtogroup DACEx_Private_Macros + * @{ + */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ + defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ @@ -134,149 +245,41 @@ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) -/** - * @} - */ -/** @defgroup DACEx_wave_generationbis DACEx wave generation bis - * @{ - */ -#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup DACEx_Exported_Macros DACEx Exported Macros - * @{ - */ - -/** @defgroup DAC_trigger_selection DAC trigger selection - * @{ - */ -#if defined(STM32F051x8) || defined(STM32F058xx) - -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ - ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) - -#endif /* STM32F051x8 || STM32F058xx */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ - ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - -/** @defgroup DAC_Channel_selection DAC Channel selection - * @{ - */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) - -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ - ((CHANNEL) == DAC_CHANNEL_2)) - -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - -#if defined(STM32F051x8) || defined(STM32F058xx) - -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1)) - -#endif /* STM32F051x8 || STM32F058xx */ - -/** - * @} - */ - /** * @} */ /* Exported functions --------------------------------------------------------*/ -/* Extension features functions ***********************************************/ /** @addtogroup DACEx_Exported_Functions * @{ */ -/** @addtogroup DACEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * @{ - */ +/** @addtogroup DACEx_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); -void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); -void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); -void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); -void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** * @} */ - - /** - * @} - */ -#endif /* */ + +/** @addtogroup DACEx_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ + +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); /** * @} @@ -285,13 +288,23 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** * @} */ - -#ifdef __cplusplus -} + +/** + * @} + */ + #endif /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + #endif /*__STM32F0xx_HAL_DAC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h index 62bb2973bc..aa9a07a0d2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f0xx_hal_def.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -46,6 +46,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx.h" +#include "stm32_hal_legacy.h" +#include /* Exported types ------------------------------------------------------------*/ @@ -70,9 +72,6 @@ typedef enum } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ -#ifndef NULL - #define NULL 0 -#endif #define HAL_MAX_DELAY 0xFFFFFFFF diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c index 64123ec361..003e10a2bd 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_dma.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -73,7 +73,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -107,12 +107,13 @@ * @{ */ +#ifdef HAL_DMA_MODULE_ENABLED + /** @defgroup DMA DMA * @brief DMA HAL module driver * @{ */ -#ifdef HAL_DMA_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -125,6 +126,13 @@ */ /* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions @@ -141,7 +149,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t * @{ */ -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim @@ -186,6 +194,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + if(hdma->State == HAL_DMA_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -259,7 +273,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* Initialise the error code */ + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ @@ -386,7 +400,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Disable the channel */ __HAL_DMA_DISABLE(hdma); - /* Get timeout */ + /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DMA Channel is effectively disabled */ @@ -441,7 +455,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); } - /* Get timeout */ + /* Get tick */ tickstart = HAL_GetTick(); while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) @@ -649,7 +663,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) * @} */ -/** @addtogroup DMA_Private_Functions DMA Private Functions +/** @addtogroup DMA_Private_Functions * @{ */ @@ -691,10 +705,10 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t * @} */ -#endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h index 07bed3c233..6b95e18244 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_dma.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,6 +55,7 @@ */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ @@ -87,7 +88,6 @@ typedef struct uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ - } DMA_InitTypeDef; /** @@ -106,12 +106,11 @@ typedef enum typedef enum { HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */ + HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ - + HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ }HAL_DMA_StateTypeDef; /** @@ -121,9 +120,7 @@ typedef enum { HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ - -}HAL_DMA_LevelCompleteTypeDef; - +}HAL_DMA_LevelCompleteTypeDef; /** * @brief DMA handle Structure definition @@ -136,7 +133,7 @@ typedef struct __DMA_HandleTypeDef HAL_LockTypeDef Lock; /*!< DMA locking object */ - HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ void *Parent; /*!< Parent object state */ @@ -147,13 +144,14 @@ typedef struct __DMA_HandleTypeDef void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ - } DMA_HandleTypeDef; + /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup DMA_Exported_Constants DMA Exported Constants * @{ */ @@ -175,29 +173,15 @@ typedef struct __DMA_HandleTypeDef #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) /** * @} */ - -/** @defgroup DMA_Data_buffer_size DMA Data buffer size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - + /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) /** * @} */ @@ -207,9 +191,6 @@ typedef struct __DMA_HandleTypeDef */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) /** * @} */ @@ -220,25 +201,16 @@ typedef struct __DMA_HandleTypeDef #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) /** * @} */ - /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) /** * @} */ @@ -248,9 +220,6 @@ typedef struct __DMA_HandleTypeDef */ #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) /** * @} */ @@ -262,11 +231,6 @@ typedef struct __DMA_HandleTypeDef #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} */ @@ -275,11 +239,9 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ - #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) - /** * @} */ @@ -317,16 +279,78 @@ typedef struct __DMA_HandleTypeDef #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */ #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @defgroup HAL_DMA_remapping HAL DMA remapping + * Elements values convention: 0xYYYYYYYY + * - YYYYYYYY : Position in the SYSCFG register CFGR1 + * @{ + */ +#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap + 0: No remap (ADC DMA requests mapped on DMA channel 1 + 1: Remap (ADC DMA requests mapped on DMA channel 2 */ +#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap + 0: No remap (USART1_TX DMA request mapped on DMA channel 2 + 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ +#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap + 0: No remap (USART1_RX DMA request mapped on DMA channel 3 + 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ +#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap + 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) + 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ +#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap + 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 + 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ +#if defined (STM32F070xB) +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. + 0: Disabled, need to remap before use + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ + +#endif + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) + 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ +#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only + 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) + 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ +#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) + 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) + 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ +#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) + 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ +#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) + 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ +#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) + 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ +#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) + 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ +#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. + 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) + 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ +#endif /** * @} */ +#endif /* SYSCFG_CFGR1_DMA_RMP */ /** * @} */ -/* Exported macros -----------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros * @{ */ @@ -340,14 +364,14 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Channel. * @param __HANDLE__: DMA handle - * @retval None. + * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) /** * @brief Disable the specified DMA Channel. * @param __HANDLE__: DMA handle - * @retval None. + * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) @@ -379,7 +403,7 @@ typedef struct __DMA_HandleTypeDef #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) /** - * @brief Checks whether the specified DMA Channel interrupt has occurred or not. + * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt source to check. * This parameter can be one of the following values: @@ -390,6 +414,18 @@ typedef struct __DMA_HandleTypeDef */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#if defined(SYSCFG_CFGR1_DMA_RMP) +/** @brief DMA remapping enable/disable macros + * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping + */ +#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 |= (__DMA_REMAP__); \ + }while(0) +#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ + SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ + }while(0) +#endif /* SYSCFG_CFGR1_DMA_RMP */ + /** * @} */ @@ -398,11 +434,11 @@ typedef struct __DMA_HandleTypeDef #include "stm32f0xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions DMA Exported Functions +/** @addtogroup DMA_Exported_Functions * @{ */ + /** @addtogroup DMA_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *****************************/ @@ -413,10 +449,9 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); */ /** @addtogroup DMA_Exported_Functions_Group2 - * @brief I/O operation functions * @{ */ -/* IO operation functions *****************************************************/ +/* Input and Output operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); @@ -426,25 +461,91 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); * @} */ -/* Peripheral State and Error functions ***************************************/ /** @addtogroup DMA_Exported_Functions_Group3 - * @brief Peripheral State functions * @{ */ +/* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} - */ - -/** - * @} - */ + */ /** * @} */ +/** @addtogroup DMA_Private_Macros + * @{ + */ +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +#if defined(SYSCFG_CFGR1_DMA_RMP) + +#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ + ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ + ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ + ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ + ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ + ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) +#elif defined (STM32F070xB) +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ + ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#else +#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ + ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ + ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ + ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ + ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) +#endif + +#endif /* SYSCFG_CFGR1_DMA_RMP */ + + +/** + * @} + */ + +/** + * @} + */ + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h index fd85710b2f..60d08fbe99 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of DMA HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,9 +50,10 @@ * @{ */ -/** @addtogroup DMAEx +/** @defgroup DMAEx DMAEx + * @brief DMA HAL module driver * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c index 64232f81bb..214e095566 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_flash.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -14,11 +14,11 @@ @verbatim ============================================================================== ##### FLASH peripheral features ##### - ============================================================================== + ============================================================================== [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. - + [..] The Flash memory interface accelerates code execution with a system of instruction prefetch. @@ -28,12 +28,13 @@ (+) Read / write protections (+) Prefetch on I-Code (+) Option Bytes programming - + + ##### How to use this driver ##### ============================================================================== [..] This driver provides functions and macros to configure and program the FLASH - memory of all STM32F0xx devices. These functions are split in 3 groups: + memory of all STM32F0xx devices. (#) FLASH Memory I/O Programming functions: this group includes all needed functions to erase and program the main memory: @@ -41,15 +42,17 @@ (++) Erase function: Erase page, erase all pages (++) Program functions: half word, word and doubleword - (#) Option Bytes Programming functions: this group includes all needed + (#) FLASH Option Bytes Programming functions: this group includes all needed functions to manage the Option Bytes: (++) Lock and Unlock the Option Bytes - (++) Erase Option Bytes (++) Set/Reset the write protection (++) Set the Read protection Level (++) Program the user Option Bytes - (++) Program the data Option Bytes (++) Launch the Option Bytes loader + (++) Erase Option Bytes + (++) Program the data Option Bytes + (++) Get the Write protection. + (++) Get the user option bytes. (#) Interrupts and flags management functions : this group includes all needed functions to: @@ -69,7 +72,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -103,23 +106,23 @@ * @{ */ -/** @defgroup FLASH FLASH HAL module driver +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH * @brief FLASH HAL module driver * @{ */ -#ifdef HAL_FLASH_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Defines FLASH Private Define +/** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ /** * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macro ---------------------------- ---------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ @@ -130,27 +133,20 @@ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ + * @{ + */ /* Variables used for Erase pages under interruption*/ FLASH_ProcessTypeDef pFlash; /** * @} */ - + /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ -/* Erase operations */ -void FLASH_PageErase(uint32_t PageAddress); - -/* Program operations */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); - -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -static void FLASH_SetErrorCode(void); - + * @{ + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_SetErrorCode(void); /** * @} */ @@ -160,17 +156,10 @@ static void FLASH_SetErrorCode(void); * @{ */ -/** @defgroup FLASH_Exported_Functions_Group1 I/O operation functions - * @brief Data transfers functions +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions * @verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH - program operations (write/erase). - @endverbatim * @{ */ @@ -203,20 +192,20 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint __HAL_LOCK(&pFlash); /* Check the parameters */ - assert_param(IS_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - if(TypeProgram == TYPEPROGRAM_HALFWORD) + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { /* Program halfword (16-bit) at a specified address. */ nbiterations = 1; } - else if(TypeProgram == TYPEPROGRAM_WORD) + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { /* Program word (32-bit = 2*16-bit) at a specified address. */ nbiterations = 2; @@ -231,12 +220,11 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint { FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index))); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - /* If the program operation is completed, disable the PG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); /* In case of error, stop programation procedure */ if (status != HAL_OK) { @@ -274,22 +262,22 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u __HAL_LOCK(&pFlash); /* Check the parameters */ - assert_param(IS_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR)); + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); pFlash.Address = Address; pFlash.Data = Data; - if(TypeProgram == TYPEPROGRAM_HALFWORD) + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; /*Program halfword (16-bit) at a specified address.*/ pFlash.DataRemaining = 1; } - else if(TypeProgram == TYPEPROGRAM_WORD) + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; /*Program word (32-bit : 2*16-bit) at a specified address.*/ @@ -315,7 +303,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u void HAL_FLASH_IRQHandler(void) { uint32_t addresstmp = 0; - + /* Check FLASH operation error flags */ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { @@ -339,92 +327,93 @@ void HAL_FLASH_IRQHandler(void) /* Process can continue only if no error detected */ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /* Nb of pages to erased can be decreased */ - pFlash.DataRemaining--; - - /* Indicate user which page address has been erased*/ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - - /* Check if there are still pages to erase*/ - if(pFlash.DataRemaining != 0) + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) { - /* Increment page address to next page */ - pFlash.Address += FLASH_PAGE_SIZE; - addresstmp = pFlash.Address; + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Indicate user which page address has been erased*/ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + + /* Check if there are still pages to erase*/ + if(pFlash.DataRemaining != 0) + { + /* Increment page address to next page */ + pFlash.Address += FLASH_PAGE_SIZE; + addresstmp = pFlash.Address; /* Operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - FLASH_PageErase(addresstmp); - } - else - { - /*No more pages to Erase*/ + FLASH_PageErase(addresstmp); + } + else + { + /*No more pages to Erase*/ - /*Reset Address and stop Erase pages procedure*/ - pFlash.Address = 0xFFFFFFFF; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /*Reset Address and stop Erase pages procedure*/ + pFlash.Address = 0xFFFFFFFF; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } } - } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) - { + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { /* Operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - /*MassErase ended. Return the selected bank*/ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0); + /* MassErase ended. Return the selected bank*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0); - /* Stop Mass Erase procedure*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - else - { - /* Nb of 16-bit data to program can be decreased */ - pFlash.DataRemaining--; - - /* Check if there are still 16-bit data to program */ - if(pFlash.DataRemaining != 0) + /* Stop Mass Erase procedure*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + else { - /* Increment address to 16-bit */ - pFlash.Address += 2; - addresstmp = pFlash.Address; - - /* Shift to have next 16-bit data */ - pFlash.Data = (pFlash.Data >> 16); - + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0) + { + /* Increment address to 16-bit */ + pFlash.Address += 2; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16); + /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); - } - else - { - /*Program ended. Return the selected address*/ - /* FLASH EOP interrupt user callback */ - if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address); + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); } - else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + else { - HAL_FLASH_EndOfOperationCallback(pFlash.Address-2); + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6); + } + + /* Reset Address and stop Program procedure*/ + pFlash.Address = 0xFFFFFFFF; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } - else - { - HAL_FLASH_EndOfOperationCallback(pFlash.Address-6); - } - - /* Reset Address and stop Program procedure*/ - pFlash.Address = 0xFFFFFFFF; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } - } } + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { @@ -432,7 +421,7 @@ void HAL_FLASH_IRQHandler(void) CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); /* Disable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_DISABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR)); + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); /* Process Unlocked */ __HAL_UNLOCK(&pFlash); @@ -495,17 +484,17 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { - if((READ_BIT(FLASH->CR, FLASH_CR_LOCK)) != RESET) + if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK)) { /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->KEYR, FLASH_FKEY1); - WRITE_REG(FLASH->KEYR, FLASH_FKEY2); + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); } else { return HAL_ERROR; } - + return HAL_OK; } @@ -518,6 +507,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); + return HAL_OK; } @@ -528,7 +518,7 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { - if((READ_BIT(FLASH->CR, FLASH_CR_OPTWRE)) == RESET) + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); @@ -553,36 +543,34 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) return HAL_OK; } - + /** * @brief Launch the option byte loading. - * @retval HAL status + * @note This function will reset automatically the MCU. + * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { - /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; - - /* Set the bit to force the option byte reloading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); - + /* Set the OBL_Launch bit to lauch the option byte loading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); } /** * @} - */ + */ -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions * @verbatim =============================================================================== - ##### Peripheral Errors functions ##### + ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permit to get in run-time Errors of the FLASH peripheral. + This subsection permit to get in run-time the status of the FLASH peripheral. @endverbatim * @{ @@ -591,42 +579,23 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) /** * @brief Get the specific FLASH error flag. * @retval FLASH_ErrorCode: The returned value can be: - * @arg FLASH_ERROR_PG: FLASH Programming error flag - * @arg FLASH_ERROR_WRP: FLASH Write protected error flag + * @ref FLASH_Error_Codes */ uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; -} +} /** * @} */ /** * @} - */ + */ /** @addtogroup FLASH_Private_Functions - * @{ - */ -/** - * @brief Erase the specified FLASH memory page - * @param PageAddress: FLASH page to erase - * The value of this parameter depend on device used within the same series - * - * @retval None - */ -void FLASH_PageErase(uint32_t PageAddress) -{ - /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; - - /* Proceed to erase the page */ - SET_BIT(FLASH->CR, FLASH_CR_PER); - WRITE_REG(FLASH->AR, PageAddress); - SET_BIT(FLASH->CR, FLASH_CR_STRT); -} - + * @{ + */ /** * @brief Program a half-word (16-bit) at a specified address. * @param Address: specifies the address to be programmed. @@ -636,11 +605,12 @@ void FLASH_PageErase(uint32_t PageAddress) static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; - - /* Proceed to program the new data */ - SET_BIT(FLASH->CR, FLASH_CR_PG); + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Write data in the address */ *(__IO uint16_t*)Address = Data; } @@ -650,7 +620,7 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ +{ /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ @@ -659,9 +629,9 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { return HAL_TIMEOUT; } @@ -674,7 +644,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } - + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { /*Save the error code*/ @@ -687,34 +657,35 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) } + /** * @brief Set the specific FLASH error flag. * @retval None */ static void FLASH_SetErrorCode(void) -{ +{ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) { - pFlash.ErrorCode |= FLASH_ERROR_WRP; + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { - pFlash.ErrorCode |= FLASH_ERROR_PG; + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; } + /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); -} - +} /** * @} */ +/** + * @} + */ + #endif /* HAL_FLASH_MODULE_ENABLED */ -/** - * @} - */ - /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h index 29b37cecc3..cc4db15471 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_flash.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -45,67 +45,43 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal_def.h" - + /** @addtogroup STM32F0xx_HAL_Driver * @{ */ /** @addtogroup FLASH * @{ - */ + */ + +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1)) + +/** + * @} + */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ */ -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. - This parameter can be a value of @ref FLASH_Type_Erase */ - - uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled - This parameter must be a value of @ref FLASHEx_Address */ - - uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. - This parameter must be a value between 1 and (max number of pages - value of initial page)*/ - -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Options bytes program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< OptionType: Option byte to be configured. - This parameter can be a value of @ref FLASH_OB_Type */ - - uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. - This parameter can be a value of @ref FLASH_OB_WRP_State */ - - uint32_t WRPPage; /*!< WRPSector: specifies the page(s) to be write protected - This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ - - uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. - This parameter can be a value of @ref FLASH_OB_Read_Protection */ - - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: - IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY - This parameter can be a combination of @ref FLASH_OB_Watchdog, @ref FLASH_OB_nRST_STOP, - @ref FLASH_OB_nRST_STDBY, @ref FLASH_OB_BOOT1, @ref FLASH_OB_VDDA_Analog_Monitoring and - @ref FLASH_OB_RAM_Parity_Check_Enable */ - - uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be prgrammed - This parameter can be a value of @ref FLASH_OB_Data_Address */ - - uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA - This parameter can have any value */ - -} FLASH_OBProgramInitTypeDef; /** * @brief FLASH Procedure structure definition @@ -136,8 +112,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< FLASH locking object */ __IO uint32_t ErrorCode; /*!< FLASH error code - This parameter can be a value of @ref FLASH_Error */ - + This parameter can be a value of @ref FLASH_Error_Codes */ } FLASH_ProcessTypeDef; /** @@ -145,29 +120,18 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ */ -/** @defgroup FLASH_Error FLASH Error +/** @defgroup FLASH_Error_Codes FLASH Error Codes * @{ - */ -#define FLASH_ERROR_NONE ((uint32_t)0x00000000) -#define FLASH_ERROR_PG ((uint32_t)0x00000001) -#define FLASH_ERROR_WRP ((uint32_t)0x00000002) -/** - * @} */ + +#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00) +#define HAL_FLASH_ERROR_PROG ((uint32_t)0x01) +#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02) -/** @defgroup FLASH_Type_Erase FLASH Type Erase - * @{ - */ -#define TYPEERASE_PAGES ((uint32_t)0x00) /*!ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) + + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + /** * @} */ @@ -380,8 +233,8 @@ typedef struct /** * @} */ - -/** @defgroup FLASH_Interrupt FLASH Interrupt + +/** @defgroup FLASH_Interrupt FLASH Interrupts * @brief macros to handle FLASH interrupts * @{ */ @@ -394,7 +247,7 @@ typedef struct * @arg FLASH_IT_ERR: Error Interrupt * @retval none */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) /** * @brief Disable the specified FLASH interrupt. @@ -404,30 +257,31 @@ typedef struct * @arg FLASH_IT_ERR: Error Interrupt * @retval none */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) /** * @brief Get the specified FLASH flag status. * @param __FLAG__: specifies the FLASH flag to check. * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGERR : FLASH Programming error flag - * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGERR : FLASH Programming error flag * @retval The new state of __FLAG__ (SET or RESET). */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__)) +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) /** * @brief Clear the specified FLASH flag. * @param __FLAG__: specifies the FLASH flags to clear. * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGERR : FLASH Programming error flag + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGERR : FLASH Programming error flag * @retval none */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) /** * @} @@ -436,56 +290,49 @@ typedef struct /** * @} */ - -/* Include FLASH HAL Extension module */ + +/* Include FLASH HAL Extended module */ #include "stm32f0xx_hal_flash_ex.h" /* Exported functions --------------------------------------------------------*/ - /** @addtogroup FLASH_Exported_Functions * @{ - */ - -/** @addtogroup FLASH_Exported_Functions_Group1 - * @brief Data transfers functions - * @{ - */ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler method */ -void HAL_FLASH_IRQHandler(void); +void HAL_FLASH_IRQHandler(void); /* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group2 - * @brief management functions - * @{ - */ - -/* FLASH Memory Programming functions *****************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); - -/* Option Bytes Programming functions *****************************************/ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** * @} */ -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ /* Peripheral State and Error functions ***************************************/ uint32_t HAL_FLASH_GetError(void); @@ -493,6 +340,17 @@ uint32_t HAL_FLASH_GetError(void); * @} */ +/** + * @} + */ + +/* Private function -------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +void FLASH_PageErase(uint32_t PageAddress); +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c index e24ea27d5a..530dd5a1e2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32f0xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Extended FLASH HAL module driver. + * * This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: * + Extended Initialization/de-initialization functions * + Extended I/O operation functions * + Extended Peripheral Control functions - * + Extended Peripheral State functions * @verbatim ============================================================================== @@ -22,15 +22,15 @@ [..] This driver provides functions to configure and program the FLASH memory of all STM32F0xxx devices. It includes - (+) Set/Reset the write protection - (+) Program the user Option Bytes - (+) Get the Read protection Level + (++) Set/Reset the write protection + (++) Program the user Option Bytes + (++) Get the Read protection Level @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,46 +63,53 @@ /** @addtogroup STM32F0xx_HAL_Driver * @{ */ +#ifdef HAL_FLASH_MODULE_ENABLED -/** @defgroup FLASHEx FLASHEx Extended HAL module driver +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx FLASHEx * @brief FLASH Extended HAL module driver * @{ */ -#ifdef HAL_FLASH_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ - -/** @addtogroup FLASHEx_Private_Constants FLASHEx Private Constants - * @{ - */ -#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ - +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_POSITION_IWDGSW_BIT (uint32_t)8 /** * @} */ - + /* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Variables FLASHEx Private Variables +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros * @{ - */ - -/* Variables used for Erase pages under interruption*/ -extern FLASH_ProcessTypeDef pFlash; - + */ /** * @} - */ - + */ + +/* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ - +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ /* Erase operations */ -extern void FLASH_PageErase(uint32_t PageAddress); static void FLASH_MassErase(void); /* Option bytes control */ @@ -112,29 +119,20 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); static uint32_t FLASH_OB_GetWRP(void); -static FlagStatus FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetRDP(void); static uint8_t FLASH_OB_GetUser(void); /** * @} */ -/** @defgroup FLASHEx_Extern_Functions FLASHEx Extern Functions - * @{ - */ -/* Private functions ---------------------------------------------------------*/ -extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); - -/** - * @} - */ - +/* Exported functions ---------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ - -/** @defgroup FLASHEx_Exported_Functions_Group2 Extended I/O operation functions - * @brief Extended I/O operation functions + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended Input and Output operation functions + * @brief I/O operation functions * @verbatim =============================================================================== @@ -144,76 +142,83 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); @endverbatim * @{ */ + + /** - * @brief Perform a mass erase or erase the specified FLASH memory pages + * @brief Perform a mass erase or erase the specified FLASH memory pages * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. - * + * * @param[out] PageError: pointer to variable that - * contains the configuration information on faulty page in case of error + * contains the configuration information on faulty page in case of error * (0xFFFFFFFF means that all the pages have been correctly erased) - * + * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { HAL_StatusTypeDef status = HAL_ERROR; uint32_t address = 0; - + /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ - assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { - if (pEraseInit->TypeErase == TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ - FLASH_MassErase(); - + /* Mass Erase requested for Bank1 */ /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the MER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_MER); - } - else - { - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); - - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFF; - - /* Erase by page by page to be done*/ - for(address = pEraseInit->PageAddress; - address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE); - address += FLASH_PAGE_SIZE) + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { - FLASH_PageErase(address); - + /*Mass erase to be done*/ + FLASH_MassErase(); + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_PER); - - if (status != HAL_OK) + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + } + } + else + { + /* Page Erase is requested */ + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + /* Page Erase requested on address located on bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFF; + + /* Erase by page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE); + address += FLASH_PAGE_SIZE) { - /* In case of error, stop erase procedure and return the faulty address */ - *PageError = address; - break; + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } } } - } } /* Process Unlocked */ @@ -228,7 +233,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. - * + * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) @@ -245,16 +250,16 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) } /* Check the parameters */ - assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR)); - - if (pEraseInit->TypeErase == TYPEERASE_MASSERASE) + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; - FLASH_MassErase(); + FLASH_MassErase(); } else { @@ -279,8 +284,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) * @} */ -/** @defgroup FLASHEx_Exported_Functions_Group3 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @defgroup FLASHEx_Exported_Functions_Group2 Extended Peripheral Control functions + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -293,12 +298,13 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) @endverbatim * @{ */ + /** * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). + * @note This functions erases all option bytes except the Read protection (RDP). * The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * @retval HAL status */ @@ -307,39 +313,32 @@ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) { uint8_t rdptmp = OB_RDP_LEVEL_0; HAL_StatusTypeDef status = HAL_ERROR; - FLASH_OBProgramInitTypeDef optionsbytes; /* Get the actual read protection Option Byte value */ - HAL_FLASHEx_OBGetConfig(&optionsbytes); - if(optionsbytes.RDPLevel != RESET) - { - rdptmp = OB_RDP_LEVEL_1; - } + rdptmp = FLASH_OB_GetRDP(); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* If the previous operation is completed, proceed to erase the option bytes */ SET_BIT(FLASH->CR, FLASH_CR_OPTER); SET_BIT(FLASH->CR, FLASH_CR_STRT); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + /* If the erase operation is completed, disable the OPTER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); if(status == HAL_OK) { /* Restore the last read protection Option Byte value */ - optionsbytes.OptionType = OPTIONBYTE_RDP; - optionsbytes.RDPLevel = rdptmp; - status = HAL_FLASHEx_OBProgram(&optionsbytes); + status = FLASH_OB_RDP_LevelConfig(rdptmp); } } @@ -351,18 +350,18 @@ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) * @brief Program option bytes * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes - * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * * @param pOBInit: pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. - * + * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { HAL_StatusTypeDef status = HAL_ERROR; - + /* Check the parameters */ assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); @@ -370,7 +369,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) { assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if (pOBInit->WRPState == WRPSTATE_ENABLE) + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) { /* Enable of Write protection on the selected page */ status = FLASH_OB_EnableWRP(pOBInit->WRPPage); @@ -407,7 +406,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) * @brief Get the Option byte configuration * @param pOBInit: pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. - * + * * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) @@ -432,29 +431,30 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) * @} */ -/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ /** - * @brief Mass erase of FLASH memory - * @retval None + * @brief Full erase of FLASH memory Bank + * + * @retval HAL Status */ static void FLASH_MassErase(void) { - /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - /* Proceed to erase all sectors */ - SET_BIT(FLASH->CR, FLASH_CR_MER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); + /* Only bank1 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); } /** * @brief Enable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if CortexM4 + * it is not possible to program or erase the flash page i if * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * * @param WriteProtectPage: specifies the page(s) to be write protected. @@ -464,96 +464,103 @@ static void FLASH_MassErase(void) static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ - defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) uint16_t WRP0_Data = 0xFFFF; -#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) +#if defined(OB_WRP1_WRP1) uint16_t WRP1_Data = 0xFFFF; -#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */ +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFF; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFF; +#endif /* OB_WRP3_WRP3 */ /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); - WriteProtectPage = (uint32_t)(~WriteProtectPage); -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ - defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) + /* Get current write protected pages and the new pages to be protected ******/ + WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + +#if defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); -#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); -#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx)|| defined(STM32F030xC) +#elif defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); +#elif defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16); -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24); -#endif /* STM32F071xB || STM32F072xB || STM32F078xx */ -#if defined(STM32F091xC) || defined(STM32F098xx) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); -#endif /* STM32F091xC || STM32F098xx */ -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */ +#endif /* OB_WRP_PAGES32TO47MASK */ +#if defined(OB_WRP_PAGES48TO63MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); +#endif /* OB_WRP_PAGES48TO63MASK */ + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) - { + { /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - - if(WRP0_Data != 0xFF) + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) { - OB->WRP0 &= WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } + /* Enable write protection */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); -#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - if((status == HAL_OK) && (WRP1_Data != 0xFF)) - { - OB->WRP1 &= WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } -#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || STM32F070xB || - STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - if((status == HAL_OK) && (WRP2_Data != 0xFF)) - { - OB->WRP2 &= WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFF) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ - if((status == HAL_OK) && (WRP3_Data != 0xFF)) - { - OB->WRP3 &= WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC*/ +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFF)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFF)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFF)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } } return status; @@ -561,8 +568,9 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) /** * @brief Disable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash page i if CortexM4 + * it is not possible to program or erase the flash page i if * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * * @param WriteProtectPage: specifies the page(s) to be write unprotected. @@ -572,96 +580,103 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ - defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) uint16_t WRP0_Data = 0xFFFF; -#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) +#if defined(OB_WRP1_WRP1) uint16_t WRP1_Data = 0xFFFF; -#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */ +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFF; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFF; +#endif /* OB_WRP3_WRP3 */ /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || STM32F070x6 || \ - defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) + /* Get current write protected pages and the new pages to be unprotected ******/ + WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + +#if defined(OB_WRP_PAGES0TO31MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK); -#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); -#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ -#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#elif defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES32TO63MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); +#elif defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16); -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24); -#endif /* STM32F071xB || STM32F072xB || STM32F078xx */ -#if defined(STM32F091xC) || defined(STM32F098xx) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); -#endif /* STM32F091xC || STM32F098xx */ -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */ +#endif /* OB_WRP_PAGES32TO47MASK */ +#if defined(OB_WRP_PAGES48TO63MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24); +#elif defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); +#endif /* OB_WRP_PAGES48TO63MASK */ + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) - { + { /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; - - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - if(WRP0_Data != 0xFF) + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) { - OB->WRP0 |= WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); -#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - if((status == HAL_OK) && (WRP1_Data != 0xFF)) - { - OB->WRP1 |= WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } -#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || STM32F070xB || - STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - if((status == HAL_OK) && (WRP2_Data != 0xFF)) - { - OB->WRP2 |= WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFF) + { + OB->WRP0 |= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ - if((status == HAL_OK) && (WRP3_Data != 0xFF)) - { - OB->WRP3 |= WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - } -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */ +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFF)) + { + OB->WRP1 |= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ - /* if the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFF)) + { + OB->WRP2 |= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFF)) + { + OB->WRP3 |= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } return status; } @@ -672,9 +687,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Read protection of the memory * @arg OB_RDP_LEVEL_2: Full chip protection - * * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) @@ -683,26 +696,39 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); - + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + if(status == HAL_OK) { /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; - - /* Enable the Option Bytes Programming operation */ - SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - - WRITE_REG(OB->RDP, ReadProtectLevel); + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + WRITE_REG(OB->RDP, ReadProtectLevel); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } + } return status; } @@ -710,8 +736,9 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) /** * @brief Program the FLASH User Option Byte. * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) - * @param UserConfig: The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4), + * @param UserConfig: The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7). * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) @@ -719,36 +746,36 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ - assert_param(IS_OB_WDG_SOURCE((UserConfig&OB_WDG_SW))); + assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_RAM_PARITY_CHECK_RESET))); -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6) +#if defined(FLASH_OBR_BOOT_SEL) assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET))); assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET))); -#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */ +#endif /* FLASH_OBR_BOOT_SEL */ /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; - + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Enable the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6) + +#if defined(FLASH_OBR_BOOT_SEL) OB->USER = UserConfig; #else OB->USER = (UserConfig | 0x88); -#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */ - +#endif /* FLASH_OBR_BOOT_SEL */ + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); @@ -772,28 +799,28 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) { HAL_StatusTypeDef status = HAL_ERROR; - + /* Check the parameters */ assert_param(IS_OB_DATA_ADDRESS(Address)); - + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + if(status == HAL_OK) { /* Clean the error context */ - pFlash.ErrorCode = FLASH_ERROR_NONE; + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enables the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); *(__IO uint16_t*)Address = Data; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - /* If the program operation is completed, disable the OPTPG Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); - } + /* If the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } /* Return the Option Byte Data Program Status */ return status; } @@ -811,16 +838,26 @@ static uint32_t FLASH_OB_GetWRP(void) /** * @brief Returns the FLASH Read Protection level. * @retval FLASH ReadOut Protection Status: - * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set - * - RESET, when OB_RDP_Level_0 is set + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection */ -static FlagStatus FLASH_OB_GetRDP(void) +static uint8_t FLASH_OB_GetRDP(void) { - FlagStatus readstatus = RESET; + uint8_t readstatus = OB_RDP_LEVEL_0; - if ((uint8_t)READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT1) != RESET) + if (HAL_IS_BIT_SET(FLASH->OBR, FLASH_OBR_RDPRT1)) { - readstatus = SET; + readstatus = OB_RDP_LEVEL_1; + } + else if (HAL_IS_BIT_SET(FLASH->OBR, FLASH_OBR_RDPRT2)) + { + readstatus = OB_RDP_LEVEL_2; + } + else + { + readstatus = OB_RDP_LEVEL_0; } return readstatus; @@ -828,20 +865,51 @@ static FlagStatus FLASH_OB_GetRDP(void) /** * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4), - * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit0), FLASH_OBR_nRST_STOP(Bit1), + * FLASH_OBR_nRST_STDBY(Bit2), FLASH_OBR_nBOOT1(Bit4), + * FLASH_OBR_VDDA_MONITOR(Bit5), FLASH_OBR_RAM_PARITY_CHECK(Bit6) and FLASH_OBR_BOOT_SEL(Bit7) (*). + * @note (*) not present on all the devices. */ static uint8_t FLASH_OB_GetUser(void) { /* Return the User Option Byte */ - return (uint8_t)(READ_REG(FLASH->OBR) >> 8); + return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); } /** * @} */ -#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Erase the specified FLASH memory page + * @param PageAddress: FLASH page to erase + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, PageAddress); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} /** * @} @@ -851,4 +919,13 @@ static uint8_t FLASH_OB_GetUser(void) * @} */ +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h index 69d52579c2..c280bb0046 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 - * @brief Header file of FLASH HAL Extension module. + * @version V1.3.0 + * @date 26-June-2015 + * @brief Header file of Flash HAL Extended module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,68 +54,152 @@ * @{ */ +/** @addtogroup FLASHEx_Private_Macros + * @{ + */ +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)) + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1))/*||\ + ((LEVEL) == OB_RDP_LEVEL_2))*/ + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) + +#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) + +#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_RAM_PARITY_CHECK_SET) || ((PARITY) == OB_RAM_PARITY_CHECK_RESET)) + +#if defined(FLASH_OBR_BOOT_SEL) +#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET)) +#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET)) +#endif /* FLASH_OBR_BOOT_SEL */ + +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END) + +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) + +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END)) + +/** + * @} + */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled + This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */ + + uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. + This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Options bytes program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_OB_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_OB_WRP_State */ + + uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected + This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. + This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ + + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: + IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY + This parameter can be a combination of @ref FLASHEx_OB_Watchdog, @ref FLASHEx_OB_nRST_STOP, + @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and + @ref FLASHEx_OB_RAM_Parity_Check_Enable */ + + uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed + This parameter can be a value of @ref FLASHEx_OB_Data_Address */ + + uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ +} FLASH_OBProgramInitTypeDef; +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants * @{ */ -/** @defgroup FLASHEx_Address FLASHEx Address - * @{ - */ -#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx) || defined(STM32F070x6) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x08007FFF)) -#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */ - -#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF)) -#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) -#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB*/ - -#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) -#endif /* STM32F091xC || STM32F098xx || STM32F030xC*/ -/** - * @} - */ - /** @defgroup FLASHEx_Page_Size FLASHEx Page Size * @{ */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \ - defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6) +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \ + || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6) #define FLASH_PAGE_SIZE 0x400 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */ -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) #define FLASH_PAGE_SIZE 0x800 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */ /** * @} */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!
      © COPYRIGHT(c) 2014 STMicroelectronics
      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -139,7 +132,7 @@ * @{ */ -/** @defgroup GPIO GPIO HAL module driver +/** @defgroup GPIO GPIO * @brief GPIO HAL module driver * @{ */ @@ -147,8 +140,8 @@ #ifdef HAL_GPIO_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Define GPIO Private Define +/* Private defines -----------------------------------------------------------*/ +/** @defgroup GPIO_Private_Defines GPIO Private Defines * @{ */ #define GPIO_MODE ((uint32_t)0x00000003) @@ -160,15 +153,14 @@ #define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) #define GPIO_NUMBER ((uint32_t)16) - /** * @} */ - -/* Private macro -------------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Exporte functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Functions GPIO Exported Functions * @{ @@ -187,10 +179,8 @@ */ /** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx - * @note GPIOE is only available on STM32F07xx and STM32F09xx * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None @@ -225,15 +215,15 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + CLEAR_BIT(temp, (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); GPIOx->AFR[position >> 3] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODER0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); GPIOx->MODER = temp; /* In case of Output or Alternate function mode selection */ @@ -244,21 +234,21 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - temp |= (GPIO_Init->Speed << (position * 2)); + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - temp &= ~(GPIO_OTYPER_OT_0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); GPIOx->OTYPER = temp; } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - temp |= ((GPIO_Init->Pull) << (position * 2)); + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); GPIOx->PUPDR = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ @@ -266,44 +256,44 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable SYSCFG Clock */ - __SYSCFG_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))); + CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03))); + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); SYSCFG->EXTICR[position >> 2] = temp; /* Clear EXTI line configuration */ temp = EXTI->IMR; - temp &= ~((uint32_t)iocurrent); + CLEAR_BIT(temp, (uint32_t)iocurrent); if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { - temp |= iocurrent; + SET_BIT(temp, iocurrent); } EXTI->IMR = temp; temp = EXTI->EMR; - temp &= ~((uint32_t)iocurrent); + CLEAR_BIT(temp, (uint32_t)iocurrent); if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { - temp |= iocurrent; + SET_BIT(temp, iocurrent); } EXTI->EMR = temp; /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; - temp &= ~((uint32_t)iocurrent); + CLEAR_BIT(temp, (uint32_t)iocurrent); if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { - temp |= iocurrent; + SET_BIT(temp, iocurrent); } EXTI->RTSR = temp; temp = EXTI->FTSR; - temp &= ~((uint32_t)iocurrent); + CLEAR_BIT(temp, (uint32_t)iocurrent); if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { - temp |= iocurrent; + SET_BIT(temp, iocurrent); } EXTI->FTSR = temp; } @@ -314,10 +304,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) } /** - * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @brief De-initialize the GPIOx peripheral registers to their default reset values. * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx - * @note GPIOE is only available on STM32F07xx and STM32F09xx * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None @@ -342,19 +330,19 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO Direction in Input Floting Mode */ - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); + CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + CLEAR_BIT(GPIOx->AFR[position >> 3], (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2)); /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ @@ -364,15 +352,15 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) { tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~tmp; + CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp); /* Clear EXTI line configuration */ - EXTI->IMR &= ~((uint32_t)iocurrent); - EXTI->EMR &= ~((uint32_t)iocurrent); + CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~((uint32_t)iocurrent); - EXTI->FTSR &= ~((uint32_t)iocurrent); + CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); } } @@ -397,10 +385,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) */ /** - * @brief Reads the specified input port pin. + * @brief Read the specified input port pin. * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx - * @note GPIOE is only available on STM32F07xx and STM32F09xx * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. @@ -424,13 +410,12 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) } /** - * @brief Sets or clears the selected data port bit. - * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx - * @note GPIOE is only available on STM32F07xx and STM32F09xx + * + * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32F0 family * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @param PinState: specifies the value to be written to the selected bit. @@ -451,16 +436,14 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin } else { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + GPIOx->BRR = (uint32_t)GPIO_Pin; } } /** - * @brief Toggles the specified GPIO pin + * @brief Toggle the specified GPIO pin. * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family - * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx - * @note GPIOE is only available on STM32F07xx and STM32F09xx - * @param GPIO_Pin: specifies the pins to be toggled. + * @param GPIO_Pin: specifies the pin to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -477,10 +460,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. -* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family -* @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx -* @note GPIOE is only available on STM32F07xx and STM32F09xx -* @param GPIO_Pin: specifies the port bit to be locked. + * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family + * @param GPIO_Pin: specifies the port bits to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ @@ -493,7 +474,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Apply lock key write sequence */ - tmp |= GPIO_Pin; + SET_BIT(tmp, GPIO_Pin); /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ @@ -514,7 +495,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) } /** - * @brief This function handles EXTI interrupt request. + * @brief Handle EXTI interrupt request. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ @@ -529,13 +510,13 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) } /** - * @brief EXTI line detection callbacks. + * @brief EXTI line detection callback. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h index 9fcbe451bd..118fbf5b6a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -93,19 +93,9 @@ typedef enum */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ */ - -/** @defgroup GPIO_pin_actions GPIO pin actions - * @{ - */ -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -/** - * @} - */ - /** @defgroup GPIO_pins GPIO pins * @{ */ @@ -128,8 +118,6 @@ typedef enum #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ - -#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK) != (uint32_t)0x00) /** * @} */ @@ -149,30 +137,13 @@ typedef enum #define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ #define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ - -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ - +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ #define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - #define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ - ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ - ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ - ((MODE) == GPIO_MODE_AF_PP) ||\ - ((MODE) == GPIO_MODE_AF_OD) ||\ - ((MODE) == GPIO_MODE_IT_RISING) ||\ - ((MODE) == GPIO_MODE_IT_FALLING) ||\ - ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING) ||\ - ((MODE) == GPIO_MODE_EVT_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_ANALOG)) - /** * @} */ @@ -185,8 +156,6 @@ typedef enum #define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */ #define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */ -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \ - ((SPEED) == GPIO_SPEED_HIGH)) /** * @} */ @@ -198,9 +167,6 @@ typedef enum #define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ #define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ #define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ - -#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ - ((PULL) == GPIO_PULLDOWN)) /** * @} */ @@ -210,13 +176,12 @@ typedef enum */ /* Exported macro ------------------------------------------------------------*/ - /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ */ /** - * @brief Checks whether the specified EXTI line flag is set or not. + * @brief Check whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__: specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). @@ -224,7 +189,7 @@ typedef enum #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** - * @brief Clears the EXTI's line pending flags. + * @brief Clear the EXTI's line pending flags. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None @@ -232,7 +197,7 @@ typedef enum #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** - * @brief Checks whether the specified EXTI line is asserted or not. + * @brief Check whether the specified EXTI line is asserted or not. * @param __EXTI_LINE__: specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). @@ -240,7 +205,7 @@ typedef enum #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** - * @brief Clears the EXTI's line pending bits. + * @brief Clear the EXTI's line pending bits. * @param __EXTI_LINE__: specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None @@ -248,7 +213,7 @@ typedef enum #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** - * @brief Generates a Software interrupt on selected EXTI line. + * @brief Generate a Software interrupt on selected EXTI line. * @param __EXTI_LINE__: specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None @@ -259,7 +224,39 @@ typedef enum * @} */ -/* Include GPIO HAL Extension module */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ #include "stm32f0xx_hal_gpio_ex.h" /* Exported functions --------------------------------------------------------*/ @@ -315,4 +312,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif /* __STM32F0xx_HAL_GPIO_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h index b737e4e5fd..39b8f57b27 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @defgroup GPIOEx GPIOEx Extended HAL module driver +/** @defgroup GPIOEx GPIOEx * @{ */ @@ -82,6 +82,7 @@ #define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */ #define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */ /* AF 2 */ #define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */ @@ -613,6 +614,7 @@ /* AF 3 */ #define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */ #define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */ /* AF 4 */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c index 0b386ad15f..a980fdb780 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral State functions + * + Peripheral State and Errors functions * @verbatim ============================================================================== @@ -21,32 +21,32 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API: - (++) Enable the I2Cx interface clock - (++) I2C pins configuration + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs (+++) Configure I2C pins as alternate function open-drain - (++) NVIC configuration if you need to use interrupt process + (##) NVIC configuration if you need to use interrupt process (+++) Configure the I2Cx interrupt priority (+++) Enable the NVIC I2C IRQ Channel - (++) DMA Configuration if you need to use DMA process + (##) DMA Configuration if you need to use DMA process (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx channel - (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel - (#) Configure the Communication Clock Timing, Own Address1, Master Adressing Mode, Dual Addressing mode, + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing Mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the HAL_I2C_Init() API: - (++) These API s configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - (#) For I2C IO and IO MEM operations, three modes of operations are available within this driver : + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -66,70 +66,70 @@ *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** Interrupt mode IO MEM operation *** ======================================= [..] - (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using HAL_I2C_Mem_Write_IT() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using HAL_I2C_Mem_Read_IT() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] - (+) Transmit in master mode an amount of data in non blocking mode (DMA) using + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback - (+) Receive in master mode an amount of data in non blocking mode (DMA) using + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback - (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback - (+) Receive in slave mode an amount of data in non blocking mode (DMA) using + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO MEM operation *** ================================= [..] - (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using HAL_I2C_Mem_Write_DMA() - (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback - (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using HAL_I2C_Mem_Read_DMA() - (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -137,12 +137,12 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG : Clears the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enables the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disables the specified I2C interrupt + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt [..] (@) You can refer to the I2C HAL driver header file for more useful macros @@ -151,7 +151,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -185,7 +185,7 @@ * @{ */ -/** @defgroup I2C I2C HAL module driver +/** @defgroup I2C I2C * @brief I2C HAL module driver * @{ */ @@ -230,9 +230,9 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout); static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c); @@ -246,7 +246,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui * @} */ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup I2C_Exported_Functions I2C Exported Functions * @{ @@ -257,10 +257,10 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui * @verbatim =============================================================================== - ##### Initialization and Configuration functions ##### + ##### Initialization and de-initialization functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the I2Cx peripheral: + deinitialize the I2Cx peripheral: (+) User must Implement HAL_I2C_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). @@ -277,7 +277,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui (++) Nostretch mode (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx periperal. + of the selected I2Cx peripheral. @endverbatim * @{ @@ -285,7 +285,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui /** * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and create the associated handle. + * in the I2C_InitTypeDef and initialize the associated handle. * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status @@ -310,6 +310,9 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) if(hi2c->State == HAL_I2C_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); } @@ -365,7 +368,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) } /** - * @brief DeInitializes the I2C peripheral. + * @brief DeInitialize the I2C peripheral. * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status @@ -390,6 +393,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) HAL_I2C_MspDeInit(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; /* Release Lock */ @@ -399,27 +403,27 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) } /** - * @brief I2C MSP Init. + * @brief Initialize the I2C MSP. * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspInit could be implemented in the user file */ } /** - * @brief I2C MSP DeInit + * @brief DeInitialize the I2C MSP. * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspDeInit could be implemented in the user file */ } @@ -439,7 +443,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) This subsection provides a set of functions allowing to manage the I2C data transfers. - (#) There is two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function after finishing transfer. @@ -474,7 +478,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Mem_Write_DMA() (++) HAL_I2C_Mem_Read_DMA() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_I2C_MemTxCpltCallback() (++) HAL_I2C_MemRxCpltCallback() (++) HAL_I2C_MasterTxCpltCallback() @@ -592,7 +596,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -706,7 +710,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -963,7 +967,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /** - * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress: Target device address @@ -1035,7 +1039,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D } /** - * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress: Target device address @@ -1106,7 +1110,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De } /** - * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData: Pointer to data buffer @@ -1156,7 +1160,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** - * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData: Pointer to data buffer @@ -1206,7 +1210,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa } /** - * @brief Transmit in master mode an amount of data in no-blocking mode with DMA + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress: Target device address @@ -1297,7 +1301,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t } /** - * @brief Receive in master mode an amount of data in no-blocking mode with DMA + * @brief Receive in master mode an amount of data in non-blocking mode with DMA * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress: Target device address @@ -1378,7 +1382,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D } /** - * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData: Pointer to data buffer @@ -1464,7 +1468,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p } /** - * @brief Receive in slave mode an amount of data in no-blocking mode with DMA + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData: Pointer to data buffer @@ -1533,7 +1537,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD return HAL_BUSY; } } - /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains @@ -1662,7 +1665,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -1800,7 +1803,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -1814,9 +1817,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, return HAL_BUSY; } } - /** - * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress: Target device address @@ -1909,7 +1911,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /** - * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress: Target device address @@ -1999,9 +2001,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre return HAL_BUSY; } } - /** - * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress: Target device address @@ -2110,7 +2111,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /** - * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address. + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress: Target device address @@ -2241,7 +2242,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd do { /* Generate Start */ - hi2c->Instance->CR2 = __HAL_I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ @@ -2325,6 +2326,13 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ /** * @brief This function handles I2C event interrupt request. @@ -2408,7 +2416,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* Call the Error Callback in case of Error detected */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { hi2c->State = HAL_I2C_STATE_READY; @@ -2424,7 +2432,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) */ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_TxCpltCallback could be implemented in the user file */ } @@ -2437,7 +2445,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_TxCpltCallback could be implemented in the user file */ } @@ -2449,7 +2457,7 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) */ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_TxCpltCallback could be implemented in the user file */ } @@ -2462,7 +2470,7 @@ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_TxCpltCallback could be implemented in the user file */ } @@ -2475,7 +2483,7 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) */ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_TxCpltCallback could be implemented in the user file */ } @@ -2488,7 +2496,7 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) */ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_TxCpltCallback could be implemented in the user file */ } @@ -2501,7 +2509,7 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) */ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ErrorCallback could be implemented in the user file */ } @@ -2518,7 +2526,7 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) ##### Peripheral State and Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -2526,20 +2534,22 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) */ /** - * @brief Returns the I2C state. - * @param hi2c : I2C handle + * @brief Return the I2C handle state. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL state */ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) { + /* Return I2C handle state */ return hi2c->State; } /** -* @brief Return the I2C error code -* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains +* @brief Return the I2C error code. + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. -* @retval I2C Error Code + * @retval I2C Error Code */ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { @@ -2631,7 +2641,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -2738,7 +2748,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -2949,13 +2959,13 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) @@ -2971,7 +2981,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ @@ -3014,13 +3024,13 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } - /* If Mememory address size is 16Bit */ + /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) @@ -3036,7 +3046,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ @@ -3092,7 +3102,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3149,7 +3159,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3183,7 +3193,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -3299,7 +3309,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3362,7 +3372,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3397,7 +3407,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -3514,7 +3524,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3571,7 +3581,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3605,7 +3615,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -3670,7 +3680,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3733,7 +3743,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3767,7 +3777,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -3953,7 +3963,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State= HAL_I2C_STATE_READY; @@ -4030,7 +4040,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_AF; hi2c->State= HAL_I2C_STATE_READY; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h index 80fbdfcb80..8b8558b32b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -81,11 +81,11 @@ typedef struct uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_own_address2_masks. */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_own_address2_masks */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_general_call_addressing_mode. */ + This parameter can be a value of @ref I2C_general_call_addressing_mode */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. This parameter can be a value of @ref I2C_nostretch_mode */ @@ -114,9 +114,24 @@ typedef enum HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */ HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */ HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ - }HAL_I2C_StateTypeDef; +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */ /** * @} */ @@ -125,7 +140,6 @@ typedef enum * @brief I2C handle Structure definition * @{ */ - typedef struct { I2C_TypeDef *Instance; /*!< I2C registers base address */ @@ -146,8 +160,7 @@ typedef struct __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - __IO uint32_t ErrorCode; /*!< I2C Error code - This parameter can be a value of @ref I2C_Error */ + __IO uint32_t ErrorCode; /*!< I2C Error code */ }I2C_HandleTypeDef; /** @@ -163,33 +176,11 @@ typedef struct * @{ */ -/** @defgroup I2C_Error I2C Error - * @brief I2C Error - * @{ - */ - -#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< AF error */ -#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */ - -/** - * @} - */ - - /** @defgroup I2C_addressing_mode I2C addressing mode * @{ */ #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) #define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) /** * @} */ @@ -197,12 +188,8 @@ typedef struct /** @defgroup I2C_dual_addressing_mode I2C dual addressing mode * @{ */ - -#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000) -#define I2C_DUALADDRESS_ENABLED I2C_OAR2_OA2EN - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLED)) +#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} */ @@ -210,7 +197,6 @@ typedef struct /** @defgroup I2C_own_address2_masks I2C own address2 masks * @{ */ - #define I2C_OA2_NOMASK ((uint8_t)0x00) #define I2C_OA2_MASK01 ((uint8_t)0x01) #define I2C_OA2_MASK02 ((uint8_t)0x02) @@ -219,15 +205,6 @@ typedef struct #define I2C_OA2_MASK05 ((uint8_t)0x05) #define I2C_OA2_MASK06 ((uint8_t)0x06) #define I2C_OA2_MASK07 ((uint8_t)0x07) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) /** * @} */ @@ -235,11 +212,8 @@ typedef struct /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode * @{ */ -#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000) -#define I2C_GENERALCALL_ENABLED I2C_CR1_GCEN - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \ - ((CALL) == I2C_GENERALCALL_ENABLED)) +#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} */ @@ -247,11 +221,8 @@ typedef struct /** @defgroup I2C_nostretch_mode I2C nostretch mode * @{ */ -#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000) -#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLED)) +#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} */ @@ -261,9 +232,6 @@ typedef struct */ #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) /** * @} */ @@ -271,14 +239,9 @@ typedef struct /** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition * @{ */ - #define I2C_RELOAD_MODE I2C_CR2_RELOAD #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND #define I2C_SOFTEND_MODE ((uint32_t)0x00000000) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) /** * @} */ @@ -286,17 +249,10 @@ typedef struct /** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition * @{ */ - #define I2C_NO_STARTSTOP ((uint32_t)0x00000000) #define I2C_GENERATE_STOP I2C_CR2_STOP #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define I2C_GENERATE_START_WRITE I2C_CR2_START - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - /** * @} */ @@ -323,7 +279,6 @@ typedef struct /** @defgroup I2C_Flag_definition I2C Flag definition * @{ */ - #define I2C_FLAG_TXE I2C_ISR_TXE #define I2C_FLAG_TXIS I2C_ISR_TXIS #define I2C_FLAG_RXNE I2C_ISR_RXNE @@ -354,107 +309,117 @@ typedef struct * @{ */ -/** @brief Reset I2C handle state - * @param __HANDLE__: I2C handle. +/** @brief Reset I2C handle state. + * @param __HANDLE__: specifies the I2C Handle. * @retval None */ #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -/** @brief Enables or disables the specified I2C interrupts. +/** @brief Enable the specified I2C interrupt. * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__: specifies the interrupt source to enable. * This parameter can be one of the following values: - * @arg I2C_IT_ERRI: Errors interrupt enable - * @arg I2C_IT_TCI: Transfer complete interrupt enable + * @arg I2C_IT_ERRI: Errors interrupt enable + * @arg I2C_IT_TCI: Transfer complete interrupt enable * @arg I2C_IT_STOPI: STOP detection interrupt enable * @arg I2C_IT_NACKI: NACK received interrupt enable * @arg I2C_IT_ADDRI: Address match interrupt enable - * @arg I2C_IT_RXI: RX interrupt enable - * @arg I2C_IT_TXI: TX interrupt enable + * @arg I2C_IT_RXI: RX interrupt enable + * @arg I2C_IT_TXI: TX interrupt enable * * @retval None */ #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + +/** @brief Disable the specified I2C interrupt. * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __INTERRUPT__: specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_ERRI: Errors interrupt enable - * @arg I2C_IT_TCI: Transfer complete interrupt enable + * @param __INTERRUPT__: specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg I2C_IT_ERRI: Errors interrupt enable + * @arg I2C_IT_TCI: Transfer complete interrupt enable * @arg I2C_IT_STOPI: STOP detection interrupt enable * @arg I2C_IT_NACKI: NACK received interrupt enable * @arg I2C_IT_ADDRI: Address match interrupt enable - * @arg I2C_IT_RXI: RX interrupt enable - * @arg I2C_IT_TXI: TX interrupt enable - * - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks whether the specified I2C flag is set or not. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_TXE: Transmit data register empty - * @arg I2C_FLAG_TXIS: Transmit interrupt status - * @arg I2C_FLAG_RXNE: Receive data register not empty - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure received flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_TC: Transfer complete (master mode) - * @arg I2C_FLAG_TCR: Transfer complete reload - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus alert - * @arg I2C_FLAG_BUSY: Bus busy - * @arg I2C_FLAG_DIR: Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_ADDR: Address matched (slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_STOPF: STOP detection flag - * @arg I2C_FLAG_BERR: Bus error - * @arg I2C_FLAG_ARLO: Arbitration lost - * @arg I2C_FLAG_OVR: Overrun/Underrun - * @arg I2C_FLAG_PECERR: PEC error in reception - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag - * @arg I2C_FLAG_ALERT: SMBus alert + * @arg I2C_IT_RXI: RX interrupt enable + * @arg I2C_IT_TXI: TX interrupt enable * * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__: specifies the I2C Handle. + * @param __INTERRUPT__: specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_ERRI: Errors interrupt enable + * @arg I2C_IT_TCI: Transfer complete interrupt enable + * @arg I2C_IT_STOPI: STOP detection interrupt enable + * @arg I2C_IT_NACKI: NACK received interrupt enable + * @arg I2C_IT_ADDRI: Address match interrupt enable + * @arg I2C_IT_RXI: RX interrupt enable + * @arg I2C_IT_TXI: TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) -#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__: specifies the I2C Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_TXE: Transmit data register empty + * @arg I2C_FLAG_TXIS: Transmit interrupt status + * @arg I2C_FLAG_RXNE: Receive data register not empty + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure received flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_TC: Transfer complete (master mode) + * @arg I2C_FLAG_TCR: Transfer complete reload + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus alert + * @arg I2C_FLAG_BUSY: Bus busy + * @arg I2C_FLAG_DIR: Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define I2C_FLAG_MASK ((uint32_t)0x0001FFFF) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) -#define __HAL_I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__: specifies the I2C Handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure received flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK)) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__: specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) -#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__: specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) -#define __HAL_I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) /** * @} */ @@ -470,13 +435,11 @@ typedef struct /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ - -/* Initialization/de-initialization functions **********************************/ +/* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); - /** * @} */ @@ -484,9 +447,7 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions * @{ */ - -/* IO operation functions *****************************************************/ - +/* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -511,7 +472,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +/** + * @} + */ +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -522,7 +489,6 @@ void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); - /** * @} */ @@ -530,8 +496,7 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions * @{ */ - -/* Peripheral State and Errors functions **************************************/ +/* Peripheral State and Errors functions *************************************/ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); @@ -543,6 +508,76 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); * @} */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32l4xx_hal_i2c.c file */ +/** + * @} + */ + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c index 6026fff2c0..7a3b839e29 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c @@ -2,19 +2,19 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 - * @brief I2C Extension HAL module driver. + * @version V1.3.0 + * @date 26-June-2015 + * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following - * functionalities of I2C extension peripheral: - * + Extension features functions + * functionalities of I2C Extended peripheral: + * + Extended features functions * @verbatim ============================================================================== - ##### I2C peripheral extension features ##### + ##### I2C peripheral Extended features ##### ============================================================================== - [..] Comparing to other previous devices, the I2C interface for STM32F0XX + [..] Comparing to other previous devices, the I2C interface for STM32F0xx devices contains the following additional features (+) Possibility to disable or enable Analog Noise Filter @@ -24,17 +24,19 @@ ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure Noise Filter - (#) Configure I2C Analog noise filter using the function HAL_I2CEx_AnalogFilter_Config() - (#) Configure I2C Digital noise filter using the function HAL_I2CEx_DigitalFilter_Config() - (#) Configure the enabling or disabling of I2C Wake Up Mode using the functions : + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : (++) HAL_I2CEx_EnableWakeUp() (++) HAL_I2CEx_DisableWakeUp() - + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisbleFastModePlus() @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -68,7 +70,7 @@ * @{ */ -/** @defgroup I2CEx I2CEx Extended HAL module driver +/** @defgroup I2CEx I2CEx * @brief I2C Extended HAL module driver * @{ */ @@ -82,7 +84,7 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup I2CEx_Exported_Functions I2CEx Exported Functions +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ @@ -91,7 +93,7 @@ * @verbatim =============================================================================== - ##### Extension features functions ##### + ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters @@ -107,7 +109,7 @@ * @param AnalogFilter : new state of the Analog filter. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -150,7 +152,7 @@ HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_ * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { uint32_t tmpreg = 0; @@ -272,6 +274,43 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) return HAL_OK; } #endif /* !(STM32F030x6) && !(STM32F030x8) && !(STM32F070x6) && !(STM32F070xB) && !(STM32F030xC) */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus: selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus: selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h index 1452a42e57..4a1ce13499 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 - * @brief Header file of I2C HAL Extension module. + * @version V1.3.0 + * @date 26-June-2015 + * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup I2CEx I2CEx Extended HAL module driver +/** @addtogroup I2CEx I2CEx * @{ */ @@ -64,23 +64,55 @@ /** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter * @{ */ -#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000) -#define I2C_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF - -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLED)) +#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} */ -/** @defgroup I2CEx_Digital_Filter I2CEx Digital Filter +/** @defgroup I2CEx_FastModePlus I2CEx Fast Mode Plus * @{ */ -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) +#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ +#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */ +#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */ +#elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F030xC) +#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ +#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ +#elif defined(STM32F070xB) +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ +#else /* defined(STM32F030x8) || defined(STM32F051xx) || defined(STM32F058xx) */ +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ +#endif /** * @} */ - + /** * @} */ @@ -98,17 +130,78 @@ */ /* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c); #endif /* !(STM32F030x6) && !(STM32F030x8) && !(STM32F070x6) && !(STM32F070xB) && !(STM32F030xC) */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ /** * @} */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)) +#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)) +#elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F030xC) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)) +#elif defined(STM32F070xB) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)) +#else /* defined(STM32F030x8) || defined(STM32F051xx) || defined(STM32F058xx) */ +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9)) +#endif +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */ /** * @} */ @@ -120,7 +213,16 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c); /** * @} */ - + +/** + * @} + */ + +/** + * @} + */ + + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c index c1a03a8b25..e56e057a76 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_i2s.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -108,7 +108,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -150,7 +150,7 @@ * @{ */ -/** @defgroup I2S I2S HAL module driver +/** @defgroup I2S I2S * @brief I2S HAL module driver * @{ */ @@ -238,6 +238,9 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) if(hi2s->State == HAL_I2S_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hi2s->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2S_MspInit(hi2s); } @@ -982,18 +985,18 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN); hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN); - /* Disable the I2S DMA channel */ - __HAL_DMA_DISABLE(hi2s->hdmatx); - __HAL_DMA_DISABLE(hi2s->hdmarx); - /* Abort the I2S DMA tx channel */ if(hi2s->hdmatx != NULL) { + /* Disable the I2S DMA channel */ + __HAL_DMA_DISABLE(hi2s->hdmatx); HAL_DMA_Abort(hi2s->hdmatx); } /* Abort the I2S DMA rx channel */ if(hi2s->hdmarx != NULL) { + /* Disable the I2S DMA channel */ + __HAL_DMA_DISABLE(hi2s->hdmarx); HAL_DMA_Abort(hi2s->hdmarx); } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h index 38e7841ee0..a4e3a1d7fc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_i2s.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c index 3bb9b44478..1dce50627f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c @@ -2,106 +2,116 @@ ****************************************************************************** * @file stm32f0xx_hal_irda.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief IRDA HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the IrDA (Infrared Data Association) Peripheral + * This file provides firmware functions to manage the following + * functionalities of the IrDA (Infrared Data Association) Peripheral * (IRDA) - * + Initialization and de-initialization function - * + IO operation function - * + Peripheral Control function + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + Peripheral Control functions * - * - @verbatim - =============================================================================== + @verbatim + ============================================================================== ##### How to use this driver ##### - =============================================================================== - [..] + ============================================================================== + [..] The IRDA HAL driver can be used as follows: - - (#) Declare a IRDA_HandleTypeDef handle structure. - (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API: - (##) Enable the USARTx interface clock. - (##) IRDA pins configuration: - (+++) Enable the clock for the IRDA GPIOs. - (+++) Configure these IRDA pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() - and HAL_IRDA_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() + + (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda). + (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API + in setting the associated USART or UART in IRDA mode: + (++) Enable the USARTx/UARTx interface clock. + (++) USARTx/UARTx pins configuration: + (+++) Enable the clock for the USARTx/UARTx GPIOs. + (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input). + (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() + and HAL_IRDA_Receive_IT() APIs): + (+++) Configure the USARTx/UARTx interrupt priority. + (+++) Enable the NVIC USARTx/UARTx IRQ handle. + (+++) The specific IRDA interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. + + (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() and HAL_IRDA_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle. + (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), - the normal or low power mode and the clock prescaler in the hirda Init structure. + the normal or low power mode and the clock prescaler in the hirda handle Init structure. (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: - (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_IRDA_MspInit() API. - - -@@- The specific IRDA interrupts (Transmission complete interrupt, + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_IRDA_MspInit() API. + + -@@- The specific IRDA interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. (#) Three operation modes are available within this driver : - + *** Polling mode IO operation *** ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() + [..] + (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_IRDA_ErrorCallback - *** DMA mode IO operation *** + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback() + + *** DMA mode IO operation *** ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_IRDA_ErrorCallback + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA() + (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA() + (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback() *** IRDA HAL driver macros list *** ==================================== [..] Below the list of most used macros in IRDA HAL driver. - - (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral - (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral + + (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral + (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt - - [..] + (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled + + [..] (@) You can refer to the IRDA HAL driver header file for more useful macros @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -125,7 +135,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -133,107 +143,122 @@ #ifdef HAL_IRDA_MODULE_ENABLED -#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** @addtogroup STM32F0xx_HAL_Driver * @{ */ -/** @defgroup IRDA IRDA HAL module driver +/** @defgroup IRDA IRDA * @brief HAL IRDA module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup IRDA_Private_Constants IRDA Private Constants +/** @defgroup IRDA_Private_Constants IRDA Private Constants * @{ */ -#define TEACK_REACK_TIMEOUT 1000 +#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */ #define IRDA_TXDMA_TIMEOUTVALUE 22000 #define IRDA_TIMEOUT_VALUE 22000 #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ - | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) + | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ /** * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup IRDA_Private_Functions IRDA Private Functions +/** @addtogroup IRDA_Private_Functions IRDA Private Functions * @{ */ -static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); /** * @} */ -/* Exported functions ---------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ /** @defgroup IRDA_Exported_Functions IRDA Exported Functions * @{ */ -/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== - ##### Initialization and Configuration functions ##### + ##### Initialization and Configuration functions ##### ============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx - in IRDA mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits) - or by the M1 and M0 bits (7-bit, 8-bit or 9-bit), - the possible IRDA frame formats are as listed in the following table: - +---------------------------------------------------------------+ - | M bit | PCE bit | IRDA frame | - |-----------|-----------|---------------------------------------| - | 0 | 0 | | SB | 8-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7-bit data | PB | STB | | - |-----------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8-bit data | PB | STB | | - +---------------------------------------------------------------+ - | M1M0 bits | PCE bit | IRDA frame | - |-----------------------|---------------------------------------| - | 10 | 0 | | SB | 7-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 10 | 1 | | SB | 6-bit data | PB | STB | | - +---------------------------------------------------------------+ - + [..] + This subsection provides a set of functions allowing to initialize the USARTx + in asynchronous IRDA mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + According to device capability (support or not of 7-bit word length), + frame length is either defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). + Possible IRDA frame formats are as listed in the following table: + + (+++) Table 1. IRDA frame format. + (+++) +-----------------------------------------------------------------------+ + (+++) | M bit | PCE bit | IRDA frame | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 0 | 0 | | SB | 8-bit data | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 1 | 0 | | SB | 9-bit data | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | | + (+++) +-----------------------------------------------------------------------+ + (+++) | M1 bit | M0 bit | PCE bit | IRDA frame | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + (+++) +-----------------------------------------------------------------------+ + (++) Power mode - (++) Prescaler setting + (++) Prescaler setting (++) Receiver/transmitter modes - [..] - The HAL_IRDA_Init() function follows IRDA configuration procedures - (details for the procedures are available in reference manual). + [..] + The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures + (details for the procedures are available in reference manual). @endverbatim * @{ */ /** - * @brief Initializes the IRDA mode according to the specified - * parameters in the IRDA_InitTypeDef and creates the associated handle . - * @param hirda: IRDA handle + * @brief Initialize the IRDA mode according to the specified + * parameters in the IRDA_InitTypeDef and initialize the associated handle. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) @@ -243,46 +268,50 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) { return HAL_ERROR; } - + /* Check the USART/UART associated to the IRDA handle */ assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - + if(hirda->State == HAL_IRDA_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + hirda->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_IRDA_MspInit(hirda); } - + hirda->State = HAL_IRDA_STATE_BUSY; - + /* Disable the Peripheral to update the configuration registers */ __HAL_IRDA_DISABLE(hirda); - + /* Set the IRDA Communication parameters */ if (IRDA_SetConfig(hirda) == HAL_ERROR) { return HAL_ERROR; - } - - /* In IRDA mode, the following bits must be kept cleared: + } + + /* In IRDA mode, the following bits must be kept cleared: - LINEN, STOP and CLKEN bits in the USART_CR2 register, - SCEN and HDSEL bits in the USART_CR3 register.*/ - hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP); - hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL); - + hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP); + hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL); + /* set the UART/USART in IRDA mode */ - hirda->Instance->CR3 |= USART_CR3_IREN; - + hirda->Instance->CR3 |= USART_CR3_IREN; + /* Enable the Peripheral */ __HAL_IRDA_ENABLE(hirda); - + /* TEACK and/or REACK to check before moving hirda->State to Ready */ return (IRDA_CheckIdleState(hirda)); } /** - * @brief DeInitializes the IRDA peripheral - * @param hirda: IRDA handle + * @brief DeInitialize the IRDA peripheral. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) @@ -292,140 +321,147 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) { return HAL_ERROR; } - + /* Check the USART/UART associated to the IRDA handle */ assert_param(IS_IRDA_INSTANCE(hirda->Instance)); hirda->State = HAL_IRDA_STATE_BUSY; - + /* DeInit the low level hardware */ HAL_IRDA_MspDeInit(hirda); /* Disable the Peripheral */ __HAL_IRDA_DISABLE(hirda); - + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->State = HAL_IRDA_STATE_RESET; - + /* Process Unlock */ __HAL_UNLOCK(hirda); - + return HAL_OK; } /** - * @brief IRDA MSP Init - * @param hirda: IRDA handle + * @brief Initialize the IRDA MSP. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) { - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_MspInit can be implemented in the user file - */ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_MspInit can be implemented in the user file + */ } /** - * @brief IRDA MSP DeInit - * @param hirda: IRDA handle + * @brief DeInitialize the IRDA MSP. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) { - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_MspDeInit can be implemented in the user file - */ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_MspDeInit can be implemented in the user file + */ } /** * @} */ -/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions - * @brief IRDA Transmit and Receive functions +/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions + * @brief IRDA Transmit and Receive functions * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== [..] This subsection provides a set of functions allowing to manage the IRDA data transfers. [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) Non Blocking mode: The communication is performed using Interrupts - or DMA, these API s return the HAL status. - The end of the data processing will be indicated through the - dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the Transmit or Receive process - The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected + (++) Blocking mode: the communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: the communication is performed using Interrupts + or DMA, these API's return the HAL status. + The end of the data processing will be indicated through the + dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks + will be executed respectively at the end of the Transmit or Receive process + The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected - (#) Blocking mode API s are : + (#) Blocking mode APIs are : (++) HAL_IRDA_Transmit() - (++) HAL_IRDA_Receive() - - (#) Non Blocking mode API s with Interrupt are : + (++) HAL_IRDA_Receive() + + (#) Non Blocking mode APIs with Interrupt are : (++) HAL_IRDA_Transmit_IT() (++) HAL_IRDA_Receive_IT() (++) HAL_IRDA_IRQHandler() - (++) IRDA_Transmit_IT() - (++) IRDA_Receive_IT() (#) Non Blocking mode functions with DMA are : (++) HAL_IRDA_Transmit_DMA() (++) HAL_IRDA_Receive_DMA() + (++) HAL_IRDA_DMAPause() + (++) HAL_IRDA_DMAResume() + (++) HAL_IRDA_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: + (++) HAL_IRDA_TxHalfCpltCallback() (++) HAL_IRDA_TxCpltCallback() + (++) HAL_IRDA_RxHalfCpltCallback() (++) HAL_IRDA_RxCpltCallback() (++) HAL_IRDA_ErrorCallback() - + @endverbatim * @{ */ /** - * @brief Send an amount of data in blocking mode - * @param hirda: IRDA handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Duration of the timeout + * @brief Send an amount of data in blocking mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer. + * @param Size: Amount of data to be sent. + * @param Timeout: Specify timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; - - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) + uint16_t* tmp; + + if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hirda); + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + if(hirda->State == HAL_IRDA_STATE_BUSY_RX) { hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; } else { hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - + } + hirda->TxXferSize = Size; hirda->TxXferCount = Size; while(hirda->TxXferCount > 0) @@ -439,79 +475,81 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { tmp = (uint16_t*) pData; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - pData += 2; + hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); + pData +=2; } else { - hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF); + hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF); } } if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; - } + } - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) { hirda->State = HAL_IRDA_STATE_BUSY_RX; } else { hirda->State = HAL_IRDA_STATE_READY; - } - + } + /* Process Unlocked */ __HAL_UNLOCK(hirda); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in blocking mode - * @param hirda: IRDA handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Duration of the timeout + * @brief Receive an amount of data in blocking mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer. + * @param Size: Amount of data to be received. + * @param Timeout: Specify timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ +{ uint16_t* tmp; uint16_t uhMask; - - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) + + if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) + { + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hirda); + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) { hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; } else { hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - - hirda->RxXferSize = Size; + } + + hirda->RxXferSize = Size; hirda->RxXferCount = Size; - /* Computation of the mask to apply to the RDR register + /* Computation of the mask to apply to the RDR register of the UART associated to the IRDA */ - __HAL_IRDA_MASK_COMPUTATION(hirda); + IRDA_MASK_COMPUTATION(hirda); uhMask = hirda->Mask; /* Check data remaining to be received */ @@ -520,7 +558,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui hirda->RxXferCount--; if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; } if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) @@ -531,11 +569,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui } else { - *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); } } - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) { hirda->State = HAL_IRDA_STATE_BUSY_TX; } @@ -543,43 +581,45 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui { hirda->State = HAL_IRDA_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(hirda); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Send an amount of data in interrupt mode - * @param hirda: IRDA handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in interrupt mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer. + * @param Size: Amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) + if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hirda); - + hirda->pTxBuffPtr = pData; hirda->TxXferSize = Size; hirda->TxXferCount = Size; hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + + if(hirda->State == HAL_IRDA_STATE_BUSY_RX) { hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; } @@ -588,52 +628,53 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->State = HAL_IRDA_STATE_BUSY_TX; } + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - /* Enable the IRDA Transmit Data Register Empty Interrupt */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in interrupt mode - * @param hirda: IRDA handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in interrupt mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer. + * @param Size: Amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) +{ + if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hirda); - + hirda->pRxBuffPtr = pData; hirda->RxXferSize = Size; hirda->RxXferCount = Size; - /* Computation of the mask to apply to the RDR register + /* Computation of the mask to apply to the RDR register of the UART associated to the IRDA */ - __HAL_IRDA_MASK_COMPUTATION(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + IRDA_MASK_COMPUTATION(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) { hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; } @@ -641,55 +682,56 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, { hirda->State = HAL_IRDA_STATE_BUSY_RX; } - - /* Enable the IRDA Parity Error Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); - - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); - + /* Process Unlocked */ __HAL_UNLOCK(hirda); - + /* Enable the IRDA Data Register not empty Interrupt */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); - + + /* Enable the IRDA Parity Error Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Send an amount of data in DMA mode - * @param hirda: IRDA handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in DMA mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) + + if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hirda); - + hirda->pTxBuffPtr = pData; hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - + hirda->TxXferCount = Size; + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + + if(hirda->State == HAL_IRDA_STATE_BUSY_RX) { hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; } @@ -697,60 +739,68 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat { hirda->State = HAL_IRDA_STATE_BUSY_TX; } - + /* Set the IRDA DMA transfer complete callback */ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; - + + /* Set the IRDA DMA half transfer complete callback */ + hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; + /* Set the DMA error callback */ hirda->hdmatx->XferErrorCallback = IRDA_DMAError; /* Enable the IRDA transmit DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size); - + + /* Clear the TC flag in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); + /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the IRDA CR3 register */ + in the USART CR3 register */ hirda->Instance->CR3 |= USART_CR3_DMAT; - + /* Process Unlocked */ __HAL_UNLOCK(hirda); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in DMA mode - * @param hirda: IRDA handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @note When the IRDA parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) + * @brief Receive an amount of data in DMA mode. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData: Pointer to data buffer. + * @param Size: Amount of data to be received. + * @note When the IRDA parity is enabled (PCE = 1) the received data contains + * the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - - if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) + + if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hirda); - + hirda->pRxBuffPtr = pData; hirda->RxXferSize = Size; hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) { hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; } @@ -758,10 +808,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData { hirda->State = HAL_IRDA_STATE_BUSY_RX; } - + /* Set the IRDA DMA transfer complete callback */ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; - + + /* Set the IRDA DMA half transfer complete callback */ + hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; + /* Set the DMA error callback */ hirda->hdmarx->XferErrorCallback = IRDA_DMAError; @@ -769,400 +822,326 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the IRDA CR3 register */ + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ hirda->Instance->CR3 |= USART_CR3_DMAR; - + /* Process Unlocked */ __HAL_UNLOCK(hirda); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } - + + /** - * @brief This function handles IRDA interrupt request. - * @param hirda: IRDA handle + * @brief Pause the DMA Transfer. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + /* Disable the IRDA DMA Tx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + /* Disable the IRDA DMA Rx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + /* Disable the IRDA DMA Tx & Rx requests */ + CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + { + /* Enable the IRDA DMA Tx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_IRDA_CLEAR_OREFLAG(hirda); + /* Enable the IRDA DMA Rx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_IRDA_CLEAR_OREFLAG(hirda); + /* Enable the IRDA DMA Tx & Rx request */ + SET_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / + HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback(): + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is + generated if the DMA transfer interruption occurs at the middle or at the end of the stream + and the corresponding call back is executed. + */ + + /* Disable the IRDA Tx/Rx DMA requests */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA tx channel */ + if(hirda->hdmatx != NULL) + { + HAL_DMA_Abort(hirda->hdmatx); + } + /* Abort the IRDA DMA rx channel */ + if(hirda->hdmarx != NULL) + { + HAL_DMA_Abort(hirda->hdmarx); + } + + hirda->State = HAL_IRDA_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief Handle IRDA interrupt request. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) { /* IRDA parity error interrupt occurred -------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET)) - { + { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); hirda->ErrorCode |= HAL_IRDA_ERROR_PE; /* Set the IRDA state ready to be able to start again the process */ hirda->State = HAL_IRDA_STATE_READY; } - - /* IRDA frame error interrupt occured --------------------------------------*/ + + /* IRDA frame error interrupt occurred --------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) - { + { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); hirda->ErrorCode |= HAL_IRDA_ERROR_FE; /* Set the IRDA state ready to be able to start again the process */ hirda->State = HAL_IRDA_STATE_READY; } - - /* IRDA noise error interrupt occured --------------------------------------*/ + + /* IRDA noise error interrupt occurred --------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) - { + { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); - hirda->ErrorCode |= HAL_IRDA_ERROR_NE; + hirda->ErrorCode |= HAL_IRDA_ERROR_NE; /* Set the IRDA state ready to be able to start again the process */ hirda->State = HAL_IRDA_STATE_READY; } - - /* IRDA Over-Run interrupt occured -----------------------------------------*/ + + /* IRDA Over-Run interrupt occurred -----------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) - { + { __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); - hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; + hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; /* Set the IRDA state ready to be able to start again the process */ hirda->State = HAL_IRDA_STATE_READY; } - + /* Call IRDA Error Call back function if need be --------------------------*/ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) { HAL_IRDA_ErrorCallback(hirda); - } + } /* IRDA in mode Receiver ---------------------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET)) - { + { IRDA_Receive_IT(hirda); /* Clear RXNE interrupt flag */ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); } - + /* IRDA in mode Transmitter ------------------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET)) { IRDA_Transmit_IT(hirda); - } - + } + /* IRDA in mode Transmitter (transmission end) -----------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET)) { IRDA_EndTransmit_IT(hirda); - } - -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup IRDA_Private_Functions IRDA Private Functions - * @{ - */ - -/** - * @brief DMA IRDA Tx transfer completed callback - * @param hdma: DMA handle - * @retval None - */ -static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hirda->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the IRDA CR3 register */ - hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); - - /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); -} - -/** - * @brief DMA IRDA Rx Transfer completed callback - * @param hdma: DMA handle - * @retval None - */ -static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hirda->RxXferCount = 0; - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the IRDA CR3 register */ - hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; } - HAL_IRDA_RxCpltCallback(hirda); } /** - * @brief DMA IRDA communication error callback - * @param hdma: DMA handle - * @retval None - */ -static void IRDA_DMAError(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hirda->RxXferCount = 0; - hirda->TxXferCount = 0; - hirda->State= HAL_IRDA_STATE_READY; - hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; - HAL_IRDA_ErrorCallback(hirda); -} -/** - * @} - */ - -/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions - * @{ - */ - -/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/** - * @brief Tx Transfer completed callback - * @param hirda: irda handle + * @brief Tx Transfer completed callback. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) { - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback - * @param hirda: irda handle - * @retval None - */ -__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_TxCpltCallback can be implemented in the user file + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_TxCpltCallback can be implemented in the user file. */ } /** - * @brief IRDA error callback - * @param hirda: IRDA handle + * @brief Tx Half Transfer completed callback. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ + __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer complete callback. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA error callback. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) { - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_ErrorCallback can be implemented in the user file - */ + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_ErrorCallback can be implemented in the user file. + */ } /** * @} */ -/** - * @} - */ - -/** @addtogroup IRDA_Private_Functions IRDA Private Functions - * @{ - */ - -/** - * @brief Receive an amount of data in non blocking mode. - * Function called under interruption only, once - * interruptions have been enabled by HAL_IRDA_Transmit_IT() - * @param hirda: IRDA handle - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) -{ - uint16_t* tmp; - - if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) - { - - if(hirda->TxXferCount == 0) - { - /* Disable the IRDA Transmit Data Register Empty Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - - /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); - - return HAL_OK; - } - else - { - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - tmp = (uint16_t*) hirda->pTxBuffPtr; - hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); - hirda->pTxBuffPtr += 2; - } - else - { - hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF); - } - hirda->TxXferCount--; - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) -{ - /* Disable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State = HAL_IRDA_STATE_READY; - } - - HAL_IRDA_TxCpltCallback(hirda); - - return HAL_OK; -} - - -/** - * @brief Receive an amount of data in non blocking mode. - * Function called under interruption only, once - * interruptions have been enabled by HAL_IRDA_Receive_IT() - * @param hirda: IRDA handle - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) -{ - uint16_t* tmp; - uint16_t uhMask = hirda->Mask; - - if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) - { - - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - tmp = (uint16_t*) hirda->pRxBuffPtr ; - *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); - hirda->pRxBuffPtr +=2; - } - else - { - *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); - } - - if(--hirda->RxXferCount == 0) - { - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - /* Disable the IRDA Parity Error Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State = HAL_IRDA_STATE_READY; - } - - HAL_IRDA_RxCpltCallback(hirda); - - return HAL_OK; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @} - */ - -/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions - * @{ - */ - -/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief IRDA control functions +/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions + * @brief IRDA State and Errors functions * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the IRDA. - (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral. - (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters. +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of IrDA + communication process and also return Peripheral Errors occurred during communication process + (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state + of the IRDA peripheral handle. + (+) HAL_IRDA_GetError() checks in run-time errors that could occur during + communication. + @endverbatim * @{ */ /** - * @brief return the IRDA state - * @param hirda: irda handle + * @brief Return the IRDA handle state. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL state */ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { + /* Return IRDA handle state */ return hirda->State; } /** -* @brief Return the IRDA error code -* @param hirda : pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA. -* @retval IRDA Error Code -*/ + * @brief Return the IRDA handle error code. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval IRDA Error Code + */ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) { return hirda->ErrorCode; @@ -1174,74 +1153,77 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) /** * @} - */ + */ /** @addtogroup IRDA_Private_Functions IRDA Private Functions * @{ */ - + + /** - * @brief Configure the IRDA peripheral - * @param hirda: irda handle + * @brief Configure the IRDA peripheral. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval None */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { uint32_t tmpreg = 0x00000000; IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED; - HAL_StatusTypeDef ret = HAL_OK; - - /* Check the communication parameters */ - assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the communication parameters */ + assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); - assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); - assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); + assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); + assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Configure the IRDA Word Length, Parity and transfer Mode: - Set the M bits according to hirda->Init.WordLength value + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the IRDA Word Length, Parity and transfer Mode: + Set the M bits according to hirda->Init.WordLength value Set PCE and PS bits according to hirda->Init.Parity value Set TE and RE bits according to hirda->Init.Mode value */ tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ; - + MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg); - + /*-------------------------- USART CR3 Configuration -----------------------*/ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); - - /*-------------------------- USART GTPR Configuration ----------------------*/ + + /*-------------------------- USART GTPR Configuration ----------------------*/ MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); - - /*-------------------------- USART BRR Configuration -----------------------*/ - __HAL_IRDA_GETCLOCKSOURCE(hirda, clocksource); + + /*-------------------------- USART BRR Configuration -----------------------*/ + IRDA_GETCLOCKSOURCE(hirda, clocksource); switch (clocksource) { - case IRDA_CLOCKSOURCE_PCLK1: + case IRDA_CLOCKSOURCE_PCLK1: hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate); break; - case IRDA_CLOCKSOURCE_HSI: - hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_SYSCLK: - hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate); - break; - case IRDA_CLOCKSOURCE_LSE: - hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate); + case IRDA_CLOCKSOURCE_HSI: + hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_SYSCLK: + hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_LSE: + hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate); + break; + case IRDA_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; break; - case IRDA_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; } - - return ret; + + return ret; } /** - * @brief Check the IRDA Idle State - * @param hirda: IRDA handle + * @brief Check the IRDA Idle State. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) @@ -1250,67 +1232,79 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) /* Initialize the IRDA ErrorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - /* Check if the Transmitter is enabled */ - if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices). + Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature. + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) + if (IS_UART_WAKEUP_INSTANCE(hirda->Instance)) { - /* Wait until TEACK flag is set */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout Occured */ - return HAL_TIMEOUT; - } - } + /* Check if the Transmitter is enabled */ + if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ - if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout Occured */ - return HAL_TIMEOUT; - } + if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } } - +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ + /* Initialize the IRDA state*/ - hirda->State= HAL_IRDA_STATE_READY; + hirda->State= HAL_IRDA_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hirda); - + return HAL_OK; } /** * @brief Handle IRDA Communication Timeout. - * @param hirda: IRDA handle + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. * @param Flag: specifies the IRDA flag to check. - * @param Status: the flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status. + * @param Status: the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status. * @param Timeout: Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - + /* Wait until flag is set */ if(Status == RESET) - { + { while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - + hirda->State= HAL_IRDA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hirda); - + return HAL_TIMEOUT; } } @@ -1322,26 +1316,268 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - + hirda->State= HAL_IRDA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hirda); - + return HAL_TIMEOUT; } } } } - return HAL_OK; + return HAL_OK; +} + +/** + * @brief DMA IRDA transmit process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + { + hirda->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the IRDA CR3 register */ + hirda->Instance->CR3 &= ~(USART_CR3_DMAT); + + /* Enable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); + } + /* DMA Circular mode */ + else + { + HAL_IRDA_TxCpltCallback(hirda); + } +} + +/** + * @brief DMA IRDA transmit process half complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_IRDA_TxHalfCpltCallback(hirda); +} + +/** + * @brief DMA IRDA receive process complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + { + hirda->RxXferCount = 0; + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the IRDA CR3 register */ + hirda->Instance->CR3 &= ~(USART_CR3_DMAR); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + else + { + hirda->State = HAL_IRDA_STATE_READY; + } + } + + HAL_IRDA_RxCpltCallback(hirda); +} + +/** + * @brief DMA IRDA receive process half complete callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_IRDA_RxHalfCpltCallback(hirda); +} + +/** + * @brief DMA IRDA communication error callback. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hirda->RxXferCount = 0; + hirda->TxXferCount = 0; + hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; + hirda->State= HAL_IRDA_STATE_READY; + + HAL_IRDA_ErrorCallback(hirda); +} + + +/** + * @brief Send an amount of data in non-blocking mode. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Transmit_IT(). + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) +{ + uint16_t* tmp; + + if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) + { + if(hirda->TxXferCount == 0) + { + /* Disable the IRDA Transmit Data Register Empty Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); + + /* Enable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); + + return HAL_OK; + } + else + { + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t*) hirda->pTxBuffPtr; + hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF); + hirda->pTxBuffPtr += 2; + } + else + { + hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF); + } + hirda->TxXferCount--; + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + else + { + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State = HAL_IRDA_STATE_READY; + } + + HAL_IRDA_TxCpltCallback(hirda); + + return HAL_OK; +} + + +/** + * @brief Receive an amount of data in non-blocking mode. + * Function is called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Receive_IT(). + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) +{ + uint16_t* tmp; + uint16_t uhMask = hirda->Mask; + + if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) + { + + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t*) hirda->pRxBuffPtr ; + *tmp = (uint16_t)(hirda->Instance->RDR & uhMask); + hirda->pRxBuffPtr +=2; + } + else + { + *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + } + + if(--hirda->RxXferCount == 0) + { + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); + + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_TX; + } + else + { + /* Disable the IRDA Parity Error Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State = HAL_IRDA_STATE_READY; + } + + HAL_IRDA_RxCpltCallback(hirda); + + return HAL_OK; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } } /** @@ -1356,7 +1592,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, * @} */ -#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ #endif /* HAL_IRDA_MODULE_ENABLED */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h index 1dd71b5091..96272f3a3b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f0xx_hal_irda.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief This file contains all the functions prototypes for the IRDA * firmware library. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -55,16 +55,16 @@ /** @addtogroup IRDA * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup IRDA_Exported_Types IRDA Exported Types * @{ - */ + */ -/** - * @brief IRDA Init Structure definition - */ +/** + * @brief IRDA Init Structure definition + */ typedef struct { uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. @@ -74,32 +74,32 @@ typedef struct uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref IRDAEx_Word_Length */ - uint16_t Parity; /*!< Specifies the parity mode. + uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref IRDA_Parity @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ - - uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref IRDA_Mode */ - + uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock to achieve low-power frequency. @note Prescaler value 0 is forbidden */ - + uint16_t PowerMode; /*!< Specifies the IRDA power mode. This parameter can be a value of @ref IRDA_Low_Power */ }IRDA_InitTypeDef; -/** - * @brief HAL IRDA State structures definition - */ +/** + * @brief HAL IRDA State structures definition + */ typedef enum { - HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ + HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ @@ -116,56 +116,56 @@ typedef enum IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ + IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ }IRDA_ClockSourceTypeDef; -/** - * @brief IRDA handle Structure definition - */ +/** + * @brief IRDA handle Structure definition + */ typedef struct { USART_TypeDef *Instance; /*!< USART registers base address */ - + IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ - + uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ - + uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ - + uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ - + uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */ - + uint16_t RxXferSize; /*!< IRDA Rx Transfer size */ - + uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ - - uint16_t Mask; /*!< USART RX RDR register mask */ - + + uint16_t Mask; /*!< USART RX RDR register mask */ + DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ - + DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */ - + HAL_LockTypeDef Lock; /*!< Locking object */ - HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */ - + __IO HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */ + __IO uint32_t ErrorCode; /*!< IRDA Error code This parameter can be a value of @ref IRDA_Error */ }IRDA_HandleTypeDef; -/** - * @brief IRDA Configuration enumeration values definition +/** + * @brief IRDA Configuration enumeration values definition */ -typedef enum +typedef enum { - IRDA_BAUDRATE = 0x00, - IRDA_PARITY = 0x01, - IRDA_WORDLENGTH = 0x02, - IRDA_MODE = 0x03, - IRDA_PRESCALER = 0x04, - IRDA_POWERMODE = 0x05 + IRDA_BAUDRATE = 0x00, /*!< IRDA Baud rate */ + IRDA_PARITY = 0x01, /*!< IRDA frame parity */ + IRDA_WORDLENGTH = 0x02, /*!< IRDA frame length */ + IRDA_MODE = 0x03, /*!< IRDA communication mode */ + IRDA_PRESCALER = 0x04, /*!< IRDA prescaling */ + IRDA_POWERMODE = 0x05 /*!< IRDA power mode */ }IRDA_ControlTypeDef; /** @@ -173,13 +173,13 @@ typedef enum */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup IRDA_Exported_Constants IRDA Exported constants +/** @defgroup IRDA_Exported_Constants IRDA Exported Constants * @{ */ /** @defgroup IRDA_Error IRDA Error * @{ - */ + */ #define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */ #define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */ @@ -188,62 +188,51 @@ typedef enum #define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ /** * @} - */ + */ -/** @defgroup IRDA_Parity IRDA Parity +/** @defgroup IRDA_Parity IRDA Parity * @{ - */ -#define IRDA_PARITY_NONE ((uint16_t)0x0000) -#define IRDA_PARITY_EVEN ((uint16_t)USART_CR1_PCE) -#define IRDA_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ - ((PARITY) == IRDA_PARITY_EVEN) || \ - ((PARITY) == IRDA_PARITY_ODD)) -/** - * @} - */ - - -/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode - * @{ - */ -#define IRDA_MODE_RX ((uint16_t)USART_CR1_RE) -#define IRDA_MODE_TX ((uint16_t)USART_CR1_TE) -#define IRDA_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_IRDA_TX_RX_MODE(MODE) ((((MODE) & ((uint16_t)(~((uint16_t)(IRDA_MODE_TX_RX))))) == (uint16_t)0x00) && ((MODE) != (uint16_t)0x00)) + */ +#define IRDA_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ +#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ +#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ /** * @} */ -/** @defgroup IRDA_Low_Power IRDA Low Power +/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode * @{ */ -#define IRDA_POWERMODE_NORMAL ((uint16_t)0x0000) -#define IRDA_POWERMODE_LOWPOWER ((uint16_t)USART_CR3_IRLP) -#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ - ((MODE) == IRDA_POWERMODE_NORMAL)) +#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */ +#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */ +#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */ /** * @} */ - - /** @defgroup IRDA_State IRDA State + +/** @defgroup IRDA_Low_Power IRDA Low Power * @{ - */ -#define IRDA_STATE_DISABLE ((uint16_t)0x0000) -#define IRDA_STATE_ENABLE ((uint16_t)USART_CR1_UE) -#define IS_IRDA_STATE(STATE) (((STATE) == IRDA_STATE_DISABLE) || \ - ((STATE) == IRDA_STATE_ENABLE)) + */ +#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) /*!< IRDA normal power mode */ +#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */ +/** + * @} + */ + + /** @defgroup IRDA_State IRDA State + * @{ + */ +#define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */ +#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */ /** * @} */ /** @defgroup IRDA_Mode IRDA Mode * @{ - */ -#define IRDA_MODE_DISABLE ((uint16_t)0x0000) -#define IRDA_MODE_ENABLE ((uint16_t)USART_CR3_IREN) -#define IS_IRDA_MODE(STATE) (((STATE) == IRDA_MODE_DISABLE) || \ - ((STATE) == IRDA_MODE_ENABLE)) + */ +#define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */ +#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */ /** * @} */ @@ -251,58 +240,62 @@ typedef enum /** @defgroup IRDA_One_Bit IRDA One Bit Sampling * @{ */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED ((uint16_t)0x00000000) -#define IRDA_ONE_BIT_SAMPLE_ENABLED ((uint16_t)USART_CR3_ONEBIT) -#define IS_IRDA_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLED) || \ - ((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLED)) +#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disabled */ +#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */ /** * @} - */ - + */ + /** @defgroup IRDA_DMA_Tx IRDA DMA Tx * @{ */ -#define IRDA_DMA_TX_DISABLE ((uint16_t)0x00000000) -#define IRDA_DMA_TX_ENABLE ((uint16_t)USART_CR3_DMAT) -#define IS_IRDA_DMA_TX(DMATX) (((DMATX) == IRDA_DMA_TX_DISABLE) || \ - ((DMATX) == IRDA_DMA_TX_ENABLE)) +#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA TX disabled */ +#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */ /** * @} - */ - + */ + /** @defgroup IRDA_DMA_Rx IRDA DMA Rx * @{ */ -#define IRDA_DMA_RX_DISABLE ((uint16_t)0x0000) -#define IRDA_DMA_RX_ENABLE ((uint16_t)USART_CR3_DMAR) -#define IS_IRDA_DMA_RX(DMARX) (((DMARX) == IRDA_DMA_RX_DISABLE) || \ - ((DMARX) == IRDA_DMA_RX_ENABLE)) +#define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA RX disabled */ +#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */ /** * @} */ - + +/** @defgroup IRDA_Request_Parameters IRDA Request Parameters + * @{ + */ +#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ +#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ +#define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +/** + * @} + */ + /** @defgroup IRDA_Flags IRDA Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define IRDA_FLAG_REACK ((uint32_t)0x00400000) -#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) -#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) -#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) -#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) -#define IRDA_FLAG_TXE ((uint32_t)0x00000080) -#define IRDA_FLAG_TC ((uint32_t)0x00000040) -#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) -#define IRDA_FLAG_ORE ((uint32_t)0x00000008) -#define IRDA_FLAG_NE ((uint32_t)0x00000004) -#define IRDA_FLAG_FE ((uint32_t)0x00000002) -#define IRDA_FLAG_PE ((uint32_t)0x00000001) +#define IRDA_FLAG_REACK ((uint32_t)0x00400000) /*!< IRDA Receive enable acknowledge flag */ +#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) /*!< IRDA Transmit enable acknowledge flag */ +#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) /*!< IRDA Busy flag */ +#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) /*!< IRDA Auto baud rate flag */ +#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) /*!< IRDA Auto baud rate error */ +#define IRDA_FLAG_TXE ((uint32_t)0x00000080) /*!< IRDA Transmit data register empty */ +#define IRDA_FLAG_TC ((uint32_t)0x00000040) /*!< IRDA Transmission complete */ +#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) /*!< IRDA Read data register not empty */ +#define IRDA_FLAG_ORE ((uint32_t)0x00000008) /*!< IRDA Overrun error */ +#define IRDA_FLAG_NE ((uint32_t)0x00000004) /*!< IRDA Noise error */ +#define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Noise error */ +#define IRDA_FLAG_PE ((uint32_t)0x00000001) /*!< IRDA Parity error */ /** * @} - */ + */ -/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definition +/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition * Elements values convention: 0000ZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) @@ -310,16 +303,14 @@ typedef enum * - 10: CR2 register * - 11: CR3 register * - ZZZZ : Flag position in the ISR register(4bits) - * @{ - */ -#define IRDA_IT_PE ((uint16_t)0x0028) -#define IRDA_IT_TXE ((uint16_t)0x0727) -#define IRDA_IT_TC ((uint16_t)0x0626) -#define IRDA_IT_RXNE ((uint16_t)0x0525) -#define IRDA_IT_IDLE ((uint16_t)0x0424) + * @{ + */ +#define IRDA_IT_PE ((uint16_t)0x0028) /*!< IRDA Parity error interruption */ +#define IRDA_IT_TXE ((uint16_t)0x0727) /*!< IRDA Transmit data register empty interruption */ +#define IRDA_IT_TC ((uint16_t)0x0626) /*!< IRDA Transmission complete interruption */ +#define IRDA_IT_RXNE ((uint16_t)0x0525) /*!< IRDA Read data register not empty interruption */ +#define IRDA_IT_IDLE ((uint16_t)0x0424) /*!< IRDA Idle interruption */ - - /** Elements values convention: 000000000XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) @@ -327,18 +318,18 @@ typedef enum * - 10: CR2 register * - 11: CR3 register */ -#define IRDA_IT_ERR ((uint16_t)0x0060) +#define IRDA_IT_ERR ((uint16_t)0x0060) /*!< IRDA Error interruption */ /** Elements values convention: 0000ZZZZ00000000b * - ZZZZ : Flag position in the ISR register(4bits) */ -#define IRDA_IT_ORE ((uint16_t)0x0300) -#define IRDA_IT_NE ((uint16_t)0x0200) -#define IRDA_IT_FE ((uint16_t)0x0100) +#define IRDA_IT_ORE ((uint16_t)0x0300) /*!< IRDA Overrun error interruption */ +#define IRDA_IT_NE ((uint16_t)0x0200) /*!< IRDA Noise error interruption */ +#define IRDA_IT_FE ((uint16_t)0x0100) /*!< IRDA Frame error interruption */ /** * @} */ - + /** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags * @{ */ @@ -349,54 +340,96 @@ typedef enum #define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ /** * @} - */ + */ - - -/** @defgroup IRDA_Request_Parameters IRDA Request Parameters +/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask * @{ */ -#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ -#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ -#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \ - ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \ - ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST)) +#define IRDA_IT_MASK ((uint16_t)0x001F) /*!< IRDA Interruptions flags mask */ /** * @} */ - -/** @defgroup IRDA_Interruption_Mask IRDA interruptions flag mask - * @{ - */ -#define IRDA_IT_MASK ((uint16_t)0x001F) -/** - * @} - */ - + /** * @} */ -/* Exported macro ------------------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ /** @defgroup IRDA_Exported_Macros IRDA Exported Macros * @{ */ - -/** @brief Reset IRDA handle state + +/** @brief Reset IRDA handle state. * @param __HANDLE__: IRDA handle. * @retval None */ #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) -/** @brief Checks whether the specified IRDA flag is set or not. +/** @brief Flush the IRDA DR register. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ + } while(0) + + +/** @brief Clear the specified IRDA pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg IRDA_CLEAR_PEF + * @arg IRDA_CLEAR_FEF + * @arg IRDA_CLEAR_NEF + * @arg IRDA_CLEAR_OREF + * @arg IRDA_CLEAR_TCF + * @arg IRDA_CLEAR_IDLEF + * @retval None + */ +#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the IRDA PE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) + + +/** @brief Clear the IRDA FE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) + +/** @brief Clear the IRDA NE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) + +/** @brief Clear the IRDA ORE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) + +/** @brief Clear the IRDA IDLE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) + +/** @brief Check whether the specified IRDA flag is set or not. * @param __HANDLE__: specifies the IRDA Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or * UART peripheral * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg IRDA_FLAG_REACK: Receive enable ackowledge flag - * @arg IRDA_FLAG_TEACK: Transmit enable ackowledge flag + * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag + * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag * @arg IRDA_FLAG_BUSY: Busy flag * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag @@ -410,9 +443,10 @@ typedef enum * @arg IRDA_FLAG_PE: Parity Error flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) -/** @brief Enables the specified IRDA interrupt. + +/** @brief Enable the specified IRDA interrupt. * @param __HANDLE__: specifies the IRDA Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or * UART peripheral @@ -430,7 +464,7 @@ typedef enum ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) -/** @brief Disables the specified IRDA interrupt. +/** @brief Disable the specified IRDA interrupt. * @param __HANDLE__: specifies the IRDA Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or * UART peripheral @@ -447,9 +481,9 @@ typedef enum #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) - - -/** @brief Checks whether the specified IRDA interrupt has occurred or not. + + +/** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__: specifies the IRDA Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or * UART peripheral @@ -462,12 +496,12 @@ typedef enum * @arg IRDA_IT_ORE: OverRun Error interrupt * @arg IRDA_IT_NE: Noise Error interrupt * @arg IRDA_IT_FE: Framing Error interrupt - * @arg IRDA_IT_PE: Parity Error interrupt + * @arg IRDA_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08))) +#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08))) -/** @brief Checks whether the specified IRDA interrupt source is enabled. +/** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__: specifies the IRDA Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or * UART peripheral @@ -480,28 +514,28 @@ typedef enum * @arg IRDA_IT_ORE: OverRun Error interrupt * @arg IRDA_IT_NE: Noise Error interrupt * @arg IRDA_IT_FE: Framing Error interrupt - * @arg IRDA_IT_PE: Parity Error interrupt + * @arg IRDA_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) -/** @brief Clears the specified IRDA ISR flag, in setting the proper ICR register flag. +/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__: specifies the IRDA Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or * UART peripheral * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: - * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag - * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag - * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag - * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag - * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag + * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag + * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag + * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag + * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag + * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag * @retval None */ -#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) +#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific IRDA request flag. @@ -510,25 +544,39 @@ typedef enum * UART peripheral * @param __REQ__: specifies the request flag to set * This parameter can be one of the following values: - * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request - * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request - * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request + * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request + * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request * * @retval None - */ -#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + */ +#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) +/** @brief Enable the IRDA one bit sample method. + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) +/** @brief Disable the IRDA one bit sample method. + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or + * UART peripheral + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) -/** @brief Enable UART/USART associated to IRDA Handle +/** @brief Enable UART/USART associated to IRDA Handle. * @param __HANDLE__: specifies the IRDA Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or * UART peripheral * @retval None - */ + */ #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) -/** @brief Disable UART/USART associated to IRDA Handle +/** @brief Disable UART/USART associated to IRDA Handle. * @param __HANDLE__: specifies the IRDA Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or * UART peripheral @@ -536,32 +584,112 @@ typedef enum */ #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) -/** @brief Ensure that IRDA Baud rate is less or equal to maximum value +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup IRDA_Private_Macros IRDA Private Macros + * @{ + */ + +/** @brief Ensure that IRDA Baud rate is less or equal to maximum value. * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. * @retval True or False - */ + */ #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) -/** @brief Ensure that IRDA prescaler value is strictly larger than 0 +/** @brief Ensure that IRDA prescaler value is strictly larger than 0. * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. * @retval True or False - */ -#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) + */ +#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) +/** + * @brief Ensure that IRDA frame parity is valid. + * @param __PARITY__: IRDA frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ + ((__PARITY__) == IRDA_PARITY_EVEN) || \ + ((__PARITY__) == IRDA_PARITY_ODD)) + +/** + * @brief Ensure that IRDA communication mode is valid. + * @param __MODE__: IRDA communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) + +/** + * @brief Ensure that IRDA power mode is valid. + * @param __MODE__: IRDA power mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ + ((__MODE__) == IRDA_POWERMODE_NORMAL)) + +/** + * @brief Ensure that IRDA state is valid. + * @param __STATE__: IRDA state mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ + ((__STATE__) == IRDA_STATE_ENABLE)) + +/** + * @brief Ensure that IRDA associated UART/USART mode is valid. + * @param __MODE__: IRDA associated UART/USART mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ + ((__MODE__) == IRDA_MODE_ENABLE)) + +/** + * @brief Ensure that IRDA sampling rate is valid. + * @param __ONEBIT__: IRDA sampling rate. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that IRDA DMA TX mode is valid. + * @param __DMATX__: IRDA DMA TX mode. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ + ((__DMATX__) == IRDA_DMA_TX_ENABLE)) + +/** + * @brief Ensure that IRDA DMA RX mode is valid. + * @param __DMARX__: IRDA DMA RX mode. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ + ((__DMARX__) == IRDA_DMA_RX_ENABLE)) + +/** + * @brief Ensure that IRDA request is valid. + * @param __PARAM__: IRDA request. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) /** * @} */ /* Include IRDA HAL Extended module */ -#include "stm32f0xx_hal_irda_ex.h" +#include "stm32f0xx_hal_irda_ex.h" /* Exported functions --------------------------------------------------------*/ - /** @addtogroup IRDA_Exported_Functions IRDA Exported Functions * @{ */ - -/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -575,7 +703,7 @@ void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); * @} */ -/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions +/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions * @{ */ @@ -586,41 +714,48 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); /** * @} */ -/** @addtogroup IRDA_Exported_Functions_Group3 +/* Peripheral Control functions ************************************************/ + +/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} */ #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ - + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h index 56cffaafed..700c6b902c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of IRDA HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -52,9 +52,9 @@ * @{ */ -/** @addtogroup IRDAEx IRDAEx Extended HAL module driver +/** @addtogroup IRDAEx IRDAEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -68,43 +68,40 @@ #if defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined (STM32F098xx) -#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) -#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) -#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) -#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \ - ((LENGTH) == IRDA_WORDLENGTH_8B) || \ - ((LENGTH) == IRDA_WORDLENGTH_9B)) +#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */ +#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */ +#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */ #else -#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) -#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \ - ((LENGTH) == IRDA_WORDLENGTH_9B)) +#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */ +#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */ #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined (STM32F098xx)*/ /** * @} */ - - + /** * @} */ /* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ -/** @defgroup IRDAEx_Exported_Macros IRDAEx Exported Macros +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros * @{ */ - -/** @brief Reports the IRDA clock source. - * @param __HANDLE__: specifies the IRDA Handle - * @param __CLOCKSOURCE__ : output variable + +/** @brief Report the IRDA clock source. + * @param __HANDLE__: specifies the IRDA Handle. + * @param __CLOCKSOURCE__: output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F031x6) || defined(STM32F038xx) -#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ switch(__HAL_RCC_GET_USART1_SOURCE()) \ { \ @@ -127,7 +124,7 @@ } while(0) #elif defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F051x8) || defined (STM32F058xx) -#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -160,7 +157,7 @@ } \ } while(0) #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) -#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -218,7 +215,7 @@ } \ } while(0) #elif defined(STM32F091xC) || defined(STM32F098xx) -#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -308,19 +305,23 @@ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0) - + #endif /* defined(STM32F031x6) || defined(STM32F038xx) */ - - -/** @brief Computes the mask to apply to retrieve the received data + + +/** @brief Compute the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. * @param __HANDLE__: specifies the IRDA Handle - * @retval none + * @retval None, the mask to apply to IRDA RDR register is stored in (__HANDLE__)->Mask field. */ #if defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined (STM32F098xx) -#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \ +#define IRDA_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ { \ @@ -357,7 +358,7 @@ } \ } while(0) #else -#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \ +#define IRDA_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ { \ @@ -385,23 +386,38 @@ #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined(STM32F098xx) */ + +/** + * @brief Ensure that IRDA frame length is valid. + * @param __LENGTH__: IRDA frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) +#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_9B)) +#else +#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_9B)) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx)*/ + /** * @} */ - + /* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions ****************************/ -/* IO operation functions *****************************************************/ -/* Peripheral Control functions ***********************************************/ -/* Peripheral State and Error functions ***************************************/ /** * @} - */ + */ /** * @} - */ + */ #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c index d8ade7223c..d0aac3a339 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_iwdg.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: @@ -69,15 +69,15 @@ (+) __HAL_IWDG_START: Enable the IWDG peripheral (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register - (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers - (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers + (+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers + (+) IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -101,8 +101,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -111,7 +111,7 @@ * @{ */ -/** @defgroup IWDG IWDG HAL module driver +/** @defgroup IWDG IWDG * @brief IWDG HAL module driver. * @{ */ @@ -120,7 +120,6 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ - /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ @@ -130,43 +129,42 @@ /** * @} */ - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup IWDG_Exported_Functions IWDG Exported Functions * @{ */ /** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. + * @brief Initialization and Configuration functions. * -@verbatim +@verbatim =============================================================================== - ##### Initialization functions ##### + ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize the IWDG according to the specified parameters + (+) Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and create the associated handle (+) Manage Window option (+) Initialize the IWDG MSP - (+) DeInitialize IWDG MSP - + (+) DeInitialize the IWDG MSP + @endverbatim * @{ */ /** - * @brief Initializes the IWDG according to the specified - * parameters in the IWDG_InitTypeDef and creates the associated handle. + * @brief Initialize the IWDG according to the specified + * parameters in the IWDG_InitTypeDef and initialize the associated handle. * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) -{ +{ uint32_t tickstart = 0; /* Check the IWDG handle allocation */ @@ -174,7 +172,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); @@ -188,24 +186,27 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { return HAL_ERROR; } - + if(hiwdg->State == HAL_IWDG_STATE_RESET) - { - /* Init the low level hardware */ - HAL_IWDG_MspInit(hiwdg); + { + /* Allocate lock resource and initialize it */ + hiwdg->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_IWDG_MspInit(hiwdg); } /* Change IWDG peripheral state */ hiwdg->State = HAL_IWDG_STATE_BUSY; - /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */ - /* by writing 0x5555 in KR */ - __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg); - + /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */ + /* by writing 0x5555 in KR */ + IWDG_ENABLE_WRITE_ACCESS(hiwdg); + /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler); MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload); - + /* check if window option is enabled */ if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE)) { @@ -214,34 +215,34 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /* Wait for register to be updated */ while((uint32_t)(hiwdg->Instance->SR) != RESET) { - if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) - { + if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) + { /* Set IWDG state */ hiwdg->State = HAL_IWDG_STATE_TIMEOUT; return HAL_TIMEOUT; - } + } } /* Write to IWDG WINR the IWDG_Window value to compare with */ MODIFY_REG(hiwdg->Instance->WINR, IWDG_WINR_WIN, hiwdg->Init.Window); + } - } /* Change IWDG peripheral state */ hiwdg->State = HAL_IWDG_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief Initializes the IWDG MSP. + * @brief Initialize the IWDG MSP. * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval None */ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_IWDG_MspInit could be implemented in the user file */ } @@ -253,10 +254,10 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Start the IWDG. (+) Refresh the IWDG. @@ -266,82 +267,83 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) */ /** - * @brief Starts the IWDG. + * @brief Start the IWDG. * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) -{ +{ uint32_t tickstart = 0; - /* Process Locked */ + /* Process locked */ __HAL_LOCK(hiwdg); - - /* Change IWDG peripheral state */ + + /* Change IWDG peripheral state */ hiwdg->State = HAL_IWDG_STATE_BUSY; - + /* Reload IWDG counter with value defined in the RLR register */ if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE) { - __HAL_IWDG_RELOAD_COUNTER(hiwdg); + __HAL_IWDG_RELOAD_COUNTER(hiwdg); } - /* Enable the IWDG peripheral */ + /* Start the IWDG peripheral */ __HAL_IWDG_START(hiwdg); tickstart = HAL_GetTick(); /* Wait until PVU, RVU, WVU flag are RESET */ while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) ) + &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) + &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) ) { - if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) - { + + if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) + { /* Set IWDG state */ hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - - /* Process unlocked */ + + /* Process unlocked */ __HAL_UNLOCK(hiwdg); - + return HAL_TIMEOUT; - } + } } - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hiwdg); - + /* Return function status */ return HAL_OK; } /** - * @brief Refreshes the IWDG. + * @brief Refresh the IWDG. * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) - { +{ uint32_t tickstart = 0; /* Process Locked */ - __HAL_LOCK(hiwdg); - - /* Change IWDG peripheral state */ + __HAL_LOCK(hiwdg); + + /* Change IWDG peripheral state */ hiwdg->State = HAL_IWDG_STATE_BUSY; - + tickstart = HAL_GetTick(); /* Wait until RVU flag is RESET */ while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) { - if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) - { + if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) + { /* Set IWDG state */ hiwdg->State = HAL_IWDG_STATE_TIMEOUT; @@ -349,18 +351,18 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) __HAL_UNLOCK(hiwdg); return HAL_TIMEOUT; - } + } } /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - + + /* Change IWDG peripheral state */ + hiwdg->State = HAL_IWDG_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hiwdg); - + /* Return function status */ return HAL_OK; } @@ -370,28 +372,28 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) */ /** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. + * @brief Peripheral State functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. + This subsection permits to get in run-time the status of the peripheral. @endverbatim * @{ */ /** - * @brief Returns the IWDG state. + * @brief Return the IWDG handle state. * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL state */ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) { + /* Return IWDG handle state */ return hiwdg->State; } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h index 0607b4122a..dd508dedeb 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_iwdg.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -52,55 +52,54 @@ /** @addtogroup IWDG * @{ - */ - -/* Exported types ------------------------------------------------------------*/ + */ +/* Exported types ------------------------------------------------------------*/ /** @defgroup IWDG_Exported_Types IWDG Exported Types * @{ */ /** - * @brief IWDG HAL State Structure definition - */ + * @brief IWDG HAL State Structure definition + */ typedef enum { - HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */ - HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */ - HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */ - HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */ - HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ + HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */ + HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */ + HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */ + HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */ + HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ }HAL_IWDG_StateTypeDef; /** - * @brief IWDG Init structure definition + * @brief IWDG Init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Select the prescaler of the IWDG. - This parameter can be a value of @ref IWDG_Prescaler */ - - uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ - - uint32_t Window; /*!< Specifies the window value to be compared to the down-counter. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + uint32_t Prescaler; /*!< Select the prescaler of the IWDG. + This parameter can be a value of @ref IWDG_Prescaler */ + + uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t Window; /*!< Specifies the window value to be compared to the down-counter. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ } IWDG_InitTypeDef; /** * @brief IWDG Handle Structure definition - */ + */ typedef struct { - IWDG_TypeDef *Instance; /*!< Register base address */ - - IWDG_InitTypeDef Init; /*!< IWDG required parameters */ - - HAL_LockTypeDef Lock; /*!< IWDG Locking object */ - - __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */ + IWDG_TypeDef *Instance; /*!< Register base address */ + + IWDG_InitTypeDef Init; /*!< IWDG required parameters */ + + HAL_LockTypeDef Lock; /*!< IWDG Locking object */ + + __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */ }IWDG_HandleTypeDef; @@ -109,134 +108,63 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup IWDG_Exported_Constants IWDG Exported Constants * @{ */ -/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask - * @brief IWDG registers bit mask - * @{ - */ -/* --- KR Register ---*/ -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */ -#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */ -#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */ -#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */ - -#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \ - ((__KR__) == KR_KEY_ENABLE))|| \ - ((__KR__) == KR_KEY_EWA)) || \ - ((__KR__) == KR_KEY_DWA)) -/** - * @} - */ - -/** @defgroup IWDG_Flag_definition IWDG Flag definition - * @{ - */ -#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */ -#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */ -#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update Flag */ - -/** - * @} - */ - /** @defgroup IWDG_Prescaler IWDG Prescaler * @{ - */ -#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ -#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ -#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ -#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ -#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ - -#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ - ((__PRESCALER__) == IWDG_PRESCALER_8) || \ - ((__PRESCALER__) == IWDG_PRESCALER_16) || \ - ((__PRESCALER__) == IWDG_PRESCALER_32) || \ - ((__PRESCALER__) == IWDG_PRESCALER_64) || \ - ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ - ((__PRESCALER__) == IWDG_PRESCALER_256)) - + */ +#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ /** * @} */ -/** @defgroup IWDG_Reload_Value IWDG Reload Value - * @{ - */ -#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) -/** - * @} - */ - -/** @defgroup IWDG_CounterWindow_Value IWDG CounterWindow Value +/** @defgroup IWDG_Window IWDG Window * @{ */ -#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFF) +#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF) /** * @} - */ -/** @defgroup IWDG_Window_option IWDG Window option - * @{ */ -#define IWDG_WINDOW_DISABLE 0xFFF -/** - * @} - */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ - /** @defgroup IWDG_Exported_Macros IWDG Exported Macros - * @{ - */ + * @{ + */ -/** @brief Reset IWDG handle state +/** @brief Reset IWDG handle state. * @param __HANDLE__: IWDG handle. * @retval None */ -#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) +#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) /** - * @brief Enables the IWDG peripheral. + * @brief Enable the IWDG peripheral. * @param __HANDLE__: IWDG handle * @retval None */ -#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE) +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) /** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @brief Reload IWDG counter with value defined in the reload register. * @param __HANDLE__: IWDG handle * @retval None */ -#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD) +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) /** - * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle - * @retval None - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA) - -/** - * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle - * @retval None - */ -#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA) - -/** - * @brief Gets the selected IWDG's flag status. + * @brief Get the selected IWDG flag status. * @param __HANDLE__: IWDG handle * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: @@ -245,14 +173,13 @@ typedef struct * @arg IWDG_FLAG_WVU: Watchdog counter window value flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) +#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** * @} */ /* Exported functions --------------------------------------------------------*/ - /** @addtogroup IWDG_Exported_Functions * @{ */ @@ -262,45 +189,115 @@ typedef struct */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); -void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); - +void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); /** * @} */ - + /** @addtogroup IWDG_Exported_Functions_Group2 * @{ */ /* I/O operation functions ****************************************************/ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg); HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); - /** * @} */ - + /** @addtogroup IWDG_Exported_Functions_Group3 * @{ */ /* Peripheral State functions ************************************************/ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); +/** + * @} + */ /** * @} - */ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup IWDG_Private_Defines + * @{ + */ +/** + * @brief IWDG Key Register BitMask + */ +#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */ + +/** + * @brief IWDG Flag definition + */ +#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */ +#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */ +#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update flag */ /** * @} - */ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Macro IWDG Private Macros + * @{ + */ +/** + * @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) + +/** + * @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) + +/** + * @brief Check IWDG prescaler value. + * @param __PRESCALER__: IWDG prescaler value + * @retval None + */ +#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ + ((__PRESCALER__) == IWDG_PRESCALER_8) || \ + ((__PRESCALER__) == IWDG_PRESCALER_16) || \ + ((__PRESCALER__) == IWDG_PRESCALER_32) || \ + ((__PRESCALER__) == IWDG_PRESCALER_64) || \ + ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_256)) + +/** + * @brief Check IWDG reload value. + * @param __RELOAD__: IWDG reload value + * @retval None + */ +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) + +/** + * @brief Check IWDG window value. + * @param __WINDOW__: IWDG window value + * @retval None + */ +#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF) /** * @} - */ + */ /** * @} - */ - + */ + +/** + * @} + */ + + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c index ecec1e265b..1c6622ca5d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -28,7 +28,7 @@ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using - (+++) __USB_CLK_ENABLE); + (+++) __HAL_RCC_USB_CLK_ENABLE); (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -44,7 +44,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,15 +74,15 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) - /** @addtogroup STM32F0xx_HAL_Driver * @{ */ -/** @defgroup PCD PCD HAL module driver +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) + +/** @defgroup PCD PCD * @brief PCD HAL module driver * @{ */ @@ -110,8 +110,8 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui /** * @} */ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup PCD_Exported_Functions PCD Exported Functions * @{ */ @@ -150,11 +150,17 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - hpcd->State = PCD_BUSY; + if(hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); + } + hpcd->State = HAL_PCD_STATE_BUSY; + /* Init endpoints structures */ for (i = 0; i < hpcd->Init.dev_endpoints ; i++) { @@ -200,7 +206,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->Instance->CNTR = wInterrupt_Mask; hpcd->USB_Address = 0; - hpcd->State= PCD_READY; + hpcd->State= HAL_PCD_STATE_READY; return HAL_OK; } @@ -218,7 +224,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) return HAL_ERROR; } - hpcd->State = PCD_BUSY; + hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ HAL_PCD_Stop(hpcd); @@ -226,7 +232,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) /* DeInit the low level hardware */ HAL_PCD_MspDeInit(hpcd); - hpcd->State = PCD_READY; + hpcd->State = HAL_PCD_STATE_RESET; return HAL_OK; } @@ -275,7 +281,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) */ /** - * @brief Start The USB OTG Device. + * @brief Start the USB device. * @param hpcd: PCD handle * @retval HAL status */ @@ -288,7 +294,7 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) } /** - * @brief Stop The USB OTG Device. + * @brief Stop the USB device. * @param hpcd: PCD handle * @retval HAL status */ @@ -308,234 +314,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) __HAL_UNLOCK(hpcd); return HAL_OK; } -/** - * @} - */ - -/** - * @} - */ -/** @addtogroup PCD_Private_Functions PCD Private Functions - * @{ - */ -/** - * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) -{ - PCD_EPTypeDef *ep; - uint16_t count=0; - uint8_t EPindex; - __IO uint16_t wIstr; - __IO uint16_t wEPVal = 0; - - /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) - { - /* extract highest priority endpoint number */ - EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - - if (EPindex == 0) - { - /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0) - { - /* DIR = 0 */ - - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); - ep = &hpcd->IN_ep[0]; - - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff += ep->xfer_count; - - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); - - - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) - { - hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; - } - - } - else - { - /* DIR = 1 */ - - /* DIR = 1 & CTR_RX => SETUP or OUT int */ - /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ - ep = &hpcd->OUT_ep[0]; - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if ((wEPVal & USB_EP_SETUP) != 0) - { - /* Get SETUP Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - - /* Process SETUP Packet*/ - HAL_PCD_SetupStageCallback(hpcd); - } - - else if ((wEPVal & USB_EP_CTR_RX) != 0) - { - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - /* Get Control Data OUT Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - ep->xfer_buff+=ep->xfer_count; - } - - /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); - - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); - } - } - } - else - { - - /* Decode and service non control endpoints interrupt */ - - /* process related endpoint register */ - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) - { - /* clear int flag */ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); - ep = &hpcd->OUT_ep[EPindex]; - - /* OUT double Buffering*/ - if (ep->doublebuffer == 0) - { - count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) - { - /*read from endpoint BUF0Addr buffer*/ - count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); - } - /*multi-packet on the NON control OUT endpoint*/ - ep->xfer_count+=count; - ep->xfer_buff+=count; - - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) - { - /* RX COMPLETE */ - HAL_PCD_DataOutStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - - } /* if((wEPVal & EP_CTR_RX) */ - - if ((wEPVal & USB_EP_CTR_TX) != 0) - { - ep = &hpcd->IN_ep[EPindex]; - - /* clear int flag */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); - - /* IN double Buffering*/ - if (ep->doublebuffer == 0) - { - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) - { - /*read from endpoint BUF0Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); - } - /*multi-packet on the NON control IN endpoint*/ - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff+=ep->xfer_count; - - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - } - } - } - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup PCD_Exported_Functions - * @{ - */ - -/** @defgroup PCD_Exported_Functions_Group2 IO operation functions - * @{ - */ - /** * @brief This function handles PCD interrupt request. * @param hpcd: PCD handle @@ -641,7 +420,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /** * @brief Setup stage callback - * @param hpcd: ppp handle + * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) @@ -739,7 +518,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Disconnection event callbacks - * @param hpcd: ppp handle + * @param hpcd: PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) @@ -851,7 +630,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint __HAL_LOCK(hpcd); -/* initialize Endpoint */ + /* initialize Endpoint */ switch (ep->type) { case PCD_EP_TYPE_CTRL: @@ -1108,18 +887,20 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } else { - /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); - /*Write the data to the USB endpoint*/ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) { + /*Set the Double buffer counter for pmabuffer1*/ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr1; } else { + /*Set the Double buffer counter for pmabuffer0*/ + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr0; } + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len); PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in); } @@ -1229,22 +1010,22 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** - * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling + * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling * @param hpcd: PCD handle - * @retval status + * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { hpcd->Instance->CNTR |= USB_CNTR_RESUME; return HAL_OK; } /** - * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling + * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling * @param hpcd: PCD handle - * @retval status + * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME); return HAL_OK; @@ -1253,9 +1034,37 @@ HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) * @} */ +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD state + * @param hpcd : PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +{ + return hpcd->State; +} /** * @} - */ + */ + +/** + * @} + */ /** @addtogroup PCD_Private_Functions * @{ @@ -1306,46 +1115,212 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui pbUsrBuf++; } } -/** - * @} - */ - -/** @addtogroup PCD_Exported_Functions - * @{ - */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ /** - * @brief Return the PCD state - * @param hpcd : PCD handle - * @retval HAL state + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd: PCD handle + * @retval HAL status */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { - return hpcd->State; -} -/** - * @} - */ + PCD_EPTypeDef *ep; + uint16_t count=0; + uint8_t EPindex; + __IO uint16_t wIstr; + __IO uint16_t wEPVal = 0; -/** - * @} - */ - + /* stay in loop while pending interrupts */ + while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) + { + /* extract highest priority endpoint number */ + EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (EPindex == 0) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + ep = &hpcd->IN_ep[0]; + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, 0); + + + if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) + { + hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0; + } + + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if ((wEPVal & USB_EP_SETUP) != 0) + { + /* Get SETUP Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); + /* SETUP bit kept frozen while CTR_RX = 1*/ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Process SETUP Packet*/ + HAL_PCD_SetupStageCallback(hpcd); + } + + else if ((wEPVal & USB_EP_CTR_RX) != 0) + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + /* Get Control Data OUT Packet*/ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + ep->xfer_buff+=ep->xfer_count; + } + + /* Process Control Data OUT Packet*/ + HAL_PCD_DataOutStageCallback(hpcd, 0); + + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + } + } + else + { + + /* Decode and service non control endpoints interrupt */ + + /* process related endpoint register */ + wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex); + if ((wEPVal & USB_EP_CTR_RX) != 0) + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex); + ep = &hpcd->OUT_ep[EPindex]; + + /* OUT double Buffering*/ + if (ep->doublebuffer == 0) + { + count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + } + } + else + { + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) + { + /*read from endpoint BUF0Addr buffer*/ + count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (count != 0) + { + PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); + } + /*multi-packet on the NON control OUT endpoint*/ + ep->xfer_count+=count; + ep->xfer_buff+=count; + + if ((ep->xfer_len == 0) || (count < ep->maxpacket)) + { + /* RX COMPLETE */ + HAL_PCD_DataOutStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + + } /* if((wEPVal & EP_CTR_RX) */ + + if ((wEPVal & USB_EP_CTR_TX) != 0) + { + ep = &hpcd->IN_ep[EPindex]; + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); + + /* IN double Buffering*/ + if (ep->doublebuffer == 0) + { + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); + } + } + else + { + if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) + { + /*read from endpoint BUF0Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); + } + } + else + { + /*read from endpoint BUF1Addr buffer*/ + ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 0) + { + PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); + } + } + PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); + } + /*multi-packet on the NON control IN endpoint*/ + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff+=ep->xfer_count; + + /* Zero Length Packet? */ + if (ep->xfer_len == 0) + { + /* TX COMPLETE */ + HAL_PCD_DataInStageCallback(hpcd, ep->num); + } + else + { + HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + } + } + } + } + return HAL_OK; +} /** * @} */ @@ -1357,4 +1332,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) #endif /* HAL_PCD_MODULE_ENABLED */ +/** + * @} + */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h index 47fc4318a3..895bcd3f99 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -62,25 +62,30 @@ */ /** - * @brief PCD State structures definition + * @brief PCD State structure definition */ typedef enum { - PCD_READY = 0x00, - PCD_ERROR = 0x01, - PCD_BUSY = 0x02, - PCD_TIMEOUT = 0x03 + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 } PCD_StateTypeDef; +/** + * @brief PCD double buffered endpoint direction + */ typedef enum { - /* double buffered endpoint direction */ PCD_EP_DBUF_OUT, PCD_EP_DBUF_IN, PCD_EP_DBUF_ERR, }PCD_EP_DBUF_DIR; -/* endpoint buffer number */ +/** + * @brief PCD endpoint buffer number + */ typedef enum { PCD_EP_NOBUF, @@ -93,31 +98,31 @@ typedef enum */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Core_Speed */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref PCD_EP0_MPS */ - - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_Core_PHY */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. - This parameter can be set to ENABLE or DISABLE */ - - uint32_t low_power_enable; /*!< Enable or disable Low Power mode - This parameter can be set to ENABLE or DISABLE */ - - uint32_t lpm_enable; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. - This parameter can be set to ENABLE or DISABLE */ - + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Core_Speed */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. + This parameter can be any value of @ref PCD_EP0_MPS */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_Core_PHY */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t low_power_enable; /*!< Enable or disable Low Power mode + This parameter can be set to ENABLE or DISABLE */ + + uint32_t lpm_enable; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + }PCD_InitTypeDef; typedef struct @@ -136,16 +141,13 @@ typedef struct uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - + uint16_t pmaaddr0; /*!< PMA Address0 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - + uint16_t pmaaddr1; /*!< PMA Address1 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - + uint8_t doublebuffer; /*!< Double buffer enable This parameter can be 0 or 1 */ @@ -153,7 +155,6 @@ typedef struct This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - uint32_t xfer_len; /*!< Current transfer length */ @@ -168,15 +169,15 @@ typedef USB_TypeDef PCD_TypeDef; */ typedef struct { - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - void *pData; /*!< Pointer to upper stack Handler */ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + void *pData; /*!< Pointer to upper stack Handler */ } PCD_HandleTypeDef; @@ -184,7 +185,9 @@ typedef struct * @} */ -#include "stm32f0xx_hal_pcd_ex.h" +/* Include PCD HAL Extension module */ +#include "stm32f0xx_hal_pcd_ex.h" + /* Exported constants --------------------------------------------------------*/ /** @defgroup PCD_Exported_Constants PCD Exported Constants * @{ @@ -203,6 +206,112 @@ typedef struct * @{ */ #define PCD_PHY_EMBEDDED 2 +/** + * @} + */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) + +#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE +#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) +#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ /** * @} */ @@ -226,63 +335,44 @@ typedef struct /** @defgroup PCD_EP_Type PCD EP Type * @{ */ -#define PCD_EP_TYPE_CTRL 0 -#define PCD_EP_TYPE_ISOC 1 -#define PCD_EP_TYPE_BULK 2 -#define PCD_EP_TYPE_INTR 3 +#define PCD_EP_TYPE_CTRL 0 +#define PCD_EP_TYPE_ISOC 1 +#define PCD_EP_TYPE_BULK 2 +#define PCD_EP_TYPE_INTR 3 /** * @} */ -/** @defgroup PCD_ENDP_Type PCD_ENDP_Type +/** @defgroup PCD_ENDP PCD ENDP * @{ */ - -#define PCD_ENDP0 ((uint8_t)0) -#define PCD_ENDP1 ((uint8_t)1) -#define PCD_ENDP2 ((uint8_t)2) -#define PCD_ENDP3 ((uint8_t)3) -#define PCD_ENDP4 ((uint8_t)4) -#define PCD_ENDP5 ((uint8_t)5) -#define PCD_ENDP6 ((uint8_t)6) -#define PCD_ENDP7 ((uint8_t)7) - -/* Endpoint Kind */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 - -#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE +#define PCD_ENDP0 ((uint8_t)0) +#define PCD_ENDP1 ((uint8_t)1) +#define PCD_ENDP2 ((uint8_t)2) +#define PCD_ENDP3 ((uint8_t)3) +#define PCD_ENDP4 ((uint8_t)4) +#define PCD_ENDP5 ((uint8_t)5) +#define PCD_ENDP6 ((uint8_t)6) +#define PCD_ENDP7 ((uint8_t)7) /** * @} - */ + */ -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations +/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind * @{ */ -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) - -#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ - -#define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP -#define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP) -#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) - +#define PCD_SNG_BUF 0 +#define PCD_DBL_BUF 1 /** * @} - */ + */ -/* Internal macros -----------------------------------------------------------*/ +/** + * @} + */ -/** @defgroup PCD_Private_Macros PCD Private Macros - * @brief macros to handle interrupts and specific clock configurations +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup PCD_Private_Macros PCD Private Macros * @{ */ @@ -662,7 +752,7 @@ typedef struct {PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\ else if((bDir) == PCD_EP_DBUF_IN)\ /* IN endpoint */\ - *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ + *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ } /* SetEPDblBuf1Count */ #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ @@ -679,81 +769,10 @@ typedef struct #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PCD_Exported_Functions +/** @defgroup PCD_Instance_definition PCD Instance definition * @{ */ - -/** @addtogroup PCD_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); - -/** - * @} - */ - -/** @addtogroup PCD_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ - /* Non Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); - -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); - -/** - * @} - */ - -/** @addtogroup PCD_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/** @addtogroup PCD_Exported_Functions_Group4 - * @{ - */ -/* Peripheral State functions **************************************************/ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c index b25c170dee..07d4b81228 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -42,36 +42,39 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) - /** @addtogroup STM32F0xx_HAL_Driver * @{ */ -/** @defgroup PCDEx PCDEx Extended HAL module driver - * @brief PCDEx PCDEx Extended HAL module driver +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) + +/** @defgroup PCDEx PCDEx + * @brief PCD Extended HAL module driver * @{ */ + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ - /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions * @{ */ -/** @defgroup PCDEx_Exported_Functions_Group2 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * +/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * @verbatim =============================================================================== - ##### Peripheral extended features methods ##### + ##### Extended Peripheral Control functions ##### =============================================================================== + [..] This section provides functions allowing to: + (+) Update PMA configuration + @endverbatim * @{ */ @@ -116,7 +119,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, { /*Single Buffer*/ ep->doublebuffer = 0; - /*Configure te PMA*/ + /*Configure the PMA*/ ep->pmaadress = (uint16_t)pmaadress; } else /*USB_DBL_BUF*/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h index 167070957d..5bf50a5040 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of PCD HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -61,15 +61,12 @@ /* Exported macros -----------------------------------------------------------*/ /* Internal macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PCDEx_Exported_Functions +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions * @{ */ - -/** @addtogroup PCDEx_Exported_Functions_Group2 +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ - */ - + */ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c index a651527631..4f48ee6d14 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -48,7 +48,7 @@ * @{ */ -/** @defgroup PWR PWR HAL module Driver +/** @defgroup PWR PWR * @brief PWR HAL module driver * @{ */ @@ -79,7 +79,7 @@ write accesses. To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() macro. + __HAL_RCC_PWR_CLK_ENABLE() macro. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. @endverbatim @@ -92,13 +92,13 @@ */ void HAL_PWR_DeInit(void) { - __PWR_FORCE_RESET(); - __PWR_RELEASE_RESET(); + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); } /** * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers). + * backup data registers when present). * @note If the HSE divided by 32 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None @@ -110,7 +110,7 @@ void HAL_PWR_EnableBkUpAccess(void) /** * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers). + * backup data registers when present). * @note If the HSE divided by 32 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h index 5725323644..a6069a706e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup PWR PWR HAL module Driver +/** @addtogroup PWR PWR * @{ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c index 55dd4a3831..41a241e10e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -47,7 +47,7 @@ * @{ */ -/** @defgroup PWREx PWREx Extended HAL module driver +/** @defgroup PWREx PWREx * @brief PWREx HAL module driver * @{ */ @@ -93,7 +93,7 @@ (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through - HAL_PWR_PVDConfig(), HAL_PWR_EnablePVD() functions. + HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions. (+) The PVD is stopped in Standby mode. -@- PVD is not available on STM32F030x4/x6/x8 @@ -104,7 +104,7 @@ to VREFInt Voltage (+) This monitor is internally connected to the EXTI line31 and can generate an interrupt if enabled. This is done through - HAL_PWR_EnableVddio2Monitor() function. + HAL_PWREx_EnableVddio2Monitor() function. -@- VDDIO2 is available on STM32F07x/09x/04x @endverbatim @@ -123,7 +123,7 @@ * detection level. * @retval None */ -void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); @@ -135,7 +135,7 @@ void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); /* Configure interrupt mode */ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) @@ -152,12 +152,12 @@ void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { - __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER(); + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { - __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER(); + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } } @@ -222,20 +222,20 @@ __weak void HAL_PWR_PVDCallback(void) NVIS has to be enable by user. * @retval None */ -void HAL_PWR_EnableVddio2Monitor(void) +void HAL_PWREx_EnableVddio2Monitor(void) { __HAL_PWR_VDDIO2_EXTI_ENABLE_IT(); - __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER(); + __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE(); } /** * @brief Disable the Vddio2 Monitor. * @retval None */ -void HAL_PWR_DisableVddio2Monitor(void) +void HAL_PWREx_DisableVddio2Monitor(void) { __HAL_PWR_VDDIO2_EXTI_DISABLE_IT(); - __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER(); + __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE(); } @@ -244,13 +244,13 @@ void HAL_PWR_DisableVddio2Monitor(void) * @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler(). * @retval None */ -void HAL_PWR_Vddio2Monitor_IRQHandler(void) +void HAL_PWREx_Vddio2Monitor_IRQHandler(void) { /* Check PWR exti flag */ if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET) { /* PWR Vddio2 monitor interrupt user callback */ - HAL_PWR_Vddio2MonitorCallback(); + HAL_PWREx_Vddio2MonitorCallback(); /* Clear PWR Exti pending bit */ __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG(); @@ -261,10 +261,10 @@ void HAL_PWR_Vddio2Monitor_IRQHandler(void) * @brief PWR Vddio2 Monitor interrupt callback * @retval None */ -__weak void HAL_PWR_Vddio2MonitorCallback(void) +__weak void HAL_PWREx_Vddio2MonitorCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_Vddio2MonitorCallback could be implemented in the user file + the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file */ } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h index 43e482263a..ec1987a1cb 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -130,7 +130,7 @@ typedef struct defined (STM32F071xB) || defined (STM32F072xB) || \ defined (STM32F091xC) -#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ /* defined (STM32F071xB) || defined (STM32F072xB) || */ @@ -140,7 +140,7 @@ typedef struct defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined (STM32F098xx) -#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)0x80000000) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */ +#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */ #endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ @@ -255,23 +255,41 @@ typedef struct #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) /** - * @brief PVD EXTI line configuration: clear falling edge and rising edge trigger. + * @brief Disable the PVD Extended Interrupt Rising Trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_PVD); \ - EXTI->RTSR &= ~(PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + /** * @brief PVD EXTI line configuration: set falling edge trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) /** * @brief PVD EXTI line configuration: set rising edge trigger. * @retval None. */ -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); /** * @brief Check whether the specified PVD EXTI interrupt flag is set or not. @@ -315,14 +333,14 @@ typedef struct * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger. * @retval None. */ -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ +#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2) /** * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger. * @retval None. */ -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2) +#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2) /** * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not. @@ -373,8 +391,8 @@ void HAL_PWR_PVDCallback(void); #if defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined (STM32F098xx) -void HAL_PWR_Vddio2Monitor_IRQHandler(void); -void HAL_PWR_Vddio2MonitorCallback(void); +void HAL_PWREx_Vddio2Monitor_IRQHandler(void); +void HAL_PWREx_Vddio2MonitorCallback(void); #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined (STM32F098xx) */ @@ -383,7 +401,7 @@ void HAL_PWR_Vddio2MonitorCallback(void); #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ defined (STM32F071xB) || defined (STM32F072xB) || \ defined (STM32F091xC) -void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ @@ -393,8 +411,8 @@ void HAL_PWR_DisablePVD(void); #if defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined (STM32F098xx) -void HAL_PWR_EnableVddio2Monitor(void); -void HAL_PWR_DisableVddio2Monitor(void); +void HAL_PWREx_EnableVddio2Monitor(void); +void HAL_PWREx_DisableVddio2Monitor(void); #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined (STM32F098xx) */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c index 34315ac045..be7d15b65a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c @@ -2,21 +2,21 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions - * - @verbatim + * + @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== - [..] + [..] After reset the device is running from Internal High Speed oscillator - (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled, + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; all peripherals mapped on these busses are running at HSI speed. @@ -26,10 +26,10 @@ [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings + (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB busses prescalers (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not + (+) Configure the clock source(s) for peripherals whose clocks are not derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..) ##### RCC Limitations ##### @@ -37,25 +37,20 @@ [..] A delay between an RCC peripheral clock enable and the effective peripheral enabling should be taken into account in order to manage the peripheral read/write - from/to registeres. + from/to registers. (+) This delay depends on the peripheral mapping. - (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle - after the clock enable bit is set on the hardware register - (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle - after the clock enable bit is set on the hardware register + (++) AHB & APB peripherals, 1 dummy read is necessary [..] - Possible Workarounds: - (#) Enable the peripheral clock sometimes before the peripheral read/write - register is required. - (#) For AHB peripheral, insert two dummy read to the peripheral register. - (#) For APB peripheral, insert a dummy read to the peripheral register. - -@endverbatim + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -79,8 +74,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** +*/ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -89,8 +84,8 @@ * @{ */ -/** @defgroup RCC RCC HAL module driver - * @brief RCC HAL module driver +/** @defgroup RCC RCC +* @brief RCC HAL module driver * @{ */ @@ -98,22 +93,21 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Define RCC Private Define - * @{ - */ -#define RCC_CFGR_HPRE_BITNUMBER 4 -#define RCC_CFGR_PPRE_BITNUMBER 8 +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ /** * @} */ - /* Private macro -------------------------------------------------------------*/ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ -#define __MCO_CLK_ENABLE() __GPIOA_CLK_ENABLE() -#define MCO_GPIO_PORT GPIOA -#define MCO_PIN GPIO_PIN_8 + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + /** * @} */ @@ -122,96 +116,95 @@ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ */ -const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ /* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ /** @defgroup RCC_Exported_Functions RCC Exported Functions * @{ */ -/** @defgroup RCC_Exported_Functions_Group1 Initialization/de-initialization function - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== ##### Initialization and de-initialization function ##### - =============================================================================== + =============================================================================== [..] - This section provide functions allowing to configure the internal/external oscillators + This section provides functions allowing to configure the internal/external oscillators (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB and APB1). [..] Internal/external clock and PLL configuration - (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through - the PLL as System clock source. + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + the PLL as System clock source. The HSI clock can be used also to clock the USART and I2C peripherals. - (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock + (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock the ADC peripheral. - (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC - clock source. + (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + clock source. - (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. + (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks: - (++) The first output is used to generate the high speed system clock (up to 48 MHz) - (++) The second output is used to generate the clock for the USB FS (48 MHz) - (++) The third output may be used to generate the clock for the TIM, I2C and USART - peripherals (up to 48 MHz) + (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 48 MHz) + (++) The second output is used to generate the clock for the USB FS (48 MHz) + (++) The third output may be used to generate the clock for the TIM, I2C and USART + peripherals (up to 48 MHz) - (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clockis automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M0 NMI - (Non-Maskable Interrupt) exception vector. + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clockis automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M0 NMI + (Non-Maskable Interrupt) exception vector. - (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL - clock (divided by 2) output on pin (such as PA8 pin). + (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL + clock (divided by 2) output on pin (such as PA8 pin). - [..] System, AHB and APB busses clocks configuration - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + [..] System, AHB and APB busses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: - (++) The FLASH program/erase clock which is always HSI 8MHz clock. - (++) The USB 48 MHz clock which is derived from the PLL VCO clock. - (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. - (++) The I2C clock which can be derived as well from HSI 8MHz clock. - (++) The ADC clock which is derived from PLL output. - (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC - (HSE divided by a programmable prescaler). The System clock (SYSCLK) - frequency must be higher or equal to the RTC clock frequency. - (++) IWDG clock which is always the LSI clock. + (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: + (++) The FLASH program/erase clock which is always HSI 8MHz clock. + (++) The USB 48 MHz clock which is derived from the PLL VCO clock. + (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. + (++) The I2C clock which can be derived as well from HSI 8MHz clock. + (++) The ADC clock which is derived from PLL output. + (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC + (HSE divided by a programmable prescaler). The System clock (SYSCLK) + frequency must be higher or equal to the RTC clock frequency. + (++) IWDG clock which is always the LSI clock. - (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, - Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: - +-----------------------------------------------+ - | Latency | SYSCLK clock frequency (MHz) | - |---------------|-------------------------------| - |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | - |---------------|-------------------------------| - |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | - +-----------------------------------------------+ + (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz, + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: + +-----------------------------------------------+ + | Latency | SYSCLK clock frequency (MHz) | + |---------------|-------------------------------| + |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + |---------------|-------------------------------| + |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + +-----------------------------------------------+ - (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and - prefetch is disabled. - -@endverbatim + (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + prefetch is disabled. + @endverbatim * @{ */ @@ -221,11 +214,11 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, * - HSI ON and used as system clock source * - HSE and PLL OFF * - AHB, APB1 prescaler set to 1. - * - CSS, MCO OFF + * - CSS and MCO1 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks + * - Peripheral clocks + * - LSI, LSE and RTC clocks * @retval None */ void HAL_RCC_DeInit(void) @@ -252,7 +245,7 @@ void HAL_RCC_DeInit(void) CLEAR_REG(RCC->CFGR3); /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); + CLEAR_REG(RCC->CIR); } /** @@ -263,26 +256,461 @@ void HAL_RCC_DeInit(void) * @note The PLL is not disabled when used as system clock. * @retval HAL status */ -__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - /* Note : This function is defined into this file for library reference. */ - /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */ - /* handle the possible oscillators present in STM32F0xx devices */ + uint32_t tickstart = 0; - /* Return error status as not implemented here */ - return HAL_ERROR; + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ + __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ + __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*----------------------------- HSI14 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); + + /* Check the HSI14 State */ + if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) + { + /* Enable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_ENABLE(); + + /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ + __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); + } + else + { + /* Disable ADC control of the Internal High Speed oscillator HSI14 */ + __HAL_RCC_HSI14ADC_DISABLE(); + + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI14_DISABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + +#if defined(RCC_CR2_HSI48ON) + /*----------------------------- HSI48 Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* When the HSI48 is used as system clock it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) + { + return HAL_ERROR; + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal High Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) + { + if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } +#endif /* RCC_CR2_HSI48ON */ + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, predivider and multiplication factor. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PREDIV, + RCC_OscInitStruct->PLL.PLLMUL); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + return HAL_ERROR; + } + } + + return HAL_OK; } /** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. - * @param FLatency: FLASH Latency + * @param FLatency: FLASH Latency * This parameter can be one of the following values: * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle - * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by HAL_RCC_GetHCLKFreq() function called within this function * @@ -290,82 +718,327 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc * startup from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). - * + * * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). + * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. * @retval HAL status */ -__weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - /* Note : This function is defined into this file for library reference. */ - /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */ - /* handle the possible oscillators present in STM32F0xx devices */ + uint32_t tickstart = 0; - /* Return error status as not implemented here */ - return HAL_ERROR; + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + + /* Increasing the CPU frequency */ + if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } +#if defined(RCC_CR2_HSI48ON) + /* HSI48 is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + /* Check the HSI48 ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + return HAL_ERROR; + } + } +#endif /* RCC_CR2_HSI48ON */ + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#if defined(RCC_CR2_HSI48ON) + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#endif /* RCC_CR2_HSI48ON */ + else + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /* Decreasing the CPU frequency */ + else + { + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration -------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } +#if defined(RCC_CR2_HSI48ON) + /* HSI48 is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + /* Check the HSI48 ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) + { + return HAL_ERROR; + } + } +#endif /* RCC_CR2_HSI48ON */ + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#if defined(RCC_CR2_HSI48ON) + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } +#endif /* RCC_CR2_HSI48ON */ + else + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + } + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (TICK_INT_PRIORITY); + + return HAL_OK; } /** * @} */ -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control function - * @brief RCC clocks control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control function ##### - =============================================================================== +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. -@endverbatim + @endverbatim * @{ */ /** - * @brief Selects the clock source to output on MCO pin(such as PA8). - * @note MCO pin (such as PA8) should be configured in alternate function mode. + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. * @param RCC_MCOx: specifies the output direction for the clock source. * This parameter can be one of the following values: - * @arg RCC_MCO: Clock source to output on MCO pin(such as PA8). + * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8). * @param RCC_MCOSource: specifies the clock source to output. * This parameter can be one of the following values: - * @arg RCC_MCOSOURCE_LSI: LSI clock selected as MCO source - * @arg RCC_MCOSOURCE_HSI: HSI clock selected as MCO source - * @arg RCC_MCOSOURCE_LSE: LSE clock selected as MCO source - * @arg RCC_MCOSOURCE_HSE: HSE clock selected as MCO source - * @arg RCC_MCOSOURCE_PLLCLK_NODIV: main PLL clock not divided selected as MCO source (not applicable to STM32F05x devices) - * @arg RCC_MCOSOURCE_PLLCLK_DIV2: main PLL clock divided by 2 selected as MCO source - * @arg RCC_MCOSOURCE_SYSCLK: System clock (SYSCLK) selected as MCO source - * @param RCC_MCODiv: specifies the MCOx prescaler. + * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock + * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock + * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock + * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock + * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock (not applicable to STM32F05x devices) + * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock + * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock + * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock + * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock + * @param RCC_MCODiv: specifies the MCO DIV. * This parameter can be one of the following values: - * @arg RCC_MCO_NODIV: no division applied to MCO clock + * @arg RCC_MCODIV_1: no division applied to MCO clock * @retval None */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio; + /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - /* RCC_MCO */ - assert_param(IS_RCC_MCOSOURCE(RCC_MCOSource)); - + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + /* MCO Clock Enable */ - __MCO_CLK_ENABLE(); - - /* Configue the MCO pin in alternate function mode */ - gpio.Pin = MCO_PIN; + MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Pin = MCO1_PIN; gpio.Mode = GPIO_MODE_AF_PP; gpio.Speed = GPIO_SPEED_HIGH; gpio.Pull = GPIO_NOPULL; gpio.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO_GPIO_PORT, &gpio); - + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + /* Configure the MCO clock source */ __HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv); } @@ -375,13 +1048,13 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. * @retval None */ void HAL_RCC_EnableCSS(void) { - SET_BIT(RCC->CR, RCC_CR_CSSON); + SET_BIT(RCC->CR, RCC_CR_CSSON) ; } /** @@ -390,68 +1063,125 @@ void HAL_RCC_EnableCSS(void) */ void HAL_RCC_DisableCSS(void) { - CLEAR_BIT(RCC->CR, RCC_CR_CSSON); + CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ; } /** - * @brief Returns the SYSCLK frequency - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*) - * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*) + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE * divided by PREDIV factor(**) * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the * PLL factor . - * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file - * (default values 8 MHz and 48MHz). + * @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * @note The result of this function could be not correct when using fractional * value for HSE crystal. - * - * @note This function can be used by the user application to compute the + * + * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. - * + * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * + * + * * @retval SYSCLK frequency */ -__weak uint32_t HAL_RCC_GetSysClockFreq(void) +uint32_t HAL_RCC_GetSysClockFreq(void) { - /* Note : This function is defined into this file for library reference. */ - /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */ - /* handle the possible oscillators present in STM32F0xx devices */ + const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 16, 16}; + const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, + 9,10, 11, 12, 13, 14, 15, 16}; + + uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0; + uint32_t sysclockfreq = 0; - /* Return error status as not implemented here */ - return HAL_ERROR; + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; + if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (HSE_VALUE/prediv) * pllmul; + } +#if defined(RCC_CR2_HSI48ON) + else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) + { + /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ + pllclk = (HSI48_VALUE/prediv) * pllmul; + } +#endif /* RCC_CR2_HSI48ON */ + else + { +#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)) + /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ + pllclk = (HSI_VALUE/prediv) * pllmul; +#else + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); +#endif + } + sysclockfreq = pllclk; + break; + } +#if defined(RCC_CR2_HSI48ON) + case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ + { + sysclockfreq = HSI48_VALUE; + break; + } +#endif /* RCC_CR2_HSI48ON */ + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; } /** - * @brief Returns the HCLK frequency + * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function - * * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; return SystemCoreClock; } /** - * @brief Returns the PCLK1 frequency + * @brief Returns the PCLK1 frequency * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency @@ -459,27 +1189,34 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]); -} + return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]); +} /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14; +#if defined(RCC_CR2_HSI48ON) + RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; +#endif /* RCC_CR2_HSI48ON */ + /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } - else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } @@ -487,9 +1224,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } - + /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } @@ -497,15 +1234,15 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber); - + /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } - else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } @@ -513,9 +1250,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } - + /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } @@ -523,9 +1260,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } - + /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } @@ -536,7 +1273,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); - + /* Get the HSI14 configuration -----------------------------------------------*/ if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON) { @@ -548,35 +1285,40 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_CR2_HSI14TRIM_BitNumber); - + +#if defined(RCC_CR2_HSI48ON) /* Get the HSI48 configuration if any-----------------------------------------*/ RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE(); +#endif /* RCC_CR2_HSI48ON */ } /** - * @brief Get the RCC_ClkInitStruct according to the internal + * @brief Get the RCC_ClkInitStruct according to the internal * RCC configuration registers. - * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that * contains the current clock configuration. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(pFLatency != NULL); + /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; - - /* Get the SYSCLK configuration --------------------------------------------*/ + + /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); } /** @@ -590,8 +1332,8 @@ void HAL_RCC_NMI_IRQHandler(void) if(__HAL_RCC_GET_IT(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CCSCallback(); - + HAL_RCC_CSSCallback(); + /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); } @@ -601,11 +1343,11 @@ void HAL_RCC_NMI_IRQHandler(void) * @brief RCC Clock Security System interrupt callback * @retval none */ -__weak void HAL_RCC_CCSCallback(void) +__weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CCSCallback could be implemented in the user file - */ + the HAL_RCC_CSSCallback could be implemented in the user file + */ } /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h index 7b9785c515..2eeaec4264 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0xx_HAL_RCC_H @@ -51,54 +51,199 @@ */ /** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Constants * @{ */ -/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ + +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x04 +#define RCC_CIR_OFFSET 0x08 +#define RCC_BDCR_OFFSET 0x20 +#define RCC_CSR_OFFSET 0x24 + +/** + * @} + */ + + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1) +#define CR2_REG_INDEX 2 +#define BDCR_REG_INDEX 3 +#define CSR_REG_INDEX 4 + +/* Flags in the CFGR register */ +#define RCC_CFGR_PLLMUL_BITNUMBER 18 +#define RCC_CFGR_HPRE_BITNUMBER 4 +#define RCC_CFGR_PPRE_BITNUMBER 8 +/* Flags in the CFGR2 register */ +#define RCC_CFGR2_PREDIV_BITNUMBER 0 +/* Flags in the CR register */ +#define RCC_CR_HSIRDY_BitNumber 1 +#define RCC_CR_HSERDY_BitNumber 17 +#define RCC_CR_PLLRDY_BitNumber 25 +/* Flags in the CR2 register */ +#define RCC_CR2_HSI14RDY_BitNumber 1 +#define RCC_CR2_HSI48RDY_BitNumber 16 +/* Flags in the BDCR register */ +#define RCC_BDCR_LSERDY_BitNumber 1 +/* Flags in the CSR register */ +#define RCC_CSR_LSIRDY_BitNumber 1 +#define RCC_CSR_V18PWRRSTF_BitNumber 23 +#define RCC_CSR_RMVF_BitNumber 24 +#define RCC_CSR_OBLRSTF_BitNumber 25 +#define RCC_CSR_PINRSTF_BitNumber 26 +#define RCC_CSR_PORRSTF_BitNumber 27 +#define RCC_CSR_SFTRSTF_BitNumber 28 +#define RCC_CSR_IWDGRSTF_BitNumber 29 +#define RCC_CSR_WWDGRSTF_BitNumber 30 +#define RCC_CSR_LPWRRSTF_BitNumber 31 +/* Flags in the HSITRIM register */ +#define RCC_CR_HSITRIM_BitNumber 3 +#define RCC_FLAG_MASK ((uint8_t)0x1F) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) +#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ + ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ + ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ + ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ + ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ + ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ + ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ + ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ + ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ + ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ + ((__MUL__) == RCC_PLL_MUL16)) +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO)) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Types RCC Exported Types * @{ */ -/** - * @brief RCC PLL configuration structure definition +/** + * @brief RCC PLL configuration structure definition */ typedef struct { - uint32_t PLLState; /*!< PLLState: The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ - uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ - uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ + + uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ - uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */ - -}RCC_PLLInitTypeDef; - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { - uint32_t OscillatorType; /*!< The Oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + uint32_t HSI14State; /*!< The new state of the HSI14. This parameter can be a value of @ref RCC_HSI14_Config */ @@ -108,94 +253,53 @@ typedef struct uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices). This parameter can be a value of @ref RCCEx_HSI48_Config */ - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ -}RCC_OscInitTypeDef; +} RCC_OscInitTypeDef; -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ - uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_Clock_Source */ - -}RCC_ClkInitTypeDef; + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Source */ + +} RCC_ClkInitTypeDef; /** * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants RCC Exported Constants * @{ */ -/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion - * @brief RCC registers bit address in the alias region +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ -#define RCC_CR_OFFSET (RCC_OFFSET + 0x00) -/* --- CFGR Register ---*/ -#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04) -/* --- CIR Register ---*/ -#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08) -/* --- BDCR Register ---*/ -#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20) -/* --- CSR Register ---*/ -#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24) -/* --- CR2 Register ---*/ -#define RCC_CR2_OFFSET (RCC_OFFSET + 0x34) -/* CR register byte 2 (Bits[23:16]) base address */ -#define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02) +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ -/* CIR register byte 1 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02) - -/* CSR register byte 1 (Bits[15:8]) base address */ -#define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01) - -/* BDCR register byte 0 (Bits[7:0] base address */ -#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) - -#define RCC_CFGR_PLLMUL_BITNUMBER 18 -#define RCC_CFGR2_PREDIV_BITNUMBER 0 - -/** - * @} - */ - -/** @defgroup RCC_Timeout RCC Timeout - * @{ - */ -/* LSE state change timeout */ -#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ - -/* Disable Backup domain write protection state change timeout */ -#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ /** * @} */ - -/** @defgroup RCC_Oscillator_Type RCC Oscillator Type + +/** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) @@ -204,58 +308,43 @@ typedef struct #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) #define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010) -#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) - -#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ - (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) /** * @} */ -/** @defgroup RCC_HSE_Config RCC HSE Config +/** @defgroup RCC_HSE_Config HSE Config * @{ */ -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_BYPASS ((uint8_t)0x05) - -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_BYPASS)) +#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */ +#define RCC_HSE_ON ((uint32_t)0x00000001) /*!< HSE clock activation */ +#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for HSE clock */ /** * @} */ -/** @defgroup RCC_LSE_Config RCC_LSE_Config +/** @defgroup RCC_LSE_Config LSE Config * @{ */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_BYPASS ((uint8_t)0x05) +#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */ +#define RCC_LSE_ON ((uint32_t)0x00000001) /*!< LSE clock activation */ +#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for LSE clock */ -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_BYPASS)) /** * @} */ -/** @defgroup RCC_HSI_Config RCC HSI Config +/** @defgroup RCC_HSI_Config HSI Config * @{ */ -#define RCC_HSI_OFF ((uint8_t)0x00) -#define RCC_HSI_ON ((uint8_t)0x01) +#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ -#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ /** * @} */ - + /** @defgroup RCC_HSI14_Config RCC HSI14 Config * @{ */ @@ -263,36 +352,107 @@ typedef struct #define RCC_HSI14_ON RCC_CR2_HSI14ON #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS) -#define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL)) - #define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */ /** * @} */ + -/** @defgroup RCC_LSI_Config RCC LSI Config +/** @defgroup RCC_LSI_Config LSI Config * @{ */ -#define RCC_LSI_OFF ((uint8_t)0x00) -#define RCC_LSI_ON ((uint8_t)0x01) +#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ -#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) /** * @} */ -/** @defgroup RCC_PLL_Config RCC PLL Config +/** @defgroup RCC_PLL_Config PLL Config * @{ */ -#define RCC_PLL_NONE ((uint8_t)0x00) -#define RCC_PLL_OFF ((uint8_t)0x01) -#define RCC_PLL_ON ((uint8_t)0x02) +#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */ +#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */ +#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */ -#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) /** * @} */ +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) /*!< PLL selected as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1) +#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2) +#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4) +#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8) +#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16) +#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64) +#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128) +#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256) +#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_BDCR_RTCSEL_LSE) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_BDCR_RTCSEL_LSI) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)RCC_BDCR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor * @{ */ @@ -313,18 +473,10 @@ typedef struct #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 -#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \ - ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \ - ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \ - ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \ - ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \ - ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \ - ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \ - ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16)) /** * @} */ - + /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor * @{ */ @@ -344,110 +496,6 @@ typedef struct #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 -#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \ - ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \ - ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \ - ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \ - ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \ - ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \ - ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \ - ((MUL) == RCC_PLL_MUL16)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source - * @{ - */ -#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type RCC System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) - -#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ - (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ - (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source RCC System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 - -#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \ - ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \ - ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \ - ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \ - ((DIV) == RCC_SYSCLK_DIV512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 - -#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \ - ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \ - ((DIV) == RCC_HCLK_DIV16)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI -#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE - -#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32)) /** * @} */ @@ -460,10 +508,6 @@ typedef struct #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI -#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) /** * @} */ @@ -474,18 +518,15 @@ typedef struct #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK -#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ - ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)) /** * @} */ - -/** @defgroup RCC_MCOx_Index RCC MCOx Index +/** @defgroup RCC_MCO_Index MCO Index * @{ */ -#define RCC_MCO ((uint32_t)0x00000000) +#define RCC_MCO1 ((uint32_t)0x00000000) +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ -#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO) /** * @} */ @@ -501,70 +542,45 @@ typedef struct #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL #define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14 + /** * @} */ - -/** @defgroup RCC_Interrupt RCC Interrupt + +/** @defgroup RCC_Interrupt Interrupts * @{ */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_HSI14 ((uint8_t)0x20) -#define RCC_IT_CSS ((uint8_t)0x80) +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_HSI14 ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */ +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ /** * @} */ -/** @defgroup RCC_Flag RCC Flag - * Elements values convention: 0XXYYYYYb +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb * - YYYYY : Flag position in the register - * - XX : Register index - * - 00: CR register - * - 01: CR2 register - * - 10: BDCR register - * - 11: CSR register + * - XXX : Register index + * - 001: CR register + * - 010: CR2 register + * - 011: BDCR register + * - 0100: CSR register * @{ */ -#define CR_REG_INDEX 0 -#define CR2_REG_INDEX 1 -#define BDCR_REG_INDEX 2 -#define CSR_REG_INDEX 3 - /* Flags in the CR register */ -#define RCC_CR_HSIRDY_BitNumber 1 -#define RCC_CR_HSERDY_BitNumber 17 -#define RCC_CR_PLLRDY_BitNumber 25 - #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber)) #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber)) #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber)) /* Flags in the CR2 register */ -#define RCC_CR2_HSI14RDY_BitNumber 1 - #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber)) -/* Flags in the BDCR register */ -#define RCC_BDCR_LSERDY_BitNumber 1 - -#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber)) /* Flags in the CSR register */ -#define RCC_CSR_LSIRDY_BitNumber 1 -#define RCC_CSR_V18PWRRSTF_BitNumber 23 -#define RCC_CSR_RMVF_BitNumber 24 -#define RCC_CSR_OBLRSTF_BitNumber 25 -#define RCC_CSR_PINRSTF_BitNumber 26 -#define RCC_CSR_PORRSTF_BitNumber 27 -#define RCC_CSR_SFTRSTF_BitNumber 28 -#define RCC_CSR_IWDGRSTF_BitNumber 29 -#define RCC_CSR_WWDGRSTF_BitNumber 30 -#define RCC_CSR_LPWRRSTF_BitNumber 31 - #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber)) #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber)) #define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber)) @@ -575,45 +591,23 @@ typedef struct #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber)) #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber)) #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber)) -/** - * @} - */ -/** @defgroup RCC_Calibration_values RCC Calibration values - * @{ - */ -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber)) /** * @} - */ - -/** @addtogroup RCC_Timeout - * @{ - */ - -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ -#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ + */ /** * @} - */ + */ -/** - * @} - */ - /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ + * @{ + */ /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable * @brief Enable or disable the AHB peripheral clock. @@ -622,27 +616,102 @@ typedef struct * using it. * @{ */ -#define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN)) -#define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN)) -#define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN)) -#define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN)) -#define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) -#define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) -#define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN)) -#define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN)) +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) -#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) -#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) -#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) -#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) -#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) -#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) -#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) /** * @} */ +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) +#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) +/** + * @} + */ + /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -650,20 +719,72 @@ typedef struct * using it. * @{ */ -#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) -#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN)) -#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) -#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) -#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0) -#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) -#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) /** * @} */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. @@ -672,42 +793,117 @@ typedef struct * using it. * @{ */ -#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) -#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) -#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN)) -#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) -#define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN)) -#define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN)) -#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) -#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN)) +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) -#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) -#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) -#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) -#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) -#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN)) /** * @} */ +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET) +/** + * @} + */ + /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset * @brief Force or release AHB peripheral reset. * @{ */ -#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) -#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) -#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) -#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) -#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) -#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) -#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) -#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) -#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) -#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) /** * @} */ @@ -716,19 +912,19 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ -#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) -#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) -#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) -#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) /** * @} */ @@ -737,88 +933,87 @@ typedef struct * @brief Force or release APB2 peripheral reset. * @{ */ -#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) -#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) -#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) -#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) -#define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) -#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) -#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) -#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) -#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) -#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) -#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) -#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) -#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) -#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST)) /** * @} */ - -/** @defgroup RCC_HSI_Configuration RCC HSI Configuration +/** @defgroup RCC_HSI_Configuration HSI Configuration * @{ */ - + /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. + * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. + * system clock source. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - */ + * clock cycles. + */ #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) -/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. +/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICalibrationValue__: specifies the calibration trimming value + * @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value. * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F. - */ -#define RCC_CR_HSITRIM_BitNumber 3 -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber) + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber) + /** * @} */ -/** @defgroup RCC_LSI_Configuration RCC LSI Configuration +/** @defgroup RCC_LSI_Configuration LSI Configuration * @{ */ - -/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. + * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - */ -#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + /** * @} */ -/** @defgroup RCC_HSE_Configuration RCC HSE Configuration +/** @defgroup RCC_HSE_Configuration HSE Configuration * @{ */ - + /** * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. @@ -836,31 +1031,55 @@ typedef struct * @arg RCC_HSE_ON: turn ON the HSE oscillator * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__)) +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0) /** * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. * @note Predivision factor can not be changed if PLL is used as system clock * In this case, you have to select another source of the system clock, disable the PLL and * then change the HSE predivision factor. - * @param __HSEPredivValue__: specifies the division value applied to HSE. + * @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE. * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. */ -#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__)) +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) + /** * @} */ -/** @defgroup RCC_LSE_Configuration RCC LSE Configuration +/** @defgroup RCC_LSE_Configuration LSE Configuration * @{ - */ + */ + /** * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using + * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). + * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. @@ -868,11 +1087,32 @@ typedef struct * This parameter can be one of the following values: * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__)) +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + }while(0) + /** * @} */ @@ -963,235 +1203,247 @@ typedef struct * @} */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macros to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macros to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. + * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock + * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \ + do { \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \ + } while(0) + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC)) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock + * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock + * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) + +/** + * @} + */ + /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration * @{ */ -/** @brief Macros to enable or disable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) -#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) -/** @brief Macro to configure the RTC clock (RTCCLK). +/** @brief Macro to configures the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). - * @param __RTCCLKSource__: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 * - * @note If the LSE is used as RTC clock source, the RTC continues to + * @param __RTC_CLKSOURCE__: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, * the RTC cannot be used in STOP and STANDBY modes. * @note The system must always be configured so as to get a PCLK frequency greater than or * equal to the RTCCLK frequency for a proper operation of the RTC. */ -#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__)) - -/** @brief Macro to get the RTC clock source. +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + +/** @brief macros to get the RTC clock source. * @retval The clock source can be one of the following values: - * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock + * @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock + * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 */ -#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macros to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macros to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macros to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + /** * @} */ -/** @defgroup RCC_Force_Release_Backup RCC Force Release Backup - * @{ - */ - -/** @brief Macro to force or release the Backup domain reset. - * @note These macros reset the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - */ -#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) -#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) -/** - * @} - */ - -/** @defgroup RCC_PLL_Configuration RCC PLL Configuration - * @{ - */ - -/** @brief Macro to enable or disable the PLL. - * @note After enabling the PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The PLL can not be disabled if it is used as system clock source - * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) -#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to configure the PLL clock source, multiplication and division factors. - * @note This macro must be used only when the PLL is disabled. - * - * @param __RCC_PLLSource__: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock - * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. - * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock - * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. - * - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \ - do { \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \ - } while(0) -/** - * @} - */ - -/** @defgroup RCC_Get_Clock_source RCC Get Clock source - * @{ - */ - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. - * The returned value can be one of the following value: - * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock - * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock - * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS))) - -/** @brief Macro to get the oscillator used as PLL clock source. - * @retval The oscillator used as PLL clock source. The returned value can be one - * of the following: - * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) -/** - * @} - */ - -/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable - * the selected interrupts.). +/** @brief Enable RCC interrupt. * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt enable - * @arg RCC_IT_LSERDY: LSE ready interrupt enable - * @arg RCC_IT_HSIRDY: HSI ready interrupt enable - * @arg RCC_IT_HSERDY: HSE ready interrupt enable - * @arg RCC_IT_PLLRDY: PLL ready interrupt enable + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable - * the selected interrupts.). +/** @brief Disable RCC interrupt. * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt enable - * @arg RCC_IT_LSERDY: LSE ready interrupt enable - * @arg RCC_IT_HSIRDY: HSI ready interrupt enable - * @arg RCC_IT_HSERDY: HSE ready interrupt enable - * @arg RCC_IT_PLLRDY: PLL ready interrupt enable + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) -/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __IT__: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt clear - * @arg RCC_IT_LSERDY: LSE ready interrupt clear - * @arg RCC_IT_HSIRDY: HSI ready interrupt clear - * @arg RCC_IT_HSERDY: HSE ready interrupt clear - * @arg RCC_IT_PLLRDY: PLL ready interrupt clear - * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear - * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices) - * @arg RCC_IT_CSS: Clock Security System interrupt clear +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) */ -#define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__)) +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) -/** @brief Check the RCC's interrupt has occurred or not. - * @param __IT__: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt flag - * @arg RCC_IT_LSERDY: LSE ready interrupt flag - * @arg RCC_IT_HSIRDY: HSI ready interrupt flag - * @arg RCC_IT_HSERDY: HSE ready interrupt flag - * @arg RCC_IT_PLLRDY: PLL ready interrupt flag - * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag - * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices) - * @arg RCC_IT_CSS: Clock Security System interrupt flag - * @retval The new state of __IT__ (TRUE or FALSE). +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices) + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__)) +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) -/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) /** @brief Check RCC flag is set or not. * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. + * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices) - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. * @arg RCC_FLAG_OBLRST: Option Byte Load reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset + * @arg RCC_FLAG_PINRST: Pin reset. + * @arg RCC_FLAG_PORRST: POR/PDR reset. + * @arg RCC_FLAG_SFTRST: Software reset. + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. + * @arg RCC_FLAG_LPWRRST: Low Power reset. * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define RCC_FLAG_MASK ((uint8_t)0x1F) #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \ (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \ (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \ RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) - +/** + * @} + */ /** * @} - */ - -/** - * @} - */ + */ /* Include RCC HAL Extension module */ #include "stm32f0xx_hal_rcc_ex.h" /* Exported functions --------------------------------------------------------*/ - /** @addtogroup RCC_Exported_Functions * @{ */ @@ -1200,10 +1452,10 @@ typedef struct * @{ */ -/* Initialization and de-initialization functions ***************************/ -void HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +/* Initialization and de-initialization functions ******************************/ +void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} @@ -1212,22 +1464,22 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uin /** @addtogroup RCC_Exported_Functions_Group2 * @{ */ - -/* Peripheral Control functions *********************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -void HAL_RCC_DisableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); /* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); +void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CCSCallback(void); +void HAL_RCC_CSSCallback(void); /** * @} @@ -1235,16 +1487,16 @@ void HAL_RCC_CCSCallback(void); /** * @} - */ + */ + +/** + * @} + */ /** * @} */ - -/** - * @} - */ - + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c index 00a4cc1238..47e5cac2d3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Extended RCC HAL module driver * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -60,7 +60,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -94,20 +94,18 @@ * @{ */ -/** @defgroup RCCEx RCCEx Extended HAL module driver +#ifdef HAL_RCC_MODULE_ENABLED + +/** @defgroup RCCEx RCCEx * @brief RCC Extension HAL module driver. * @{ */ -#ifdef HAL_RCC_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Define RCCEx Private Define +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ -#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ - /* Bit position in register */ #define CRS_CFGR_FELIM_BITNUMBER 16 #define CRS_CR_TRIM_BITNUMBER 8 @@ -117,17 +115,13 @@ */ /* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Variables RCCEx Private Variables +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros * @{ */ -const uint8_t PLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 13, 14, 15, 16, 16}; -const uint8_t PredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, - 9,10, 11, 12, 13, 14, 15, 16}; /** * @} */ +/* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ @@ -155,834 +149,6 @@ const uint8_t PredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, * @{ */ -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) - { - return HAL_ERROR; - } - } - else - { - /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ - __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG((uint8_t)RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) - { - /* When the HSI is used as system clock it is not allowed to be disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Enable Power Clock */ - __PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ - __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if(RCC_OscInitStruct->LSEState == RCC_LSE_ON) - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - - /*----------------------------- HSI14 Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); - - /* Check the HSI14 State */ - if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) - { - /* Disable ADC control of the Internal High Speed oscillator HSI14 */ - __HAL_RCC_HSI14ADC_DISABLE(); - - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI14_ENABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ - __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); - } - else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) - { - /* Enable ADC control of the Internal High Speed oscillator HSI14 */ - __HAL_RCC_HSI14ADC_ENABLE(); - - /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ - __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); - } - else - { - /* Disable ADC control of the Internal High Speed oscillator HSI14 */ - __HAL_RCC_HSI14ADC_DISABLE(); - - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI14_DISABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - /*----------------------------- HSI48 Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); - - /* When the HSI48 is used as system clock it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) - { - return HAL_ERROR; - } - } - else - { - /* Check the HSI State */ - if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) - { - /* Enable the Internal High Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_ENABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal High Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_DISABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); - assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, predivider and multiplication factor. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PREDIV, - RCC_OscInitStruct->PLL.PLLMUL); - - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - return HAL_ERROR; - } - } - return HAL_OK; -} - -/** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency: FLASH Latency - * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle - * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * @retval None - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) of the device. */ - - /* Increasing the CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - /* HSI48 is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) - { - /* Check the HSI48 ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) - { - return HAL_ERROR; - } - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /* Decreasing the CPU frequency */ - else - { - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - /* HSI48 is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) - { - /* Check the HSI48 ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) - { - return HAL_ERROR; - } - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_HCLK_DIV(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); - } - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); - - return HAL_OK; -} - -/** - * @brief Returns the SYSCLK frequency - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*) - * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*) - * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE - * divided by PREDIV factor(**) - * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE - * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based - * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the - * PLL factor . - * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file - * (default values 8 MHz and 48MHz). - * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t tmpreg = 0, prediv = 0, pllmul = 0, pllclk = 0; - uint32_t sysclockfreq = 0; - - tmpreg = RCC->CFGR; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (tmpreg & RCC_CFGR_SWS) - { - case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ - sysclockfreq = HSE_VALUE; - break; - - case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ - pllmul = PLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; - prediv = PredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; - if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) - { - /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ - pllclk = (HSE_VALUE/prediv) * pllmul; - } -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) - { - /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ - pllclk = (HSI48_VALUE/prediv) * pllmul; - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - else - { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ - pllclk = (HSI_VALUE/prediv) * pllmul; -#else - /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ - pllclk = (HSI_VALUE >> 1) * pllmul; -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || - STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB - STM32F091xC || STM32F098xx || STM32F030xC */ - } - sysclockfreq = pllclk; - break; - -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ - sysclockfreq = HSI48_VALUE; - break; -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - - case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - default: - sysclockfreq = HSI_VALUE; - break; - } - return sysclockfreq; -} - /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. @@ -1000,7 +166,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tickstart = 0; - uint32_t tmpreg = 0; + uint32_t temp_reg = 0; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection)); @@ -1008,51 +174,51 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { - /* Enable Power Clock*/ - __PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Reset the Backup domain only if the RTC Clock source selction is modified */ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg; - } - - /* If LSE is selected as RTC clock source, wait for LSE reactivation */ - if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + RCC->BDCR = temp_reg; + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)) { - if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - return HAL_TIMEOUT; - } - } + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } /*------------------------------- USART1 Configuration ------------------------*/ @@ -1065,8 +231,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /*----------------------------- USART2 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) { @@ -1113,10 +279,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /*------------------------------ CEC clock Configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) { @@ -1154,8 +320,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the I2C1 clock source -----------------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; /* Get the USART2 clock source ---------------------------------------------*/ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); @@ -1174,10 +340,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; /* Get the CEC clock source ------------------------------------------------*/ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); @@ -1188,9 +354,271 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +/** + * @brief Returns the peripheral clock frequency + * @note Returns 0 if peripheral clock is unknown + * @param PeriphClk: Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg RCC_PERIPHCLK_USART2 USART2 peripheral clock (*) + * @arg RCC_PERIPHCLK_USART3 USART3 peripheral clock (*) + * @arg RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg RCC_PERIPHCLK_USB USB peripheral clock (*) + * @arg RCC_PERIPHCLK_CEC CEC peripheral clock (*) + * @note (*) means that this peripheral is not present on all the STM32F0xx devices + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t frequency = 0; + uint32_t srcclk = 0; +#if defined(USB) + uint32_t pllmull = 0, pllsource = 0, predivfactor = 0; +#endif /* USB */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLK(PeriphClk)); + + switch (PeriphClk) + { + case RCC_PERIPHCLK_RTC: + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + { + frequency = HSE_VALUE / 32; + } + /* Clock not enabled for RTC*/ + else + { + frequency = 0; + } + break; + } + case RCC_PERIPHCLK_USART1: + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + /* Check if USART1 clock selection is PCLK1 */ + if (srcclk == RCC_USART1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART1 clock selection is HSI */ + else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART1 clock selection is SYSCLK */ + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART1 clock selection is LSE */ + else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART1*/ + else + { + frequency = 0; + } + break; + } +#if defined(RCC_CFGR3_USART2SW) + case RCC_PERIPHCLK_USART2: + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + /* Check if USART2 clock selection is PCLK1 */ + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART2 clock selection is HSI */ + else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART2 clock selection is SYSCLK */ + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART2 clock selection is LSE */ + else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART2*/ + else + { + frequency = 0; + } + break; + } +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) + case RCC_PERIPHCLK_USART3: + { + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + /* Check if USART3 clock selection is PCLK1 */ + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART3 clock selection is HSI */ + else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART3 clock selection is SYSCLK */ + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART3 clock selection is LSE */ + else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART3*/ + else + { + frequency = 0; + } + break; + } +#endif /* RCC_CFGR3_USART3SW */ + case RCC_PERIPHCLK_I2C1: + { + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Check if HSI is ready and if I2C1 clock selection is HSI */ + if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if I2C1 clock selection is SYSCLK */ + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Clock not enabled for I2C1*/ + else + { + frequency = 0; + } + break; + } +#if defined(USB) + case RCC_PERIPHCLK_USB: + { + /* Get the current USB source */ + srcclk = __HAL_RCC_GET_USB_SOURCE(); + + /* Check if PLL is ready and if USB clock selection is PLL */ + if ((srcclk == RCC_USBCLKSOURCE_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */ + frequency = (HSE_VALUE/predivfactor) * pllmull; + } +#if defined(RCC_CR2_HSI48ON) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */ + frequency = (HSI48_VALUE / predivfactor) * pllmull; + } +#endif /* RCC_CR2_HSI48ON */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB) + /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */ + frequency = (HSI_VALUE / predivfactor) * pllmull; +#else + /* HSI used as PLL clock source : frequency = HSI/2 * PLLMUL */ + frequency = (HSI_VALUE >> 1) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */ + } + } +#if defined(RCC_CR2_HSI48ON) + /* Check if HSI48 is ready and if USB clock selection is HSI48 */ + else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY))) + { + frequency = HSI48_VALUE; + } +#endif /* RCC_CR2_HSI48ON */ + /* Clock not enabled for USB*/ + else + { + frequency = 0; + } + break; + } +#endif /* USB */ +#if defined(CEC) + case RCC_PERIPHCLK_CEC: + { + /* Get the current CEC source */ + srcclk = __HAL_RCC_GET_CEC_SOURCE(); + + /* Check if HSI is ready and if CEC clock selection is HSI */ + if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if LSE is ready and if CEC clock selection is LSE */ + else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for CEC */ + else + { + frequency = 0; + } + break; + } +#endif /* CEC */ + default: + { + break; + } + } + return(frequency); +} + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Start automatic synchronization using polling mode * @param pInit Pointer on RCC_CRSInitTypeDef structure @@ -1210,8 +638,8 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) /* CONFIGURATION */ /* Before configuration, reset CRS registers to their default values*/ - __CRS_FORCE_RESET(); - __CRS_RELEASE_RESET(); + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); /* Configure Synchronization input */ /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */ @@ -1395,10 +823,11 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) * @} */ -#endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ + +#endif /* HAL_RCC_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h index c070dcb62e..152cb7ef29 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -37,7 +37,7 @@ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0xx_HAL_RCC_EX_H -#define __STM32F0xx_HAL_RCC_EX_H +#define __HAL_RCC_STM32F0xx_HAL_RCC_EX_H #ifdef __cplusplus extern "C" { @@ -50,10 +50,363 @@ * @{ */ +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) +#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) +#else +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)) +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\ + || defined(STM32F070xB) || defined(STM32F030xC) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ + ((SOURCE) == RCC_MCOSOURCE_LSI) || \ + ((SOURCE) == RCC_MCOSOURCE_LSE) || \ + ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI) || \ + ((SOURCE) == RCC_MCOSOURCE_HSE) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI14)) + +#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */ + +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ + ((SOURCE) == RCC_MCOSOURCE_LSI) || \ + ((SOURCE) == RCC_MCOSOURCE_LSE) || \ + ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI) || \ + ((SOURCE) == RCC_MCOSOURCE_HSE) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI14)) + +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ + ((SOURCE) == RCC_MCOSOURCE_LSI) || \ + ((SOURCE) == RCC_MCOSOURCE_LSE) || \ + ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI) || \ + ((SOURCE) == RCC_MCOSOURCE_HSE) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \ + ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI14) || \ + ((SOURCE) == RCC_MCOSOURCE_HSI48)) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Constants + * @{ + */ +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +/** @addtogroup RCC_PLL_Clock_Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV +#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV + +/** + * @} + */ + +/** @addtogroup RCC_Oscillator_Type + * @{ + */ +#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) +/** + * @} + */ + +/** @addtogroup RCC_Interrupt + * @{ + */ +#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +/** + * @} + */ + +/** @addtogroup RCC_Flag + * @{ + */ +#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber)) +/** + * @} + */ + +/** @addtogroup RCC_System_Clock_Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 +/** + * @} + */ + +/** @addtogroup RCC_System_Clock_Source_Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 +/** + * @} + */ + +#else +/** @addtogroup RCC_PLL_Clock_Source + * @{ + */ + +#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV +#else +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 +#endif + +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +/** @addtogroup RCC_MCO_Clock_Source + * @{ + */ + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\ + || defined(STM32F070xB) || defined(STM32F030xC) + +#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) + +#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48 +#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + /** @addtogroup RCCEx * @{ */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || + STM32F030xC */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB)) +#endif /* STM32F042x6 || STM32F048xx */ + +#if defined(STM32F051x8) || defined(STM32F058xx) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) +#endif /* STM32F051x8 || STM32F058xx */ + +#if defined(STM32F071xB) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F071xB */ + +#if defined(STM32F072xB) || defined(STM32F078xx) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) +#endif /* STM32F072xB || STM32F078xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) +#endif /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK)) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ + +#if defined(STM32F070x6) || defined(STM32F070xB) + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK)) + +#endif /* STM32F070x6 || STM32F070xB */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) +#endif /* STM32F091xC || STM32F098xx */ + + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) + +#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ + +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB)\ + || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \ + ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \ + ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \ + ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128)) + +#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) +#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ + ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) +#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) +#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF)) +#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF)) +#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F)) +#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ + ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + /* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types @@ -63,8 +416,8 @@ /** * @brief RCC extended clocks structure definition */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \ - defined(STM32F030xC) +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. @@ -228,9 +581,9 @@ typedef struct }RCC_PeriphCLKInitTypeDef; #endif /* STM32F091xC || STM32F098xx */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief RCC_CRS Init structure definition @@ -294,13 +647,22 @@ typedef struct * @{ */ +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) +/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF ((uint8_t)0x00) +#define RCC_HSI48_ON ((uint8_t)0x01) + +/** + * @} + */ + /** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - #define RCC_CRS_NONE ((uint32_t)0x00000000) #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001) #define RCC_CRS_SYNCOK ((uint32_t)0x00000002) @@ -309,24 +671,33 @@ typedef struct #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010) #define RCC_CRS_TRIMOV ((uint32_t)0x00000020) -#endif /* STM32F042x6 || STM32F048xx */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ /** * @} */ +#else + +/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF ((uint8_t)0x00) +/** + * @} + */ + +#endif /* STM32F042x6 || STM32F048xx */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection * @{ */ -#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \ - defined(STM32F030xC) +#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F030xC) #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_RTC)) #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F030xC */ @@ -336,8 +707,6 @@ typedef struct #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) -#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) #endif /* STM32F070x6 || STM32F070xB */ #if defined(STM32F042x6) || defined(STM32F048xx) @@ -347,9 +716,6 @@ typedef struct #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) -#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_USB)) #endif /* STM32F042x6 || STM32F048xx */ #if defined(STM32F051x8) || defined(STM32F058xx) @@ -358,8 +724,6 @@ typedef struct #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) #endif /* STM32F051x8 || STM32F058xx */ #if defined(STM32F071xB) @@ -369,9 +733,6 @@ typedef struct #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) -#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ - RCC_PERIPHCLK_RTC)) #endif /* STM32F071xB */ #if defined(STM32F072xB) || defined(STM32F078xx) @@ -382,9 +743,6 @@ typedef struct #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) -#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) #endif /* STM32F072xB || STM32F078xx */ #if defined(STM32F091xC) || defined(STM32F098xx) @@ -395,80 +753,12 @@ typedef struct #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000) -#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) #endif /* STM32F091xC || STM32F098xx */ /** * @} */ -/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source - * @{ - */ - -#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030xC) - -#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) - -#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ - ((SOURCE) == RCC_MCOSOURCE_LSI) || \ - ((SOURCE) == RCC_MCOSOURCE_LSE) || \ - ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCOSOURCE_HSI) || \ - ((SOURCE) == RCC_MCOSOURCE_HSE) || \ - ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \ - ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCOSOURCE_HSI14)) - -#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */ - -#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) - -#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ - ((SOURCE) == RCC_MCOSOURCE_LSI) || \ - ((SOURCE) == RCC_MCOSOURCE_LSE) || \ - ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCOSOURCE_HSI) || \ - ((SOURCE) == RCC_MCOSOURCE_HSE) || \ - ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCOSOURCE_HSI14)) - -#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ - -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - -#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48 -#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) - -#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ - ((SOURCE) == RCC_MCOSOURCE_LSI) || \ - ((SOURCE) == RCC_MCOSOURCE_LSE) || \ - ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCOSOURCE_HSI) || \ - ((SOURCE) == RCC_MCOSOURCE_HSE) || \ - ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \ - ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \ - ((SOURCE) == RCC_MCOSOURCE_HSI14) || \ - ((SOURCE) == RCC_MCOSOURCE_HSI48)) - -#define RCC_IT_HSI48 ((uint8_t)0x40) - -/* Flags in the CR2 register */ -#define RCC_CR2_HSI48RDY_BitNumber 16 - -#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber)) - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ -/** - * @} - */ - #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source @@ -477,8 +767,6 @@ typedef struct #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK -#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ - ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK)) /** * @} */ @@ -492,15 +780,14 @@ typedef struct */ #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK -#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK)) /** * @} */ #endif /* STM32F070x6 || STM32F070xB */ -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source * @{ @@ -510,10 +797,6 @@ typedef struct #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI -#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) /** * @} */ @@ -531,10 +814,6 @@ typedef struct #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI -#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) /** * @} */ @@ -542,10 +821,10 @@ typedef struct #endif /* STM32F091xC || STM32F098xx */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source * @{ @@ -553,8 +832,6 @@ typedef struct #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE -#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_CECCLKSOURCE_LSE)) /** * @} */ @@ -564,115 +841,20 @@ typedef struct /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) - -/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source - * @{ - */ -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV -#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV - -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) -/** - * @} - */ - -/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 - -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) - -#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 - -#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) -/** - * @} - */ - -/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF ((uint8_t)0x00) -#define RCC_HSI48_ON ((uint8_t)0x01) - -#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) -/** - * @} - */ -#else -/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source - * @{ - */ - -#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV -#else -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 -#endif - -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) -/** - * @} - */ - -/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source - * @{ - */ -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) - -#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF ((uint8_t)0x00) - -#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF)) -/** - * @} - */ - -#endif /* STM32F042x6 || STM32F048xx || */ - /* STM32F071xB || STM32F072xB || STM32F078xx || */ - /* STM32F091xC || STM32F098xx */ - - /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler * @{ */ #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) -#define RCC_MCO_NODIV ((uint32_t)0x00000000) - -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV)) +#define RCC_MCODIV_1 ((uint32_t)0x00000000) #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */ -#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ - defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB) || \ - defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB)\ + || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) #define RCC_MCO_DIV1 ((uint32_t)0x00000000) #define RCC_MCO_DIV2 ((uint32_t)0x10000000) @@ -683,11 +865,6 @@ typedef struct #define RCC_MCO_DIV64 ((uint32_t)0x60000000) #define RCC_MCO_DIV128 ((uint32_t)0x70000000) -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \ - ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \ - ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \ - ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128)) - #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */ /* STM32F091xC || STM32F098xx || STM32F030xC */ @@ -696,9 +873,9 @@ typedef struct * @} */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource * @{ @@ -707,9 +884,6 @@ typedef struct #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ -#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ - ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ - ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) /** * @} */ @@ -726,10 +900,6 @@ typedef struct #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ -#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) /** * @} */ @@ -740,8 +910,6 @@ typedef struct #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */ #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ -#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ - ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) /** * @} */ @@ -752,7 +920,6 @@ typedef struct #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ -#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF)) /** * @} */ @@ -762,7 +929,6 @@ typedef struct */ #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */ -#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF)) /** * @} */ @@ -774,7 +940,6 @@ typedef struct The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ -#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F)) /** * @} */ @@ -785,8 +950,6 @@ typedef struct #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */ #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ -#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ - ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) /** * @} */ @@ -841,38 +1004,56 @@ typedef struct * using it. * @{ */ -#if defined(STM32F030x6) || defined(STM32F030x8) || \ - defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x6) || defined(STM32F030x8)\ + || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN)) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) #endif /* STM32F030x6 || STM32F030x8 || */ /* STM32F051x8 || STM32F058xx || STM32F070xB || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN)) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN)) +#define __HAL_RCC_TSC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) +#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) #endif /* STM32F042x6 || STM32F048xx || */ /* STM32F051x8 || STM32F058xx || */ @@ -881,9 +1062,15 @@ typedef struct #if defined(STM32F091xC) || defined(STM32F098xx) -#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN)) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) #endif /* STM32F091xC || STM32F098xx */ @@ -892,32 +1079,63 @@ typedef struct * is disabled and the application software has to enable this clock before * using it. */ -#if defined(STM32F030x8) || \ - defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) -#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) -#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F031x6) || defined(STM32F038xx) || \ - defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #endif /* STM32F031x6 || STM32F038xx || */ /* STM32F042x6 || STM32F048xx || */ @@ -925,88 +1143,148 @@ typedef struct /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ -#if defined(STM32F030x8) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) -#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) #endif /* STM32F030x8 || */ /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) #endif /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN)) +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) #endif /* STM32F042x6 || STM32F048xx || */ /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) -#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN)) -#define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN)) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_USART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) -#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ /* STM32F072xB || STM32F078xx || STM32F070xB */ -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN)) -#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ /* STM32F091xC || STM32F098xx */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN)) +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) -#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) +#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) #endif /* STM32F042x6 || STM32F048xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ @@ -1014,9 +1292,15 @@ typedef struct #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN)) +#define __HAL_RCC_USART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) +#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ @@ -1025,14 +1309,20 @@ typedef struct * is disabled and the application software has to enable this clock before * using it. */ -#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN)) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ /* STM32F051x8 || STM32F058xx || */ @@ -1041,19 +1331,37 @@ typedef struct #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN)) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ #if defined(STM32F091xC) || defined(STM32F098xx) -#define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN)) -#define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN)) +#define __HAL_RCC_USART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_USART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) -#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) +#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) +#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) #endif /* STM32F091xC || STM32F098xx */ @@ -1069,38 +1377,38 @@ typedef struct /** @brief Force or release AHB peripheral reset. */ -#if defined(STM32F030x6) || defined(STM32F030x8) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x6) || defined(STM32F030x8)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) -#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) #endif /* STM32F030x6 || STM32F030x8 || */ /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) -#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) +#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) -#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) +#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) #endif /* STM32F042x6 || STM32F048xx || */ /* STM32F051x8 || STM32F058xx || */ @@ -1109,32 +1417,32 @@ typedef struct /** @brief Force or release APB1 peripheral reset. */ -#if defined(STM32F030x8) || \ - defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x8) \ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F031x6) || defined(STM32F038xx) || \ - defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) #endif /* STM32F031x6 || STM32F038xx || */ /* STM32F042x6 || STM32F048xx || */ @@ -1142,89 +1450,89 @@ typedef struct /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ -#if defined(STM32F030x8) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) ||\ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) -#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) #endif /* STM32F030x8 || */ /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) #endif /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) -#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) #endif /* STM32F042x6 || STM32F048xx || */ /* STM32F051x8 || STM32F058xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || STM32F098xx */ -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) -#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) -#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) -#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ /* STM32F072xB || STM32F078xx || STM32F070xB */ -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) -#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ /* STM32F091xC || STM32F098xx */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) -#define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) +#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) -#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) +#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) #endif /* STM32F042x6 || STM32F048xx || */ /* STM32F071xB || STM32F072xB || STM32F078xx || */ @@ -1232,23 +1540,23 @@ typedef struct #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) +#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) -#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) +#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ /** @brief Force or release APB2 peripheral reset. */ -#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) -#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ /* STM32F051x8 || STM32F058xx || */ @@ -1257,25 +1565,244 @@ typedef struct #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) -#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) -#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ #if defined(STM32F091xC) || defined(STM32F098xx) -#define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) -#define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) +#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) +#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) -#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) -#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) +#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) +#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) #endif /* STM32F091xC || STM32F098xx */ /** * @} */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +/** @brief AHB Peripheral Clock Enable Disable Status + */ +#if defined(STM32F030x6) || defined(STM32F030x8)\ + || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) + +#endif /* STM32F030x6 || STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || STM32F070xB || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) +#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx */ + +/** @brief APB1 Peripheral Clock Enable Disable Status + */ +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F030x8)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) + +#endif /* STM32F031x6 || STM32F038xx || */ + /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F030x8) \ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) + +#endif /* STM32F030x8 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) + +#endif /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET) + +#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) + +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F072xB || STM32F078xx || STM32F070xB */ + +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET) + +#endif /* STM32F042x6 || STM32F048xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || */ + /* STM32F091xC || STM32F098xx */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET) +#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +/** @brief APB1 Peripheral Clock Enable Disable Status + */ +#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) + +#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ + /* STM32F051x8 || STM32F058xx || */ + /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ + /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx || STM32F030xC */ + +#if defined(STM32F091xC) || defined(STM32F098xx) + +#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET) +#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET) +#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET) +#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET) + +#endif /* STM32F091xC || STM32F098xx */ +/** + * @} + */ + /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). @@ -1289,9 +1816,9 @@ typedef struct * clock cycles. * @{ */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) @@ -1323,9 +1850,9 @@ typedef struct /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config * @{ */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F070x6) || defined(STM32F070xB) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F070x6) || defined(STM32F070xB) /** @brief Macro to configure the USB clock (USBCLK). * @param __USBCLKSource__: specifies the USB clock source. @@ -1338,7 +1865,7 @@ typedef struct /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: - * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB) + * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) @@ -1347,10 +1874,10 @@ typedef struct /* STM32F072xB || STM32F078xx || */ /* STM32F070x6 || STM32F070xB */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F051x8) || defined(STM32F058xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /** @brief Macro to configure the CEC clock. * @param __CECCLKSource__: specifies the CEC clock source. @@ -1373,10 +1900,10 @@ typedef struct /* STM32F071xB || STM32F072xB || STM32F078xx || */ /* STM32F091xC || defined(STM32F098xx) */ -#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \ - defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \ - defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)\ + || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ + || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) /** @brief Macro to configure the MCO clock. * @param __MCOCLKSource__: specifies the MCO clock source. @@ -1418,7 +1945,7 @@ typedef struct * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock * @param __MCODiv__: specifies the MCO clock prescaler. * This parameter can be one of the following values: - * @arg RCC_MCO_NODIV: No division applied on MCO clock source + * @arg RCC_MCODIV_1: No division applied on MCO clock source */ #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__) @@ -1428,8 +1955,8 @@ typedef struct /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ /* STM32F091xC || STM32F098xx || STM32F030xC */ -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /** @brief Macro to configure the USART2 clock (USART2CLK). * @param __USART2CLKSource__: specifies the USART2 clock source. * This parameter can be one of the following values: @@ -1477,9 +2004,9 @@ typedef struct * @} */ -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag * @{ @@ -1642,10 +2169,11 @@ typedef struct HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); -#if defined(STM32F042x6) || defined(STM32F048xx) || \ - defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ - defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F042x6) || defined(STM32F048xx)\ + || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ + || defined(STM32F091xC) || defined(STM32F098xx) void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c index 2783c28b54..bd4ebcdb52 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c @@ -2,68 +2,20 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization + * functionalities of the Real Time Clock (RTC) peripheral: + * + Initialization and de-initialization functions * + RTC Time and Date functions * + RTC Alarm functions - * + Backup Data Registers configuration - * + Interrupts and flags management - * + * + Peripheral Control functions + * + Peripheral State functions + * @verbatim - - =============================================================================== - ##### RTC Operating Condition ##### - =============================================================================== - [..] The real-time clock (RTC) and the RTC backup registers can be powered - from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC - when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC to operate even when the main digital supply (VDD) - is turned off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) PC13 to PC15 I/Os (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected - to VDD), the following pins are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_OUT pin - - [..] When the backup domain is supplied by VBAT (analog switch connected - to VBAT because VDD is not present), the following pins are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_OUT pin - - ##### Backup Domain Reset ##### - =============================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR - register to their reset values. - A backup domain reset is generated when one of the following events - occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - - ##### Backup Domain Access ##### - =================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (#) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() function. - (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. - (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. - - - ##### How to use this driver ##### + ============================================================================== + ##### How to use RTC Driver ##### =================================================================== [..] (+) Enable the RTC domain access (see description in the section above). @@ -80,8 +32,9 @@ *** Alarm configuration *** =========================== [..] - (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the + HAL_RTC_SetAlarm_IT() function. (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. ##### RTC and low power modes ##### @@ -104,7 +57,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -138,7 +91,7 @@ * @{ */ -/** @defgroup RTC RTC HAL module driver +/** @addtogroup RTC * @brief RTC HAL module driver * @{ */ @@ -152,11 +105,11 @@ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ -/** @defgroup RTC_Exported_Functions RTC Exported Functions +/** @addtogroup RTC_Exported_Functions * @{ */ -/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup RTC_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim @@ -191,9 +144,9 @@ */ /** - * @brief Initializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Initialize the RTC according to the specified parameters + * in the RTC_InitTypeDef structure and initialize the associated handle. + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) @@ -215,6 +168,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) if(hrtc->State == HAL_RTC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); } @@ -264,14 +220,21 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) } /** - * @brief DeInitializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note This function doesn't reset the RTC Backup Data registers. + * @brief DeInitialize the RTC peripheral. + * @param hrtc: RTC handle + * @note This function doesn't reset the RTC Backup Data registers. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { +#if defined (STM32F030xC) || defined (STM32F070xB) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) + uint32_t tickstart = 0; +#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) ||*/ + /* Check the parameters */ assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); @@ -297,8 +260,42 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Reset TR, DR and CR registers */ hrtc->Instance->TR = (uint32_t)0x00000000; hrtc->Instance->DR = (uint32_t)0x00002101; + +#if defined (STM32F030xC) || defined (STM32F070xB) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) + /* Reset All CR bits except CR[2:0] */ + hrtc->Instance->CR &= (uint32_t)0x00000007; + + tickstart = HAL_GetTick(); + + /* Wait till WUTWF flag is set and if Time out is reached exit */ + while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } +#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) ||*/ + /* Reset all RTC CR register bits */ hrtc->Instance->CR &= (uint32_t)0x00000000; +#if defined (STM32F030xC) || defined (STM32F070xB) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) + hrtc->Instance->WUTR = (uint32_t)0x0000FFFF; +#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) ||*/ hrtc->Instance->PRER = (uint32_t)0x007F00FF; hrtc->Instance->ALRMAR = (uint32_t)0x00000000; hrtc->Instance->SHIFTR = (uint32_t)0x00000000; @@ -327,7 +324,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) } /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* De-Initialize RTC MSP */ HAL_RTC_MspDeInit(hrtc); @@ -341,27 +338,25 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) } /** - * @brief Initializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Initialize the RTC MSP. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTC_MspInit could be implemented in the user file */ } /** - * @brief DeInitializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief DeInitialize the RTC MSP. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTC_MspDeInit could be implemented in the user file */ } @@ -370,7 +365,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) * @} */ -/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions +/** @addtogroup RTC_Exported_Functions_Group2 * @brief RTC Time and Date functions * @verbatim @@ -378,21 +373,20 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) ##### RTC Time and Date functions ##### =============================================================================== - [..] This section provide functions allowing to configure Time and Date features + [..] This section provides functions allowing to configure Time and Date features @endverbatim * @{ */ /** - * @brief Sets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set RTC current time. + * @param hrtc: RTC handle * @param sTime: Pointer to Time structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) @@ -409,7 +403,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) { @@ -473,14 +467,14 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); /* Clear the bits to be configured */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; - + hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK); + /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - + hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) { @@ -510,17 +504,17 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } /** - * @brief Gets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Get RTC current time. + * @param hrtc: RTC handle * @param sTime: Pointer to Time structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read + * to ensure consistency between the time and date values. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) @@ -543,7 +537,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); /* Check the input parameters format */ - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { /* Convert the time structure parameters to Binary format */ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); @@ -555,14 +549,13 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } /** - * @brief Sets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set RTC current date. + * @param hrtc: RTC handle * @param sDate: Pointer to date structure * @param Format: specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) @@ -577,14 +570,14 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) { sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { assert_param(IS_RTC_YEAR(sDate->Year)); assert_param(IS_RTC_MONTH(sDate->Month)); @@ -632,8 +625,8 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - + hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) { @@ -664,14 +657,13 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat } /** - * @brief Gets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Get RTC current date. + * @param hrtc: RTC handle * @param sDate: Pointer to Date structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN : Binary data format - * @arg FORMAT_BCD : BCD data format + * @arg RTC_FORMAT_BIN : Binary data format + * @arg RTC_FORMAT_BCD : BCD data format * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values * in the higher-order calendar shadow registers to ensure consistency between the time and date values. * Reading RTC current time locks the values in calendar shadow registers until Current date is read. @@ -694,7 +686,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { /* Convert the date structure parameters to Binary format */ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); @@ -708,7 +700,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @} */ -/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions +/** @addtogroup RTC_Exported_Functions_Group3 * @brief RTC Alarm functions * @verbatim @@ -722,14 +714,13 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @{ */ /** - * @brief Sets the specified RTC Alarm. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set the specified RTC Alarm. + * @param hrtc: RTC handle * @param sAlarm: Pointer to Alarm structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) @@ -739,8 +730,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(sAlarm->Alarm)); - assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); @@ -750,7 +741,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) { @@ -831,9 +822,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) { @@ -870,14 +859,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } /** - * @brief Sets the specified RTC Alarm with Interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set the specified RTC Alarm with Interrupt. + * @param hrtc: RTC handle * @param sAlarm: Pointer to Alarm structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @note The Alarm register can only be written when the corresponding Alarm * is disabled (Use the HAL_RTC_DeactivateAlarm()). * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. @@ -890,8 +878,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(sAlarm->Alarm)); - assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); @@ -901,7 +889,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) { @@ -1007,9 +995,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT); + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1023,9 +1011,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } /** - * @brief Deactive the specified RTC Alarm - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Deactivate the specified RTC Alarm. + * @param hrtc: RTC handle * @param Alarm: Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA @@ -1036,7 +1023,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar uint32_t tickstart = 0; /* Check the parameters */ - assert_param(IS_ALARM(Alarm)); + assert_param(IS_RTC_ALARM(Alarm)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -1051,7 +1038,6 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - /* Get tick */ tickstart = HAL_GetTick(); /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ @@ -1082,17 +1068,16 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar } /** - * @brief Gets the RTC Alarm value and masks. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Get the RTC Alarm value and masks. + * @param hrtc: RTC handle * @param sAlarm: Pointer to Date structure * @param Alarm: Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) @@ -1101,7 +1086,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(Alarm)); + assert_param(IS_RTC_ALARM(Alarm)); sAlarm->Alarm = RTC_ALARM_A; @@ -1118,7 +1103,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); @@ -1130,9 +1115,8 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } /** - * @brief This function handles Alarm interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Handle Alarm interrupt request. + * @param hrtc: RTC handle * @retval None */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) @@ -1142,16 +1126,16 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /* Get the status of the Interrupt */ if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET) { - /* AlarmA callback */ + /* AlarmA callback */ HAL_RTC_AlarmAEventCallback(hrtc); - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); + + /* Clear the AlarmA interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); } } /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT); + __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1159,30 +1143,26 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /** * @brief Alarm A callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTC_AlarmAEventCallback could be implemented in the user file */ } /** - * @brief This function handles AlarmA Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Handle AlarmA Polling request. + * @param hrtc: RTC handle * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; +{ - /* Get tick */ - tickstart = HAL_GetTick(); + uint32_t tickstart = HAL_GetTick(); while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) { @@ -1209,7 +1189,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * @} */ -/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions +/** @addtogroup RTC_Exported_Functions_Group4 * @brief Peripheral Control functions * @verbatim @@ -1225,18 +1205,17 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T */ /** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are * synchronized with RTC APB clock. * @note The RTC Resynchronization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wake-up from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) @@ -1245,8 +1224,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) /* Clear RSF flag */ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Get tick */ + tickstart = HAL_GetTick(); /* Wait the registers to be synchronised */ @@ -1265,7 +1243,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) * @} */ -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions +/** @addtogroup RTC_Exported_Functions_Group5 * @brief Peripheral State functions * @verbatim @@ -1280,13 +1258,13 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) * @{ */ /** - * @brief Returns the RTC state. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Return the RTC handle state. + * @param hrtc: RTC handle * @retval HAL state */ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) { + /* Return RTC handle state */ return hrtc->State; } @@ -1298,19 +1276,15 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) * @} */ -/** @defgroup RTC_Private_Functions RTC Private Functions +/** @addtogroup RTC_Private_Functions * @{ */ - /** - * @brief Enters the RTC Initialization mode. + * @brief Enter the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status: - * - HAL_OK : RTC is in Init mode - * - HAL_TIMEOUT : RTC is not in Init mode and in Timeout + * @param hrtc: RTC handle + * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { @@ -1322,7 +1296,6 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) /* Set the Initialization mode */ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - /* Get tick */ tickstart = HAL_GetTick(); /* Wait till RTC is in INIT state and if Time out is reached exit */ @@ -1340,7 +1313,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) /** - * @brief Converts a 2 digit decimal to BCD format. + * @brief Convert a 2 digit decimal to BCD format. * @param Value: Byte to be converted * @retval Converted byte */ @@ -1358,7 +1331,7 @@ uint8_t RTC_ByteToBcd2(uint8_t Value) } /** - * @brief Converts from 2 digit BCD to Binary. + * @brief Convert from 2 digit BCD to Binary. * @param Value: BCD value to be converted * @retval Converted word */ @@ -1368,16 +1341,17 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value) tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; return (tmp + (Value & (uint8_t)0x0F)); } - /** * @} */ #endif /* HAL_RTC_MODULE_ENABLED */ + /** * @} */ - + + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h index 277112e5ff..00047e519f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,8 +32,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0xx_HAL_RTC_H @@ -50,50 +50,50 @@ * @{ */ -/** @addtogroup RTC RTC HAL module driver +/** @defgroup RTC RTC * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup RTC_Exported_Types RTC Exported Types * @{ */ - + /** * @brief HAL State structures definition - */ + */ typedef enum { HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ - + HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ + }HAL_RTCStateTypeDef; /** - * @brief RTC Configuration Structure definition + * @brief RTC Configuration Structure definition */ typedef struct { uint32_t HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ + This parameter can be a value of @ref RTC_Hour_Formats */ uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ - - uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. - This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ - - uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. - This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ + This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ + + uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. + This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ }RTC_InitTypeDef; /** @@ -103,232 +103,163 @@ typedef struct { uint8_t Hours; /*!< Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ uint8_t Minutes; /*!< Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - + uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ - + This parameter can be a value of @ref RTC_AM_PM_Definitions */ + uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ - + uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit in CR register to store the operation. This parameter can be a value of @ref RTC_StoreOperation_Definitions */ -}RTC_TimeTypeDef; - +}RTC_TimeTypeDef; + /** - * @brief RTC Date structure definition + * @brief RTC Date structure definition */ typedef struct { uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. This parameter can be a value of @ref RTC_WeekDay_Definitions */ - + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). This parameter can be a value of @ref RTC_Month_Date_Definitions */ uint8_t Date; /*!< Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - + uint8_t Year; /*!< Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ - + }RTC_DateTypeDef; /** - * @brief RTC Alarm structure definition + * @brief RTC Alarm structure definition */ typedef struct { RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ - + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_AlarmMask_Definitions */ uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. - This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ + This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ - + uint32_t Alarm; /*!< Specifies the alarm . - This parameter can be a value of @ref RTC_Alarms_Definitions */ + This parameter can be a value of @ref RTC_Alarms_Definitions */ }RTC_AlarmTypeDef; /** - * @brief Time Handle Structure definition - */ + * @brief RTC Handle Structure definition + */ typedef struct { - RTC_TypeDef *Instance; /*!< Register base address */ - - RTC_InitTypeDef Init; /*!< RTC required parameters */ - - HAL_LockTypeDef Lock; /*!< RTC locking object */ - - __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ - + RTC_TypeDef *Instance; /*!< Register base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + }RTC_HandleTypeDef; + /** * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup RTC_Exported_Constants RTC Exported Constants * @{ */ -/** @defgroup RTC_Mask_Definition RTC Mask Definition - * @{ - */ -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) - -#define RTC_TIMEOUT_VALUE 1000 -/** - * @} - */ - /** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ - */ + */ #define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) #define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ - ((FORMAT) == RTC_HOURFORMAT_24)) /** * @} - */ + */ /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ - */ + */ #define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) #define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) - -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((POL) == RTC_OUTPUT_POLARITY_LOW)) /** * @} - */ + */ /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ - */ + */ #define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) #define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000) - -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ - ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) - /** * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider RTC Asynchronous Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) -/** - * @} - */ - -/** @defgroup RTC_Synchronous_Predivider RTC Synchronous Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions RTC Time Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) -/** - * @} - */ + */ /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ - */ + */ #define RTC_HOURFORMAT12_AM ((uint8_t)0x00) #define RTC_HOURFORMAT12_PM ((uint8_t)0x40) - -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) /** * @} - */ + */ -/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions * @{ - */ + */ #define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) #define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) #define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) - -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) /** * @} */ -/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions +/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions * @{ - */ + */ #define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) #define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) - -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ - ((OPERATION) == RTC_STOREOPERATION_SET)) /** * @} */ /** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions * @{ - */ -#define FORMAT_BIN ((uint32_t)0x000000000) -#define FORMAT_BCD ((uint32_t)0x000000001) - -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD)) -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions RTC Year Date Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) + */ +#define RTC_FORMAT_BIN ((uint32_t)0x000000000) +#define RTC_FORMAT_BCD ((uint32_t)0x000000001) /** * @} */ /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions * @{ - */ - + */ /* Coded in BCD format */ #define RTC_MONTH_JANUARY ((uint8_t)0x01) #define RTC_MONTH_FEBRUARY ((uint8_t)0x02) @@ -342,16 +273,13 @@ typedef struct #define RTC_MONTH_OCTOBER ((uint8_t)0x10) #define RTC_MONTH_NOVEMBER ((uint8_t)0x11) #define RTC_MONTH_DECEMBER ((uint8_t)0x12) - -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) /** * @} - */ + */ /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ - */ + */ #define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) #define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) #define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) @@ -359,134 +287,80 @@ typedef struct #define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) #define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) #define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) - -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) /** * @} - */ + */ -/** @defgroup RTC_Alarm_Definitions RTC Alarm Definitions +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -/** - * @} - */ - -/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions - * @{ - */ + */ #define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ - ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) /** * @} - */ + */ -/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions +/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions * @{ - */ + */ #define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) #define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 #define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 #define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) - -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) /** * @} - */ + */ /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions * @{ - */ + */ #define RTC_ALARM_A RTC_CR_ALRAE -#define IS_ALARM(ALARM) ((ALARM) == RTC_ALARM_A) /** * @} - */ + */ -/** @defgroup RTC_Alarm_Sub_Seconds_Value RTC Alarm Sub Seconds Value +/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ - */ -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) -/** - * @} - */ - - /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions - * @{ - */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds + */ +#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm +#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match +#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match to activate alarm. */ - -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_None)) /** * @} - */ + */ /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ @@ -495,9 +369,9 @@ typedef struct #define RTC_IT_WUT ((uint32_t)0x00004000) #define RTC_IT_ALRA ((uint32_t)0x00001000) #define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) -#define RTC_IT_TAMP2 ((uint32_t)0x00040000) -#define RTC_IT_TAMP3 ((uint32_t)0x00080000) +#define RTC_IT_TAMP1 ((uint32_t)0x00020000) /*only for RTC_ISR flag check*/ +#define RTC_IT_TAMP2 ((uint32_t)0x00040000) /*only for RTC_ISR flag check*/ +#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /*only for RTC_ISR flag check*/ /** * @} */ @@ -525,14 +399,14 @@ typedef struct /** * @} - */ - -/* Exported macros -----------------------------------------------------------*/ + */ + +/* Exported macros ------------------------------------------------------------*/ /** @defgroup RTC_Exported_Macros RTC Exported Macros * @{ */ - -/** @brief Reset RTC handle state + +/** @brief Reset RTC handle state * @param __HANDLE__: RTC handle. * @retval None */ @@ -557,8 +431,8 @@ typedef struct #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ do{ \ (__HANDLE__)->Instance->WPR = 0xFF; \ - } while(0) - + } while(0) + /** * @brief Enable the RTC ALARMA peripheral. * @param __HANDLE__: specifies the RTC handle. @@ -596,17 +470,27 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET) + +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) /** * @brief Get the selected RTC Alarm's flag status. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __FLAG__: specifies the RTC Alarm Flag sources to check. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRAWF @@ -617,84 +501,103 @@ typedef struct /** * @brief Clear the RTC Alarm's pending flags. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. * This parameter can be: * @arg RTC_FLAG_ALRAF * @retval None */ #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - - -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ - + /** - * @brief Enable the RTC Exti line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @brief Enable interrupt on the RTC Alarm associated Exti line. * @retval None */ -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) - -/* alias define maintained for legacy */ -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable the RTC Exti line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @brief Disable interrupt on the RTC Alarm associated Exti line. * @retval None */ -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) - -/* alias define maintained for legacy */ -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) /** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None + * @brief Enable event on the RTC Alarm associated Exti line. + * @retval None. */ -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__)) +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Clear the RTC Exti flags. - * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None + * @brief Disable event on the RTC Alarm associated Exti line. + * @retval None. */ -#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) -/* alias define maintained for legacy */ -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +/** + * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) +/** + * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Clear the RTC Alarm associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Generate a Software interrupt on RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) /** * @} */ -/* Include RTC HAL Extension module */ +/* Include RTC HAL Extended module */ #include "stm32f0xx_hal_rtc_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTC_Exported_Functions RTC Exported Functions +/** @defgroup RTC_Exported_Functions RTC Exported Functions * @{ */ -/** @addtogroup RTC_Exported_Functions_Group1 +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -707,7 +610,7 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); * @} */ -/** @addtogroup RTC_Exported_Functions_Group2 +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions * @{ */ @@ -720,7 +623,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @} */ -/** @addtogroup RTC_Exported_Functions_Group3 +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions * @{ */ /* RTC Alarm functions ********************************************************/ @@ -735,7 +638,7 @@ void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); * @} */ -/** @addtogroup RTC_Exported_Functions_Group4 +/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions * @{ */ /* Peripheral Control functions ***********************************************/ @@ -744,7 +647,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); * @} */ -/** @addtogroup RTC_Exported_Functions_Group5 +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions * @{ */ /* Peripheral State functions *************************************************/ @@ -757,23 +660,125 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @} */ -/** @addtogroup RTC_Private_Functions +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Constants RTC Private Constants * @{ - */ + */ +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ + RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ + RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ + RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ + RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) + +#define RTC_TIMEOUT_VALUE 1000 + +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC Private Macros + * @{ + */ + +/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters + * @{ + */ +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ + ((FORMAT) == RTC_HOURFORMAT_24)) + +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((POL) == RTC_OUTPUT_POLARITY_LOW)) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ + ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) +#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) + +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ + ((OPERATION) == RTC_STOREOPERATION_SET)) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) +#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ + ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) +#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A) +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) + +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); uint8_t RTC_ByteToBcd2(uint8_t Value); uint8_t RTC_Bcd2ToByte(uint8_t Value); /** * @} - */ + */ /** * @} - */ - - /** + */ + +/** * @} - */ + */ #ifdef __cplusplus } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c index 4566192adf..98255fbaa3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c @@ -2,35 +2,35 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extension peripheral: - * + RTC TimeStamp functions - * + RTC Tamper functions + * functionalities of the Real Time Clock (RTC) Extended peripheral: + * + RTC Time Stamp functions + * + RTC Tamper functions * + RTC Wake-up functions - * + Extension Control functions - * + Extension RTC features functions + * + Extended Control functions + * + Extended RTC features functions * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - (+) Enable the RTC domain access (see description in the section above). + (+) Enable the RTC domain access. (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour format using the HAL_RTC_Init() function. *** RTC Wake-up configuration *** ================================ [..] - (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() - function. You can also configure the RTC Wake-up timer in interrupt mode + (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() + function. You can also configure the RTC Wakeup timer with interrupt mode using the HAL_RTCEx_SetWakeUpTimer_IT() function. - (+) To read the RTC Wake-up Counter register, use the HAL_RTCEx_GetWakeUpTimer() + (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() function. - (@) Not available on F030x6/x8/xC and F070x6/xB + (@) Not available on F030x4/x6/x8 and F070x6 *** TimeStamp configuration *** =============================== @@ -57,14 +57,14 @@ function. (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() function. - (@) Not available on F030x6/x8/xC and F070x6/xB + (@) Not available on F030x6/x8/xC and F070x6/xB (F0xx Value Line devices) @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -98,8 +98,10 @@ * @{ */ -/** @defgroup RTCEx RTCEx Extended HAL module driver - * @brief RTCEx Extended HAL module driver + + +/** @addtogroup RTCEx + * @brief RTC Extended HAL module driver * @{ */ @@ -112,11 +114,12 @@ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions +/** @addtogroup RTCEx_Exported_Functions * @{ */ - -/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions + + +/** @addtogroup RTCEx_Exported_Functions_Group1 * @brief RTC TimeStamp and Tamper functions * @verbatim @@ -131,11 +134,10 @@ */ /** - * @brief Sets TimeStamp. - * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @brief Set TimeStamp. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc: RTC handle + * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the @@ -144,7 +146,7 @@ * falling edge of the related pin. * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) @@ -186,9 +188,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS } /** - * @brief Sets TimeStamp with Interrupt. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set TimeStamp with Interrupt. + * @param hrtc: RTC handle * @note This API must be called before enabling the TimeStamp feature. * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is * activated. @@ -199,7 +200,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS * falling edge of the related pin. * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) @@ -232,9 +233,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -248,9 +249,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti } /** - * @brief Deactivates TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Deactivate TimeStamp. + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) @@ -286,15 +286,15 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) } /** - * @brief Gets the RTC TimeStamp value. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Get the RTC TimeStamp value. + * @param hrtc: RTC handle + * @param sTimeStamp: Pointer to Time structure * @param sTimeStampDate: Pointer to Date structure * @param Format: specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) @@ -322,7 +322,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { /* Convert the TimeStamp structure parameters to Binary format */ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); @@ -342,10 +342,9 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe } /** - * @brief Sets Tamper - * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set Tamper + * @note By calling this API we disable the tamper interrupt for all tampers. + * @param hrtc: RTC handle * @param sTamper: Pointer to Tamper Structure. * @retval HAL status */ @@ -354,13 +353,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef uint32_t tmpreg = 0; /* Check the parameters */ - assert_param(IS_TAMPER(sTamper->Tamper)); - assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -403,13 +402,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType uint32_t tmpreg = 0; /* Check the parameters */ - assert_param(IS_TAMPER(sTamper->Tamper)); - assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -436,9 +435,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE; /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); - - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); hrtc->State = HAL_RTC_STATE_READY; @@ -449,16 +448,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType } /** - * @brief Deactivates Tamper. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Deactivate Tamper. + * @param hrtc: RTC handle * @param Tamper: Selected tamper pin. * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) { - assert_param(IS_TAMPER(Tamper)); + assert_param(IS_RTC_TAMPER(Tamper)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -477,9 +475,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T } /** - * @brief This function handles TimeStamp interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Handle TimeStamp interrupt request. + * @param hrtc: RTC handle * @retval None */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) @@ -491,9 +488,9 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { /* TIMESTAMP callback */ HAL_RTCEx_TimeStampEventCallback(hrtc); - + /* Clear the TIMESTAMP interrupt pending bit */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); } } @@ -503,11 +500,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the TAMPER Interrupt enable bit and pending bit */ if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET) { - /* Tamper callback */ + /* Tamper1 callback */ HAL_RTCEx_Tamper1EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + + /* Clear the Tamper1 interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); } } @@ -517,10 +514,10 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the TAMPER Interrupt enable bit and pending bit */ if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) { - /* Tamper callback */ + /* Tamper2 callback */ HAL_RTCEx_Tamper2EventCallback(hrtc); - - /* Clear the Tamper interrupt pending bit */ + + /* Clear the Tamper2 interrupt pending bit */ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); } } @@ -532,17 +529,17 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the TAMPER Interrupt enable bit and pending bit */ if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET) { - /* Tamper callback */ + /* Tamper3 callback */ HAL_RTCEx_Tamper3EventCallback(hrtc); - /* Clear the Tamper interrupt pending bit */ + /* Clear the Tamper3 interrupt pending bit */ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); } } #endif /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -550,44 +547,41 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief TimeStamp callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file */ } /** - * @brief Tamper 1 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Tamper 1 callback. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file */ } /** * @brief Tamper 2 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file */ } -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) /** * @brief Tamper 3 callback. * @param hrtc: RTC handle @@ -595,31 +589,27 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) */ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file */ } #endif /** - * @brief This function handles TimeStamp polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Handle TimeStamp polling request. + * @param hrtc: RTC handle * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); +{ + uint32_t tickstart = HAL_GetTick(); while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) { if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) { - /* Clear the TIMESTAMP Overrun Flag */ + /* Clear the TIMESTAMP OverRun Flag */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); /* Change TIMESTAMP state */ @@ -640,23 +630,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - + return HAL_OK; } /** - * @brief This function handles Tamper1 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Handle Tamper 1 Polling. + * @param hrtc: RTC handle * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); +{ + uint32_t tickstart = HAL_GetTick(); /* Get the status of the Interrupt */ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET) @@ -673,26 +659,22 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ /* Clear the Tamper Flag */ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); - + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; + + return HAL_OK; } /** - * @brief This function handles Tamper2 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Handle Tamper 2 Polling. + * @param hrtc: RTC handle * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); +{ + uint32_t tickstart = HAL_GetTick(); /* Get the status of the Interrupt */ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET) @@ -718,18 +700,14 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) /** - * @brief This function handles Tamper3 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Handle Tamper 3 Polling. + * @param hrtc: RTC handle * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); + uint32_t tickstart = HAL_GetTick(); /* Get the status of the Interrupt */ while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET) @@ -758,10 +736,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ * @} */ -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) -/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions - * @brief RTC Wake-up functions - * +#if defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @brief RTC Wake-up functions + * @verbatim =============================================================================== ##### RTC Wake-up functions ##### @@ -774,11 +752,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ */ /** - * @brief Sets wake up timer. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set wake up timer. + * @param hrtc: RTC handle * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param WakeUpClock: Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -786,8 +763,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak uint32_t tickstart = 0; /* Check the parameters */ - assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -798,8 +775,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Get tick */ + tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ @@ -819,16 +795,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } } - /* Clear the Wake-up Timer clock source bits in CR register */ + /* Clear the Wakeup Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; - /* Configure the Wake-up Timer counter */ + /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - /* Enable the Wake-up Timer */ + /* Enable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ @@ -843,9 +819,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } /** - * @brief Sets wake up timer with interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set wake up timer with interrupt. + * @param hrtc: RTC handle * @param WakeUpCounter: Wake up counter * @param WakeUpClock: Wake up clock * @retval HAL status @@ -855,8 +830,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t uint32_t tickstart = 0; /* Check the parameters */ - assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -868,7 +843,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* Get tick */ tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ @@ -888,24 +862,24 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t } } - /* Configure the Wake-up Timer counter */ + /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - /* Clear the Wake-up Timer clock source bits in CR register */ + /* Clear the Wakeup Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); /* Configure the Interrupt in the RTC_CR register */ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); - - /* Enable the Wake-up Timer */ + + /* Enable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ @@ -920,9 +894,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t } /** - * @brief Deactivates wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Deactivate wake up timer counter. + * @param hrtc: RTC handle * @retval HAL status */ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) @@ -937,15 +910,13 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Disable the Wake-up Timer */ + /* Disable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); - /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) { @@ -975,9 +946,8 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) } /** - * @brief Gets wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Get wake up timer counter. + * @param hrtc: RTC handle * @retval Counter value */ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) @@ -987,9 +957,8 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) } /** - * @brief This function handles Wake Up Timer interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Handle Wake Up Timer interrupt request. + * @param hrtc: RTC handle * @retval None */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) @@ -999,53 +968,49 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) /* Get the status of the Interrupt */ if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET) { - /* WAKEUPTIMER callback */ + /* WAKEUPTIMER callback */ HAL_RTCEx_WakeUpTimerEventCallback(hrtc); - + /* Clear the WAKEUPTIMER interrupt pending bit */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); } } /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); - + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } /** * @brief Wake Up Timer callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file */ } + /** - * @brief This function handles Wake Up Timer Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Handle Wake Up Timer Polling. + * @param hrtc: RTC handle * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); + uint32_t tickstart = HAL_GetTick(); while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; @@ -1056,7 +1021,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /* Clear the WAKEUPTIMER Flag */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1066,14 +1031,14 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** * @} */ -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */ +#endif /* defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) | defined(STM32F030xC) */ -/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions - * @brief Extension Peripheral Control functions - * +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @brief Extended Peripheral Control functions + * @verbatim =============================================================================== - ##### Extension Peripheral Control functions ##### + ##### Extended Peripheral Control functions ##### =============================================================================== [..] This subsection provides functions allowing to @@ -1096,9 +1061,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** - * @brief Writes a data in a specified RTC Backup data register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Write a data in a specified RTC Backup data register. + * @param hrtc: RTC handle * @param BackupRegister: RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to * specify the register. @@ -1111,7 +1075,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); - + tmp = (uint32_t)&(hrtc->Instance->BKP0R); tmp += (BackupRegister * 4); @@ -1121,8 +1085,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /** * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param BackupRegister: RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to * specify the register. @@ -1137,16 +1100,15 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) tmp = (uint32_t)&(hrtc->Instance->BKP0R); tmp += (BackupRegister * 4); - + /* Read the specified register */ return (*(__IO uint32_t *)tmp); } #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ /** - * @brief Sets the Smooth calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Set the Smooth calibration parameters. + * @param hrtc: RTC handle * @param SmoothCalibPeriod: Select the Smooth Calibration Period. * This parameter can be can be one of the following values : * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. @@ -1156,21 +1118,21 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) * This parameter can be one of the following values: * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. * This parameter can be one any value from 0 to 0x000001FF. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmouthCalibMinusPulsesValue must be equal to 0. + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmoothCalibMinusPulsesValue mut be equal to 0. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) { uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -1183,7 +1145,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo /* check if a calibration is pending*/ if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) { - /* Get tick */ tickstart = HAL_GetTick(); /* check if a calibration is pending*/ @@ -1206,7 +1167,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo } /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); + hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1221,10 +1182,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo } /** - * @brief Configures the Synchronization Shift Control Settings. + * @brief Configure the Synchronization Shift Control Settings. * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. * This parameter can be one of the following values : * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. @@ -1249,7 +1209,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Get tick */ tickstart = HAL_GetTick(); /* Wait until the shift is completed*/ @@ -1319,12 +1278,11 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh } /** - * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc: RTC handle * @param CalibOutput : Select the Calibration output Selection . * This parameter can be one of the following values: - * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. * @retval HAL status */ @@ -1362,9 +1320,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 } /** - * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) @@ -1392,9 +1349,8 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) } /** - * @brief Enables the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Enable the RTC reference clock detection. + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) @@ -1443,8 +1399,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Disable the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) @@ -1456,7 +1411,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - + /* Set Initialization mode */ if(RTC_EnterInitMode(hrtc) != HAL_OK) { @@ -1492,10 +1447,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) } /** - * @brief Enables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note When the Bypass Shadow is enabled the calendar value are taken + * @brief Enable the Bypass Shadow feature. + * @param hrtc: RTC handle + * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @retval HAL status */ @@ -1525,9 +1479,8 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) } /** - * @brief Disables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Disable the Bypass Shadow feature. + * @param hrtc: RTC handle * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @retval HAL status @@ -1543,7 +1496,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; + hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1566,6 +1519,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) */ #endif /* HAL_RTC_MODULE_ENABLED */ + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h index 9bc612815a..3ef1eac0d9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 - * @brief Header file of RTC HAL Extension module. + * @version V1.3.0 + * @date 26-June-2015 + * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup RTCEx +/** @defgroup RTCEx RTCEx * @{ */ @@ -100,18 +100,10 @@ typedef struct */ #define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) #define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) #define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) #endif -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP)) -#else -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA)) -#endif /** * @} */ @@ -125,8 +117,6 @@ typedef struct #define RTC_BKP_DR2 ((uint32_t)0x00000002) #define RTC_BKP_DR3 ((uint32_t)0x00000003) #define RTC_BKP_DR4 ((uint32_t)0x00000004) - -#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) /** * @} */ @@ -138,12 +128,20 @@ typedef struct #define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) #define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) -#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ - ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) /** * @} */ +/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection + * @{ + */ +#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) + +/** + * @} + */ + + /** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definition * @{ */ @@ -153,27 +151,11 @@ typedef struct #define RTC_TAMPER_3 RTC_TAFCR_TAMP3E #endif -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) -#define IS_TAMPER(TAMPER) (((TAMPER) == RTC_TAMPER_1) || \ - ((TAMPER) == RTC_TAMPER_2) || \ - ((TAMPER) == RTC_TAMPER_3)) -#else -#define IS_TAMPER(TAMPER) (((TAMPER) == RTC_TAMPER_1) || \ - ((TAMPER) == RTC_TAMPER_2)) -#endif /** * @} */ -/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection - * @{ - */ -#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000) -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13)) -/** - * @} - */ /** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definition * @{ @@ -183,10 +165,6 @@ typedef struct #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE -#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) /** * @} @@ -204,10 +182,6 @@ typedef struct #define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 consecutive samples at the active level. */ -#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ - ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) /** * @} */ @@ -232,14 +206,6 @@ typedef struct #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ -#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) /** * @} */ @@ -256,10 +222,6 @@ typedef struct #define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ -#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) /** * @} */ @@ -270,8 +232,6 @@ typedef struct #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) /** * @} */ @@ -279,11 +239,9 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definition * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling */ #define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ -#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ - ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) /** * @} */ @@ -299,14 +257,7 @@ typedef struct #define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) #define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) -#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) -#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) /** * @} */ @@ -322,9 +273,6 @@ typedef struct #define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds */ -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) /** * @} */ @@ -338,16 +286,15 @@ typedef struct #define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0] */ -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ - ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) /** * @} */ - -/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTCEx Smooth calib Minus pulses Definition + /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions * @{ */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) +#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) +#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) + /** * @} */ @@ -358,41 +305,23 @@ typedef struct #define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) #define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ - ((SEL) == RTC_SHIFTADD1S_SET)) +/** + * @} + */ + /** * @} */ -/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value RTCEx Substract Fraction Of Second Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) -/** - * @} - */ - - /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definition - * @{ - */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) -#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) - -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ - ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros * @{ */ - + +/* ---------------------------------WAKEUPTIMER---------------------------------*/ +/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer + * @{ + */ #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** * @brief Enable the RTC WakeUp Timer peripheral. @@ -400,31 +329,498 @@ typedef struct * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ /** - * @brief Enable the RTC TimeStamp peripheral. + * @brief Disable the RTC WakeUp Timer peripheral. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) + +/** + * @brief Enable the RTC WakeUpTimer interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC WakeUpTimer interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) + +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** + * @brief Get the selected RTC WakeUpTimer's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_WUTF + * @arg RTC_FLAG_WUTWF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) + +/** + * @brief Clear the RTC Wake Up timer's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_WUTF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/* WAKE-UP TIMER EXTI */ +/* ------------------ */ +/** + * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Clear the RTC WakeUp Timer associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ +/** + * @} + */ + +/* ---------------------------------TIMESTAMP---------------------------------*/ +/** @defgroup RTCEx_Timestamp RTC Timestamp + * @{ + */ +/** + * @brief Enable the RTC TimeStamp peripheral. * @param __HANDLE__: specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) /** - * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ - -/** - * @brief Disable the RTC TimeStamp peripheral. + * @brief Disable the RTC TimeStamp peripheral. * @param __HANDLE__: specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) +/** + * @brief Enable the RTC TimeStamp interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC TimeStamp interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) + +/** + * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** + * @brief Get the selected RTC TimeStamp's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TSF + * @arg RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Time Stamp's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Alarm Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TSF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @} + */ + +/* ---------------------------------TAMPER------------------------------------*/ +/** @defgroup RTCEx_Tamper RTC Tamper + * @{ + */ + +/** + * @brief Enable the RTC Tamper1 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E)) + +/** + * @brief Disable the RTC Tamper1 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E)) + +/** + * @brief Enable the RTC Tamper2 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E)) + +/** + * @brief Disable the RTC Tamper2 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E)) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) +/** + * @brief Enable the RTC Tamper3 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E)) + +/** + * @brief Disable the RTC Tamper3 input detection. + * @param __HANDLE__: specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E)) + +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ +/** + * @brief Enable the RTC Tamper interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP: Tamper interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC Tamper interrupt. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP: Tamper interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__)) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. + * This parameter can be: + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) +#else + +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. + * This parameter can be: + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) + +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ + +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__: specifies the RTC handle. + * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TAMP: Tamper interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET) + +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @arg RTC_FLAG_TAMP2F + * @arg RTC_FLAG_TAMP3F + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @arg RTC_FLAG_TAMP2F + * @arg RTC_FLAG_TAMP3F + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#else + +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @arg RTC_FLAG_TAMP2F + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__: specifies the RTC handle. + * @param __FLAG__: specifies the RTC Tamper Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F + * @arg RTC_FLAG_TAMP2F + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ +/** + * @} + */ + +/* --------------------------TAMPER/TIMESTAMP---------------------------------*/ +/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI + * @{ + */ + +/* TAMPER TIMESTAMP EXTI */ +/* --------------------- */ +/** + * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable event on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable event on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Clear the RTC Tamper and Timestamp associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) +/** + * @} + */ + +/* ------------------------------Calibration----------------------------------*/ +/** @defgroup RTCEx_Calibration RTC Calibration + * @{ + */ + /** * @brief Enable the RTC calibration output. * @param __HANDLE__: specifies the RTC handle. @@ -453,171 +849,33 @@ typedef struct */ #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) -/** - * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) -/** - * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ - -/** - * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) -/** - * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ - -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TAMP1 - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) -/** - * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ - -/** - * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) -/** - * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @arg RTC_FLAG_WUTWF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - /** * @brief Get the selected RTC shift operation's flag status. * @param __HANDLE__: specifies the RTC handle. * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_SHPF + * This parameter can be: + * @arg RTC_FLAG_SHPF * @retval None */ #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) -/** - * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) -#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */ /** * @} */ - + +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTCEx_Exported_Functions +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions * @{ */ -/** @addtogroup RTCEx_Exported_Functions_Group1 +/* RTC TimeStamp and Tamper functions *****************************************/ +/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions * @{ */ -/* RTC TimeStamp and Tamper functions *****************************************/ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); @@ -645,11 +903,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ */ #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) -/** @addtogroup RTCEx_Exported_Functions_Group2 +/* RTC Wake-up functions ******************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions * @{ */ -/* RTC Wake-up functions ******************************************************/ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); @@ -662,11 +920,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @} */ -/** @addtogroup RTCEx_Exported_Functions_Group3 +/* Extended Control functions ************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions * @{ */ - -/* Extension Control functions ************************************************/ + #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB) void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); @@ -684,20 +942,119 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); * @} */ -/* Extension RTC features functions *******************************************/ +/* Extended RTC features functions *******************************************/ /** * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Constants RTCEx Private Constants + * @{ + */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR19) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR20) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Macros RTCEx Private Macros + * @{ + */ + +/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters + * @{ + */ +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP)) +#else +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA)) +#endif + +#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) + +#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ + ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) +#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) + +#else +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) + +#endif + +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) + + +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) +#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ + ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) +#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) +#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) +#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) + +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) + + +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ + ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) + + +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ + ((SEL) == RTC_SHIFTADD1S_SET)) +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ + ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) +/** + * @} + */ + /** * @} */ /** * @} - */ + */ +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c index 27cd92a6b9..f1a13592e7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c @@ -2,109 +2,112 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief SMARTCARD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions * + Peripheral Control functions * - @verbatim - =============================================================================== + @verbatim + ============================================================================== ##### How to use this driver ##### - =============================================================================== - [..] + ============================================================================== + [..] The SMARTCARD HAL driver can be used as follows: - - (#) Declare a SMARTCARD_HandleTypeDef handle structure. - (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit ()API: + + (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard). + (#) Associate a USART to the SMARTCARD handle hsmartcard. + (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: (++) Enable the USARTx interface clock. - (++) SMARTCARD pins configuration: - (+++) Enable the clock for the SMARTCARD GPIOs. - (+++) Configure these SMARTCARD pins as alternate function pull-up. + (++) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() and HAL_SMARTCARD_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission - error enabling or disabling in the hsmartcard Init structure. - - (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...) - in the hsmartcard AdvancedInit structure. + error enabling or disabling in the hsmartcard handle Init structure. - (#) Initialize the SMARTCARD associated USART registers by calling the HAL_SMARTCARD_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) by - calling the customed HAL_SMARTCARD_MspInit() API. - - -@@- The specific SMARTCARD interrupts (Transmission complete interrupt, + (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...) + in the hsmartcard handle AdvancedInit structure. + + (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API: + (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SMARTCARD_MspInit() API. + [..] + (@) The specific SMARTCARD interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. - (#) Three operation modes are available within this driver : - + [..] + [..] Three operation modes are available within this driver : + *** Polling mode IO operation *** ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() + [..] + (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT() - (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT() - (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback - (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback - *** DMA mode IO operation *** + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback() + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback() + + *** DMA mode IO operation *** ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() - (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() - (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback - (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback() + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback() *** SMARTCARD HAL driver macros list *** ======================================== [..] Below the list of most used macros in SMARTCARD HAL driver. - - (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral - (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral - (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not + + (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral + (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral + (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt - - [..] + (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled + + [..] (@) You can refer to the SMARTCARD HAL driver header file for more useful macros @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -128,7 +131,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -136,35 +139,35 @@ #ifdef HAL_SMARTCARD_MODULE_ENABLED -#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** @addtogroup STM32F0xx_HAL_Driver * @{ */ -/** @defgroup SMARTCARD SMARTCARD HAL module driver +/** @defgroup SMARTCARD SMARTCARD * @brief HAL SMARTCARD module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ -#define TEACK_REACK_TIMEOUT 1000 +/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants + * @{ + */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */ #define SMARTCARD_TXDMA_TIMEOUTVALUE 22000 #define SMARTCARD_TIMEOUT_VALUE 22000 #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ /** * @} */ - -/* Private macro -------------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions @@ -172,88 +175,88 @@ */ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard); -static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); /** * @} */ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions * @{ */ -/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in Smartcard mode. +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx + associated to the SmartCard. [..] The Smartcard interface is designed to support asynchronous protocol Smartcards as defined in the ISO 7816-3 standard. [..] The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived + In smartcard mode, SCLK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. [..] - (+) For the Smartcard mode only these parameters can be configured: - (++) Baud Rate - (++) Parity: parity should be enabled, - Frame Length is fixed to 8 bits plus parity: - the USART frame format is given in the following table: - +---------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|-----------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +---------------------------------------------------------------+ - or - +---------------------------------------------------------------+ - | M1M0 bits | PCE bit | USART frame | - |-----------------------|---------------------------------------| - | 01 | 1 | | SB | 8 bit data | PB | STB | | - +---------------------------------------------------------------+ + (+) These parameters can be configured: + (++) Baud Rate + (++) Parity: parity should be enabled, + Frame Length is fixed to 8 bits plus parity: + the SMARTCARD frame format is given in the following table: + (+++) +---------------------------------------------------------------+ + (+++) | M bit | PCE bit | SMARTCARD frame | + (+++) |---------------------|-----------------------------------------| + (+++) | 1 | 1 | | SB | 8 bit data | PB | STB | | + (+++) +---------------------------------------------------------------+ + (+++) or + (+++) +---------------------------------------------------------------+ + (+++) | M1M0 bits | PCE bit | SMARTCARD frame | + (+++) |-----------------------|---------------------------------------| + (+++) | 01 | 1 | | SB | 8 bit data | PB | STB | | + (+++) +---------------------------------------------------------------+ - (++) Receiver/transmitter modes - (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) - (++) Prescaler value - (++) Guard bit time - (++) NACK enabling or disabling on transmission error + (++) Receiver/transmitter modes + (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) + (++) Prescaler value + (++) Guard bit time + (++) NACK enabling or disabling on transmission error - (+) The following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) Time out enabling (and if activated, timeout value) - (++) Block length - (++) Auto-retry counter - - [..] - The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures - (details for the procedures are available in reference manual). + (+) The following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) Time out enabling (and if activated, timeout value) + (++) Block length + (++) Auto-retry counter + [..] + The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures + (details for the procedures are available in reference manual). @endverbatim * @{ */ /** - * @brief Initializes the SMARTCARD mode according to the specified - * parameters in the SMARTCARD_InitTypeDef and creates the associated handle . - * @param hsmartcard: SMARTCARD handle + * @brief Initialize the SMARTCARD mode according to the specified + * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) @@ -263,52 +266,56 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) { return HAL_ERROR; } - + /* Check the USART associated to the SmartCard */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); - + if(hsmartcard->State == HAL_SMARTCARD_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + hsmartcard->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_SMARTCARD_MspInit(hsmartcard); } - + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + /* Set the SMARTCARD Communication parameters */ if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR) { return HAL_ERROR; - } - + } + if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT) { SMARTCARD_AdvFeatureConfig(hsmartcard); } - - /* In SmartCard mode, the following bits must be kept cleared: + + /* In SmartCard mode, the following bits must be kept cleared: - LINEN in the USART_CR2 register, - HDSEL and IREN bits in the USART_CR3 register.*/ - hsmartcard->Instance->CR2 &= ~(USART_CR2_LINEN); - hsmartcard->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN); - - /* set the USART in SMARTCARD mode */ - hsmartcard->Instance->CR3 |= USART_CR3_SCEN; - + hsmartcard->Instance->CR2 &= ~(USART_CR2_LINEN); + hsmartcard->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN); + + /* set the USART in SMARTCARD mode */ + hsmartcard->Instance->CR3 |= USART_CR3_SCEN; + /* Enable the Peripheral */ __HAL_SMARTCARD_ENABLE(hsmartcard); - + /* TEACK and/or REACK to check before moving hsmartcard->State to Ready */ return (SMARTCARD_CheckIdleState(hsmartcard)); } /** - * @brief DeInitializes the SMARTCARD peripheral - * @param hsmartcard: SMARTCARD handle + * @brief DeInitialize the SMARTCARD peripheral. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) @@ -318,135 +325,140 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_SMARTCARD_DISABLE(hsmartcard); - + hsmartcard->Instance->CR1 = 0x0; hsmartcard->Instance->CR2 = 0x0; hsmartcard->Instance->CR3 = 0x0; hsmartcard->Instance->RTOR = 0x0; hsmartcard->Instance->GTPR = 0x0; - + /* DeInit the low level hardware */ HAL_SMARTCARD_MspDeInit(hsmartcard); hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->State = HAL_SMARTCARD_STATE_RESET; - + /* Process Unlock */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } /** - * @brief SMARTCARD MSP Init - * @param hsmartcard: SMARTCARD handle + * @brief Initialize the SMARTCARD MSP. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspInit can be implemented in the user file - */ + */ } /** - * @brief SMARTCARD MSP DeInit - * @param hsmartcard: SMARTCARD handle + * @brief DeInitialize the SMARTCARD MSP. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMARTCARD_MspDeInit can be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions - * @brief SMARTCARD Transmit and Receive functions +/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions + * @brief SMARTCARD Transmit and Receive functions * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== [..] This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. [..] - Smartcard is a single wire half duplex communication protocol. + Smartcard is a single wire half duplex communication protocol. The Smartcard interface is designed to support asynchronous protocol Smartcards as defined in the ISO 7816-3 standard. The USART should be configured as: - - 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register - - 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. + (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register + (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API s return the HAL status. - The end of the data processing will be indicated through the - dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process - The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected + [..] + (+) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, the relevant API's return the HAL status. + The end of the data processing will be indicated through the + dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + will be executed respectively at the end of the Transmit or Receive process + The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication + error is detected. - (#) Blocking mode API s are : + (+) Blocking mode APIs are : (++) HAL_SMARTCARD_Transmit() - (++) HAL_SMARTCARD_Receive() - - (#) Non Blocking mode API s with Interrupt are : + (++) HAL_SMARTCARD_Receive() + + (+) Non Blocking mode APIs with Interrupt are : (++) HAL_SMARTCARD_Transmit_IT() (++) HAL_SMARTCARD_Receive_IT() (++) HAL_SMARTCARD_IRQHandler() - (#) Non Blocking mode functions with DMA are : + (+) Non Blocking mode functions with DMA are : (++) HAL_SMARTCARD_Transmit_DMA() (++) HAL_SMARTCARD_Receive_DMA() - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SMARTCARD_TxCpltCallback() (++) HAL_SMARTCARD_RxCpltCallback() (++) HAL_SMARTCARD_ErrorCallback() - + @endverbatim * @{ */ /** - * @brief Send an amount of data in blocking mode - * @param hsmartcard: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout : Timeout duration + * @brief Send an amount of data in blocking mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. + * @param Timeout : Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) { if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Check if a non-blocking receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; } @@ -454,24 +466,24 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; } - + hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; while(hsmartcard->TxXferCount > 0) { - hsmartcard->TxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) - { + hsmartcard->TxXferCount--; + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) + { return HAL_TIMEOUT; - } - hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF); + } + hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF); } - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) - { + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } /* Check if a non-blocking receive Process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; } @@ -479,216 +491,220 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui { hsmartcard->State = HAL_SMARTCARD_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in blocking mode - * @param hsmartcard: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout : Timeout duration + * @brief Receive an amount of data in blocking mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. + * @param Timeout : Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ +{ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)) - { - if((pData == NULL) || (Size == 0)) + { + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Check if a non-blocking transmit process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; } else { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - - hsmartcard->RxXferSize = Size; + } + + hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; /* Check the remain data to be received */ while(hsmartcard->RxXferCount > 0) { - hsmartcard->RxXferCount--; - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + hsmartcard->RxXferCount--; + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { return HAL_TIMEOUT; - } - *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); + } + *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); } - + /* Check if a non-blocking transmit Process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; } else { hsmartcard->State = HAL_SMARTCARD_STATE_READY; - } - + } + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Send an amount of data in interrupt mode - * @param hsmartcard: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in interrupt mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->pTxBuffPtr = pData; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; - + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; } else { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - + } + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - + /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - + __HAL_UNLOCK(hsmartcard); + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TXE); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in interrupt mode - * @param hsmartcard: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in interrupt mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->pRxBuffPtr = pData; hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; - - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Check if a transmit process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; } else { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - + } + /* Enable the SMARTCARD Parity Error Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE); - + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + /* Enable the SMARTCARD Data Register not empty Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Send an amount of data in DMA mode - * @param hsmartcard: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in DMA mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - + if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->pTxBuffPtr = pData; hsmartcard->TxXferSize = Size; - hsmartcard->TxXferCount = Size; - - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->TxXferCount = Size; + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; } @@ -696,72 +712,76 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; } - + /* Set the SMARTCARD DMA transfer complete callback */ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; - + /* Set the SMARTCARD error callback */ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError; /* Enable the SMARTCARD transmit DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hsmartcard->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsmartcard->Instance->TDR, Size); - + + /* Clear the TC flag in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_TCF); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the SMARTCARD associated USART CR3 register */ hsmartcard->Instance->CR3 |= USART_CR3_DMAT; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in DMA mode - * @param hsmartcard: SMARTCARD handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), - * the received data contain the parity bit (MSB position) + * @brief Receive an amount of data in DMA mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. + * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), + * the received data contain the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - + if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->pRxBuffPtr = pData; hsmartcard->RxXferSize = Size; hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a transmit rocess is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) + /* Check if a transmit process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; } else { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - + } + /* Set the SMARTCARD DMA transfer complete callback */ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; - + /* Set the SMARTCARD DMA error callback */ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError; @@ -769,69 +789,70 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, *(uint32_t*)tmp, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the SMARTCARD associated USART CR3 register */ hsmartcard->Instance->CR3 |= USART_CR3_DMAR; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } - + /** - * @brief SMARTCARD interrupt requests handling. - * @param hsmartcard: SMARTCARD handle + * @brief Handle SMARTCARD interrupt requests. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { /* SMARTCARD parity error interrupt occurred -------------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_PE) != RESET)) - { + { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; /* Set the SMARTCARD state ready to be able to start again the process */ hsmartcard->State = HAL_SMARTCARD_STATE_READY; } - - /* SMARTCARD frame error interrupt occured --------------------------------------*/ + + /* SMARTCARD frame error interrupt occurred --------------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET)) - { + { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; /* Set the SMARTCARD state ready to be able to start again the process */ hsmartcard->State = HAL_SMARTCARD_STATE_READY; } - - /* SMARTCARD noise error interrupt occured --------------------------------------*/ + + /* SMARTCARD noise error interrupt occurred --------------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET)) - { + { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; /* Set the SMARTCARD state ready to be able to start again the process */ hsmartcard->State = HAL_SMARTCARD_STATE_READY; } - - /* SMARTCARD Over-Run interrupt occured -----------------------------------------*/ + + /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET)) - { + { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; /* Set the SMARTCARD state ready to be able to start again the process */ hsmartcard->State = HAL_SMARTCARD_STATE_READY; } - - /* SMARTCARD receiver timeout interrupt occured -----------------------------------------*/ + + /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RTO) != RESET)) - { + { __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; /* Set the SMARTCARD state ready to be able to start again the process */ hsmartcard->State = HAL_SMARTCARD_STATE_READY; } @@ -840,105 +861,108 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) { HAL_SMARTCARD_ErrorCallback(hsmartcard); - } - + } + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET)) - { + { SMARTCARD_Receive_IT(hsmartcard); /* Clear RXNE interrupt flag */ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); } - + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET)) - { + { hsmartcard->State = HAL_SMARTCARD_STATE_READY; - __HAL_UNLOCK(hsmartcard); + __HAL_UNLOCK(hsmartcard); HAL_SMARTCARD_RxCpltCallback(hsmartcard); /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information * to be available during HAL_SMARTCARD_RxCpltCallback() processing */ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); - } + } /* SMARTCARD in mode Transmitter ------------------------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET)) { SMARTCARD_Transmit_IT(hsmartcard); - } - + } + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET)) { SMARTCARD_EndTransmit_IT(hsmartcard); - } -} + } +} /** - * @brief Tx Transfer completed callbacks - * @param hsmartcard: SMARTCARD handle + * @brief Tx Transfer completed callback. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file - */ + the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. + */ } /** - * @brief Rx Transfer completed callbacks - * @param hsmartcard: SMARTCARD handle + * @brief Rx Transfer completed callback. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file + the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. */ } /** - * @brief SMARTCARD error callbacks - * @param hsmartcard: SMARTCARD handle + * @brief SMARTCARD error callback. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) +__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_ErrorCallback can be implemented in the user file - */ + the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. + */ } /** * @} */ - -/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions + +/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SMARTCARD State and Errors functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] + ============================================================================== + [..] This subsection provides a set of functions allowing to return the State of SmartCard - communication process and also return Peripheral Errors occurred during communication process - (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SMARTCARD peripheral - (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during - communication. - - (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral - (+) SMARTCARD_AdvFeatureConfig() API optionally configures the SMARTCARD advanced features - (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + handle and also return Peripheral Errors occurred during communication process + (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state + of the SMARTCARD peripheral. + (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during + communication. + @endverbatim * @{ */ + /** - * @brief return the SMARTCARD state - * @param hsmartcard: SMARTCARD handle - * @retval HAL state + * @brief Return the SMARTCARD handle state. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD handle state */ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) { @@ -946,10 +970,10 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar } /** -* @brief Return the SMARTCARD error code -* @param hsmartcard : pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD. -* @retval SMARTCARD Error Code + * @brief Return the SMARTCARD handle error code. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. +* @retval SMARTCARD handle Error Code */ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) { @@ -959,48 +983,164 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) /** * @} */ - + /** * @} - */ + */ /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions * @{ */ - + /** - * @brief This function handles SMARTCARD Communication Timeout. - * @param hsmartcard: SMARTCARD handle - * @param Flag: specifies the SMARTCARD flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @brief Send an amount of data in non-blocking mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() * @retval HAL status */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + { + + if(hsmartcard->TxXferCount == 0) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); + + return HAL_OK; + } + else + { + hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); + hsmartcard->TxXferCount--; + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; + } + else + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + HAL_SMARTCARD_TxCpltCallback(hsmartcard); + + return HAL_OK; +} + + +/** + * @brief Receive an amount of data in non-blocking mode. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT(). + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + { + + *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + + if(--hsmartcard->RxXferCount == 0) + { + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); + + /* Check if a transmit Process is ongoing or not */ + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + { + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; + } + else + { + /* Disable the SMARTCARD Parity Error Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); + + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); + + hsmartcard->State = HAL_SMARTCARD_STATE_READY; + } + + HAL_SMARTCARD_RxCpltCallback(hsmartcard); + + return HAL_OK; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Handle SMARTCARD Communication Timeout. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param Flag: specifies the SMARTCARD flag to check. + * @param Status: The new Flag status (SET or RESET). + * @param Timeout: Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - + /* Wait until flag is set */ if(Status == RESET) - { + { while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) == RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - + hsmartcard->State= HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_TIMEOUT; } } @@ -1012,64 +1152,64 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - + hsmartcard->State= HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - + return HAL_TIMEOUT; } } } } - return HAL_OK; + return HAL_OK; } /** - * @brief DMA SMARTCARD transmit process complete callback. + * @brief DMA SMARTCARD transmit process complete callback. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) { SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hsmartcard->TxXferCount = 0; - + /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); - - /* Enable the SMARTCARD Transmit Complete Interrupt */ + + /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); } /** - * @brief DMA SMARTCARD receive process complete callback. + * @brief DMA SMARTCARD receive process complete callback. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hsmartcard->RxXferCount = 0; - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the SMARTCARD associated USART CR3 register */ hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR); - + /* Check if a transmit Process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) { hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; } @@ -1077,17 +1217,17 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { hsmartcard->State = HAL_SMARTCARD_STATE_READY; } - + HAL_SMARTCARD_RxCpltCallback(hsmartcard); } /** - * @brief DMA SMARTCARD communication error callback. + * @brief DMA SMARTCARD communication error callback. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) { SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; hsmartcard->RxXferCount = 0; @@ -1098,159 +1238,46 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief Send an amount of data in non blocking mode - * @param hsmartcard: SMARTCARD handle. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) -{ - if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) - { - - if(hsmartcard->TxXferCount == 0) - { - /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE); - - /* Enable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); - - return HAL_OK; - } - else - { - hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF); - hsmartcard->TxXferCount--; - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - - hsmartcard->State = HAL_SMARTCARD_STATE_READY; - } - - HAL_SMARTCARD_TxCpltCallback(hsmartcard); - - return HAL_OK; -} - - -/** - * @brief Receive an amount of data in non blocking mode - * @param hsmartcard: SMARTCARD handle. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard) -{ - if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)) - { - - *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); - - if(--hsmartcard->RxXferCount == 0) - { - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE); - - /* Check if a transmit Process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - /* Disable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE); - - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - - hsmartcard->State = HAL_SMARTCARD_STATE_READY; - } - - HAL_SMARTCARD_RxCpltCallback(hsmartcard); - - return HAL_OK; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure the SMARTCARD associated USART peripheral - * @param hsmartcard: SMARTCARD handle + * @brief Configure the SMARTCARD associated USART peripheral. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t tmpreg = 0x00000000; SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED; - HAL_StatusTypeDef ret = HAL_OK; - - /* Check the parameters */ + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); - assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate)); - assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength)); - assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits)); + assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate)); + assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength)); + assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits)); assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity)); assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode)); assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity)); assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase)); - assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit)); - assert_param(IS_SMARTCARD_ONEBIT_SAMPLING(hsmartcard->Init.OneBitSampling)); + assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit)); + assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling)); assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable)); assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable)); - assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount)); + assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount)); /*-------------------------- USART CR1 Configuration -----------------------*/ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity). * Oversampling is forced to 16 (OVER8 = 0). - * Configure the Parity and Mode: + * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; - /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor - the bidirectional line to detect a NACK signal in case of parity error. + /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLED)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { - tmpreg |= USART_CR1_RE; + tmpreg |= USART_CR1_RE; } tmpreg |= (uint32_t) hsmartcard->Init.WordLength; MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); @@ -1259,157 +1286,170 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /* Stop bits are forced to 1.5 (STOP = 11) */ tmpreg = hsmartcard->Init.StopBits; /* Synchronous mode is activated by default */ - tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - one-bit sampling method versus three samples' majority rule - * according to hsmartcard->Init.OneBitSampling - * - NACK transmission in case of parity error according - * to hsmartcard->Init.NACKEnable + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - one-bit sampling method versus three samples' majority rule + * according to hsmartcard->Init.OneBitSampling + * - NACK transmission in case of parity error according + * to hsmartcard->Init.NACKEnable * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS); MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg); - + /*-------------------------- USART GTPR Configuration ----------------------*/ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS)); - MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg); - - /*-------------------------- USART RTOR Configuration ----------------------*/ + MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg); + + /*-------------------------- USART RTOR Configuration ----------------------*/ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS); - if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLED) + if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) { assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg); - - /*-------------------------- USART BRR Configuration -----------------------*/ - __HAL_SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); + + /*-------------------------- USART BRR Configuration -----------------------*/ + SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); switch (clocksource) { - case SMARTCARD_CLOCKSOURCE_PCLK1: + case SMARTCARD_CLOCKSOURCE_PCLK1: hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsmartcard->Init.BaudRate); break; - case SMARTCARD_CLOCKSOURCE_HSI: - hsmartcard->Instance->BRR = (uint16_t)(HSI_VALUE / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_SYSCLK: - hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_LSE: - hsmartcard->Instance->BRR = (uint16_t)(LSE_VALUE / hsmartcard->Init.BaudRate); + case SMARTCARD_CLOCKSOURCE_HSI: + hsmartcard->Instance->BRR = (uint16_t)(HSI_VALUE / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_SYSCLK: + hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_LSE: + hsmartcard->Instance->BRR = (uint16_t)(LSE_VALUE / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; break; - case SMARTCARD_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; } - - return ret; -} - -/** - * @brief Check the SMARTCARD Idle State - * @param hsmartcard: SMARTCARD handle - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) -{ - - /* Initialize the SMARTCARD ErrorCode */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if the Transmitter is enabled */ - if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) - { - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) - { - return HAL_TIMEOUT; - } - } - - /* Initialize the SMARTCARD state*/ - hsmartcard->State= HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - return HAL_OK; + return ret; } - + + /** - * @brief Configure the SMARTCARD associated USART peripheral advanced feautures - * @param hsmartcard: SMARTCARD handle + * @brief Configure the SMARTCARD associated USART peripheral advanced features. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval None */ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Check whether the set of advanced features to configure is properly set */ +{ + /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit)); - + /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT)) { assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert); } - + /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT)) { assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert); } - + /* if required, configure data inversion */ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT)) { assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert)); MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert); } - + /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT)) { assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap)); MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap); } - + /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { - assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable)); + assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable)); MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable); } - + /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT)) { - assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError)); + assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError)); MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError); } - - /* if required, configure MSB first on communication line */ + + /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) { - assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst)); + assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst)); MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst); - } + } + +} + +/** + * @brief Check the SMARTCARD Idle State. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) +{ + + /* Initialize the SMARTCARD ErrorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices). + Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature. + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) + if (IS_UART_WAKEUP_INSTANCE(hsmartcard->Instance)) + { + /* Check if the Transmitter is enabled */ + if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + { + return HAL_TIMEOUT; + } + } + } +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ + + /* Initialize the SMARTCARD state*/ + hsmartcard->State= HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; } /** @@ -1424,7 +1464,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) * @} */ -#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ #endif /* HAL_SMARTCARD_MODULE_ENABLED */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h index b5d5746f04..cb8fcfc3d0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -54,23 +54,22 @@ /** @addtogroup SMARTCARD * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types * @{ - */ + */ - -/** - * @brief SMARTCARD Init Structure definition - */ +/** + * @brief SMARTCARD Init Structure definition + */ typedef struct { uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate. The baud rate register is computed using the following formula: Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */ - + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ @@ -82,7 +81,7 @@ typedef struct @note The parity is enabled by default (PCE is forced to 1). Since the WordLength is forced to 8 bits + parity, M is forced to 1 and the parity bit is the 9th bit. */ - + uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref SMARTCARD_Mode */ @@ -95,85 +94,85 @@ typedef struct uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler */ - + uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time */ - + uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled in case of parity error. - This parameter can be a value of @ref SMARTCARD_NACK_Enable */ - - uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled. + This parameter can be a value of @ref SMARTCARD_NACK_Enable */ + + uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled. This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/ - - uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks: - it is used to implement the Character Wait Time (CWT) and - Block Wait Time (BWT). It is coded over 24 bits. */ - + + uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks: + it is used to implement the Character Wait Time (CWT) and + Block Wait Time (BWT). It is coded over 24 bits. */ + uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode. - This parameter can be any value from 0x0 to 0xFF */ - + This parameter can be any value from 0x0 to 0xFF */ + uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in - receive and transmit mode). When set to 0, retransmission is + receive and transmit mode). When set to 0, retransmission is disabled. Otherwise, its maximum value is 7 (before signalling - an error) */ - + an error) */ + }SMARTCARD_InitTypeDef; -/** - * @brief SMARTCARD advanced features initalization structure definition +/** + * @brief SMARTCARD advanced features initalization structure definition */ -typedef struct +typedef struct { uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several - advanced features may be initialized at the same time. This parameter - can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */ + advanced features may be initialized at the same time. This parameter + can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. This parameter can be a value of @ref SMARTCARD_Tx_Inv */ - + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. This parameter can be a value of @ref SMARTCARD_Rx_Inv */ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of @ref SMARTCARD_Data_Inv */ - - uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */ - - uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. This parameter can be a value of @ref SMARTCARD_Overrun_Disable */ - - uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */ - - uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ }SMARTCARD_AdvFeatureInitTypeDef; -/** - * @brief HAL State structures definition - */ +/** + * @brief HAL State structures definition + */ typedef enum { HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ }HAL_SMARTCARD_StateTypeDef; -/** - * @brief SMARTCARD clock sources +/** + * @brief SMARTCARD clock sources */ typedef enum { @@ -181,43 +180,43 @@ typedef enum SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ + SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ }SMARTCARD_ClockSourceTypeDef; -/** - * @brief SMARTCARD handle Structure definition - */ +/** + * @brief SMARTCARD handle Structure definition + */ typedef struct { USART_TypeDef *Instance; /*!< USART registers base address */ - + SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ - + SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ - + uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ - + uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ - + uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ - + uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ - + uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ - + uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ - + DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ - + DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ - + HAL_LockTypeDef Lock; /*!< Locking object */ - - HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */ - + + __IO HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */ + __IO uint32_t ErrorCode; /*!< SmartCard Error code This parameter can be a value of @ref SMARTCARD_Error */ - + }SMARTCARD_HandleTypeDef; /** @@ -225,11 +224,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants +/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants * @{ */ -/** @defgroup SMARTCARD_Error SMARTCARD Error +/** @defgroup SMARTCARD_Error SMARTCARD Error * @{ */ #define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ @@ -243,73 +242,64 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length +/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length * @{ */ -#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) -#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B) +#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */ /** * @} */ - -/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits - * @{ - */ -#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP)) -#define IS_SMARTCARD_STOPBITS(STOPBITS) ((STOPBITS) == SMARTCARD_STOPBITS_1_5) -/** - * @} - */ -/** @defgroup SMARTCARD_Parity SMARTCARD Parity +/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits * @{ - */ -#define SMARTCARD_PARITY_EVEN ((uint16_t)USART_CR1_PCE) -#define SMARTCARD_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \ - ((PARITY) == SMARTCARD_PARITY_ODD)) + */ +#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */ /** * @} - */ + */ -/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode +/** @defgroup SMARTCARD_Parity SMARTCARD Parity * @{ - */ -#define SMARTCARD_MODE_RX ((uint16_t)USART_CR1_RE) -#define SMARTCARD_MODE_TX ((uint16_t)USART_CR1_TE) -#define SMARTCARD_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) + */ +#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */ +#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */ /** * @} */ -/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity +/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode * @{ */ -#define SMARTCARD_POLARITY_LOW ((uint16_t)0x0000) -#define SMARTCARD_POLARITY_HIGH ((uint16_t)USART_CR2_CPOL) -#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) +#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */ +#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */ +#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */ /** * @} - */ + */ + +/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity + * @{ + */ +#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) /*!< SMARTCARD frame low polarity */ +#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */ +/** + * @} + */ /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase * @{ */ -#define SMARTCARD_PHASE_1EDGE ((uint16_t)0x0000) -#define SMARTCARD_PHASE_2EDGE ((uint16_t)USART_CR2_CPHA) -#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) +#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SMARTCARD frame phase on first clock transition */ +#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */ /** * @} */ -/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit +/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit * @{ */ -#define SMARTCARD_LASTBIT_DISABLED ((uint16_t)0x0000) -#define SMARTCARD_LASTBIT_ENABLED ((uint16_t)USART_CR2_LBCL) -#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLED) || \ - ((LASTBIT) == SMARTCARD_LASTBIT_ENABLED)) +#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ +#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ /** * @} */ @@ -317,56 +307,42 @@ typedef struct /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method * @{ */ -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED ((uint16_t)0x0000) -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED ((uint16_t)USART_CR3_ONEBIT) -#define IS_SMARTCARD_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_DISABLED) || \ - ((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_ENABLED)) +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame one-bit sample disabled */ +#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */ /** * @} - */ + */ -/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable +/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable * @{ */ -#define SMARTCARD_NACK_ENABLED ((uint16_t)USART_CR3_NACK) -#define SMARTCARD_NACK_DISABLED ((uint16_t)0x0000) -#define IS_SMARTCARD_NACK(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \ - ((NACK) == SMARTCARD_NACK_DISABLED)) +#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */ +#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD NACK transmission enabled */ /** * @} */ -/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable +/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable * @{ */ -#define SMARTCARD_TIMEOUT_DISABLED ((uint32_t)0x00000000) -#define SMARTCARD_TIMEOUT_ENABLED ((uint32_t)USART_CR2_RTOEN) -#define IS_SMARTCARD_TIMEOUT(TIMEOUT) (((TIMEOUT) == SMARTCARD_TIMEOUT_DISABLED) || \ - ((TIMEOUT) == SMARTCARD_TIMEOUT_ENABLED)) +#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD receiver timeout disabled */ +#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */ /** * @} */ - + /** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type * @{ */ -#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) -#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) -#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) -#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) -#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) -#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) -#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) -#define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ - SMARTCARD_ADVFEATURE_TXINVERT_INIT | \ - SMARTCARD_ADVFEATURE_RXINVERT_INIT | \ - SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \ - SMARTCARD_ADVFEATURE_SWAP_INIT | \ - SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \ - SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) +#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */ +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */ +#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */ +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */ +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */ /** * @} */ @@ -374,10 +350,8 @@ typedef struct /** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion * @{ */ -#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) -#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ - ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */ /** * @} */ @@ -385,86 +359,75 @@ typedef struct /** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion * @{ */ -#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) -#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ - ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */ /** * @} */ -/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion +/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion * @{ */ -#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) -#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ - ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */ +#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */ /** * @} - */ - + */ + /** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap * @{ */ -#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) -#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ - ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */ +#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */ /** * @} - */ + */ -/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable +/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable * @{ */ -#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) -#define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ - ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */ +#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */ /** * @} - */ + */ -/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error +/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error * @{ */ -#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) -#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ - ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */ +#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */ /** * @} - */ + */ /** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first * @{ */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) -#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) -#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ - ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */ /** * @} - */ + */ -/** @defgroup SMARTCARD_Flags SMARTCARD Flags +/** @defgroup SMARTCARD_Flags SMARTCARD Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register * @{ */ -#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000) -#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000) -#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000) -#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000) -#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800) -#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080) -#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040) -#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020) -#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008) -#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004) -#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002) -#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001) +#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ +#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ +#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ +#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ +#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ +#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */ +#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ +#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */ +#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ +#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ +#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ +#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ +#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ /** * @} */ @@ -479,34 +442,67 @@ typedef struct * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ - -#define SMARTCARD_IT_PE ((uint16_t)0x0028) -#define SMARTCARD_IT_TXE ((uint16_t)0x0727) -#define SMARTCARD_IT_TC ((uint16_t)0x0626) -#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) - -#define SMARTCARD_IT_ERR ((uint16_t)0x0060) -#define SMARTCARD_IT_ORE ((uint16_t)0x0300) -#define SMARTCARD_IT_NE ((uint16_t)0x0200) -#define SMARTCARD_IT_FE ((uint16_t)0x0100) -#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) -#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) +#define SMARTCARD_IT_PE ((uint16_t)0x0028) /*!< SMARTCARD parity error interruption */ +#define SMARTCARD_IT_TXE ((uint16_t)0x0727) /*!< SMARTCARD transmit data register empty interruption */ +#define SMARTCARD_IT_TC ((uint16_t)0x0626) /*!< SMARTCARD transmission complete interruption */ +#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) /*!< SMARTCARD read data register not empty interruption */ +#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) /*!< SMARTCARD idle line detection interruption */ + +#define SMARTCARD_IT_ERR ((uint16_t)0x0060) /*!< SMARTCARD error interruption */ +#define SMARTCARD_IT_ORE ((uint16_t)0x0300) /*!< SMARTCARD overrun error interruption */ +#define SMARTCARD_IT_NE ((uint16_t)0x0200) /*!< SMARTCARD noise error interruption */ +#define SMARTCARD_IT_FE ((uint16_t)0x0100) /*!< SMARTCARD frame error interruption */ + +#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) /*!< SMARTCARD receiver timeout interruption */ /** * @} - */ - + */ /** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags * @{ */ -#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ -#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ +#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ +#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */ +#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ +#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ +#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ +#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ +#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ +/** + * @} + */ + +/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register + * @{ + */ +#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) /*!< SMARTCARD auto retry counter LSB position in CR3 register */ +/** + * @} + */ + +/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register + * @{ + */ +#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) /*!< SMARTCARD guard time value LSB position in GTPR register */ +/** + * @} + */ + +/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register + * @{ + */ +#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) /*!< SMARTCARD block length LSB position in RTOR register */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask + * @{ + */ +#define SMARTCARD_IT_MASK ((uint16_t)0x001F) /*!< SMARTCARD interruptions flags mask */ /** * @} */ @@ -516,151 +512,178 @@ typedef struct */ #define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ #define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ -#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ - ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST)) /** * @} */ - - -/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register - * @{ - */ -#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) + /** * @} */ - -/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register - * @{ - */ -#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) -/** - * @} - */ - -/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register - * @{ - */ -#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) -/** - * @} - */ - -/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flag mask - * @{ - */ -#define SMARTCARD_IT_MASK ((uint16_t)0x001F) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros * @{ */ -/** @brief Reset SMARTCARD handle state +/** @brief Reset SMARTCARD handle state. * @param __HANDLE__: SMARTCARD handle. * @retval None */ #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) -/** @brief Checks whether the specified Smartcard flag is set or not. +/** @brief Flush the Smartcard Data registers. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0) + +/** @brief Clear the specified SMARTCARD pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag + * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag + * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag + * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag + * @arg SMARTCARD_CLEAR_IDLEF: Idle line detected clear flag + * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag + * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag + * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the SMARTCARD PE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) + + +/** @brief Clear the SMARTCARD FE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) + +/** @brief Clear the SMARTCARD NE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) + +/** @brief Clear the SMARTCARD ORE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) + +/** @brief Clear the SMARTCARD IDLE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) + +/** @brief Check whether the specified Smartcard flag is set or not. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg SMARTCARD_FLAG_REACK: Receive enable ackowledge flag - * @arg SMARTCARD_FLAG_TEACK: Transmit enable ackowledge flag + * @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag + * @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag * @arg SMARTCARD_FLAG_BUSY: Busy flag - * @arg SMARTCARD_FLAG_EOBF: End of block flag - * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag + * @arg SMARTCARD_FLAG_EOBF: End of block flag + * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag - * @arg SMARTCARD_FLAG_TC: Transmission Complete flag + * @arg SMARTCARD_FLAG_TC: Transmission complete flag * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag - * @arg SMARTCARD_FLAG_ORE: OverRun Error flag - * @arg SMARTCARD_FLAG_NE: Noise Error flag - * @arg SMARTCARD_FLAG_FE: Framing Error flag - * @arg SMARTCARD_FLAG_PE: Parity Error flag + * @arg SMARTCARD_FLAG_IDLE: Idle line detection flag + * @arg SMARTCARD_FLAG_ORE: Overrun error flag + * @arg SMARTCARD_FLAG_NE: Noise error flag + * @arg SMARTCARD_FLAG_FE: Framing error flag + * @arg SMARTCARD_FLAG_PE: Parity error flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) -/** @brief Enables the specified SmartCard interrupt. +/** @brief Enable the specified SmartCard interrupt. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. * This parameter can be one of the following values: - * @arg SMARTCARD_IT_EOBF: End Of Block interrupt - * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt - * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt - * @arg SMARTCARD_IT_PE: Parity Error interrupt - * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg SMARTCARD_IT_EOB: End of block interrupt + * @arg SMARTCARD_IT_RTO: Receive timeout interrupt + * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt + * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt + * @arg SMARTCARD_IT_PE: Parity error interrupt + * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error) * @retval None */ #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) -/** @brief Disables the specified SmartCard interrupt. +/** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. * This parameter can be one of the following values: - * @arg SMARTCARD_IT_EOBF: End Of Block interrupt - * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt - * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt - * @arg SMARTCARD_IT_PE: Parity Error interrupt - * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg SMARTCARD_IT_EOB: End of block interrupt + * @arg SMARTCARD_IT_RTO: Receive timeout interrupt + * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt + * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt + * @arg SMARTCARD_IT_PE: Parity error interrupt + * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error) * @retval None */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) - -/** @brief Checks whether the specified SmartCard interrupt has occurred or not. + +/** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __IT__: specifies the SMARTCARD interrupt to check. * This parameter can be one of the following values: - * @arg SMARTCARD_IT_EOBF: End Of Block interrupt - * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt - * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt - * @arg SMARTCARD_IT_ORE: OverRun Error interrupt - * @arg SMARTCARD_IT_NE: Noise Error interrupt - * @arg SMARTCARD_IT_FE: Framing Error interrupt - * @arg SMARTCARD_IT_PE: Parity Error interrupt + * @arg SMARTCARD_IT_EOB: End of block interrupt + * @arg SMARTCARD_IT_RTO: Receive timeout interrupt + * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt + * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt + * @arg SMARTCARD_IT_ORE: Overrun error interrupt + * @arg SMARTCARD_IT_NE: Noise error interrupt + * @arg SMARTCARD_IT_FE: Framing error interrupt + * @arg SMARTCARD_IT_PE: Parity error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) -/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled. +/** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __IT__: specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: - * @arg SMARTCARD_IT_EOBF: End Of Block interrupt - * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt - * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt - * @arg SMARTCARD_IT_TC: Transmission complete interrupt - * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt - * @arg SMARTCARD_IT_ORE: OverRun Error interrupt - * @arg SMARTCARD_IT_NE: Noise Error interrupt - * @arg SMARTCARD_IT_FE: Framing Error interrupt - * @arg SMARTCARD_IT_PE: Parity Error interrupt + * @arg SMARTCARD_IT_EOB: End of block interrupt + * @arg SMARTCARD_IT_RTO: Receive timeout interrupt + * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt + * @arg SMARTCARD_IT_TC: Transmission complete interrupt + * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt + * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt + * @arg SMARTCARD_IT_ORE: Overrun error interrupt + * @arg SMARTCARD_IT_NE: Noise error interrupt + * @arg SMARTCARD_IT_FE: Framing error interrupt + * @arg SMARTCARD_IT_PE: Parity error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \ @@ -668,87 +691,261 @@ typedef struct (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) -/** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag. +/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: - * @arg USART_CLEAR_PEF: Parity Error Clear Flag - * @arg USART_CLEAR_FEF: Framing Error Clear Flag - * @arg USART_CLEAR_NEF: Noise detected Clear Flag - * @arg USART_CLEAR_OREF: OverRun Error Clear Flag - * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag - * @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag - * @arg USART_CLEAR_EOBF: End Of Block Clear Flag + * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag + * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag + * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag + * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag + * @arg SMARTCARD_CLEAR_IDLEF: Idle line detection clear flag + * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag + * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag + * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag * @retval None */ -#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) +#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific SMARTCARD request flag. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral. * @param __REQ__: specifies the request flag to set - * This parameter can be one of the following values: - * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request - * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * This parameter can be one of the following values: + * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive data flush Request + * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request * * @retval None - */ -#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + */ +#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) -/** @brief Enable the USART associated to the SMARTCARD Handle +/** @brief Enable the SMARTCARD one bit sample method. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the SMARTCARD one bit sample method. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + +/** @brief Enable the USART associated to the SMARTCARD Handle. * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral * @retval None - */ + */ #define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral * @retval None - */ + */ #define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros + * @{ + */ + /** @brief Check the Baud rate range. The maximum Baud Rate is derived from the * maximum clock on F0 (i.e. 48 MHz) divided by the oversampling used - * on the SMARTCARD (i.e. 16) + * on the SMARTCARD (i.e. 16). * @param __BAUDRATE__: Baud rate set by the configuration function. - * @retval Test result (TRUE or FALSE) - */ + * @retval Test result (TRUE or FALSE) + */ #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001) -/** @brief Check the block length range. The maximum SMARTCARD block length is 0xFF. +/** @brief Check the block length range. + * @note The maximum SMARTCARD block length is 0xFF. * @param __LENGTH__: block length. - * @retval Test result (TRUE or FALSE) + * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF) -/** @brief Check the receiver timeout value. The maximum SMARTCARD receiver timeout - * value is 0xFFFFFF. +/** @brief Check the receiver timeout value. + * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. * @param __TIMEOUTVALUE__: receiver timeout value. - * @retval Test result (TRUE or FALSE) + * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF) -/** @brief Check the SMARTCARD autoretry counter value. The maximum number of - * retransmissions is 0x7. - * @param __COUNT__: number of retransmissions - * @retval Test result (TRUE or FALSE) +/** @brief Check the SMARTCARD autoretry counter value. + * @note The maximum number of retransmissions is 0x7. + * @param __COUNT__: number of retransmissions. + * @retval Test result (TRUE or FALSE) */ #define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7) /** - * @} + * @brief Ensure that SMARTCARD frame length is valid. + * @param __LENGTH__: SMARTCARD frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) */ +#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) + +/** + * @brief Ensure that SMARTCARD frame number of stop bits is valid. + * @param __STOPBITS__: SMARTCARD frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5) + +/** + * @brief Ensure that SMARTCARD frame parity is valid. + * @param __PARITY__: SMARTCARD frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ + ((__PARITY__) == SMARTCARD_PARITY_ODD)) + +/** + * @brief Ensure that SMARTCARD communication mode is valid. + * @param __MODE__: SMARTCARD communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00)) + +/** + * @brief Ensure that SMARTCARD frame polarity is valid. + * @param __CPOL__: SMARTCARD frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) + +/** + * @brief Ensure that SMARTCARD frame phase is valid. + * @param __CPHA__: SMARTCARD frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) + +/** + * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. + * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame sampling is valid. + * @param __ONEBIT__: SMARTCARD frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that SMARTCARD NACK transmission setting is valid. + * @param __NACK__: SMARTCARD NACK transmission setting. + * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) + */ +#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ + ((__NACK__) == SMARTCARD_NACK_DISABLE)) + +/** + * @brief Ensure that SMARTCARD receiver timeout setting is valid. + * @param __TIMEOUT__: SMARTCARD receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) + +/** + * @brief Ensure that SMARTCARD advanced features initialization is valid. + * @param __INIT__: SMARTCARD advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ + SMARTCARD_ADVFEATURE_TXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_RXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \ + SMARTCARD_ADVFEATURE_SWAP_INIT | \ + SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \ + SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) + +/** + * @brief Ensure that SMARTCARD frame TX inversion setting is valid. + * @param __TXINV__: SMARTCARD frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame RX inversion setting is valid. + * @param __RXINV__: SMARTCARD frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame data inversion setting is valid. + * @param __DATAINV__: SMARTCARD frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. + * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame overrun setting is valid. + * @param __OVERRUN__: SMARTCARD frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. + * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** + * @brief Ensure that SMARTCARD frame MSB first setting is valid. + * @param __MSBFIRST__: SMARTCARD frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that SMARTCARD request parameter is valid. + * @param __PARAM__: SMARTCARD request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST)) + +/** + * @} + */ /* Include SMARTCARD HAL Extended module */ -#include "stm32f0xx_hal_smartcard_ex.h" +#include "stm32f0xx_hal_smartcard_ex.h" - /* Exported functions --------------------------------------------------------*/ - /** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions * @{ */ @@ -762,9 +959,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); + /** * @} - */ + */ /** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions * @{ @@ -780,23 +978,25 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard); -/** - * @} - */ -/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); /** * @} */ - + +/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); + /** * @} - */ + */ + +/** + * @} + */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c index 80fe713808..72088ee458 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c @@ -2,26 +2,25 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief SMARTCARD HAL module driver. * - * This file provides extended firmware functions to manage the following + * This file provides extended firmware functions to manage the following * functionalities of the SmartCard. * + Initialization and de-initialization function * + Peripheral Control function * - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The Extended SMARTCARD HAL driver can be used as follows: + * + @verbatim + ============================================================================= + ##### SMARTCARD peripheral extended features ##### + ============================================================================= + [..] + The Extended SMARTCARD HAL driver can be used as follows: - - (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), - then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, + (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), + then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut, auto-retry counter,...) in the hsmartcard AdvancedInit structure. @@ -30,7 +29,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,7 +53,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -62,50 +61,51 @@ #ifdef HAL_SMARTCARD_MODULE_ENABLED -#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** @addtogroup STM32F0xx_HAL_Driver * @{ */ -/** @defgroup SMARTCARDEx SMARTCARD Extended HAL module driver +/** @defgroup SMARTCARDEx SMARTCARDEx * @brief SMARTCARD Extended HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions * @{ */ /** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended control functions * -@verbatim - =============================================================================== +@verbatim + =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the SMARTCARD. - (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly - (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the SMARTCARD. + (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly + (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature - (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature - + (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature + @endverbatim * @{ */ /** - * @brief Update on the fly the SMARTCARD block length in RTOR register - * @param hsmartcard: SMARTCARD handle - * @param BlockLength: SMARTCARD block length (8-bit long at most) + * @brief Update on the fly the SMARTCARD block length in RTOR register. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param BlockLength: SMARTCARD block length (8-bit long at most) * @retval None */ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength) @@ -114,64 +114,67 @@ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uin } /** - * @brief Update on the fly the receiver timeout value in RTOR register - * @param hsmartcard: SMARTCARD handle + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout - * value must be less or equal to 0x0FFFFFFFF. + * value must be less or equal to 0x0FFFFFFFF. * @retval None */ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue) { assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); - MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); + MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); } /** - * @brief Enable the SMARTCARD receiver timeout feature - * @param hsmartcard: SMARTCARD handle + * @brief Enable the SMARTCARD receiver timeout feature. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; - + /* Set the USART RTOEN bit */ hsmartcard->Instance->CR2 |= USART_CR2_RTOEN; - + hsmartcard->State = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Disable the SMARTCARD receiver timeout feature - * @param hsmartcard: SMARTCARD handle + * @brief Disable the SMARTCARD receiver timeout feature. + * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) { - + /* Process Locked */ __HAL_LOCK(hsmartcard); - + hsmartcard->State = HAL_SMARTCARD_STATE_BUSY; - + /* Clear the USART RTOEN bit */ hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN); - + hsmartcard->State = HAL_SMARTCARD_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); - - return HAL_OK; + + return HAL_OK; } /** @@ -190,7 +193,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef * @} */ -#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ #endif /* HAL_SMARTCARD_MODULE_ENABLED */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h index cc053004dd..63f3379e71 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 - * @brief Header file of SMARTCARD HAL module. + * @version V1.3.0 + * @date 26-June-2015 + * @brief Header file of SMARTCARD HAL Extended module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -54,9 +54,9 @@ /** @addtogroup SMARTCARDEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ @@ -70,7 +70,7 @@ * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F031x6) || defined(STM32F038xx) -#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ switch(__HAL_RCC_GET_USART1_SOURCE()) \ { \ @@ -94,7 +94,7 @@ #elif defined (STM32F030x8) || \ defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F051x8) || defined (STM32F058xx) -#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -127,7 +127,7 @@ } \ } while(0) #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) -#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -185,7 +185,7 @@ } \ } while(0) #elif defined(STM32F091xC) || defined(STM32F098xx) -#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -279,24 +279,23 @@ /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ - -/* Initialization and de-initialization functions ****************************/ -/* IO operation functions *****************************************************/ - /** @addtogroup SMARTCARDEx_Exported_Functions * @{ */ +/* Initialization and de-initialization functions ****************************/ +/* IO operation methods *******************************************************/ + /** @addtogroup SMARTCARDEx_Exported_Functions_Group1 * @{ */ - + /* Peripheral Control functions ***********************************************/ -void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength); -void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue); +void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength); +void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue); HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); @@ -304,7 +303,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef /** * @} - */ + */ /** * @} @@ -312,7 +311,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef /** * @} - */ + */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c index a3499df665..2416ca730a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c @@ -2,16 +2,16 @@ ****************************************************************************** * @file stm32f0xx_hal_smbus.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief SMBUS HAL module driver. - * * This file provides firmware functions to manage the following * functionalities of the System Management Bus (SMBus) peripheral, - * based on I2C principales of operation : + * based on I2C principles of operation : * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -22,22 +22,22 @@ (#) Declare a SMBUS_HandleTypeDef handle structure, for example: SMBUS_HandleTypeDef hsmbus; - (#)Initialize the SMBUS low level resources by implement the HAL_SMBUS_MspInit ()API: - (##) Enable the SMBUSx interface clock - (##) SMBUS pins configuration + (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: + (++) Enable the SMBUSx interface clock with __HAL_RCC_I2Cx_CLK_ENABLE() + (++) SMBUS pins configuration (+++) Enable the clock for the SMBUS GPIOs (+++) Configure SMBUS pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process + (++) NVIC configuration if you need to use interrupt process (+++) Configure the SMBUSx interrupt priority (+++) Enable the NVIC SMBUS IRQ Channel - (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Adressing Mode, + (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing Mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, Peripheral mode and Packet Error Check mode in the hsmbus Init structure. (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: - (++) These API s configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SMBUS_MspInit(&hsmbus) API. + (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() @@ -46,35 +46,35 @@ *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback - (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback - (+) Abort a master/host SMBUS process commnunication with Interrupt using HAL_SMBUS_Master_Abort_IT() + (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process - (++) mean HAL_SMBUS_MasterTxCpltCallback in case of previous state was master transmit - (++) mean HAL_SMBUS_MasterRxCpltCallback in case of previous state was master receive + (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode - using HAL_SMBUS_Slave_Listen_IT() HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, HAL_SMBUS_SlaveAddrCallback is executed and user can + using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end HAL_SMBUS_SlaveListenCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMBUS_SlaveListenCpltCallback - (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback - (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT() (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer HAL_SMBUS_ErrorCallback + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() to check the Alert Error Code using function HAL_SMBUS_GetError() (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMBUS_ErrorCallback + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() to check the Error Code using function HAL_SMBUS_GetError() *** SMBUS HAL driver macros list *** @@ -97,7 +97,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -131,7 +131,7 @@ * @{ */ -/** @defgroup SMBUS SMBUS HAL module driver +/** @defgroup SMBUS SMBUS * @brief SMBUS HAL module driver * @{ */ @@ -139,8 +139,8 @@ #ifdef HAL_SMBUS_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup SMBUS_Private_Define SMBUS Private Define +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Define SMBUS Private Constants * @{ */ #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*Instance->ISR) -#define __SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) -/** - * @} - */ - /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup SMBUS_Private_Functions SMBUS Private Functions +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); @@ -184,7 +175,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre * @} */ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions * @{ @@ -198,7 +189,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre ##### Initialization and de-initialization functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the SMBUSx peripheral: + de-initialize the SMBUSx peripheral: (+) User must Implement HAL_SMBUS_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, IT and NVIC ). @@ -220,15 +211,15 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration - of the selected SMBUSx periperal. + of the selected SMBUSx peripheral. @endverbatim * @{ */ /** - * @brief Initializes the SMBUS according to the specified parameters - * in the SMBUS_InitTypeDef and create the associated handle. + * @brief Initialize the SMBUS according to the specified parameters + * in the SMBUS_InitTypeDef and initialize the associated handle. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status @@ -256,6 +247,9 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) if(hsmbus->State == HAL_SMBUS_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hsmbus->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_SMBUS_MspInit(hsmbus); } @@ -310,7 +304,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLED) + if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -327,7 +321,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) } /** - * @brief DeInitializes the SMBUS peripheral. + * @brief DeInitialize the SMBUS peripheral. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status @@ -362,27 +356,27 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) } /** - * @brief SMBUS MSP Init. + * @brief Initialize the SMBUS MSP. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspInit could be implemented in the user file */ } /** - * @brief SMBUS MSP DeInit + * @brief DeInitialize the SMBUS MSP. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SMBUS_MspDeInit could be implemented in the user file */ } @@ -416,7 +410,7 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) (++) HAL_SMBUS_Master_Receive_IT() (++) HAL_SMBUS_Slave_Transmit_IT() (++) HAL_SMBUS_Slave_Receive_IT() - (++) HAL_SMBUS_Slave_Listen_IT() or alias HAL_SMBUS_EnableListen_IT() + (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT() (++) HAL_SMBUS_DisableListen_IT() (++) HAL_SMBUS_EnableAlert_IT() (++) HAL_SMBUS_DisableAlert_IT() @@ -426,8 +420,8 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) (++) HAL_SMBUS_MasterRxCpltCallback() (++) HAL_SMBUS_SlaveTxCpltCallback() (++) HAL_SMBUS_SlaveRxCpltCallback() - (++) HAL_SMBUS_SlaveAddrCallback() or alias HAL_SMBUS_AddrCallback() - (++) HAL_SMBUS_SlaveListenCpltCallback() or alias HAL_SMBUS_ListenCpltCallback() + (++) HAL_SMBUS_AddrCallback() + (++) HAL_SMBUS_ListenCpltCallback() (++) HAL_SMBUS_ErrorCallback() @endverbatim @@ -435,7 +429,7 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) */ /** - * @brief Transmit in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt + * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress: Target device address @@ -499,7 +493,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -523,7 +517,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint } /** - * @brief Receive in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt + * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress: Target device address @@ -604,8 +598,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 } /** - * @brief Abort a master/host SMBUS process commnunication with Interrupt - * @note : This abort can be called only if state is ready + * @brief Abort a master/host SMBUS process communication with Interrupt. + * @note This abort can be called only if state is ready * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param DevAddress: Target device address @@ -664,7 +658,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ } /** - * @brief Transmit in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt + * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param pData: Pointer to data buffer @@ -726,7 +720,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -755,7 +749,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } /** - * @brief Receive in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt + * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param pData: Pointer to data buffer @@ -801,7 +795,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) { SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } @@ -832,12 +826,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ } /** - * @brief This function enable the Address listen mode + * @brief Enable the Address listen mode with Interrupt. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus) +HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) { hsmbus->State = HAL_SMBUS_STATE_LISTEN; @@ -848,7 +842,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus) } /** - * @brief This function disable the Address listen mode + * @brief Disable the Address listen mode with Interrupt. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status @@ -872,7 +866,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) } /** - * @brief This function enable the SMBUS alert mode. + * @brief Enable the SMBUS alert mode with Interrupt. * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUSx peripheral. * @retval HAL status @@ -891,7 +885,7 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) return HAL_OK; } /** - * @brief This function disable the SMBUS alert mode. + * @brief Disable the SMBUS alert mode with Interrupt. * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUSx peripheral. * @retval HAL status @@ -908,7 +902,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) } /** - * @brief Checks if target device is ready for communication. + * @brief Check if target device is ready for communication. * @note This function is used with Memory devices * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. @@ -939,7 +933,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t do { /* Generate Start */ - hsmbus->Instance->CR2 = __HAL_SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); + hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ @@ -1024,9 +1018,16 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ /** - * @brief This function handles SMBUS event interrupt request. + * @brief Handle SMBUS event interrupt request. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None @@ -1037,10 +1038,10 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) /* Use a local variable to store the current ISR flags */ /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ - tmpisrvalue = __SMBUS_GET_ISR_REG(hsmbus); + tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) @@ -1055,7 +1056,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1070,7 +1071,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Listener Only --------------------------------------------------*/ - if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) { if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) @@ -1081,7 +1082,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /** - * @brief This function handles SMBUS error interrupt request. + * @brief Handle SMBUS error interrupt request. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None @@ -1142,10 +1143,10 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Call the Error Callback in case of Error detected */ + /* Call the Error Callback() in case of Error detected */ if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) { - /* Do not Reset the the HAL state in case of ALERT error */ + /* Do not Reset the HAL state in case of ALERT error */ if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) { if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) @@ -1164,94 +1165,94 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /** - * @brief Master Tx Transfer completed callbacks. + * @brief Master Tx Transfer completed callback. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMBUS_TxCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_TxCpltCallback() could be implemented in the user file */ } /** - * @brief Master Rx Transfer completed callbacks. + * @brief Master Rx Transfer completed callback. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMBUS_TxCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_TxCpltCallback() could be implemented in the user file */ } -/** @brief Slave Tx Transfer completed callbacks. +/** @brief Slave Tx Transfer completed callback. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMBUS_TxCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_TxCpltCallback() could be implemented in the user file */ } /** - * @brief Slave Rx Transfer completed callbacks. + * @brief Slave Rx Transfer completed callback. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMBUS_TxCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_TxCpltCallback() could be implemented in the user file */ } /** - * @brief Slave Address Match callbacks. + * @brief Slave Address Match callback. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param TransferDirection: Master request Transfer Direction (Write/Read) * @param AddrMatchCode: Address Match Code * @retval None */ -__weak void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMBUS_SlaveAddrCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_AddrCallback() could be implemented in the user file */ } /** - * @brief Listen Complete callbacks. + * @brief Listen Complete callback. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ -__weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) +__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMBUS_SlaveListenCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file */ } /** - * @brief SMBUS error callbacks. + * @brief SMBUS error callback. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval None */ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMBUS_ErrorCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_ErrorCallback() could be implemented in the user file */ } @@ -1267,7 +1268,7 @@ __weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) ##### Peripheral State and Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1275,17 +1276,19 @@ __weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) */ /** - * @brief Returns the SMBUS state. - * @param hsmbus : SMBUS handle + * @brief Return the SMBUS handle state. + * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. * @retval HAL state */ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) { + /* Return SMBUS handle state */ return hsmbus->State; } /** -* @brief Return the SMBUS error code +* @brief Return the SMBUS error code. * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval SMBUS Error Code @@ -1309,7 +1312,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) */ /** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status @@ -1349,7 +1352,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_SMBUS_RESET_CR2(hsmbus); + SMBUS_RESET_CR2(hsmbus); /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ /* Disable the selected SMBUS peripheral */ @@ -1375,7 +1378,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_SMBUS_RESET_CR2(hsmbus); + SMBUS_RESET_CR2(hsmbus); hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1417,7 +1420,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1426,8 +1429,8 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0)) { - /* Call TxCpltCallback if no stop mode is set */ - if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + /* Call TxCpltCallback() if no stop mode is set */ + if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) @@ -1466,8 +1469,8 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Generate a Stop command */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; } - /* Call TxCpltCallback if no stop mode is set */ - else if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + /* Call TxCpltCallback() if no stop mode is set */ + else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ @@ -1506,7 +1509,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) return HAL_OK; } /** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @retval HAL status @@ -1560,8 +1563,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) { - TransferDirection = __HAL_SMBUS_GET_DIR(hsmbus); - SlaveAddrCode = __HAL_SMBUS_GET_ADDR_MATCH(hsmbus); + TransferDirection = SMBUS_GET_DIR(hsmbus); + SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ /* Other ADDRInterrupt will be treat in next Listen usecase */ @@ -1571,7 +1574,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call Slave Addr callback */ - HAL_SMBUS_SlaveAddrCallback(hsmbus, TransferDirection, SlaveAddrCode); + HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); } else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) { @@ -1629,7 +1632,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1642,7 +1645,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ + /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if(hsmbus->XferCount > 0) { @@ -1683,7 +1686,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) hsmbus->Instance->CR2 |= I2C_CR2_NACK; /* Clear Configuration Register 2 */ - __HAL_SMBUS_RESET_CR2(hsmbus); + SMBUS_RESET_CR2(hsmbus); /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); @@ -1699,7 +1702,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_UNLOCK(hsmbus); /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */ - HAL_SMBUS_SlaveListenCpltCallback(hsmbus); + HAL_SMBUS_ListenCpltCallback(hsmbus); } } @@ -1709,7 +1712,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) return HAL_OK; } /** - * @brief Manage the enabling of Interrupts + * @brief Manage the enabling of Interrupts. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition. @@ -1751,7 +1754,7 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t return HAL_OK; } /** - * @brief Manage the disabling of Interrupts + * @brief Manage the disabling of Interrupts. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition. @@ -1772,7 +1775,7 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Disable TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ @@ -1791,7 +1794,7 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Disable TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ @@ -1810,7 +1813,7 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - if(__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1825,7 +1828,7 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t return HAL_OK; } /** - * @brief This function handles SMBUS Communication Timeout. + * @brief Handle SMBUS Communication Timeout. * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param Flag: specifies the SMBUS flag to check. @@ -1882,7 +1885,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu } /** - * @brief Handles SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). + * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hsmbus: SMBUS handle. * @param DevAddress: specifies the slave address to be programmed. * @param Size: specifies the number of bytes to be programmed. diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h index 35fe420e3d..cbdc57b744 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_smbus.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,8 +59,9 @@ * @{ */ -/** +/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition * @brief SMBUS Configuration Structure definition + * @{ */ typedef struct { @@ -68,7 +69,7 @@ typedef struct This parameter calculated by referring to SMBUS initialization section in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. - This parameter can be a a value of @ref SMBUS_Analog_Filter */ + This parameter can be a value of @ref SMBUS_Analog_Filter */ uint32_t OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ @@ -102,9 +103,48 @@ typedef struct This parameter calculated by referring to SMBUS initialization section in Reference manual */ } SMBUS_InitTypeDef; - /** + * @} + */ + +/** @defgroup HAL_state_definition HAL state definition + * @brief HAL State definition + * @{ + */ +#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */ +#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */ +#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */ +#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */ +#define HAL_SMBUS_STATE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */ +/** + * @} + */ + +/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition + * @brief SMBUS Error Code definition + * @{ + */ +#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ +#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */ +#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ +#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */ +#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */ +#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */ +#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */ +/** + * @} + */ + +/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition * @brief SMBUS handle Structure definition + * @{ */ typedef struct { @@ -120,73 +160,33 @@ typedef struct __IO uint32_t XferOptions; /*!< SMBUS transfer options */ - __IO uint32_t PreviousState; /*!< SMBUS communication Previous state - This parameter can be a value of @ref SMBUS_State */ + __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ HAL_LockTypeDef Lock; /*!< SMBUS locking object */ - __IO uint32_t State; /*!< SMBUS communication state - This parameter can be a value of @ref SMBUS_State */ + __IO uint32_t State; /*!< SMBUS communication state */ - __IO uint32_t ErrorCode; /*!< SMBUS Error code - This parameter can be a value of @ref SMBUS_Error */ + __IO uint32_t ErrorCode; /*!< SMBUS Error code */ }SMBUS_HandleTypeDef; /** * @} */ +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants * @{ */ -/** @defgroup SMBUS_Error SMBUS Error - * @{ - */ -#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */ -#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */ -#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */ -#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */ -#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */ -#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */ -#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */ -#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */ -/** - * @} - */ - -/** @defgroup SMBUS_State SMBUS State - * @{ - */ - -#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */ -#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */ -#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */ - /* Aliases for inter STM32 series compatibility */ -#define HAL_SMBUS_STATE_LISTEN HAL_SMBUS_STATE_SLAVE_LISTEN - -/** - * @} - */ - /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter * @{ */ -#define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000) -#define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF - -#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \ - ((FILTER) == SMBUS_ANALOGFILTER_DISABLED)) +#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) +#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} */ @@ -196,9 +196,6 @@ typedef struct */ #define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) #define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) - -#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ - ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) /** * @} */ @@ -207,11 +204,8 @@ typedef struct * @{ */ -#define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000) -#define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN - -#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \ - ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED)) +#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000) +#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} */ @@ -228,15 +222,6 @@ typedef struct #define SMBUS_OA2_MASK05 ((uint8_t)0x05) #define SMBUS_OA2_MASK06 ((uint8_t)0x06) #define SMBUS_OA2_MASK07 ((uint8_t)0x07) - -#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ - ((MASK) == SMBUS_OA2_MASK01) || \ - ((MASK) == SMBUS_OA2_MASK02) || \ - ((MASK) == SMBUS_OA2_MASK03) || \ - ((MASK) == SMBUS_OA2_MASK04) || \ - ((MASK) == SMBUS_OA2_MASK05) || \ - ((MASK) == SMBUS_OA2_MASK06) || \ - ((MASK) == SMBUS_OA2_MASK07)) /** * @} */ @@ -245,11 +230,8 @@ typedef struct /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode * @{ */ -#define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000) -#define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN - -#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \ - ((CALL) == SMBUS_GENERALCALL_ENABLED)) +#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000) +#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} */ @@ -257,11 +239,8 @@ typedef struct /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode * @{ */ -#define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000) -#define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH - -#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \ - ((STRETCH) == SMBUS_NOSTRETCH_ENABLED)) +#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000) +#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} */ @@ -269,11 +248,8 @@ typedef struct /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode * @{ */ -#define SMBUS_PEC_DISABLED ((uint32_t)0x00000000) -#define SMBUS_PEC_ENABLED I2C_CR1_PECEN - -#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \ - ((PEC) == SMBUS_PEC_ENABLED)) +#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000) +#define SMBUS_PEC_ENABLE I2C_CR1_PECEN /** * @} */ @@ -284,10 +260,6 @@ typedef struct #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN) #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000) #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN) - -#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) /** * @} */ @@ -300,15 +272,6 @@ typedef struct #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE - -#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ - ((MODE) == SMBUS_AUTOEND_MODE) || \ - ((MODE) == SMBUS_SOFTEND_MODE) || \ - ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) - /** * @} */ @@ -321,12 +284,6 @@ typedef struct #define SMBUS_GENERATE_STOP I2C_CR2_STOP #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define SMBUS_GENERATE_START_WRITE I2C_CR2_START - -#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ - ((REQUEST) == SMBUS_GENERATE_START_READ) || \ - ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ - ((REQUEST) == SMBUS_NO_STARTSTOP)) - /** * @} */ @@ -341,14 +298,6 @@ typedef struct #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) - -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ - ((REQUEST) == SMBUS_NEXT_FRAME) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) - /** * @} */ @@ -410,16 +359,15 @@ typedef struct * @{ */ -/** @brief Reset SMBUS handle state - * @param __HANDLE__: SMBUS handle. +/** @brief Reset SMBUS handle state. + * @param __HANDLE__: specifies the SMBUS Handle. * @retval None */ #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) -/** @brief Enable or disable the specified SMBUS interrupts. +/** @brief Enable the specified SMBUS interrupts. * @param __HANDLE__: specifies the SMBUS Handle. - * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__: specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg SMBUS_IT_ERRI: Errors interrupt enable * @arg SMBUS_IT_TCI: Transfer complete interrupt enable @@ -431,13 +379,26 @@ typedef struct * * @retval None */ - #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified SMBUS interrupts. + * @param __HANDLE__: specifies the SMBUS Handle. + * @param __INTERRUPT__: specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SMBUS_IT_ERRI: Errors interrupt enable + * @arg SMBUS_IT_TCI: Transfer complete interrupt enable + * @arg SMBUS_IT_STOPI: STOP detection interrupt enable + * @arg SMBUS_IT_NACKI: NACK received interrupt enable + * @arg SMBUS_IT_ADDRI: Address match interrupt enable + * @arg SMBUS_IT_RXI: RX interrupt enable + * @arg SMBUS_IT_TXI: TX interrupt enable + * + * @retval None + */ #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) -/** @brief Checks if the specified SMBUS interrupt source is enabled or disabled. +/** @brief Check whether the specified SMBUS interrupt source is enabled or not. * @param __HANDLE__: specifies the SMBUS Handle. - * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. * @param __INTERRUPT__: specifies the SMBUS interrupt source to check. * This parameter can be one of the following values: * @arg SMBUS_IT_ERRI: Errors interrupt enable @@ -452,9 +413,8 @@ typedef struct */ #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** @brief Checks whether the specified SMBUS flag is set or not. +/** @brief Check whether the specified SMBUS flag is set or not. * @param __HANDLE__: specifies the SMBUS Handle. - * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg SMBUS_FLAG_TXE: Transmit data register empty @@ -479,9 +439,8 @@ typedef struct #define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF) #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) -/** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit. +/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__: specifies the SMBUS Handle. - * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) @@ -498,25 +457,116 @@ typedef struct */ #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +/** @brief Enable the specified SMBUS peripheral. + * @param __HANDLE__: specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) -#define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) -#define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) +/** @brief Disable the specified SMBUS peripheral. + * @param __HANDLE__: specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) -#define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) -#define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. + * @param __HANDLE__: specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) -#define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Macro SMBUS Private Macros + * @{ + */ + +#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) + +#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ + ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) + +#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) + +#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ + ((MASK) == SMBUS_OA2_MASK01) || \ + ((MASK) == SMBUS_OA2_MASK02) || \ + ((MASK) == SMBUS_OA2_MASK03) || \ + ((MASK) == SMBUS_OA2_MASK04) || \ + ((MASK) == SMBUS_OA2_MASK05) || \ + ((MASK) == SMBUS_OA2_MASK06) || \ + ((MASK) == SMBUS_OA2_MASK07)) + +#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ + ((CALL) == SMBUS_GENERALCALL_ENABLE)) + +#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ + ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) + +#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ + ((PEC) == SMBUS_PEC_ENABLE)) + +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) + +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) + + +#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) + + +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -#define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) -#define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) -#define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) -#define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) -#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK) +#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) +#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) +#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) +#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) + +#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) + +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +/* Private functions are defined in stm32l4xx_hal_smbus.c file */ /** * @} */ @@ -545,9 +595,18 @@ void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); */ /* IO operation functions *****************************************************/ +/** @addtogroup Blocking_mode_Polling Blocking mode Polling + * @{ + */ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +/** + * @} + */ +/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt + * @{ + */ /******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); @@ -557,12 +616,15 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ -/* Aliases for new API and to insure inter STM32 series compatibility */ -#define HAL_SMBUS_EnableListen_IT HAL_SMBUS_Slave_Listen_IT - +/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); @@ -570,13 +632,8 @@ void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); - -/* Aliases for new API and to insure inter STM32 series compatibility */ -#define HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveAddrCallback -#define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_SlaveListenCpltCallback - +void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); /** @@ -595,6 +652,12 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); * @} */ +/** + * @} + */ + + + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c index 6633ea8aa8..97bb8fe85d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c @@ -2,87 +2,95 @@ ****************************************************************************** * @file stm32f0xx_hal_spi.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief SPI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the SPI peripheral: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim -=============================================================================== - ##### How to use this driver ##### - =============================================================================== + ============================================================================== + ##### How to use this driver ##### + ============================================================================== [..] - The SPI HAL driver can be used as follows: - - (#) Declare a SPI_HandleTypeDef handle structure, for example: - SPI_HandleTypeDef hspi; - - (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API: - (##) Enable the SPIx interface clock - (##) SPI pins configuration - (+++) Enable the clock for the SPI GPIOs - (+++) Configure these SPI pins as alternate function push-pull - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the SPIx interrupt priority - (+++) Enable the NVIC SPI IRQ handle - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel - (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel - - (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS - management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. - - (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: - (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SPI_MspInit(&hspi) API. - - [..] - Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, - the following table resume the max SPI frequency reached with data size 8bits/16bits: - +-----------------------------------------------------------------------------------------+ - | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |--------------------|--------------------|--------------------| - | | | Master | Slave | Master | Slave | Master | Slave | - |=========================================================================================| - | T | Polling | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA | - | X |----------------|----------|---------|----------|---------|----------|---------| - | / | Interrupt | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA | - | R |----------------|----------|---------|----------|---------|----------|---------| - | X | DMA | Fcpu/32 | Fcpu/16 | NA | NA | NA | NA | - |=========|================|==========|=========|==========|=========|==========|=========| - | | Polling | Fcpu/32 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | - | |----------------|----------|---------|----------|---------|----------|---------| - | R | Interrupt | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | - | X |----------------|----------|---------|----------|---------|----------|---------| - | | DMA | Fcpu/4 | Fcpu/8 | Fcpu/4 | Fcpu/4 | Fcpu/8 | Fcpu/16 | - |=========|================|==========|=========|==========|=========|==========|=========| - | | Polling | Fcpu/16 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 | - | |----------------|----------|---------|----------|---------|----------|---------| - | T | Interrupt | Fcpu/32 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 | - | X |----------------|----------|---------|----------|---------|----------|---------| - | | DMA | Fcpu/2 | Fcpu/16 | NA | NA | Fcpu/8 | Fcpu/16 | - +-----------------------------------------------------------------------------------------+ - @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), - SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). - @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() - (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() - (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the differents + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + +----------------------------------------------------------------------------------------- + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line + | Process | Tranfert mode |---------------------|---------------------|------------------ + | | | Master | Slave | Master | Slave | Master | Slave + |========================================================================================= + | T | Polling | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA + | X |----------------|----------|----------|----------|----------|----------|------- + | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA + | R |----------------|----------|----------|----------|----------|----------|------- + | X | DMA | fPCLK/32 | fPCLK/16 | NA | NA | NA | NA + |=========|================|==========|==========|==========|==========|==========|======= + | | Polling | fPCLK/32 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/ + | |----------------|----------|----------|----------|----------|----------|------- + | R | Interrupt | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/ + | X |----------------|----------|----------|----------|----------|----------|------- + | | DMA | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/4 | fPCLK/8 | fPCLK/ + |=========|================|==========|==========|==========|==========|==========|======= + | | Polling | fPCLK/16 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/ + | |----------------|----------|----------|----------|----------|----------|------- + | T | Interrupt | fPCLK/32 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/ + | X |----------------|----------|----------|----------|----------|----------|------- + | | DMA | fPCLK/2 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/ + +----------------------------------------------------------------------------------------- + @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16 + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_S + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -106,41 +114,38 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ - + /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" - + /** @addtogroup STM32F0xx_HAL_Driver * @{ */ -/** @defgroup SPI SPI HAL module driver +/** @defgroup SPI SPI * @brief SPI HAL module driver * @{ */ #ifdef HAL_SPI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - +/* Private defines -----------------------------------------------------------*/ /** @defgroup SPI_Private_Constants SPI Private Constants * @{ */ #define SPI_DEFAULT_TIMEOUT 50 -#define SPI_FIFO_SIZE 4 /** * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup SPI_Private_Functions SPI Private Functions * @{ */ - static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); @@ -166,6 +171,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); /** * @} */ @@ -176,23 +182,23 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t * @{ */ -/** @defgroup SPI_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== - ##### Initialization and Configuration functions ##### + ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the SPIx peripheral: + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: - (+) User must Implement HAL_SPI_MspInit() function in which he configures + (+) User must implement HAL_SPI_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - (+) Call the function HAL_SPI_Init() to configure the selected device with + (+) Call the function HAL_SPI_Init() to configure the selected device with the selected configuration: (++) Mode - (++) Direction + (++) Direction (++) Data Size (++) Clock Polarity and Phase (++) NSS Management @@ -201,33 +207,33 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t (++) TIMode (++) CRC Calculation (++) CRC Polynomial if CRC enabled - (++) CRC Length, used only with Data8 and Data16 + (++) CRC Length, used only with Data8 and Data16 (++) FIFO reception threshold - (+) Call the function HAL_SPI_DeInit() to restore the default configuration - of the selected SPIx periperal. - + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + @endverbatim * @{ */ /** - * @brief Initializes the SPI according to the specified parameters - * in the SPI_InitTypeDef and create the associated handle. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { uint32_t frxth; - + /* Check the SPI handle allocation */ if(hspi == NULL) - { + { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); assert_param(IS_SPI_MODE(hspi->Init.Mode)); @@ -243,15 +249,21 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); - + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + hspi->State = HAL_SPI_STATE_BUSY; - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_SPI_MspInit(hspi); - + /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); - + /* Align by default the rs fifo threshold on the data size */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) { @@ -261,18 +273,18 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { frxth = SPI_RXFIFO_THRESHOLD_QF; } - + /* CRC calculation is valid only for 16Bit and 8 Bit */ if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT )) { /* CRC must be disabled */ - hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; } - + /* Align the CRC Length on the data size */ if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) { - /* CRC Lengtht aligned on the data size : value set by default */ + /* CRC Length aligned on the data size : value set by default */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) { hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; @@ -282,24 +294,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; } } - + /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit, CRC calculation state, CRC Length */ - hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | + hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); - + if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { hspi->Instance->CR1|= SPI_CR1_CRCL; } - + /* Configure : NSS management */ /* Configure : Rx Fifo Threshold */ hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | hspi->Init.DataSize ) | frxth; - + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ /* Configure : CRC Polynomial */ hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; @@ -309,14 +321,14 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State= HAL_SPI_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitializes the SPI peripheral - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * @brief DeInitialize the SPI peripheral. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) @@ -330,49 +342,44 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /* Check the parameters */ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); hspi->State = HAL_SPI_STATE_BUSY; - - /* check flag before the SPI disable */ - SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT); - SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT); - SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT); - + /* Disable the SPI Peripheral Clock */ __HAL_SPI_DISABLE(hspi); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_SPI_MspDeInit(hspi); - + hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State = HAL_SPI_STATE_RESET; - + __HAL_UNLOCK(hspi); - + return HAL_OK; } /** - * @brief SPI MSP Init - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Initialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ - __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_MspInit could be implenetd in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file */ } /** - * @brief SPI MSP DeInit - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief DeInitialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ - __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_MspDeInit could be implenetd in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file */ } @@ -380,64 +387,46 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) * @} */ -/** @defgroup SPI_Exported_Functions_Group2 I/O operation functions - * @brief Data transfers functions +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions * -@verbatim - =============================================================================== +@verbatim + ============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the SPI data transfers. - - [..] The SPI supports master and slave mode : + + [..] The SPI supports master and slave mode : (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) Non Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process - The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected - (#) Blocking mode APIs are : - (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceive() in full duplex mode - - (#) Non Blocking mode APIs with Interrupt are : - (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceive_IT()in full duplex mode - (++) HAL_SPI_IRQHandler() - - (#) Non Blocking mode functions with DMA are : - (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode - - (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: - (++) HAL_SPI_TxCpltCallback() - (++) HAL_SPI_RxCpltCallback() - (++) HAL_SPI_ErrorCallback() - (++) HAL_SPI_TxRxCpltCallback() + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. @endverbatim * @{ */ /** - * @brief Transmit an amount of data in blocking mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData : pointer to data buffer - * @param Size : amount of data to be sent - * @param Timeout : Timeout duration + * @brief Transmit an amount of data in blocking mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -450,49 +439,49 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Process Locked */ __HAL_LOCK(hspi); - if(hspi->State != HAL_SPI_STATE_READY) + if(hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - + if((pData == NULL ) || (Size == 0)) { errorcode = HAL_ERROR; goto error; } - /* Set the transaction information */ + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pTxBuffPtr = pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t*)NULL; + hspi->pRxBuffPtr = (uint8_t *)NULL; hspi->RxXferSize = 0; hspi->RxXferCount = 0; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_TX(hspi); + SPI_1LINE_TX(hspi); } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - /* Check if the SPI is already enabled */ + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - + /* Transmit data in 16 Bit mode */ - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Transmit data in 16 Bit mode */ while (hspi->TxXferCount > 0) @@ -507,7 +496,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint else { /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) { errorcode = HAL_TIMEOUT; goto error; @@ -525,7 +514,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if(hspi->TxXferCount > 1) { - /* write on the data register in packaing mode */ + /* write on the data register in packing mode */ hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2; @@ -533,13 +522,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint else { *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; + hspi->TxXferCount--; } } else { /* Timeout management */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) { errorcode = HAL_TIMEOUT; goto error; @@ -549,20 +538,26 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint } /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1|= SPI_CR1_CRCNEXT; } - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } - + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - errorcode = HAL_ERROR; + { + errorcode = HAL_ERROR; } error: @@ -573,12 +568,12 @@ error: } /** - * @brief Receive an amount of data in blocking mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData : pointer to data buffer - * @param Size : amount of data to be sent - * @param Timeout : Timeout duration + * @brief Receive an amount of data in blocking mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -590,11 +585,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the transmitReceive process */ + /* in this case we call the TransmitReceive process */ /* Process Locked */ return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); } - + /* Process Locked */ __HAL_LOCK(hspi); @@ -609,40 +604,40 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 errorcode = HAL_ERROR; goto error; } - + hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t*)NULL; + hspi->pTxBuffPtr = (uint8_t *)NULL; hspi->TxXferSize = 0; hspi->TxXferCount = 0; /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); /* this is done to handle the CRCNEXT before the latest data */ hspi->RxXferCount--; } - /* Set the Rx Fido thresold */ + /* Set the Rx Fido threshold */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data lenght: 16bit */ + /* set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data lenght: 8bit */ + /* set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } /* Configure communication direction 1Line and enabled SPI if needed */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_RX(hspi); + SPI_1LINE_RX(hspi); } /* Check if the SPI is already enabled */ @@ -654,7 +649,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT) { - /* Transfert loop */ + /* Transfer loop */ while(hspi->RxXferCount > 0) { /* Check the RXNE flag */ @@ -666,7 +661,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } else { - /* Timeout manamgement */ + /* Timeout management */ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) { errorcode = HAL_TIMEOUT; @@ -677,7 +672,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } else { - /* Transfert loop */ + /* Transfer loop */ while(hspi->RxXferCount > 0) { /* Check the RXNE flag */ @@ -689,8 +684,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } else { - /* Timeout mamangement */ - if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + /* Timeout management */ + if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) { errorcode = HAL_TIMEOUT; goto error; @@ -700,18 +695,19 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } /* Handle the CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* freeze the CRC before the latest data */ hspi->Instance->CR1|= SPI_CR1_CRCNEXT; - + /* Read the latest data */ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) { + /* the latest data has not been received */ errorcode = HAL_TIMEOUT; goto error; } - + /* Receive last data in 16 Bit mode */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) { @@ -722,31 +718,39 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR; } - + /* Wait until TXE flag */ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) { /* Flag Error*/ - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + hspi->ErrorCode = HAL_SPI_ERROR_CRC; + errorcode = HAL_TIMEOUT; + goto error; } - + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) { tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); } else { tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); + if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) { - /* Erreur on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + /* Error on the CRC reception */ + hspi->ErrorCode = HAL_SPI_ERROR_CRC; + errorcode = HAL_TIMEOUT; + goto error; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); } } @@ -755,22 +759,21 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check the end of the transaction */ if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK) { - errorcode = HAL_TIMEOUT; - goto error; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } - + /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { hspi->ErrorCode|= HAL_SPI_ERROR_CRC; __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } - + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { errorcode = HAL_ERROR; } - + error : hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); @@ -778,13 +781,13 @@ error : } /** - * @brief Transmit and Receive an amount of data in blocking mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData : pointer to transmission data buffer - * @param pRxData : pointer to reception data buffer to be - * @param Size : amount of data to be sent - * @param Timeout : Timeout duration + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size: amount of data to be sent and received + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -792,9 +795,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD __IO uint16_t tmpreg; uint32_t tickstart = HAL_GetTick(); HAL_StatusTypeDef errorcode = HAL_OK; - + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - assert_param(pTxData != NULL); /* Process Locked */ __HAL_LOCK(hspi); @@ -804,13 +806,13 @@ __IO uint16_t tmpreg; errorcode = HAL_BUSY; goto error; } - + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { errorcode = HAL_ERROR; goto error; } - + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = pRxData; @@ -818,36 +820,36 @@ __IO uint16_t tmpreg; hspi->RxXferSize = Size; hspi->pTxBuffPtr = pTxData; hspi->TxXferCount = Size; - hspi->TxXferSize = Size; - + hspi->TxXferSize = Size; + /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + /* Set the Rx Fido threshold */ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) { - /* set fiforxthreshold according the reception data lenght: 16bit */ + /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthreshold according the reception data lenght: 8bit */ + /* set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } - - /* Check if the SPI is already enabled */ + + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { - /* Enable SPI peripheral */ + /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - + /* Transmit and Receive data in 16 Bit mode */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { + { while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0)) { /* Check TXE flag */ @@ -856,14 +858,14 @@ __IO uint16_t tmpreg; hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; - + /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { hspi->Instance->CR1|= SPI_CR1_CRCNEXT; - } + } } - + /* Check RXNE flag */ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) { @@ -876,11 +878,11 @@ __IO uint16_t tmpreg; errorcode = HAL_TIMEOUT; goto error; } - } + } } /* Transmit and Receive data in 8 Bit mode */ else - { + { while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0)) { /* check TXE flag */ @@ -891,20 +893,20 @@ __IO uint16_t tmpreg; hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2; - } + } else { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; } - + /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } } - + /* Wait until RXNE flag is reset */ if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) { @@ -932,34 +934,42 @@ __IO uint16_t tmpreg; } } } - + /* Read CRC from DR to close CRC calculation process */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until TXE flag */ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - /* Erreur on the CRC reception */ + { + /* Error on the CRC reception */ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + errorcode = HAL_TIMEOUT; + goto error; } - + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) { tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); } else { tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); + if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) - { - /* Erreur on the CRC reception */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) + { + /* Error on the CRC reception */ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - } + errorcode = HAL_TIMEOUT; + goto error; + } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); } } @@ -971,61 +981,67 @@ __IO uint16_t tmpreg; hspi->ErrorCode|= HAL_SPI_ERROR_CRC; /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; - } - - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { + errorcode = HAL_ERROR; } -error : + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error : hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } /** - * @brief Transmit an amount of data in no-blocking mode with Interrupt - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData : pointer to data buffer - * @param Size : amount of data to be sent + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - + /* Process Locked */ __HAL_LOCK(hspi); - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { errorcode = HAL_ERROR; goto error; } - + if(hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - - /* prepore the transfer */ + + /* prepare the transfer */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pTxBuffPtr = pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t*)NULL; + hspi->pRxBuffPtr = (uint8_t *)NULL; hspi->RxXferSize = 0; hspi->RxXferCount = 0; - hspi->RxISR = (void (*)(SPI_HandleTypeDef *))NULL; + hspi->RxISR = NULL; - /* Set the function for IT treatement */ + /* Set the function for IT treatment */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) { hspi->TxISR = SPI_TxISR_16BIT; @@ -1034,81 +1050,81 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u { hspi->TxISR = SPI_TxISR_8BIT; } - + /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_TX(hspi); + SPI_1LINE_TX(hspi); } - + /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE)); - - - /* Check if the SPI is already enabled */ + + + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { - /* Enable SPI peripheral */ + /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - + error : __HAL_UNLOCK(hspi); return errorcode; } /** - * @brief Receive an amount of data in no-blocking mode with Interrupt - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData : pointer to data buffer - * @param Size : amount of data to be sent + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - + /* Process Locked */ __HAL_LOCK(hspi); - + if(hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } if((pData == NULL) || (Size == 0)) - { + { errorcode = HAL_ERROR; goto error; } - + /* Configure communication */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t*)NULL; + hspi->pTxBuffPtr = (uint8_t *)NULL; hspi->TxXferSize = 0; hspi->TxXferCount = 0; - + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { /* Process Unlocked */ __HAL_UNLOCK(hspi); /* the receive process is not supported in 2Lines direction master mode */ - /* in this we call the transmitReceive process */ + /* in this we call the TransmitReceive process */ return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size); } - - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->CRCSize = 1; if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) @@ -1120,44 +1136,44 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { hspi->CRCSize = 0; } - - hspi->TxISR = (void (*)(SPI_HandleTypeDef *))NULL; - /* check the data size to adapt Rx threshold and the set the function for IT treatement */ + + hspi->TxISR = NULL; + /* check the data size to adapt Rx threshold and the set the function for IT treatment */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) { - /* set fiforxthresold according the reception data lenght: 16 bit */ + /* set fiforxthresold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_16BIT; } else { - /* set fiforxthresold according the reception data lenght: 8 bit */ + /* set fiforxthresold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_8BIT; } - + /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_RX(hspi); + SPI_1LINE_RX(hspi); } - + /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ + + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { - /* Enable SPI peripheral */ + /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - + error : /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1165,37 +1181,37 @@ error : } /** - * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData : pointer to transmission data buffer - * @param pRxData : pointer to reception data buffer to be - * @param Size : amount of data to be sent + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size: amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - + /* Process locked */ __HAL_LOCK(hspi); - + if(!((hspi->State == HAL_SPI_STATE_READY) || \ ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; } - - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { - errorcode = HAL_ERROR; + errorcode = HAL_ERROR; goto error; } - + hspi->CRCSize = 0; - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->CRCSize = 1; if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) @@ -1203,12 +1219,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->CRCSize = 2; } } - + if(hspi->State != HAL_SPI_STATE_BUSY_RX) { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; } - + hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pTxBuffPtr = pTxData; hspi->TxXferSize = Size; @@ -1216,47 +1232,47 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->pRxBuffPtr = pRxData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; - - /* Set the function for IT treatement */ + + /* Set the function for IT treatment */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) { hspi->RxISR = SPI_2linesRxISR_16BIT; - hspi->TxISR = SPI_2linesTxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; } else { hspi->RxISR = SPI_2linesRxISR_8BIT; hspi->TxISR = SPI_2linesTxISR_8BIT; } - + /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + /* check if packing mode is enabled and if there is more than 2 data to receive */ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) { - /* set fiforxthresold according the reception data lenght: 16 bit */ + /* set fiforxthresold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data lenght: 8 bit */ + /* set fiforxthresold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } - + /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ + + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { - /* Enable SPI peripheral */ + /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - + error : /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1264,63 +1280,63 @@ error : } /** - * @brief Transmit an amount of data in no-blocking mode with DMA - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData : pointer to data buffer - * @param Size : amount of data to be sent + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ +{ HAL_StatusTypeDef errorcode = HAL_OK; assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - + /* Process Locked */ __HAL_LOCK(hspi); - - if(hspi->State != HAL_SPI_STATE_READY) + + if(hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - + if((pData == NULL) || (Size == 0)) { errorcode = HAL_ERROR; goto error; } - + hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pTxBuffPtr = pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t*)NULL; + hspi->pRxBuffPtr = (uint8_t *)NULL; hspi->RxXferSize = 0; hspi->RxXferCount = 0; - + /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_TX(hspi); + SPI_1LINE_TX(hspi); } - + /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + /* Set the SPI TxDMA Half transfer complete callback */ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; - - /* Set the SPI TxDMA transfert complete callback */ + + /* Set the SPI TxDMA transfer complete callback */ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; - + /* Set the DMA error callback */ hspi->hdmatx->XferErrorCallback = SPI_DMAError; - + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); /* packing mode is enabled only if the DMA setting is HALWORD */ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) @@ -1337,83 +1353,84 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; } } - + /* Enable the Tx DMA channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - - /* Check if the SPI is already enabled */ + + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { - /* Enable SPI peripheral */ + /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - -error : + +error : /* Process Unlocked */ __HAL_UNLOCK(hspi); return errorcode; } /** - * @brief Receive an amount of data in no-blocking mode with DMA - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData : pointer to data buffer - * @param Size : amount of data to be sent - * @retval HAL status - */ + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size: amount of data to be sent + * @retval HAL status + */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - + /* Process Locked */ __HAL_LOCK(hspi); - + if(hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; goto error; } - + if((pData == NULL) || (Size == 0)) { errorcode = HAL_ERROR; goto error; } - + hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; - hspi->pTxBuffPtr = (uint8_t*)NULL; + hspi->pTxBuffPtr = (uint8_t *)NULL; hspi->TxXferSize = 0; hspi->TxXferCount = 0; - + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { /* Process Unlocked */ - __HAL_UNLOCK(hspi); + __HAL_UNLOCK(hspi); /* the receive process is not supported in 2Lines direction master mode */ - /* in this case we call the transmitReceive process */ + /* in this case we call the TransmitReceive process */ return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size); } - + /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_RX(hspi); + SPI_1LINE_RX(hspi); } - + /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + /* packing mode management is enabled by the DMA settings */ if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) { @@ -1421,83 +1438,84 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u errorcode = HAL_ERROR; goto error; } - + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); if( hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data lenght: 16bit */ + /* set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data lenght: 8bit */ + /* set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } - + /* Set the SPI RxDMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - - /* Set the SPI Rx DMA transfert complete callback */ + + /* Set the SPI Rx DMA transfer complete callback */ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - + /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Enable Rx DMA Request */ + + /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - + /* Enable the Rx DMA channel */ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); - - /* Check if the SPI is already enabled */ + + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { - /* Enable SPI peripheral */ + /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - + error: /* Process Unlocked */ - __HAL_UNLOCK(hspi); + __HAL_UNLOCK(hspi); return errorcode; } /** - * @brief Transmit and Receive an amount of data in no-blocking mode with DMA - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData : pointer to transmission data buffer - * @param pRxData : pointer to reception data buffer - * @param Size : amount of data to be sent + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - + /* Process locked */ __HAL_LOCK(hspi); - + if(!((hspi->State == HAL_SPI_STATE_READY) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; goto error; } - - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { errorcode = HAL_ERROR; goto error; } - + /* check if the transmit Receive function is not called by a receive master */ if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { + { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; } - + hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pTxBuffPtr = (uint8_t *)pTxData; hspi->TxXferSize = Size; @@ -1505,27 +1523,27 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; - + /* Reset CRC Calculation + increase the rxsize */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + /* Reset the threshold bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); - + /* the packing mode management is enabled by the DMA settings according the spi data size */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthreshold according the reception data lenght: 16bit */ + /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data lenght: 8bit */ + /* set fiforxthresold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - + if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { if((hspi->TxXferSize & 0x1) == 0x0) @@ -1539,12 +1557,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; } } - + if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* set fiforxthresold according the reception data lenght: 16bit */ + /* set fiforxthresold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - + if((hspi->RxXferCount & 0x1) == 0x0 ) { CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); @@ -1557,7 +1575,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } } } - + /* Set the SPI Rx DMA transfer complete callback if the transfer request is a reception request (RXNE) */ if(hspi->State == HAL_SPI_STATE_BUSY_RX) @@ -1572,86 +1590,87 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; } - + /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Enable Rx DMA Request */ + + /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - + /* Enable the Rx DMA channel */ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount); - + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing is performed in DMA reception complete callback */ - hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; - + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + /* Set the DMA error callback */ hspi->hdmatx->XferErrorCallback = SPI_DMAError; - + /* Enable the Tx DMA channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } - + /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - -error : + +error : /* Process Unlocked */ __HAL_UNLOCK(hspi); return errorcode; } /** - * @brief Pauses the DMA Transfer. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. + * @brief Pause the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) { /* Process Locked */ __HAL_LOCK(hspi); - + /* Disable the SPI DMA Tx & Rx requests */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - + /* Process Unlocked */ __HAL_UNLOCK(hspi); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Resumes the DMA Transfer. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. + * @brief Resume the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) { /* Process Locked */ __HAL_LOCK(hspi); - + /* Enable the SPI DMA Tx & Rx requests */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - + /* Process Unlocked */ __HAL_UNLOCK(hspi); - + return HAL_OK; } /** - * @brief Stops the DMA Transfer. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. + * @brief Stop the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) @@ -1661,7 +1680,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() */ - + /* Abort the SPI DMA tx channel */ if(hspi->hdmatx != NULL) { @@ -1672,7 +1691,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_DMA_Abort(hspi->hdmarx); } - + /* Disable the SPI DMA Tx & Rx requests */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); hspi->State = HAL_SPI_STATE_READY; @@ -1680,16 +1699,16 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) } /** - * @brief This function handles SPI interrupt request. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval None. + * @brief Handle SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None */ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) { uint32_t itsource = hspi->Instance->CR2; uint32_t itflag = hspi->Instance->SR; - + /* SPI in mode Receiver ----------------------------------------------------*/ if(((itflag & SPI_FLAG_OVR) == RESET) && ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) @@ -1697,18 +1716,18 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) hspi->RxISR(hspi); return; } - - /* SPI in mode Tramitter ---------------------------------------------------*/ + + /* SPI in mode Transmitter ---------------------------------------------------*/ if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) - { + { hspi->TxISR(hspi); return; } - - /* SPI in Erreur Treatment ---------------------------------------------------*/ - if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) + + /* SPI in Error Treatment ---------------------------------------------------*/ + if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) { - /* SPI Overrun error interrupt occured -------------------------------------*/ + /* SPI Overrun error interrupt occurred -------------------------------------*/ if((itflag & SPI_FLAG_OVR) != RESET) { if(hspi->State != HAL_SPI_STATE_BUSY_TX) @@ -1721,21 +1740,21 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) return; } } - - /* SPI Mode Fault error interrupt occured -------------------------------------*/ + + /* SPI Mode Fault error interrupt occurred -------------------------------------*/ if((itflag & SPI_FLAG_MODF) != RESET) - { + { hspi->ErrorCode |= HAL_SPI_ERROR_MODF; __HAL_SPI_CLEAR_MODFFLAG(hspi); } - - /* SPI Frame error interrupt occured ----------------------------------------*/ + + /* SPI Frame error interrupt occurred ----------------------------------------*/ if((itflag & SPI_FLAG_FRE) != RESET) - { + { hspi->ErrorCode |= HAL_SPI_ERROR_FRE; __HAL_SPI_CLEAR_FREFLAG(hspi); } - + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); hspi->State = HAL_SPI_STATE_READY; HAL_SPI_ErrorCallback(hspi); @@ -1744,154 +1763,135 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } /** - * @brief Flush the RX fifo. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi) -{ - __IO uint32_t tmpreg; - uint8_t count = 0; - while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) - { - count++; - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); - if(count == SPI_FIFO_SIZE) - { - return HAL_TIMEOUT; - } - }; - return HAL_OK; -} - -/** - * @brief Tx Transfer completed callbacks - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Tx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxCpltCallback could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ } /** - * @brief Rx Transfer completed callbacks - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_RxCpltCallback could be implenetd in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file */ } - + /** - * @brief Tx and Rx Transfer completed callbacks - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Tx and Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxRxCpltCallback could be implenetd in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file */ } /** - * @brief Tx Half Transfer completed callbacks - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Tx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file */ } /** - * @brief Rx Half Transfer completed callbacks - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Rx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file */ } /** - * @brief Tx and Rx Transfer completed callbacks - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Tx and Rx Half Transfer callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file */ } /** - * @brief SPI error callbacks - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief SPI error callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_ErrorCallback could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ } /** * @} */ -/** @defgroup SPI_Exported_Functions_Group3 Peripheral Control functions - * @brief SPI control functions +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions * -@verbatim +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== [..] This subsection provides a set of functions allowing to control the SPI. - (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral (+) HAL_SPI_GetError() check in run-time Errors occurring during communication @endverbatim * @{ */ /** - * @brief Return the SPI state - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * @brief Return the SPI handle state. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval SPI state */ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) { + /* Return SPI handle state */ return hspi->State; } /** - * @brief Return the SPI error code - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval SPI Error Code + * @brief Return the SPI error code. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format */ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) { @@ -1907,35 +1907,41 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) * @} */ -/** @addtogroup SPI_Private_Functions SPI Private Functions - * @brief Data transfers Private functions +/** @addtogroup SPI_Private_Functions + * @brief Private functions * @{ */ /** - * @brief DMA SPI transmit process complete callback - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None. + * @brief DMA SPI transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None */ -static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { /* Disable Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */ + + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } - + hspi->TxXferCount = 0; hspi->State = HAL_SPI_STATE_READY; - + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); @@ -1946,66 +1952,73 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI receive process complete callback - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None. + * @brief DMA SPI receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None */ -static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { __IO uint16_t tmpreg; - + /* CRC handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until TXE flag */ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) { - /* Erreur on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + /* Error on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { + { tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); } else { tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); + if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) { - /* Erreur on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + /* Error on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); } } } - + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); /* Check the end of the transaction */ - SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); - + if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + { + hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + } + hspi->RxXferCount = 0; hspi->State = HAL_SPI_STATE_READY; - + /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { hspi->ErrorCode|= HAL_SPI_ERROR_CRC; __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } - + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); @@ -2016,58 +2029,65 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI transmit receive process complete callback + * @brief DMA SPI transmit receive process complete callback. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None. + * the configuration information for the specified DMA module. + * @retval None */ -static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { __IO int16_t tmpreg; /* CRC handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) - { + { if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) { - /* Erreur on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + /* Error on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); } else { if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) { - /* Erreur on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + /* Error on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); } - } - + } + + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + /* Disable Rx/Tx DMA Request */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - hspi->TxXferCount = 0; hspi->RxXferCount = 0; hspi->State = HAL_SPI_STATE_READY; - + /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { - hspi->ErrorCode = HAL_SPI_ERROR_CRC; + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } - + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { HAL_SPI_ErrorCallback(hspi); @@ -2078,10 +2098,10 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI half transmit process complete callback + * @brief DMA SPI half transmit process complete callback. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None. + * the configuration information for the specified DMA module. + * @retval None */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { @@ -2091,10 +2111,10 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI half receive process complete callback + * @brief DMA SPI half receive process complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None. + * the configuration information for the specified DMA module. + * @retval None */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { @@ -2104,12 +2124,12 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI Half transmit receive process complete callback + * @brief DMA SPI half transmit receive process complete callback. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None. + * the configuration information for the specified DMA module. + * @retval None */ -static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; @@ -2117,28 +2137,28 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI communication error callback + * @brief DMA SPI communication error callback. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None. + * the configuration information for the specified DMA module. + * @retval None */ -static void SPI_DMAError(DMA_HandleTypeDef *hdma) +static void SPI_DMAError(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - + hspi->ErrorCode|= HAL_SPI_ERROR_DMA; hspi->State = HAL_SPI_STATE_READY; HAL_SPI_ErrorCallback(hspi); } /** - * @brief Rx Handler for Transmit and Receive in Interrupt mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { @@ -2148,11 +2168,11 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount -= 2; - if(hspi->RxXferCount == 1) + if(hspi->RxXferCount == 1) { - /* set fiforxthresold according the reception data lenght: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } + /* set fiforxthresold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } } /* Receive data in 8 Bit mode */ else @@ -2160,19 +2180,20 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); hspi->RxXferCount--; } - + /* check end of the reception */ if(hspi->RxXferCount == 0) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->RxISR = SPI_2linesRxISR_8BITCRC; + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_2linesRxISR_8BITCRC; return; } - + /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + if(hspi->TxXferCount == 0) { SPI_CloseRxTx_ISR(hspi); @@ -2181,23 +2202,25 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Rx Handler for Transmit and Receive in Interrupt mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ UNUSED(tmpreg); + hspi->CRCSize--; - + /* check end of the reception */ if(hspi->CRCSize == 0) { /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + if(hspi->TxXferCount == 0) { SPI_CloseRxTx_ISR(hspi); @@ -2206,10 +2229,10 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Tx Handler for Transmit and Receive in Interrupt mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { @@ -2222,52 +2245,52 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /* Transmit data in 8 Bit mode */ else - { + { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; } - + /* check the end of the transmission */ if(hspi->TxXferCount == 0) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - + if(hspi->RxXferCount == 0) - { + { SPI_CloseRxTx_ISR(hspi); } } } /** - * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Receive data in 16 Bit mode */ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - + hspi->RxXferCount--; + if(hspi->RxXferCount == 0) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->RxISR = SPI_2linesRxISR_16BITCRC; + hspi->RxISR = SPI_2linesRxISR_16BITCRC; return; } - + /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + if(hspi->TxXferCount == 0) { SPI_CloseRxTx_ISR(hspi); @@ -2276,28 +2299,29 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { /* Receive data in 16 Bit mode */ __IO uint16_t tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); - + /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + SPI_CloseRxTx_ISR(hspi); } /** - * @brief Tx Handler for Transmit and Receive in Interrupt mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { @@ -2305,64 +2329,66 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; - + /* Enable CRC Transmission */ if(hspi->TxXferCount == 0) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } /* Disable TXE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - + if(hspi->RxXferCount == 0) - { + { SPI_CloseRxTx_ISR(hspi); } } } /** - * @brief Manage the CRC receive in Interrupt context - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t tmpreg = *((uint8_t*)&hspi->Instance->DR); + __IO uint8_t tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); + /* To avoid GCC warning */ UNUSED(tmpreg); + hspi->CRCSize--; - + if(hspi->CRCSize == 0) - { + { SPI_CloseRx_ISR(hspi); } } /** - * @brief Manage the recieve in Interrupt context - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); hspi->RxXferCount--; - + /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } - + if(hspi->RxXferCount == 0) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->RxISR = SPI_RxISR_8BITCRC; + hspi->RxISR = SPI_RxISR_8BITCRC; return; } SPI_CloseRx_ISR(hspi); @@ -2370,45 +2396,46 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Manage the CRC 16bit recieve in Interrupt context - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { __IO uint16_t tmpreg; - + tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ UNUSED(tmpreg); - + /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - + SPI_CloseRx_ISR(hspi); } /** - * @brief Manage the 16Bit recieve in Interrupt context - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; - + /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } - + if(hspi->RxXferCount == 0) - { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->RxISR = SPI_RxISR_16BITCRC; return; @@ -2418,19 +2445,19 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Handle the data 8Bit transmit in Interrupt mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; - + if(hspi->TxXferCount == 0) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Enable CRC Transmission */ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; @@ -2440,21 +2467,21 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Handle the data 16Bit transmit in Interrupt mode - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ +{ /* Transmit data in 16 Bit mode */ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; - + if(hspi->TxXferCount == 0) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Enable CRC Transmission */ hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; @@ -2464,9 +2491,9 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief This function handles SPI Communication Timeout. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * @brief Handle SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param Flag : SPI flag to check * @param State : flag state to check * @param Timeout : Timeout duration @@ -2475,7 +2502,7 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - + while((hspi->Instance->SR & Flag) != State) { if(Timeout != HAL_MAX_DELAY) @@ -2485,39 +2512,39 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ - + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); } - + /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + hspi->State= HAL_SPI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hspi); - + return HAL_TIMEOUT; } } } - - return HAL_OK; + + return HAL_OK; } /** - * @brief This function handles SPI Communication Timeout. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @param Fifo : Fifo to check * @param State : Fifo state to check * @param Timeout : Timeout duration @@ -2533,9 +2560,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) { tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); + /* To avoid GCC warning */ UNUSED(tmpreg); } - + if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) @@ -2543,40 +2571,40 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ - + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); } - + /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + hspi->State = HAL_SPI_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hspi); - + return HAL_TIMEOUT; } } } - - return HAL_OK; + + return HAL_OK; } /** - * @brief This function handles the check of the RX transaction complete. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Timeout : Timeout duration + * @brief Handle the check of the RX transaction complete. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout : Timeout duration * @retval None. */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) @@ -2585,32 +2613,66 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); - - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) - { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; - return HAL_TIMEOUT; - } - if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) + } + + /* Control the BSY flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + return HAL_TIMEOUT; + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Empty the FRLVL fifo */ + if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) { hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; return HAL_TIMEOUT; } - } + } return HAL_OK; } - + /** - * @brief This function handles the close of the RXTX transaction. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Handle the check of the RXTX or TX transaction complete. + * @param hspi: SPI handle + * @param Timeout : Timeout duration + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) +{ + /* Control if the TX fifo is empty */ + if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + return HAL_TIMEOUT; + } + /* Control the BSY flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) + { + hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + return HAL_TIMEOUT; + } + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { /* Disable ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); - + + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + { + hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + } + /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { @@ -2632,7 +2694,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { hspi->State = HAL_SPI_STATE_READY; HAL_SPI_TxRxCpltCallback(hspi); - } + } } else { @@ -2643,33 +2705,35 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) } /** - * @brief This function handles the close of the RX transaction. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Handle the end of the RX transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) { /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - + /* Check the end of the transaction */ - SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); - - hspi->State = HAL_SPI_STATE_READY; - + if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + { + hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + } + hspi->State = HAL_SPI_STATE_READY; + /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { hspi->ErrorCode|= HAL_SPI_ERROR_CRC; __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_ErrorCallback(hspi); + HAL_SPI_ErrorCallback(hspi); } else { if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) { - HAL_SPI_RxCpltCallback(hspi); + HAL_SPI_RxCpltCallback(hspi); } else { @@ -2679,22 +2743,28 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) } /** - * @brief This function handles the close of the TX transaction. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None. + * @brief Handle the end of the TX transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) { /* Disable TXE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + + /* Check the end of the transaction */ + if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) + { + hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } - + hspi->State = HAL_SPI_STATE_READY; if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { @@ -2711,6 +2781,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) */ #endif /* HAL_SPI_MODULE_ENABLED */ + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h index b9ecd1716d..ceff758fe0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_spi.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -52,26 +52,26 @@ /** @addtogroup SPI * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup SPI_Exported_Types SPI Exported Types * @{ */ -/** - * @brief SPI Configuration Structure definition +/** + * @brief SPI Configuration Structure definition */ typedef struct { uint32_t Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ + This parameter can be a value of @ref SPI_Mode */ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. This parameter can be a value of @ref SPI_Direction */ uint32_t DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ + This parameter can be a value of @ref SPI_Data_Size */ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_Clock_Polarity */ @@ -91,7 +91,7 @@ typedef struct uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not . This parameter can be a value of @ref SPI_TI_mode */ @@ -101,75 +101,74 @@ typedef struct uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ - uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. - CRC Length is only used with Data8 and Data16, not other data size - This parameter must 0 or 1 or 2*/ + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + CRC Length is only used with Data8 and Data16, not other data size + This parameter can be a value of @ref SPI_CRC_length */ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . This parameter can be a value of @ref SPI_NSSP_Mode - This mode is activated by the NSSP bit in the SPIx_CR2 register and - it takes effect only if the SPI interface is configured as Motorola SPI - master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, + This mode is activated by the NSSP bit in the SPIx_CR2 register and + it takes effect only if the SPI interface is configured as Motorola SPI + master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, CPOL setting is ignored).. */ } SPI_InitTypeDef; -/** - * @brief HAL State structures definition - */ +/** + * @brief HAL State structures definition + */ typedef enum { HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */ HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */ HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */ }HAL_SPI_StateTypeDef; -/** - * @brief SPI handle Structure definition - */ +/** + * @brief SPI handle Structure definition + */ typedef struct __SPI_HandleTypeDef { - SPI_TypeDef *Instance; /*!< SPI registers base address */ - - SPI_InitTypeDef Init; /*!< SPI communication parameters */ - - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< SPI Tx Transfer size */ - - uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + SPI_TypeDef *Instance; /* SPI registers base address */ - uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< SPI Rx Transfer size */ - - uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ - - uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ + SPI_InitTypeDef Init; /* SPI communication parameters */ - void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */ - - void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */ + uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ - DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + uint16_t TxXferSize; /* SPI Tx Transfer size */ - DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ + uint16_t TxXferCount; /* SPI Tx Transfer Counter */ - HAL_SPI_StateTypeDef State; /*!< SPI communication state */ - - __IO uint32_t ErrorCode; /*!< SPI Error code - This parameter can be a value of @ref SPI_Error */ + uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /* SPI Rx Transfer size */ + + uint16_t RxXferCount; /* SPI Rx Transfer Counter */ + + uint32_t CRCSize; /* SPI CRC size used for the transfer */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /* Locking object */ + + __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ + + uint32_t ErrorCode; /* SPI Error code */ }SPI_HandleTypeDef; /** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ @@ -177,24 +176,25 @@ typedef struct __SPI_HandleTypeDef * @{ */ -/** @defgroup SPI_Error SPI Error +/** @defgroup SPI_Error_Code SPI Error Code * @{ - */ - #define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ - #define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /*!< MODF error */ - #define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /*!< CRC error */ - #define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */ - #define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */ - #define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ - #define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020) /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */ - #define HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040) /*!< Unknow Error error */ + */ +#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */ +#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknown error */ /** * @} */ -/** @defgroup SPI_mode SPI mode + +/** @defgroup SPI_Mode SPI Mode * @{ - */ + */ #define SPI_MODE_SLAVE ((uint32_t)0x00000000) #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ @@ -203,12 +203,12 @@ typedef struct __SPI_HandleTypeDef * @} */ -/** @defgroup SPI_Direction SPI Direction +/** @defgroup SPI_Direction SPI Direction Mode * @{ */ -#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) -#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY -#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\ @@ -221,23 +221,23 @@ typedef struct __SPI_HandleTypeDef /** * @} */ - -/** @defgroup SPI_data_size SPI Data size + +/** @defgroup SPI_Data_Size SPI Data Size * @{ */ -#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) /*!< SPI Datasize = 4bits */ -#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) /*!< SPI Datasize = 5bits */ -#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) /*!< SPI Datasize = 6bits */ -#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) /*!< SPI Datasize = 7bits */ -#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) /*!< SPI Datasize = 8bits */ -#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) /*!< SPI Datasize = 9bits */ -#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) /*!< SPI Datasize = 10bits */ -#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) /*!< SPI Datasize = 11bits */ -#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) /*!< SPI Datasize = 12bits */ -#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) /*!< SPI Datasize = 13bits */ -#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */ -#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */ -#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */ +#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) /*!< SPI Datasize = 4bits */ +#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) /*!< SPI Datasize = 5bits */ +#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) /*!< SPI Datasize = 6bits */ +#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) /*!< SPI Datasize = 7bits */ +#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) /*!< SPI Datasize = 8bits */ +#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) /*!< SPI Datasize = 9bits */ +#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) /*!< SPI Datasize = 10bits */ +#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) /*!< SPI Datasize = 11bits */ +#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) /*!< SPI Datasize = 12bits */ +#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) /*!< SPI Datasize = 13bits */ +#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */ +#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */ +#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */ #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ ((DATASIZE) == SPI_DATASIZE_15BIT) || \ ((DATASIZE) == SPI_DATASIZE_14BIT) || \ @@ -251,14 +251,13 @@ typedef struct __SPI_HandleTypeDef ((DATASIZE) == SPI_DATASIZE_6BIT) || \ ((DATASIZE) == SPI_DATASIZE_5BIT) || \ ((DATASIZE) == SPI_DATASIZE_4BIT)) - /** * @} - */ + */ /** @defgroup SPI_Clock_Polarity SPI Clock Polarity * @{ - */ + */ #define SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< SPI polarity Low */ #define SPI_POLARITY_HIGH SPI_CR1_CPOL /*!< SPI polarity High */ #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ @@ -280,7 +279,7 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Slave_Select_management SPI Slave Select management * @{ - */ + */ #define SPI_NSS_SOFT SPI_CR1_SSM #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000) @@ -290,19 +289,19 @@ typedef struct __SPI_HandleTypeDef /** * @} */ - -/** @defgroup SPI_NSSP_Mode SPI NSS pulse management + +/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode * @{ - */ -#define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP -#define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000) + */ +#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP +#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000) -#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) || \ - ((NSSP) == SPI_NSS_PULSE_DISABLED)) +#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ + ((NSSP) == SPI_NSS_PULSE_DISABLE)) /** * @} */ - + /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler * @{ */ @@ -324,11 +323,11 @@ typedef struct __SPI_HandleTypeDef ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) /** * @} - */ + */ /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission * @{ - */ + */ #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ @@ -340,53 +339,53 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_TI_mode SPI TI mode * @{ */ -#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) -#define SPI_TIMODE_ENABLED SPI_CR2_FRF -#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \ - ((MODE) == SPI_TIMODE_ENABLED)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Calculation SPI CRC Calculation - * @{ - */ -#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000) -#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN -#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \ - ((CALCULATION) == SPI_CRCCALCULATION_ENABLED)) +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) +#define SPI_TIMODE_ENABLE SPI_CR2_FRF +#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ + ((MODE) == SPI_TIMODE_ENABLE)) /** * @} */ -/** @defgroup SPI_CRC_length SPI CRC length +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_length SPI CRC Length * @{ * This parameter can be one of the following values: - * SPI_CRC_LENGTH_DATASIZE: aligned with the data size + * SPI_CRC_LENGTH_DATASIZE: aligned with the data size * SPI_CRC_LENGTH_8BIT : CRC 8bit - * SPI_CRC_LENGTH_16BIT : CRC 16bit + * SPI_CRC_LENGTH_16BIT : CRC 16bit */ -#define SPI_CRC_LENGTH_DATASIZE 0 -#define SPI_CRC_LENGTH_8BIT 1 -#define SPI_CRC_LENGTH_16BIT 2 +#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000) +#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001) +#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002) #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_16BIT)) /** * @} */ - -/** @defgroup SPI_FIFO_reception_threshold SPI FIFO reception threshold + +/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold * @{ * This parameter can be one of the following values: * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : - * RXNE event is generated if the FIFO - * level is greater or equal to 1/2(16-bits). - * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO + * RXNE event is generated if the FIFO + * level is greater or equal to 1/2(16-bits). + * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO * level is greater or equal to 1/4(8 bits). */ -#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH -#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH -#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0) +#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000) /** * @} @@ -411,8 +410,8 @@ typedef struct __SPI_HandleTypeDef * Elements values convention: 0xXXXXYYYY * - XXXX : Flag register Index * - YYYY : Flag mask - * @{ - */ + * @{ + */ #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ @@ -426,25 +425,25 @@ typedef struct __SPI_HandleTypeDef * @} */ -/** @defgroup SPI_transmission_fifo_status_level SPI transmission fifo status level +/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level * @{ - */ + */ #define SPI_FTLVL_EMPTY ((uint32_t)0x0000) -#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800) -#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000) +#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800) +#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000) #define SPI_FTLVL_FULL ((uint32_t)0x1800) /** * @} - */ + */ -/** @defgroup SPI_reception_fifo_status_level SPI reception fifo status level +/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level * @{ - */ + */ #define SPI_FRLVL_EMPTY ((uint32_t)0x0000) -#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200) -#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400) -#define SPI_FRLVL_FULL ((uint32_t)0x0600) +#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200) +#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400) +#define SPI_FRLVL_FULL ((uint32_t)0x0600) /** * @} */ @@ -453,22 +452,21 @@ typedef struct __SPI_HandleTypeDef * @} */ - /* Exported macros ------------------------------------------------------------*/ /** @defgroup SPI_Exported_Macros SPI Exported Macros * @{ */ - -/** @brief Reset SPI handle state + +/** @brief Reset SPI handle state. * @param __HANDLE__: SPI handle. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -/** @brief Enables or disables the specified SPI interrupts. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Enable or disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__ : specifies the interrupt source to enable or disable. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -477,11 +475,11 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) - -/** @brief Checks if the specified SPI interrupt source is enabled or disabled. - * @param __HANDLE__ : specifies the SPI Handle. + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__ : specifies the SPI interrupt source to check. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -490,10 +488,10 @@ typedef struct __SPI_HandleTypeDef */ #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** @brief Checks whether the specified SPI flag is set or not. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__ : specifies the flag to check. + * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -501,111 +499,127 @@ typedef struct __SPI_HandleTypeDef * @arg SPI_FLAG_MODF: Mode fault flag * @arg SPI_FLAG_OVR: Overrun flag * @arg SPI_FLAG_BSY: Busy flag - * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FRE: Frame format error flag * @arg SPI_FLAG_FTLVL: SPI fifo transmission level - * @arg SPI_FLAG_FRLVL: SPI fifo reception level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) -/** @brief Clears the SPI CRCERR pending flag. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) - -/** @brief Clears the SPI MODF pending flag. - * @param __HANDLE__ : specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * - * @retval None - */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{\ - __IO uint32_t tmpreg;\ - tmpreg = (__HANDLE__)->Instance->SR;\ - UNUSED(tmpreg); \ - (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);\ - }while(0) -/** @brief Clears the SPI OVR pending flag. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * + * * @retval None - */ -#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg); \ - } while(0) - -/** @brief Clears the SPI FRE pending flag. - * @param __HANDLE__ : specifies the SPI Handle. + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * + * * @retval None - */ -#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{\ - __IO uint32_t tmpreg;\ - tmpreg = ((__HANDLE__)->Instance->SR);\ - UNUSED(tmpreg); \ - }while(0) -/** @brief Enables the SPI. - * @param __HANDLE__ : specifies the SPI Handle. + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) -/** @brief Disables the SPI. - * @param __HANDLE__ : specifies the SPI Handle. +/** @brief Disable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE)) -/** @brief Sets the SPI transmit-only mode. - * @param __HANDLE__ : specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) - -/** @brief Sets the SPI receive-only mode. - * @param __HANDLE__ : specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) - -/** @brief Resets the CRC calculation of the SPI. - * @param __HANDLE__ : specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ - (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) - - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) /** * @} */ - + +/* Private macros --------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) + +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) + +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ + (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) + + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) + + +/** + * @} + */ + +/* Include SPI HAL Extended module */ +#include "stm32f0xx_hal_spi_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SPI_Exported_Functions * @{ */ -/** @addtogroup SPI_Exported_Functions_Group1 +/* Initialization and de-initialization functions ****************************/ +/** @addtogroup SPI_Exported_Functions_Group1 * @{ */ - -/* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); @@ -613,11 +627,10 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); * @} */ +/* IO operation functions *****************************************************/ /** @addtogroup SPI_Exported_Functions_Group2 * @{ */ - -/* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); @@ -630,7 +643,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi); void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); @@ -644,13 +656,12 @@ void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); * @} */ +/* Peripheral State and Error functions ***************************************/ /** @addtogroup SPI_Exported_Functions_Group3 * @{ */ - -/* Peripheral State and Error functions ***************************************/ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); /** * @} */ @@ -658,14 +669,14 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); /** * @} */ - -/** - * @} - */ /** * @} - */ + */ + +/** + * @} + */ #ifdef __cplusplus } @@ -674,4 +685,3 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #endif /* __STM32F0xx_HAL_SPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.c new file mode 100644 index 0000000000..deaa80feb7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.c @@ -0,0 +1,133 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_spi_ex.c + * @author MCD Application Team + * @version V1.3.0 + * @date 26-June-2015 + * @brief Extended SPI HAL module driver. + * This file provides firmware functions to manage the following + * SPI peripheral extended functionalities : + * + IO operation functions + * + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @defgroup SPIEx SPIEx + * @brief SPI Extended HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPIEx_Private_Constants SPIEx Private Constants + * @{ + */ +#define SPI_FIFO_SIZE 4 +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + * @{ + */ + +/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of extended functions to manage the SPI + data transfers. + + (#) Rx data flush function: + (++) HAL_SPIEx_FlushRxFifo() + +@endverbatim + * @{ + */ + +/** + * @brief Flush the RX fifo. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg; + uint8_t count = 0; + while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) + { + count++; + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* To avoid GCC warning */ + if(count == SPI_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.h new file mode 100644 index 0000000000..3b663da0b2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.h @@ -0,0 +1,93 @@ + /** + ****************************************************************************** + * @file stm32f0xx_hal_spi_ex.h + * @author MCD Application Team + * @version V1.3.0 + * @date 26-June-2015 + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_SPI_EX_H +#define __STM32F0xx_HAL_SPI_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal_def.h" + +/** @addtogroup STM32F0xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPIEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ +/** @addtogroup SPIEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_SPI_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c index a6284fd928..3ae85fa17f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_tim.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -35,7 +35,7 @@ ============================================================================== ##### TIMER Generic features ##### ============================================================================== - [..] The Timer features include: + [..] The Timer features include: (#) 16-bit up, down, up/down auto-reload counter. (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock frequency either by any factor between 1 and 65536. @@ -43,32 +43,32 @@ (++) Input Capture (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - + (++) One-pulse mode output + ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending from feature used : - (++) Time Base : HAL_TIM_Base_MspInit() + (++) Time Base : HAL_TIM_Base_MspInit() (++) Input Capture : HAL_TIM_IC_MspInit() (++) Output Compare : HAL_TIM_OC_MspInit() (++) PWM generation : HAL_TIM_PWM_MspInit() (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - + (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. - + (#) Configure the TIM in the desired functioning mode using one of the Initialization function of this driver: (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base @@ -82,7 +82,7 @@ in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() @@ -93,12 +93,12 @@ (#) The DMA Burst is managed with the two following functions: HAL_TIM_DMABurst_WriteStart() HAL_TIM_DMABurst_ReadStart() - + @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -122,8 +122,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -132,7 +132,7 @@ * @{ */ -/** @defgroup TIM TIM HAL module driver +/** @defgroup TIM TIM * @brief TIM HAL module driver * @{ */ @@ -180,13 +180,13 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** @defgroup TIM_Exported_Functions_Group1 Time Base functions * @brief Time Base functions * -@verbatim +@verbatim ============================================================================== ##### Time Base functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: - (+) Initialize and configure the TIM base. + (+) Initialize and configure the TIM base. (+) De-initialize the TIM base. (+) Start the Time Base. (+) Stop the Time Base. @@ -194,7 +194,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, (+) Stop the Time Base and disable interrupt. (+) Start the Time Base and enable DMA transfer. (+) Stop the Time Base and disable DMA transfer. - + @endverbatim * @{ */ @@ -205,33 +205,36 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ +{ /* Check the TIM handle allocation */ if(htim == NULL) { return HAL_ERROR; } - + /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - + if(htim->State == HAL_TIM_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); } - + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - + /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - + TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the TIM state*/ htim->State= HAL_TIM_STATE_READY; - + return HAL_OK; } @@ -244,18 +247,18 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + htim->State = HAL_TIM_STATE_BUSY; - + /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + /* Release Lock */ __HAL_UNLOCK(htim); @@ -296,16 +299,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Change the TIM state*/ htim->State= HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -319,16 +322,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the TIM state*/ htim->State= HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -342,13 +345,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -364,10 +367,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -380,40 +383,40 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ +{ /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if((pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } + } /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); - + /* Enable the TIM Update DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } @@ -427,16 +430,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - + /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -444,17 +447,17 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @} */ - + /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions * @brief Time Output Compare functions * -@verbatim +@verbatim ============================================================================== ##### Time Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. + (+) Initialize and configure the TIM Output Compare. (+) De-initialize the TIM Output Compare. (+) Start the Time Output Compare. (+) Stop the Time Output Compare. @@ -462,7 +465,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) (+) Stop the Time Output Compare and disable interrupt. (+) Start the Time Output Compare and enable DMA transfer. (+) Stop the Time Output Compare and disable DMA transfer. - + @endverbatim * @{ */ @@ -484,22 +487,25 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - + if(htim->State == HAL_TIM_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); } - + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the TIM state*/ htim->State= HAL_TIM_STATE_READY; - + return HAL_OK; } @@ -512,18 +518,18 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + htim->State = HAL_TIM_STATE_BUSY; - + /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + /* Release Lock */ __HAL_UNLOCK(htim); @@ -556,32 +562,32 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle + * @param htim : TIM Output Compare handle * @param Channel : TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } @@ -601,22 +607,22 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); - } - + } + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; -} +} /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. @@ -633,45 +639,45 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); } break; - + default: break; - } + } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -679,7 +685,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -699,53 +705,53 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); } break; - + default: - break; - } - + break; + } + /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); } - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } @@ -767,104 +773,104 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } + } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); - } - + } + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } @@ -884,56 +890,56 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; - } - + } + /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); } - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -945,13 +951,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions * @brief Time PWM functions * -@verbatim +@verbatim ============================================================================== ##### Time PWM functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. + (+) Initialize and configure the TIM OPWM. (+) De-initialize the TIM PWM. (+) Start the Time PWM. (+) Stop the Time PWM. @@ -959,7 +965,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) (+) Stop the Time PWM and disable interrupt. (+) Start the Time PWM and enable DMA transfer. (+) Stop the Time PWM and disable DMA transfer. - + @endverbatim * @{ */ @@ -984,19 +990,22 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); } /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the TIM state*/ htim->State= HAL_TIM_STATE_READY; - + return HAL_OK; } @@ -1009,18 +1018,18 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + htim->State = HAL_TIM_STATE_BUSY; - + /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + /* Release Lock */ __HAL_UNLOCK(htim); @@ -1066,22 +1075,22 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Stops the PWM signal generation. @@ -1095,28 +1104,28 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ +{ /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); } - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; -} +} /** * @brief Starts the PWM signal generation in interrupt mode. @@ -1133,45 +1142,45 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); } break; - + default: break; - } - + } + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1179,10 +1188,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Stops the PWM signal generation in interrupt mode. @@ -1199,56 +1208,56 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); } break; - + default: - break; + break; } - + /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); } - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Starts the TIM PWM signal generation in DMA mode. @@ -1267,104 +1276,104 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } + } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } @@ -1384,56 +1393,56 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; - } - + } + /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); } - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1445,13 +1454,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions * @brief Time Input Capture functions * -@verbatim +@verbatim ============================================================================== ##### Time Input Capture functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. + (+) Initialize and configure the TIM Input Capture. (+) De-initialize the TIM Input Capture. (+) Start the Time Input Capture. (+) Stop the Time Input Capture. @@ -1459,7 +1468,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel (+) Stop the Time Input Capture and disable interrupt. (+) Start the Time Input Capture and enable DMA transfer. (+) Stop the Time Input Capture and disable DMA transfer. - + @endverbatim * @{ */ @@ -1480,23 +1489,26 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); if(htim->State == HAL_TIM_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); } - + /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the TIM state*/ htim->State= HAL_TIM_STATE_READY; - + return HAL_OK; } @@ -1509,18 +1521,18 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + htim->State = HAL_TIM_STATE_BUSY; - + /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspDeInit(htim); - - /* Change TIM state */ + + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(htim); @@ -1566,16 +1578,16 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); /* Return function status */ - return HAL_OK; -} + return HAL_OK; +} /** * @brief Stops the TIM Input Capture measurement. @@ -1589,16 +1601,16 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ +{ /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } @@ -1618,49 +1630,49 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); } break; - + default: break; - } + } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); /* Return function status */ - return HAL_OK; -} + return HAL_OK; +} /** * @brief Stops the TIM Input Capture measurement in interrupt mode. @@ -1677,47 +1689,47 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); } break; - + default: - break; - } - + break; + } + /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } @@ -1740,99 +1752,99 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if((pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } - + } + switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - + /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - + /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - + /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } @@ -1853,50 +1865,50 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; } /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1907,13 +1919,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions * @brief Time One Pulse functions * -@verbatim +@verbatim ============================================================================== ##### Time One Pulse functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. + (+) Initialize and configure the TIM One Pulse. (+) De-initialize the TIM One Pulse. (+) Start the Time One Pulse. (+) Stop the Time One Pulse. @@ -1921,7 +1933,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) (+) Stop the Time One Pulse and disable interrupt. (+) Start the Time One Pulse and enable DMA transfer. (+) Stop the Time One Pulse and disable DMA transfer. - + @endverbatim * @{ */ @@ -1948,33 +1960,36 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - + if(htim->State == HAL_TIM_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); } - + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - + /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - + /* Reset the OPM Bit */ htim->Instance->CR1 &= ~TIM_CR1_OPM; /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; - + /* Initialize the TIM state*/ htim->State= HAL_TIM_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitializes the TIM One Pulse + * @brief DeInitializes the TIM One Pulse * @param htim : TIM One Pulse handle * @retval HAL status */ @@ -1982,18 +1997,18 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + htim->State = HAL_TIM_STATE_BUSY; - + /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_OnePulse_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + /* Release Lock */ __HAL_UNLOCK(htim); @@ -2040,19 +2055,19 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - + No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - + /* Return function status */ return HAL_OK; } @@ -2073,19 +2088,19 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); } - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } @@ -2106,25 +2121,25 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - + No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ - + /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - + /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } - + /* Return function status */ return HAL_OK; } @@ -2141,28 +2156,28 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - + /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); } - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } @@ -2174,13 +2189,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions * @brief Time Encoder functions * -@verbatim +@verbatim ============================================================================== ##### Time Encoder functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. + (+) Initialize and configure the TIM Encoder. (+) De-initialize the TIM Encoder. (+) Start the Time Encoder. (+) Stop the Time Encoder. @@ -2188,7 +2203,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (+) Stop the Time Encoder and disable interrupt. (+) Start the Time Encoder and enable DMA transfer. (+) Stop the Time Encoder and disable DMA transfer. - + @endverbatim * @{ */ @@ -2203,13 +2218,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini uint32_t tmpsmcr = 0; uint32_t tmpccmr1 = 0; uint32_t tmpccer = 0; - + /* Check the TIM handle allocation */ if(htim == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); @@ -2223,20 +2238,23 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); if(htim->State == HAL_TIM_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); } - + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - + /* Reset the SMS bits */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; - + /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - + TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; @@ -2252,7 +2270,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); - + /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); @@ -2263,7 +2281,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); - + /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; @@ -2272,16 +2290,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; - + /* Initialize the TIM state*/ htim->State= HAL_TIM_STATE_READY; - + return HAL_OK; } /** - * @brief DeInitializes the TIM Encoder interface + * @brief DeInitializes the TIM Encoder interface * @param htim : TIM Encoder handle * @retval HAL status */ @@ -2289,18 +2307,18 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + htim->State = HAL_TIM_STATE_BUSY; - + /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Encoder_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + /* Release Lock */ __HAL_UNLOCK(htim); @@ -2338,36 +2356,37 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - + /* Enable the encoder interface channels */ switch (Channel) { case TIM_CHANNEL_1: { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; - } + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; } - } + } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -2379,38 +2398,39 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - + /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ switch (Channel) { case TIM_CHANNEL_1: { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); break; - } + } + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } default : { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; } } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -2422,42 +2442,43 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - + /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ switch (Channel) { case TIM_CHANNEL_1: { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } + break; + } case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; - } + } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; + break; } - } - + } + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -2469,45 +2490,46 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - + /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if(Channel == TIM_CHANNEL_1) { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + /* Disable the capture compare Interrupts 1 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } + } else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + /* Disable the capture compare Interrupts 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } + } else { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + /* Disable the capture compare Interrupts 1 and 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -2519,6 +2541,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @param pData1 : The destination Buffer address for IC1. * @param pData2 : The destination Buffer address for IC2. * @param Length : The length of data to be transferred from TIM peripheral to memory. @@ -2528,105 +2551,105 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch { /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) + if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } - + } + switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); - - /* Enable the TIM Input Capture DMA request */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); + + /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); } break; - + case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - + /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); } break; - + case TIM_CHANNEL_ALL: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); - + /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - + /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); } break; - + default: break; - } + } /* Return function status */ return HAL_OK; } @@ -2638,45 +2661,46 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - + /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if(Channel == TIM_CHANNEL_1) { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + /* Disable the capture compare DMA Request 1 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } + } else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + /* Disable the capture compare DMA Request 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } + } else { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + /* Disable the capture compare DMA Request 1 and 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -2687,13 +2711,13 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief IRQ handler management * -@verbatim +@verbatim ============================================================================== ##### IRQ handler management ##### - ============================================================================== - [..] + ============================================================================== + [..] This section provides Timer IRQ handler function. - + @endverbatim * @{ */ @@ -2707,12 +2731,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Capture compare 1 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + /* Input capture event */ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) { @@ -2731,13 +2755,13 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Capture compare 2 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) - { + { HAL_TIM_IC_CaptureCallback(htim); } /* Output compare event */ @@ -2747,25 +2771,25 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } + } } /* Capture compare 3 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) - { + { HAL_TIM_IC_CaptureCallback(htim); } /* Output compare event */ else { HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } @@ -2773,13 +2797,13 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Capture compare 4 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET) + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) - { + { HAL_TIM_IC_CaptureCallback(htim); } /* Output compare event */ @@ -2789,13 +2813,13 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } + } } /* TIM Update event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET) - { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) + { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); HAL_TIM_PeriodElapsedCallback(htim); } @@ -2803,8 +2827,8 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* TIM Break input event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET) - { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) + { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); HAL_TIMEx_BreakCallback(htim); } @@ -2812,8 +2836,8 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* TIM Trigger detection event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET) - { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) + { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); HAL_TIM_TriggerCallback(htim); } @@ -2821,8 +2845,8 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* TIM commutation event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET) - { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) + { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); HAL_TIMEx_CommutationCallback(htim); } @@ -2836,22 +2860,22 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions * @brief Peripheral Control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### - ============================================================================== - [..] + ============================================================================== + [..] This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. (+) Configure External Clock source. (+) Configure Complementary channels, break features and dead time. (+) Configure Master and the Slave synchronization. (+) Configure the DMA Burst Mode. - + @endverbatim * @{ */ - + /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. @@ -2868,18 +2892,18 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); - + /* Check input state */ - __HAL_LOCK(htim); - + __HAL_LOCK(htim); + htim->State = HAL_TIM_STATE_BUSY; - + switch (Channel) { case TIM_CHANNEL_1: @@ -2889,7 +2913,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT TIM_OC1_SetConfig(htim->Instance, sConfig); } break; - + case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -2897,7 +2921,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT TIM_OC2_SetConfig(htim->Instance, sConfig); } break; - + case TIM_CHANNEL_3: { assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); @@ -2905,7 +2929,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT TIM_OC3_SetConfig(htim->Instance, sConfig); } break; - + case TIM_CHANNEL_4: { assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); @@ -2913,14 +2937,14 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT TIM_OC4_SetConfig(htim->Instance, sConfig); } break; - + default: - break; + break; } htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - + + __HAL_UNLOCK(htim); + return HAL_OK; } @@ -2945,11 +2969,11 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - + __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; - + if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ @@ -2957,7 +2981,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; @@ -2968,12 +2992,12 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; @@ -2984,12 +3008,12 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, + + TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; @@ -3000,24 +3024,24 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, + + TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); } - + htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - - return HAL_OK; + + return HAL_OK; } /** @@ -3036,18 +3060,18 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) { __HAL_LOCK(htim); - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState)); - + htim->State = HAL_TIM_STATE_BUSY; - + switch (Channel) { case TIM_CHANNEL_1: @@ -3055,69 +3079,69 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); - + /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - + /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; htim->Instance->CCMR1 |= sConfig->OCFastMode; } break; - + case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); - + /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - + /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; } break; - + case TIM_CHANNEL_3: { assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); - + /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - + /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; + htim->Instance->CCMR2 |= sConfig->OCFastMode; } break; - + case TIM_CHANNEL_4: { assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); - + /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - + /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; } break; - + default: - break; + break; } - + htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - + return HAL_OK; } @@ -3139,61 +3163,61 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) { TIM_OC_InitTypeDef temp1; - + /* Check the parameters */ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - if(OutputChannel != InputChannel) + if(OutputChannel != InputChannel) { __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; - /* Extract the Ouput compare configuration from sConfig structure */ + /* Extract the Ouput compare configuration from sConfig structure */ temp1.OCMode = sConfig->OCMode; temp1.Pulse = sConfig->Pulse; temp1.OCPolarity = sConfig->OCPolarity; temp1.OCNPolarity = sConfig->OCNPolarity; temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - + temp1.OCNIdleState = sConfig->OCNIdleState; + switch (OutputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); + + TIM_OC1_SetConfig(htim->Instance, &temp1); } break; case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - + TIM_OC2_SetConfig(htim->Instance, &temp1); } break; default: - break; - } + break; + } switch (InputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ + + /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; } @@ -3201,63 +3225,63 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - + /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ + + /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; } break; - + default: - break; + break; } - + htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - + return HAL_OK; -} +} else { return HAL_ERROR; } -} +} /** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim : TIM handle * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR * @param BurstRequestSrc : TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -3269,7 +3293,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer : The Buffer address. * @param BurstLength : DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, @@ -3280,16 +3304,16 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if((BurstBuffer == 0 ) && (BurstLength > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { @@ -3299,100 +3323,100 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t switch(BurstRequestSrc) { case TIM_DMA_UPDATE: - { + { /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC1: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC2: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC3: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC4: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_COM: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; - + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_TRIGGER: - { + { /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; default: - break; + break; } /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - + htim->Instance->DCR = BurstBaseAddress | BurstLength; + /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -3407,54 +3431,54 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B { /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - + /* Abort the DMA transfer (at least disable the DMA channel) */ switch(BurstRequestSrc) { case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); } break; case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); } break; case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); } break; case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); } break; case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); } break; case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); } break; case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); } break; default: - break; + break; } - + /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** @@ -3462,25 +3486,25 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @param htim : TIM handle * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_DCR * @param BurstRequestSrc : TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -3492,7 +3516,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer : The Buffer address. * @param BurstLength : DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, @@ -3503,120 +3527,120 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if((BurstBuffer == 0 ) && (BurstLength > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } + } switch(BurstRequestSrc) { case TIM_DMA_UPDATE: - { + { /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC1: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC2: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC3: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC4: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_COM: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; - + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_TRIGGER: - { + { /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; default: - break; + break; } /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - + htim->Instance->DCR = BurstBaseAddress | BurstLength; + /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - + htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -3631,54 +3655,54 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu { /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - + /* Abort the DMA transfer (at least disable the DMA channel) */ switch(BurstRequestSrc) { case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); } break; case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); } break; case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); } break; case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); } break; case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); } break; case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); } break; case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); } break; default: - break; + break; } /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** @@ -3686,104 +3710,104 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu * @param htim : TIM handle * @param EventSource : specifies the event source. * This parameter can be one of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1, TIM15, TIM16 and TIM17. + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - + /* Process Locked */ __HAL_LOCK(htim); - + /* Change the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - + /* Set the event sources */ htim->Instance->EGR = EventSource; - + /* Change the TIM state */ htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @brief Configures the OCRef clear feature * @param htim : TIM handle * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. + * contains the OCREF clear feature and parameters for the TIM peripheral. * @param Channel : specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) { uint32_t tmpsmcr = 0; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - + /* Process Locked */ __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; - + switch (sClearInputConfig->ClearInputSource) { case TIM_CLEARINPUTSOURCE_NONE: { /* Clear the OCREF clear selection bit */ tmpsmcr &= ~TIM_SMCR_OCCS; - + /* Clear the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - + /* Set TIMx_SMCR */ htim->Instance->SMCR = tmpsmcr; } break; - + case TIM_CLEARINPUTSOURCE_ETR: { TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); - + /* Set the OCREF clear selection bit */ htim->Instance->SMCR |= TIM_SMCR_OCCS; } break; - default: - break; + default: + break; } - + switch (Channel) - { + { case TIM_CHANNEL_1: { if(sClearInputConfig->ClearInputState != RESET) @@ -3794,13 +3818,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp else { /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; } - } + } break; - case TIM_CHANNEL_2: + case TIM_CHANNEL_2: { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); if(sClearInputConfig->ClearInputState != RESET) { /* Enable the Ocref clear feature for Channel 2 */ @@ -3809,13 +3833,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp else { /* Disable the Ocref clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; } - } + } break; - case TIM_CHANNEL_3: + case TIM_CHANNEL_3: { - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); if(sClearInputConfig->ClearInputState != RESET) { /* Enable the Ocref clear feature for Channel 3 */ @@ -3824,13 +3848,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp else { /* Disable the Ocref clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; } - } + } break; - case TIM_CHANNEL_4: + case TIM_CHANNEL_4: { - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); if(sClearInputConfig->ClearInputState != RESET) { /* Enable the Ocref clear feature for Channel 4 */ @@ -3839,68 +3863,68 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp else { /* Disable the Ocref clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; } - } + } break; - default: + default: break; } - - htim->State = HAL_TIM_STATE_READY; - + + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); - - return HAL_OK; -} + + return HAL_OK; +} /** * @brief Configures the clock source to be used * @param htim : TIM handle * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. + * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) { uint32_t tmpsmcr = 0; - + /* Process Locked */ __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; - + /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); htim->Instance->SMCR = tmpsmcr; - + switch (sClockSourceConfig->ClockSource) { case TIM_CLOCKSOURCE_INTERNAL: { - assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable slave mode to clock the prescaler directly with the internal clock */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; } break; - + case TIM_CLOCKSOURCE_ETRMODE1: { /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - + /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; @@ -3912,29 +3936,29 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo htim->Instance->SMCR = tmpsmcr; } break; - + case TIM_CLOCKSOURCE_ETRMODE2: { /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - + /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; } break; - + case TIM_CLOCKSOURCE_TI1: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); } @@ -3943,9 +3967,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); } @@ -3954,8 +3978,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - TIM_TI1_ConfigInputStage(htim->Instance, + + TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); @@ -3965,7 +3989,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); } break; @@ -3973,7 +3997,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); } break; @@ -3981,7 +4005,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); } break; @@ -3989,18 +4013,18 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); } break; - + default: - break; + break; } htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - + return HAL_OK; } @@ -4019,9 +4043,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { uint32_t tmpcr2 = 0; - + /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); /* Get the TIMx CR2 register value */ @@ -4032,7 +4056,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /* Set the the TI1 selection */ tmpcr2 |= TI1_Selection; - + /* Write to TIMxCR2 */ htim->Instance->CR2 = tmpcr2; @@ -4045,7 +4069,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) @@ -4054,61 +4078,61 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - + __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - + /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - + /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - + htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - + + __HAL_UNLOCK(htim); + return HAL_OK; } - + /** * @brief Configures the TIM in Slave mode in interrupt mode * @param htim: TIM handle. * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - + __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; - + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - + /* Enable Trigger Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - + /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - + htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - + + __HAL_UNLOCK(htim); + return HAL_OK; -} +} /** * @brief Read the captured value from Capture Compare unit @@ -4124,74 +4148,74 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0; - + __HAL_LOCK(htim); - + switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - + /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; - + break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - + /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; - + break; } - + case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - + /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; - + break; } - + case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - + /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; - + break; } - + default: - break; + break; } - - __HAL_UNLOCK(htim); + + __HAL_UNLOCK(htim); return tmpreg; } /** * @} */ - + /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * -@verbatim +@verbatim ============================================================================== ##### TIM Callbacks functions ##### - ============================================================================== - [..] + ============================================================================== + [..] This section provides TIM callback functions: (+) Timer Period elapsed callback (+) Timer Output Compare callback @@ -4213,7 +4237,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /* NOTE : This function Should not be modified, when the callback is needed, the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ - + } /** * @brief Output Compare callback in non blocking mode @@ -4281,10 +4305,10 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions * @brief Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State functions ##### - ============================================================================== + ============================================================================== [..] This subsection permit to get in run-time the status of the peripheral and the data flow. @@ -4359,37 +4383,37 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @} - */ + */ /** @addtogroup TIM_Private_Functions TIM_Private_Functions * @{ - */ - + */ + /** * @brief TIM DMA error callback * @param hdma : pointer to DMA handle. * @retval None */ -void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma) +void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + htim->State= HAL_TIM_STATE_READY; - + HAL_TIM_ErrorCallback(htim); } /** - * @brief TIM DMA Delay Pulse complete callback. + * @brief TIM DMA Delay Pulse complete callback. * @param hdma : pointer to DMA handle. * @retval None */ -void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - + + htim->State= HAL_TIM_STATE_READY; + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -4412,16 +4436,16 @@ void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** - * @brief TIM DMA Capture complete callback. + * @brief TIM DMA Capture complete callback. * @param hdma : pointer to DMA handle. * @retval None */ -void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + htim->State= HAL_TIM_STATE_READY; - + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -4438,37 +4462,37 @@ void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } - - HAL_TIM_IC_CaptureCallback(htim); - + + HAL_TIM_IC_CaptureCallback(htim); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } - + /** - * @brief TIM DMA Period Elapse complete callback. + * @brief TIM DMA Period Elapse complete callback. * @param hdma : pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + htim->State= HAL_TIM_STATE_READY; - + HAL_TIM_PeriodElapsedCallback(htim); } /** - * @brief TIM DMA Trigger callback. + * @brief TIM DMA Trigger callback. * @param hdma : pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - + TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + htim->State= HAL_TIM_STATE_READY; + HAL_TIM_TriggerCallback(htim); } @@ -4482,7 +4506,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1 = 0; tmpcr1 = TIMx->CR1; - + /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) { @@ -4490,7 +4514,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); tmpcr1 |= Structure->CounterMode; } - + if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ @@ -4502,11 +4526,11 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; - + /* Set the Prescaler value */ TIMx->PSC = (uint32_t)Structure->Prescaler; - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; @@ -4527,16 +4551,16 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx = 0; uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpcr2 = 0; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; @@ -4545,7 +4569,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; - + /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; /* Set the Output Compare Polarity */ @@ -4555,7 +4579,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ @@ -4563,7 +4587,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; } - + if(IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ @@ -4580,16 +4604,16 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - + /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; - + /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; - + /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} + TIMx->CCER = tmpccer; +} /** * @brief Time Ouput Compare 2 configuration @@ -4601,33 +4625,33 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx = 0; uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpcr2 = 0; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; tmpccmrx &= ~TIM_CCMR1_CC2S; - + /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8); - + /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4); if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - { + { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); @@ -4638,7 +4662,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - + } if(IS_TIM_BREAK_INSTANCE(TIMx)) @@ -4658,15 +4682,15 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - + /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; - + /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; - + /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; + TIMx->CCER = tmpccer; } /** @@ -4679,32 +4703,32 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx = 0; uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpcr2 = 0; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; + tmpccmrx &= ~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; - + /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8); if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - { + { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); @@ -4716,7 +4740,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } - + if(IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ @@ -4734,15 +4758,15 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - + /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; - + /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; - + /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; + TIMx->CCER = tmpccer; } /** @@ -4755,26 +4779,26 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx = 0; uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpcr2 = 0; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; tmpccmrx &= ~TIM_CCMR2_CC4S; - + /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8); - + /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ @@ -4792,15 +4816,15 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; - + /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; - + /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; - + /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; + TIMx->CCER = tmpccer; } void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -4825,7 +4849,7 @@ void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - + /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { @@ -4837,92 +4861,91 @@ void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); } break; - + case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - + tmpccmr1 = htim->Instance->CCMR1; + /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - + /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - + htim->Instance->CCER = tmpccer; + } break; - + case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); } break; - + case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - + /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); } break; - + case TIM_TS_ITR0: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + case TIM_TS_ITR1: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + case TIM_TS_ITR2: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + case TIM_TS_ITR3: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); } break; - + default: break; } @@ -4933,14 +4956,14 @@ void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI : TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI : TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC : TIM Input 1 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -4964,12 +4987,12 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ { tmpccmr1 &= ~TIM_CCMR1_CC1S; tmpccmr1 |= TIM_ICSelection; - } + } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; } - + /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); @@ -4988,9 +5011,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -4999,20 +5022,20 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, { uint32_t tmpccmr1 = 0; uint32_t tmpccer = 0; - + /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - + tmpccmr1 = TIMx->CCMR1; + /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= (TIM_ICFilter << 4); - + /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= TIM_ICPolarity; - + /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; @@ -5023,14 +5046,14 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI : TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI : TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC : TIM Input 2 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5071,9 +5094,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5082,12 +5105,12 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, { uint32_t tmpccmr1 = 0; uint32_t tmpccer = 0; - + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; - + /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= (TIM_ICFilter << 12); @@ -5106,14 +5129,14 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI : TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI : TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC : TIM Input 3 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None @@ -5154,14 +5177,14 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI : TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI : TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC : TIM Input 4 is selected to be connected to TRC. + * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 @@ -5215,7 +5238,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) { uint32_t tmpsmcr = 0; - + /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the TS Bits */ @@ -5257,19 +5280,19 @@ static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; -} +} /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral * @param Channel : specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_Channel_1 : TIM Channel 1 - * @arg TIM_Channel_2 : TIM Channel 2 - * @arg TIM_Channel_3 : TIM Channel 3 - * @arg TIM_Channel_4 : TIM Channel 4 + * @arg TIM_CHANNEL_1 : TIM Channel 1 + * @arg TIM_CHANNEL_2 : TIM Channel 2 + * @arg TIM_CHANNEL_3 : TIM Channel 3 + * @arg TIM_CHANNEL_4 : TIM Channel 4 * @param ChannelState : specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) @@ -5277,7 +5300,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat uint32_t tmp = 0; /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << Channel; @@ -5285,7 +5308,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; - /* Set or reset the CCxE Bit */ + /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << Channel); } @@ -5297,9 +5320,9 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} - */ + */ /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h index 405d26d60a..18f9309c8a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_tim.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0xx_HAL_TIM_H @@ -52,15 +52,14 @@ /** @addtogroup TIM * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup TIM_Exported_Types TIM Exported Types * @{ */ - -/** - * @brief TIM Time base Configuration Structure definition +/** + * @brief TIM Time base Configuration Structure definition */ typedef struct { @@ -72,7 +71,7 @@ typedef struct uint32_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ @@ -83,20 +82,20 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. @note This parameter is valid only for TIM1 and TIM8. */ } TIM_Base_InitTypeDef; -/** - * @brief TIM Output Compare Configuration Structure definition +/** + * @brief TIM Output Compare Configuration Structure definition */ typedef struct -{ +{ uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ @@ -104,7 +103,7 @@ typedef struct uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for TIM1 and TIM8. */ - + uint32_t OCFastMode; /*!< Specifies the Fast mode state. This parameter can be a value of @ref TIM_Output_Fast_State @note This parameter is valid only in PWM1 and PWM2 mode. */ @@ -117,18 +116,18 @@ typedef struct uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OC_InitTypeDef; +} TIM_OC_InitTypeDef; -/** - * @brief TIM One Pulse Mode Configuration Structure definition +/** + * @brief TIM One Pulse Mode Configuration Structure definition */ typedef struct -{ +{ uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ @@ -152,15 +151,15 @@ typedef struct This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; -/** - * @brief TIM Input Capture Configuration Structure definition +/** + * @brief TIM Input Capture Configuration Structure definition */ typedef struct -{ +{ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -174,14 +173,14 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_IC_InitTypeDef; -/** - * @brief TIM Encoder Configuration Structure definition +/** + * @brief TIM Encoder Configuration Structure definition */ typedef struct { uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Mode */ - + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -193,7 +192,7 @@ typedef struct uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ @@ -204,48 +203,48 @@ typedef struct This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; -/** - * @brief Clock Configuration Handle Structure definition +/** + * @brief TIM Clock Configuration Handle Structure definition */ typedef struct { uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ + This parameter can be a value of @ref TIM_Clock_Source */ uint32_t ClockPolarity; /*!< TIM clock polarity This parameter can be a value of @ref TIM_Clock_Polarity */ uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a value of @ref TIM_Clock_Filter */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ }TIM_ClockConfigTypeDef; -/** - * @brief Clear Input Configuration Handle Structure definition +/** + * @brief TIM Clear Input Configuration Handle Structure definition */ typedef struct -{ +{ uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ + This parameter can be ENABLE or DISABLE */ uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ + This parameter can be a value of @ref TIM_ClearInput_Source */ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler This parameter can be a value of @ref TIM_ClearInput_Prescaler */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a value of @ref TIM_ClearInput_Filter */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ }TIM_ClearInputConfigTypeDef; -/** - * @brief TIM Slave configuration Structure definition +/** + * @brief TIM Slave configuration Structure definition */ typedef struct { uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ + This parameter can be a value of @ref TIM_Slave_Mode */ uint32_t InputTrigger; /*!< Input Trigger source This parameter can be a value of @ref TIM_Trigger_Selection */ uint32_t TriggerPolarity; /*!< Input Trigger polarity @@ -253,46 +252,46 @@ typedef struct { uint32_t TriggerPrescaler; /*!< Input trigger prescaler This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a value of @ref TIM_Trigger_Filter */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ }TIM_SlaveConfigTypeDef; -/** - * @brief HAL State structures definition +/** + * @brief HAL State structures definition */ typedef enum { HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ }HAL_TIM_StateTypeDef; -/** - * @brief HAL Active channel structures definition +/** + * @brief HAL Active channel structures definition */ typedef enum { HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ }HAL_TIM_ActiveChannel; -/** - * @brief TIM Time Base Handle Structure definition +/** + * @brief TIM Time Base Handle Structure definition */ typedef struct { - TIM_TypeDef *Instance; /*!< Register base address */ + TIM_TypeDef *Instance; /*!< Register base address */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array This array is accessed by a @ref TIM_DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ }TIM_HandleTypeDef; /** @@ -304,7 +303,7 @@ typedef struct * @{ */ -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity * @{ */ #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ @@ -317,8 +316,8 @@ typedef struct /** @defgroup TIM_ETR_Polarity TIM ETR Polarity * @{ */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ /** * @} */ @@ -337,41 +336,28 @@ typedef struct /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ - #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS - -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ - ((MODE) == TIM_COUNTERMODE_DOWN) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) /** * @} */ - + /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ - #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) - -#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV4)) /** * @} */ -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare & PWM modes +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes * @{ */ - #define TIM_OCMODE_TIMING ((uint32_t)0x0000) #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) @@ -380,78 +366,33 @@ typedef struct #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) - -#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ - ((MODE) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ - ((MODE) == TIM_OCMODE_ACTIVE) || \ - ((MODE) == TIM_OCMODE_INACTIVE) || \ - ((MODE) == TIM_OCMODE_TOGGLE) || \ - ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) /** * @} */ -/** @defgroup TIM_Output_Compare_State TIM Output Compare State - * @{ - */ - -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) - -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTSTATE_ENABLE)) -/** - * @} - */ /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) - -#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ - ((STATE) == TIM_OCFAST_ENABLE)) /** * @} */ -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State - * @{ - */ -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) - -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) -/** - * @} - */ - /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ - #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) - -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCPOLARITY_LOW)) /** * @} */ /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ - */ - + */ #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) - -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCNPOLARITY_LOW)) /** * @} */ @@ -459,11 +400,8 @@ typedef struct /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State * @{ */ - #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ - ((STATE) == TIM_OCIDLESTATE_RESET)) /** * @} */ @@ -471,11 +409,8 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State * @{ */ - #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ - ((STATE) == TIM_OCNIDLESTATE_RESET)) /** * @} */ @@ -488,22 +423,6 @@ typedef struct #define TIM_CHANNEL_3 ((uint32_t)0x0008) #define TIM_CHANNEL_4 ((uint32_t)0x000C) #define TIM_CHANNEL_ALL ((uint32_t)0x0018) - -#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4) || \ - ((CHANNEL) == TIM_CHANNEL_ALL)) - -#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3)) /** * @} */ @@ -511,14 +430,9 @@ typedef struct /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity * @{ */ - #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE - -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ - ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ - ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) /** * @} */ @@ -526,16 +440,11 @@ typedef struct /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ - #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ - -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_TRC)) /** * @} */ @@ -543,16 +452,10 @@ typedef struct /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ - #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ - -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) /** * @} */ @@ -560,31 +463,25 @@ typedef struct /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode * @{ */ - #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) - -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ - ((MODE) == TIM_OPMODE_REPETITIVE)) /** * @} */ + /** @defgroup TIM_Encoder_Mode TIM Encoder Mode * @{ - */ + */ #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) - -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ - ((MODE) == TIM_ENCODERMODE_TI2) || \ - ((MODE) == TIM_ENCODERMODE_TI12)) /** * @} */ -/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + +/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition * @{ - */ + */ #define TIM_IT_UPDATE (TIM_DIER_UIE) #define TIM_IT_CC1 (TIM_DIER_CC1IE) #define TIM_IT_CC2 (TIM_DIER_CC2IE) @@ -597,7 +494,7 @@ typedef struct * @} */ -/** @defgroup TIM_COMMUTATION TIM Commutation +/** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ */ #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) @@ -606,10 +503,10 @@ typedef struct /** * @} */ + /** @defgroup TIM_DMA_sources TIM DMA Sources * @{ */ - #define TIM_DMA_UPDATE (TIM_DIER_UDE) #define TIM_DMA_CC1 (TIM_DIER_CC1DE) #define TIM_DMA_CC2 (TIM_DIER_CC2DE) @@ -617,8 +514,6 @@ typedef struct #define TIM_DMA_CC4 (TIM_DIER_CC4DE) #define TIM_DMA_COM (TIM_DIER_COMDE) #define TIM_DMA_TRIGGER (TIM_DIER_TDE) - -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) /** * @} */ @@ -626,16 +521,14 @@ typedef struct /** @defgroup TIM_Event_Source TIM Event Source * @{ */ -#define TIM_EventSource_Update TIM_EGR_UG -#define TIM_EventSource_CC1 TIM_EGR_CC1G -#define TIM_EventSource_CC2 TIM_EGR_CC2G -#define TIM_EventSource_CC3 TIM_EGR_CC3G -#define TIM_EventSource_CC4 TIM_EGR_CC4G -#define TIM_EventSource_COM TIM_EGR_COMG -#define TIM_EventSource_Trigger TIM_EGR_TG -#define TIM_EventSource_Break TIM_EGR_BG - -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /** * @} */ @@ -643,7 +536,6 @@ typedef struct /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ - #define TIM_FLAG_UPDATE (TIM_SR_UIF) #define TIM_FLAG_CC1 (TIM_SR_CC1IF) #define TIM_FLAG_CC2 (TIM_SR_CC2IF) @@ -656,19 +548,6 @@ typedef struct #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) - -#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_TRIGGER) || \ - ((FLAG) == TIM_FLAG_BREAK) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) /** * @} */ @@ -676,8 +555,8 @@ typedef struct /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) +#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) +#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) @@ -686,17 +565,6 @@ typedef struct #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) - -#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) /** * @} */ @@ -704,52 +572,31 @@ typedef struct /** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ - -#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ /** * @} */ + /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler * @{ - */ + */ #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ - -#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) /** * @} */ -/** @defgroup TIM_Clock_Filter TIM Clock Filter - * @{ - */ - -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ /** @defgroup TIM_ClearInput_Source TIM ClearInput Source * @{ */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) +#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) - -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) /** * @} */ @@ -757,15 +604,11 @@ typedef struct /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity * @{ */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ - - -#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} - */ + */ /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler * @{ @@ -774,81 +617,53 @@ typedef struct #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ - -#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) /** * @} */ -/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state * @{ */ - -#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode - * @{ - */ #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) #define TIM_OSSR_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ - ((STATE) == TIM_OSSR_DISABLE)) /** * @} */ -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state * @{ */ #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) #define TIM_OSSI_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ - ((STATE) == TIM_OSSI_DISABLE)) /** * @} */ -/** @defgroup TIM_Lock_level TIM Lock Configuration + +/** @defgroup TIM_Lock_level TIM Lock level * @{ */ #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) - -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ - ((LEVEL) == TIM_LOCKLEVEL_1) || \ - ((LEVEL) == TIM_LOCKLEVEL_2) || \ - ((LEVEL) == TIM_LOCKLEVEL_3)) /** * @} */ -/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable * @{ */ #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) #define TIM_BREAK_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ - ((STATE) == TIM_BREAK_DISABLE)) /** * @} */ + /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) - -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ - ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) /** * @} */ @@ -857,9 +672,6 @@ typedef struct */ #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) /** * @} */ @@ -867,64 +679,42 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) - -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ - ((SOURCE) == TIM_TRGO_ENABLE) || \ - ((SOURCE) == TIM_TRGO_UPDATE) || \ - ((SOURCE) == TIM_TRGO_OC1) || \ - ((SOURCE) == TIM_TRGO_OC1REF) || \ - ((SOURCE) == TIM_TRGO_OC2REF) || \ - ((SOURCE) == TIM_TRGO_OC3REF) || \ - ((SOURCE) == TIM_TRGO_OC4REF)) - - +#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) /** * @} - */ + */ /** @defgroup TIM_Slave_Mode TIM Slave Mode * @{ */ - #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) - -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ - ((MODE) == TIM_SLAVEMODE_GATED) || \ - ((MODE) == TIM_SLAVEMODE_RESET) || \ - ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ - ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) /** * @} */ -/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode +/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode * @{ */ - #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) - -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) /** * @} */ + /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ - #define TIM_TS_ITR0 ((uint32_t)0x0000) #define TIM_TS_ITR1 ((uint32_t)0x0010) #define TIM_TS_ITR2 ((uint32_t)0x0020) @@ -934,26 +724,6 @@ typedef struct #define TIM_TS_TI2FP2 ((uint32_t)0x0060) #define TIM_TS_ETRF ((uint32_t)0x0070) #define TIM_TS_NONE ((uint32_t)0xFFFF) - -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_NONE)) /** * @} */ @@ -961,17 +731,11 @@ typedef struct /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity * @{ */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ - -#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ /** * @} */ @@ -983,20 +747,6 @@ typedef struct #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ - -#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Filter TIM Trigger Filter - * @{ - */ - -#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} */ @@ -1004,61 +754,35 @@ typedef struct /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ - #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) - -#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ - ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) - /** * @} */ -/** @defgroup TIM_DMA_Base_address TIM DMA Base address +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ -#define TIM_DMABase_CR1 (0x00000000) -#define TIM_DMABase_CR2 (0x00000001) -#define TIM_DMABase_SMCR (0x00000002) -#define TIM_DMABase_DIER (0x00000003) -#define TIM_DMABase_SR (0x00000004) -#define TIM_DMABase_EGR (0x00000005) -#define TIM_DMABase_CCMR1 (0x00000006) -#define TIM_DMABase_CCMR2 (0x00000007) -#define TIM_DMABase_CCER (0x00000008) -#define TIM_DMABase_CNT (0x00000009) -#define TIM_DMABase_PSC (0x0000000A) -#define TIM_DMABase_ARR (0x0000000B) -#define TIM_DMABase_RCR (0x0000000C) -#define TIM_DMABase_CCR1 (0x0000000D) -#define TIM_DMABase_CCR2 (0x0000000E) -#define TIM_DMABase_CCR3 (0x0000000F) -#define TIM_DMABase_CCR4 (0x00000010) -#define TIM_DMABase_BDTR (0x00000011) -#define TIM_DMABase_DCR (0x00000012) -#define TIM_DMABase_OR (0x00000013) - -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) +#define TIM_DMABASE_CR1 (0x00000000) +#define TIM_DMABASE_CR2 (0x00000001) +#define TIM_DMABASE_SMCR (0x00000002) +#define TIM_DMABASE_DIER (0x00000003) +#define TIM_DMABASE_SR (0x00000004) +#define TIM_DMABASE_EGR (0x00000005) +#define TIM_DMABASE_CCMR1 (0x00000006) +#define TIM_DMABASE_CCMR2 (0x00000007) +#define TIM_DMABASE_CCER (0x00000008) +#define TIM_DMABASE_CNT (0x00000009) +#define TIM_DMABASE_PSC (0x0000000A) +#define TIM_DMABASE_ARR (0x0000000B) +#define TIM_DMABASE_RCR (0x0000000C) +#define TIM_DMABASE_CCR1 (0x0000000D) +#define TIM_DMABASE_CCR2 (0x0000000E) +#define TIM_DMABASE_CCR3 (0x0000000F) +#define TIM_DMABASE_CCR4 (0x00000010) +#define TIM_DMABASE_BDTR (0x00000011) +#define TIM_DMABASE_DCR (0x00000012) +#define TIM_DMABASE_OR (0x00000013) /** * @} */ @@ -1066,53 +790,24 @@ typedef struct /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ - -#define TIM_DMABurstLength_1Transfer (0x00000000) -#define TIM_DMABurstLength_2Transfers (0x00000100) -#define TIM_DMABurstLength_3Transfers (0x00000200) -#define TIM_DMABurstLength_4Transfers (0x00000300) -#define TIM_DMABurstLength_5Transfers (0x00000400) -#define TIM_DMABurstLength_6Transfers (0x00000500) -#define TIM_DMABurstLength_7Transfers (0x00000600) -#define TIM_DMABurstLength_8Transfers (0x00000700) -#define TIM_DMABurstLength_9Transfers (0x00000800) -#define TIM_DMABurstLength_10Transfers (0x00000900) -#define TIM_DMABurstLength_11Transfers (0x00000A00) -#define TIM_DMABurstLength_12Transfers (0x00000B00) -#define TIM_DMABurstLength_13Transfers (0x00000C00) -#define TIM_DMABurstLength_14Transfers (0x00000D00) -#define TIM_DMABurstLength_15Transfers (0x00000E00) -#define TIM_DMABurstLength_16Transfers (0x00000F00) -#define TIM_DMABurstLength_17Transfers (0x00001000) -#define TIM_DMABurstLength_18Transfers (0x00001100) - -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) +#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) +#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) +#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) +#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) +#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) +#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) +#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) +#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) +#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) +#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) +#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) +#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) +#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) +#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) +#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) +#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) +#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) /** * @} */ @@ -1131,7 +826,7 @@ typedef struct * @} */ -/** @defgroup Channel_CC_State TIM Capture/Compare Channel State +/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State * @{ */ #define TIM_CCx_ENABLE ((uint32_t)0x0001) @@ -1145,7 +840,325 @@ typedef struct /** * @} */ - + +/* Private Constants -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ + +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) + +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ + +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ + ((MODE) == TIM_COUNTERMODE_DOWN) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ + ((DIV) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ + ((MODE) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ + ((MODE) == TIM_OCMODE_ACTIVE) || \ + ((MODE) == TIM_OCMODE_INACTIVE) || \ + ((MODE) == TIM_OCMODE_TOGGLE) || \ + ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ + ((STATE) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ + ((POLARITY) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ + ((STATE) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ + ((STATE) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3)) + +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ + ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ + ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ + ((SELECTION) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ + ((MODE) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ + ((MODE) == TIM_ENCODERMODE_TI2) || \ + ((MODE) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) + +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) + +#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_TRIGGER) || \ + ((FLAG) == TIM_FLAG_BREAK) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + +#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ + ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ + ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ + ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) + +#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) + +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ + ((STATE) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ + ((STATE) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ + ((LEVEL) == TIM_LOCKLEVEL_1) || \ + ((LEVEL) == TIM_LOCKLEVEL_2) || \ + ((LEVEL) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ + ((STATE) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ + ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ + ((SOURCE) == TIM_TRGO_ENABLE) || \ + ((SOURCE) == TIM_TRGO_UPDATE) || \ + ((SOURCE) == TIM_TRGO_OC1) || \ + ((SOURCE) == TIM_TRGO_OC1REF) || \ + ((SOURCE) == TIM_TRGO_OC2REF) || \ + ((SOURCE) == TIM_TRGO_OC3REF) || \ + ((SOURCE) == TIM_TRGO_OC4REF)) + +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ + ((MODE) == TIM_SLAVEMODE_GATED) || \ + ((MODE) == TIM_SLAVEMODE_RESET) || \ + ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ + ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) + +#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ + ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ + ((BASE) == TIM_DMABASE_CR2) || \ + ((BASE) == TIM_DMABASE_SMCR) || \ + ((BASE) == TIM_DMABASE_DIER) || \ + ((BASE) == TIM_DMABASE_SR) || \ + ((BASE) == TIM_DMABASE_EGR) || \ + ((BASE) == TIM_DMABASE_CCMR1) || \ + ((BASE) == TIM_DMABASE_CCMR2) || \ + ((BASE) == TIM_DMABASE_CCER) || \ + ((BASE) == TIM_DMABASE_CNT) || \ + ((BASE) == TIM_DMABASE_PSC) || \ + ((BASE) == TIM_DMABASE_ARR) || \ + ((BASE) == TIM_DMABASE_RCR) || \ + ((BASE) == TIM_DMABASE_CCR1) || \ + ((BASE) == TIM_DMABASE_CCR2) || \ + ((BASE) == TIM_DMABASE_CCR3) || \ + ((BASE) == TIM_DMABASE_CCR4) || \ + ((BASE) == TIM_DMABASE_BDTR) || \ + ((BASE) == TIM_DMABASE_DCR) || \ + ((BASE) == TIM_DMABASE_OR)) + +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) + +/** @brief Set TIM IC prescaler + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @param __ICPSC__: specifies the prescaler value. + * @retval None + */ +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) + +/** @brief Reset TIM IC prescaler + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @retval None + */ +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + + +/** @brief Set TIM IC polarity + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @param __POLARITY__: specifies TIM Channel Polarity + * @retval None + */ +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) + +/** @brief Reset TIM IC polarity + * @param __HANDLE__: TIM handle + * @param __CHANNEL__: specifies TIM Channel + * @retval None + */ +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) + +/** + * @} + */ + +/* Private Functions --------------------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); +/** + * @} + */ + /* Exported macros -----------------------------------------------------------*/ /** @defgroup TIM_Exported_Macros TIM Exported Macros * @{ @@ -1178,57 +1191,174 @@ typedef struct */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ { \ - if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ } \ } while(0) /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ + channels have been disabled */ /** * @brief Disable the TIM main Output. * @param __HANDLE__: TIM handle * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ { \ - if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ { \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ } \ } while(0) +/** + * @brief Enables the specified TIM interrupt. + * @param __HANDLE__: specifies the TIM Handle. + * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** + * @brief Disables the specified TIM interrupt. + * @param __HANDLE__: specifies the TIM Handle. + * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** + * @brief Enables the specified DMA request. + * @param __HANDLE__: specifies the TIM Handle. + * @param __DMA__: specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** + * @brief Disables the specified DMA request. + * @param __HANDLE__: specifies the TIM Handle. + * @param __DMA__: specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** + * @brief Checks whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__: specifies the TIM Handle. + * @param __FLAG__: specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the specified TIM interrupt flag. + * @param __HANDLE__: specifies the TIM Handle. + * @param __FLAG__: specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) -#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +/** + * @brief Checks whether the specified TIM interrupt has occurred or not. + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Clear the TIM interrupt pending bits + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @retval None + */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) -#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) -#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter + * @param __HANDLE__: TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR)) -#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) +/** + * @brief Sets the TIM active prescaler register value on update event. + * @param __HANDLE__: TIM handle. + * @param __PRESC__: specifies the active prescaler register new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) -#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) - /** * @brief Sets the TIM Capture Compare Register value on runtime without * calling another time ConfigChannel function. @@ -1242,7 +1372,7 @@ typedef struct * @param __COMPARE__: specifies the Capture Compare register new value. * @retval None */ -#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) /** @@ -1256,7 +1386,7 @@ typedef struct * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @retval None */ -#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) /** @@ -1265,16 +1395,16 @@ typedef struct * @param __COUNTER__: specifies the Counter register new value. * @retval None */ -#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Gets the TIM Counter Register value on runtime. * @param __HANDLE__: TIM handle. * @retval None */ -#define __HAL_TIM_GetCounter(__HANDLE__) \ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ ((__HANDLE__)->Instance->CNT) - + /** * @brief Sets the TIM Autoreload Register value on runtime without calling * another time any Init function. @@ -1282,7 +1412,7 @@ typedef struct * @param __AUTORELOAD__: specifies the Counter register new value. * @retval None */ -#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ do{ \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ @@ -1293,35 +1423,35 @@ typedef struct * @param __HANDLE__: TIM handle. * @retval None */ -#define __HAL_TIM_GetAutoreload(__HANDLE__) \ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ ((__HANDLE__)->Instance->ARR) - + /** * @brief Sets the TIM Clock Division value on runtime without calling - * another time any Init function. + * another time any Init function. * @param __HANDLE__: TIM handle. * @param __CKD__: specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1 * @arg TIM_CLOCKDIVISION_DIV2 - * @arg TIM_CLOCKDIVISION_DIV4 + * @arg TIM_CLOCKDIVISION_DIV4 * @retval None */ -#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ do{ \ (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \ } while(0) - + /** * @brief Gets the TIM Clock Division value on runtime - * @param __HANDLE__: TIM handle. + * @param __HANDLE__: TIM handle. * @retval None */ -#define __HAL_TIM_GetClockDivision(__HANDLE__) \ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - + /** * @brief Sets the TIM Input Capture prescaler on runtime without calling * another time HAL_TIM_IC_ConfigChannel() function. @@ -1340,11 +1470,11 @@ typedef struct * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ -#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ do{ \ - __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ - __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) /** * @brief Gets the TIM Input Capture prescaler on runtime @@ -1357,12 +1487,12 @@ typedef struct * @arg TIM_CHANNEL_4: get input capture 4 prescaler value * @retval None */ -#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) - + /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register * @param __HANDLE__: TIM handle. @@ -1388,6 +1518,28 @@ typedef struct #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) +/** + * @brief Sets the TIM Capture x input polarity on runtime. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__: Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + /** * @} */ @@ -1396,12 +1548,11 @@ typedef struct #include "stm32f0xx_hal_tim_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions TIM Exported Functions +/** @addtogroup TIM_Exported_Functions * @{ */ -/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions +/** @addtogroup TIM_Exported_Functions_Group1 * @{ */ /* Time Base functions ********************************************************/ @@ -1422,8 +1573,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); * @} */ -/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions +/** @addtogroup TIM_Exported_Functions_Group2 * @{ */ /* Timer Output Compare functions **********************************************/ @@ -1440,12 +1590,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + /** * @} */ -/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions +/** @addtogroup TIM_Exported_Functions_Group3 * @{ */ /* Timer PWM functions *********************************************************/ @@ -1466,8 +1616,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel * @} */ -/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions +/** @addtogroup TIM_Exported_Functions_Group4 * @{ */ /* Timer Input Capture functions ***********************************************/ @@ -1488,8 +1637,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions +/** @addtogroup TIM_Exported_Functions_Group5 * @{ */ /* Timer One Pulse functions ***************************************************/ @@ -1507,8 +1655,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @} */ -/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions +/** @addtogroup TIM_Exported_Functions_Group6 * @{ */ /* Timer Encoder functions *****************************************************/ @@ -1525,12 +1672,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); + /** * @} */ -/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management +/** @addtogroup TIM_Exported_Functions_Group7 * @{ */ /* Interrupt Handler functions **********************************************/ @@ -1539,8 +1686,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @} */ -/** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions +/** @addtogroup TIM_Exported_Functions_Group8 * @{ */ /* Control functions *********************************************************/ @@ -1561,12 +1707,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); + /** * @} */ /** @addtogroup TIM_Exported_Functions_Group9 - * @brief TIM Callbacks functions * @{ */ /* Callback in non blocking modes (Interrupt and DMA) *************************/ @@ -1581,7 +1727,6 @@ void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); */ /** @addtogroup TIM_Exported_Functions_Group10 - * @brief Peripheral State functions * @{ */ /* Peripheral State functions **************************************************/ @@ -1591,37 +1736,6 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ - -/* Private Macros -----------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) -/** - * @} - */ - -/* Private Functions --------------------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma); -void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); /** * @} @@ -1629,7 +1743,11 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @} - */ + */ + +/** + * @} + */ /** * @} @@ -1642,4 +1760,3 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat #endif /* __STM32F0xx_HAL_TIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c index e8d8543f6d..3e1d82487d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c @@ -2,22 +2,22 @@ ****************************************************************************** * @file stm32f0xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: * + Time Hall Sensor Interface Initialization * + Time Hall Sensor Interface Start - * + Time Complementary signal bread and dead time configuration + * + Time Complementary signal bread and dead time configuration * + Time Master and Slave synchronization configuration * + Timer remapping capabilities configuration @verbatim ============================================================================== ##### TIMER Extended features ##### ============================================================================== - [..] - The Timer Extended features include: + [..] + The Timer Extended features include: (#) Complementary outputs with programmable dead-time for : (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) @@ -26,7 +26,7 @@ interconnect several timers together. (#) Break input to put the timer output signals in reset state or in a known state. (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes + positioning purposes ##### How to use this driver ##### ============================================================================== @@ -37,19 +37,19 @@ (++) Complementary PWM generation : HAL_TIM_PWM_MspInit() (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit() (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit() - + (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. - + (#) Configure the TIM in the desired functioning mode using one of the initialization function of this driver: (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the @@ -58,18 +58,18 @@ with the Hall sensor Interface and another Timer should be used to use the commutation event). - (#) Activate the TIM peripheral using one of the start functions: + (#) Activate the TIM peripheral using one of the start functions: (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). - + @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -94,7 +94,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ +*/ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx_hal.h" @@ -103,7 +103,7 @@ * @{ */ -/** @defgroup TIMEx TIMEx Extended HAL module driver +/** @defgroup TIMEx TIMEx * @brief TIM Extended HAL module driver * @{ */ @@ -119,7 +119,7 @@ /** @defgroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); +static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); /** * @} */ @@ -133,13 +133,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions * @brief Timer Hall Sensor functions * -@verbatim +@verbatim ============================================================================== ##### Timer Hall Sensor functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. + (+) Initialize and configure TIM HAL Sensor. (+) De-initialize TIM HAL Sensor. (+) Start the Hall Sensor Interface. (+) Stop the Hall Sensor Interface. @@ -147,7 +147,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha (+) Stop the Hall Sensor Interface and disable interrupts. (+) Start the Hall Sensor Interface and enable DMA transfers. (+) Stop the Hall Sensor Interface and disable DMA transfers. - + @endverbatim * @{ */ @@ -160,13 +160,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) { TIM_OC_InitTypeDef OC_Config; - + /* Check the TIM handle allocation */ if(htim == NULL) { return HAL_ERROR; } - + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); @@ -174,34 +174,40 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); + } + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); - + /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - + /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - + /* Enable the Hall sensor interface (XOR function of the three inputs) */ htim->Instance->CR2 |= TIM_CR2_TI1S; - + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ OC_Config.OCFastMode = TIM_OCFAST_DISABLE; OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; @@ -209,15 +215,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - + OC_Config.Pulse = sConfig->Commutation_Delay; + TIM_OC2_SetConfig(htim->Instance, &OC_Config); - + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to 101 */ htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + /* Initialize the TIM state*/ htim->State= HAL_TIM_STATE_READY; @@ -225,7 +231,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen } /** - * @brief DeInitializes the TIM Hall Sensor interface + * @brief DeInitializes the TIM Hall Sensor interface * @param htim : TIM Hall Sensor handle * @retval HAL status */ @@ -235,16 +241,16 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; - + /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIMEx_HallSensor_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + /* Release Lock */ __HAL_UNLOCK(htim); @@ -284,14 +290,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -305,14 +311,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - + /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -323,20 +329,20 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ +{ /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - + /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -350,17 +356,17 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + /* Disable the capture compare Interrupts event */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -376,40 +382,40 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 { /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } - /* Enable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + /* Set the DMA Input Capture 1 Callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel for Capture 1*/ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -423,18 +429,18 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 - (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 event */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -442,15 +448,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @} */ - + /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * -@verbatim +@verbatim ============================================================================== ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] + ============================================================================== + [..] This section provides functions allowing to: (+) Start the Complementary Output Compare/PWM. (+) Stop the Complementary Output Compare/PWM. @@ -458,15 +464,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) (+) Stop the Complementary Output Compare/PWM and disable interrupts. (+) Start the Complementary Output Compare/PWM and enable DMA transfers. (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - + @endverbatim * @{ */ - + /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM Output Compare handle + * @param htim : TIM Output Compare handle * @param Channel : TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -478,20 +484,20 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - + /* Enable the Main Ouput */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Stops the TIM Output Compare signal generation on the complementary @@ -506,22 +512,22 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ +{ /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - + /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Starts the TIM Output Compare signal generation in interrupt mode @@ -538,57 +544,57 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); } break; - + default: break; - } - + } + /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - + /* Enable the Main Ouput */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Stops the TIM Output Compare signal generation in interrupt mode @@ -607,45 +613,45 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe uint32_t tmpccer = 0; /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); } break; - + default: - break; + break; } - + /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - + /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) @@ -658,10 +664,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Starts the TIM Output Compare signal generation in DMA mode @@ -680,102 +686,102 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } + } switch (Channel) { case TIM_CHANNEL_1: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; } /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - + /* Enable the Main Ouput */ __HAL_TIM_MOE_ENABLE(htim); - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } @@ -795,54 +801,54 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; - } - + } + /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - + /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -850,15 +856,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @} */ - + /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions * @brief Timer Complementary PWM functions * -@verbatim +@verbatim ============================================================================== ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] + ============================================================================== + [..] This section provides functions allowing to: (+) Start the Complementary PWM. (+) Stop the Complementary PWM. @@ -876,7 +882,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. - + @endverbatim * @{ */ @@ -895,20 +901,20 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - + /* Enable the Main Ouput */ __HAL_TIM_MOE_ENABLE(htim); - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Stops the PWM signal generation on the complementary output. @@ -922,22 +928,22 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ +{ /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Starts the PWM signal generation in interrupt mode on the @@ -954,57 +960,57 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); } break; - + default: break; - } - + } + /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - + /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - + /* Enable the Main Ouput */ __HAL_TIM_MOE_ENABLE(htim); - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Stops the PWM signal generation in interrupt mode on the @@ -1023,61 +1029,61 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan uint32_t tmpccer = 0; /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); } break; - + default: - break; + break; } - + /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - + /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } - + /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Starts the TIM PWM signal generation in DMA mode on the @@ -1096,102 +1102,102 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } + } switch (Channel) { case TIM_CHANNEL_1: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA channel */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; } /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - + /* Enable the Main Ouput */ __HAL_TIM_MOE_ENABLE(htim); - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } @@ -1211,54 +1217,54 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; - } - + } + /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - + /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1266,21 +1272,21 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @} */ - + /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * -@verbatim +@verbatim ============================================================================== ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] + ============================================================================== + [..] This section provides functions allowing to: (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. - + @endverbatim * @{ */ @@ -1298,14 +1304,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + /* Enable the Main Ouput */ __HAL_TIM_MOE_ENABLE(htim); - + /* Return function status */ return HAL_OK; } @@ -1324,17 +1330,17 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - + /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } @@ -1352,24 +1358,24 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - + /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - + /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + /* Enable the Main Ouput */ __HAL_TIM_MOE_ENABLE(htim); - + /* Return function status */ return HAL_OK; - } - + } + /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. @@ -1383,46 +1389,44 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - + /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - + /* Disable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - + /* Disable the Main Ouput */ __HAL_TIM_MOE_DISABLE(htim); - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } - - /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions * @brief Peripheral Control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### - ============================================================================== - [..] + ============================================================================== + [..] This section provides functions allowing to: (+) Configure the commutation event in case of use of the Hall sensor interface. (+) Configure Complementary channels, break features and dead time. (+) Configure Master synchronization. (+) Configure timer remapping capabilities. - + @endverbatim * @{ */ @@ -1430,7 +1434,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * @brief Configure the TIM commutation event sequence. * @note: this function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) + * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. @@ -1453,25 +1457,25 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - + __HAL_LOCK(htim); - + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { + { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } - + /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; - + __HAL_UNLOCK(htim); - + return HAL_OK; } @@ -1479,7 +1483,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * @brief Configure the TIM commutation event sequence with interrupt. * @note: this function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) + * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. @@ -1502,28 +1506,28 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - + __HAL_LOCK(htim); - + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { + { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } - + /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; - + /* Enable the Commutation Interrupt Request */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); __HAL_UNLOCK(htim); - + return HAL_OK; } @@ -1531,7 +1535,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * @brief Configure the TIM commutation event sequence with DMA. * @note: this function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) + * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. @@ -1555,43 +1559,43 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - + __HAL_LOCK(htim); - + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { + { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } - + /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; - + /* Enable the Commutation DMA Request */ /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError; - + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + /* Enable the Commutation DMA Request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); - + return HAL_OK; } /** * @brief Configures the TIM in master mode. - * @param htim : TIM handle. + * @param htim : TIM handle. * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave - * mode. + * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) @@ -1600,7 +1604,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - + __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; @@ -1614,11 +1618,11 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, htim->Instance->SMCR &= ~TIM_SMCR_MSM; /* Set or Reset the MSM Bit */ htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; - + htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - + return HAL_OK; } @@ -1627,10 +1631,10 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * and the AOE(automatic output enable). * @param htim : TIM handle * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. + * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Check the parameters */ @@ -1642,27 +1646,27 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - + /* Process Locked */ __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ - htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode | + htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode | sBreakDeadTimeConfig->OffStateIDLEMode | sBreakDeadTimeConfig->LockLevel | sBreakDeadTimeConfig->DeadTime | sBreakDeadTimeConfig->BreakState | sBreakDeadTimeConfig->BreakPolarity | sBreakDeadTimeConfig->AutomaticOutput; - - - htim->State = HAL_TIM_STATE_READY; - + + + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); - + return HAL_OK; } @@ -1674,24 +1678,24 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 - * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO + * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { __HAL_LOCK(htim); - + /* Check parameters */ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); assert_param(IS_TIM_REMAP(Remap)); - + /* Set the Timer remapping configuration */ htim->Instance->OR = Remap; - + htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - + + __HAL_UNLOCK(htim); + return HAL_OK; } @@ -1702,11 +1706,11 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions * @brief Extension Callbacks functions * -@verbatim +@verbatim ============================================================================== ##### Extension Callbacks functions ##### - ============================================================================== - [..] + ============================================================================== + [..] This section provides Extension TIM callback functions: (+) Timer Commutation callback (+) Timer Break callback @@ -1740,17 +1744,17 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief TIM DMA Commutation callback. + * @brief TIM DMA Commutation callback. * @param hdma : pointer to DMA handle. * @retval None */ -void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + htim->State= HAL_TIM_STATE_READY; - - HAL_TIMEx_CommutationCallback(htim); + + HAL_TIMEx_CommutationCallback(htim); } /** @@ -1760,10 +1764,10 @@ void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions * @brief Extension Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### Extension Peripheral State functions ##### - ============================================================================== + ============================================================================== [..] This subsection permit to get in run-time the status of the peripheral and the data flow. @@ -1788,7 +1792,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @} - */ + */ /** @addtogroup TIMEx_Private_Functions * @{ @@ -1799,11 +1803,11 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @param TIMx to select the TIM peripheral * @param Channel : specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 * @param ChannelNState : specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) @@ -1815,21 +1819,21 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; - /* Set or reset the CCxNE Bit */ + /* Set or reset the CCxNE Bit */ TIMx->CCER |= (uint32_t)(ChannelNState << Channel); } /** * @} - */ + */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} - */ + */ /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h index f7f974df5c..628478b87b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0xx_HAL_TIM_EX_H @@ -52,44 +52,45 @@ /** @addtogroup TIMEx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIMEx Extended Exported Types +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIMEx Exported Types * @{ */ -/** - * @brief TIM Hall sensor Configuration Structure definition + +/** + * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { - + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - + uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; -/** - * @brief TIM Master configuration Structure definition +/** + * @brief TIM Master configuration Structure definition */ typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ + This parameter can be a value of @ref TIM_Master_Mode_Selection */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode */ }TIM_MasterConfigTypeDef; -/** - * @brief TIM Break and Dead time configuration Structure definition +/** + * @brief TIM Break and Dead time configuration Structure definition */ typedef struct { @@ -98,7 +99,7 @@ typedef struct uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ + This parameter can be a value of @ref TIM_Lock_level */ uint32_t DeadTime; /*!< TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint32_t BreakState; /*!< TIM Break State @@ -106,18 +107,18 @@ typedef struct uint32_t BreakPolarity; /*!< TIM Break input polarity This parameter can be a value of @ref TIM_Break_Polarity */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; /** * @} - */ + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants * @{ */ - + /** @defgroup TIMEx_Remap TIMEx Remap * @{ */ @@ -135,10 +136,10 @@ typedef struct * @} */ -/** @defgroup TIM_Clock_Filter TIM Clock Filter +/** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter * @{ */ -#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) +#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) /*!< BreakDead Time */ /** * @} */ @@ -154,8 +155,7 @@ typedef struct * @{ */ -/** @addtogroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions - * @brief Timer Hall Sensor functions +/** @addtogroup TIMEx_Exported_Functions_Group1 * @{ */ /* Timer Hall Sensor functions **********************************************/ @@ -178,8 +178,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions +/** @addtogroup TIMEx_Exported_Functions_Group2 * @{ */ /* Timer Complementary Output Compare functions *****************************/ @@ -198,8 +197,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions - * @brief Timer Complementary PWM functions +/** @addtogroup TIMEx_Exported_Functions_Group3 * @{ */ /* Timer Complementary PWM functions ****************************************/ @@ -217,8 +215,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions +/** @addtogroup TIMEx_Exported_Functions_Group4 * @{ */ /* Timer Complementary One Pulse functions **********************************/ @@ -233,8 +230,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group5 Peripheral Control functions - * @brief Peripheral Control functions +/** @addtogroup TIMEx_Exported_Functions_Group5 * @{ */ /* Extended Control functions ************************************************/ @@ -248,20 +244,17 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions - * @brief Extended Callbacks functions +/** @addtogroup TIMEx_Exported_Functions_Group6 * @{ */ /* Extension Callback *********************************************************/ void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); /** * @} */ -/** @addtogroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions - * @brief Extended Peripheral State functions +/** @addtogroup TIMEx_Exported_Functions_Group7 * @{ */ /* Extension Peripheral State functions **************************************/ @@ -272,16 +265,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); /** * @} - */ + */ +/* End of exported functions -------------------------------------------------*/ +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions +* @{ +*/ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); /** - * @} - */ +* @} +*/ +/* End of private functions --------------------------------------------------*/ /** * @} */ - + +/** + * @} + */ + #ifdef __cplusplus } #endif @@ -290,4 +294,3 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); #endif /* __STM32F0xx_HAL_TIM_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c index 589d6de1b5..612fe16205 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f0xx_hal_tsc.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and DeInitialization @@ -47,10 +47,10 @@ ##### How to use this driver ##### ================================================================================ [..] - (#) Enable the TSC interface clock using __TSC_CLK_ENABLE() macro. + (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro. (#) GPIO pins configuration - (++) Enable the clock for the TSC GPIOs using __GPIOx_CLK_ENABLE() macro. + (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro. (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode, and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode using HAL_GPIO_Init() function. @@ -81,7 +81,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -121,7 +121,7 @@ * @{ */ -/** @defgroup TSC TSC HAL module driver +/** @defgroup TSC TSC * @brief TSC HAL module driver * @{ */ @@ -179,7 +179,13 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity)); assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode)); assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt)); - + + if(htsc->State == HAL_TSC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htsc->Lock = HAL_UNLOCKED; + } + /* Initialize the TSC state */ htsc->State = HAL_TSC_STATE_BUSY; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h index da76cf0eb0..5c9005d785 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f0xx_hal_tsc.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief This file contains all the functions prototypes for the TSC firmware * library. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -282,9 +282,9 @@ typedef struct /** @defgroup TSC_Synchronization_pin_polarity TSC Synchronization pin polarity * @{ */ -#define TSC_SYNC_POL_FALL ((uint32_t)0) -#define TSC_SYNC_POL_RISE_HIGH (TSC_CR_SYNCPOL) -#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POL_FALL) || ((VAL) == TSC_SYNC_POL_RISE_HIGH)) +#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0) +#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL) +#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING)) /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c index 4300a4ca3d..839fa0e2a0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c @@ -2,69 +2,68 @@ ****************************************************************************** * @file stm32f0xx_hal_uart.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - @verbatim + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + @verbatim =============================================================================== - ##### How to use this driver ##### -================================================================================ - [..] + ##### How to use this driver ##### + =============================================================================== + [..] The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure. - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit ()API: - (##) Enable the USARTx interface clock. - (##) UART pins configuration: + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: (+++) Enable the clock for the UART GPIOs. (+++) Configure these UART pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() and HAL_UART_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) are managed using the macros + __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() and HAL_UART_Receive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the UART DMA Tx/Rx handle. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the huart Init structure. - + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) - in the huart AdvancedInit structure. + in the huart handle AdvancedInit structure. (#) For the UART asynchronous mode, initialize the UART registers by calling the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the UART Multiprocessor mode, initialize the UART registers - by calling the HAL_MultiProcessor_Init() API. - (#) For the UART RS485 Driver Enabled mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. - [..] - (@) The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive process. + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. - [..] + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] (@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(), - also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by - calling the customed HAL_UART_MspInit() API. + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. Three operation modes are available within this driver : @@ -128,7 +127,7 @@ ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -152,7 +151,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -162,25 +161,27 @@ * @{ */ -/** @defgroup UART UART HAL module driver +/** @defgroup UART UART * @brief HAL UART module driver * @{ */ + #ifdef HAL_UART_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants +/** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define HAL_UART_TXDMA_TIMEOUTVALUE 22000 +#define UART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< UART TX or RX enable acknowledge time-out value */ +#define UART_TXDMA_TIMEOUTVALUE 22000 #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ /** * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions UART Private Functions @@ -190,50 +191,64 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); /** * @} */ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions * @{ */ -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy in asynchronous mode. - (+) For the asynchronous mode only these parameters can be configured: + (+) For the asynchronous mode the parameters below can be configured: (++) Baud Rate - (++) Word Length + (++) Word Length (++) Stop Bit (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible UART frame formats are as listed in the following table: - |-----------|-----------|---------------------------------------| - | M1M0 bits | PCE bit | UART frame | - |-----------------------|---------------------------------------| - | 00 | 0 | | SB | 8-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 00 | 1 | | SB | 7-bit data | PB | STB | | - |-----------|-----------|---------------------------------------| - | 01 | 0 | | SB | 9-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 01 | 1 | | SB | 8-bit data | PB | STB | | - +---------------------------------------------------------------+ - | 10 | 0 | | SB | 7-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 10 | 1 | | SB | 6-bit data | PB | STB | | - +---------------------------------------------------------------+ + According to device capability (support or not of 7-bit word length), + frame length is either defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). + Possible UART frame formats are as listed in the following table: + + (+++) Table 1. UART frame format. + (+++) +-----------------------------------------------------------------------+ + (+++) | M bit | PCE bit | UART frame | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 0 | 0 | | SB | 8-bit data | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 1 | 0 | | SB | 9-bit data | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | | + (+++) +-----------------------------------------------------------------------+ + (+++) | M1 bit | M0 bit | PCE bit | UART frame | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + (+++) +-----------------------------------------------------------------------+ (++) Hardware flow control (++) Receiver/transmitter modes (++) Over Sampling Method @@ -247,8 +262,8 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma); (++) MSB first on communication line (++) auto Baud rate detection [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init() and HAL_MultiProcessor_Init() - API follow respectively the UART asynchronous, UART Half duplex and multiprocessor + The HAL_UART_Init(), HAL_HalfDuplex_Init() and HAL_MultiProcessor_Init() + API follow respectively the UART asynchronous, UART Half duplex and multiprocessor mode configuration procedures (details for the procedures are available in reference manual). @endverbatim @@ -256,9 +271,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma); */ /** - * @brief Initializes the UART mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: uart handle + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart: UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) @@ -268,7 +283,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) { /* Check the parameters */ @@ -279,46 +294,49 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } - + if(huart->State == HAL_UART_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->State = HAL_UART_STATE_BUSY; /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; - } - + } + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - - /* In asynchronous mode, the following bits must be kept cleared: + + /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); - huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); - + huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); + huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->State to Ready */ return (UART_CheckIdleState(huart)); } /** - * @brief Initializes the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: uart handle + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart: UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) @@ -328,65 +346,68 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + /* Check UART instance */ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - + if(huart->State == HAL_UART_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->State = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; - } - + } + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - - /* In half-duplex mode, the following bits must be kept cleared: + + /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN); - + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ huart->Instance->CR3 |= USART_CR3_HDSEL; - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->State to Ready */ return (UART_CheckIdleState(huart)); } /** - * @brief Initializes the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle - * @param Address: UART node address (4-, 6-, 7- or 8-bit long) + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart: UART handle. + * @param Address: UART node address (4-, 6-, 7- or 8-bit long). * @param WakeUpMethod: specifies the UART wakeup method. * This parameter can be one of the following values: * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark * @note If the user resorts to idle line detection wake up, the Address parameter - * is useless and ignored by the initialization function. - * @note If the user resorts to address mark wake up, the address length detection - * is configured by default to 4 bits only. For the UART to be able to + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to * manage 6-, 7- or 8-bit long addresses detection, the API - * HAL_MultiProcessorEx_AddressLength_Set() must be called after - * HAL_MultiProcessor_Init(). + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) @@ -399,54 +420,57 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Check the wake up method parameter */ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - + if(huart->State == HAL_UART_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } - + huart->State = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; - } - + } + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - - /* In multiprocessor mode, the following bits must be kept cleared: + + /* In multiprocessor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); - + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) { /* If address mark wake up method is chosen, set the USART address node */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); } - + /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - + /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - + __HAL_UART_ENABLE(huart); + /* TEACK and/or REACK to check before moving huart->State to Ready */ return (UART_CheckIdleState(huart)); } /** - * @brief DeInitializes the UART peripheral - * @param huart: uart handle + * @brief DeInitialize the UART peripheral. + * @param huart: UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) @@ -456,141 +480,138 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); huart->State = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + huart->Instance->CR1 = 0x0; huart->Instance->CR2 = 0x0; huart->Instance->CR3 = 0x0; - + /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; huart->State = HAL_UART_STATE_RESET; - + /* Process Unlock */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** - * @brief UART MSP Init - * @param huart: uart handle + * @brief Initialize the UART MSP. + * @param huart: UART handle. * @retval None */ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_MspInit can be implemented in the user file - */ + */ } /** - * @brief UART MSP DeInit - * @param huart: uart handle + * @brief DeInitialize the UART MSP. + * @param huart: UART handle. * @retval None */ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit could be implemented in the user file - */ + the HAL_UART_MspDeInit can be implemented in the user file + */ } /** * @} */ -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit and Receive functions +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions * -@verbatim - ============================================================================== +@verbatim + =============================================================================== ##### IO operation functions ##### - ============================================================================== - [..] + =============================================================================== This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. (#) There are two mode of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected - (#) Blocking mode APIs are : - (++) HAL_UART_Transmit() - (++) HAL_UART_Receive() - - (#) Non Blocking mode APIs with Interrupt are : - (++) HAL_UART_Transmit_IT() - (++) HAL_UART_Receive_IT() - (++) HAL_UART_IRQHandler() - (++) UART_Transmit_IT() - (++) UART_Receive_IT() + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() - (#) Non Blocking mode APIs with DMA are : - (++) HAL_UART_Transmit_DMA() - (++) HAL_UART_Receive_DMA() - (++) HAL_UART_DMAPause() - (++) HAL_UART_DMAResume() - (++) HAL_UART_DMAStop() + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() - (#) A set of Transfer Complete Callbacks are provided in non blocking mode: - (++) HAL_UART_TxHalfCpltCallback() - (++) HAL_UART_TxCpltCallback() - (++) HAL_UART_RxHalfCpltCallback() - (++) HAL_UART_RxCpltCallback() - (++) HAL_UART_ErrorCallback() + (#) No-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() - [..] - (@) In the Half duplex communication, it is forbidden to run the transmit + (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + + -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - + @endverbatim * @{ */ /** - * @brief Send an amount of data in blocking mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout : Timeout duration + * @brief Send an amount of data in blocking mode. + * @param huart: UART handle. + * @param pData: Pointer to data buffer. + * @param Size: Amount of data to be sent. + * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint16_t* tmp; if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; /* Check if a non-blocking receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) + if(huart->State == HAL_UART_STATE_BUSY_RX) { huart->State = HAL_UART_STATE_BUSY_TX_RX; } @@ -598,33 +619,33 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u { huart->State = HAL_UART_STATE_BUSY_TX; } - + huart->TxXferSize = Size; huart->TxXferCount = Size; while(huart->TxXferCount > 0) { huart->TxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); pData += 2; } else { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFF); - } + huart->Instance->TDR = (*pData++ & (uint8_t)0xFF); + } } - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) - { + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } /* Check if a non-blocking receive Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { huart->State = HAL_UART_STATE_BUSY_RX; } @@ -632,10 +653,10 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u { huart->State = HAL_UART_STATE_READY; } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else @@ -645,31 +666,31 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u } /** - * @brief Receive an amount of data in blocking mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout : Timeout duration + * @brief Receive an amount of data in blocking mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. + * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ +{ uint16_t* tmp; uint16_t uhMask; if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) - { - if((pData == NULL ) || (Size == 0)) + { + if((pData == NULL ) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->State == HAL_UART_STATE_BUSY_TX) { huart->State = HAL_UART_STATE_BUSY_TX_RX; } @@ -677,22 +698,22 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { huart->State = HAL_UART_STATE_BUSY_RX; } - - huart->RxXferSize = Size; + + huart->RxXferSize = Size; huart->RxXferCount = Size; - + /* Computation of UART mask to apply to RDR register */ - __HAL_UART_MASK_COMPUTATION(huart); + UART_MASK_COMPUTATION(huart); uhMask = huart->Mask; - + /* as long as data have to be received */ while(huart->RxXferCount > 0) { huart->RxXferCount--; - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { return HAL_TIMEOUT; - } + } if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t*) pData ; @@ -701,56 +722,56 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } else { - *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - } + *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + } } - + /* Check if a non-blocking transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { huart->State = HAL_UART_STATE_BUSY_TX; } else { huart->State = HAL_UART_STATE_READY; - } + } /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Send an amount of data in interrupt mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in interrupt mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ +{ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) + if(huart->State == HAL_UART_STATE_BUSY_RX) { huart->State = HAL_UART_STATE_BUSY_TX_RX; } @@ -758,53 +779,53 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData { huart->State = HAL_UART_STATE_BUSY_TX; } - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - + /* Process Unlocked */ - __HAL_UNLOCK(huart); - + __HAL_UNLOCK(huart); + /* Enable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in interrupt mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in interrupt mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ +{ if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pRxBuffPtr = pData; huart->RxXferSize = Size; huart->RxXferCount = Size; - + /* Computation of UART mask to apply to RDR register */ - __HAL_UART_MASK_COMPUTATION(huart); - + UART_MASK_COMPUTATION(huart); + huart->ErrorCode = HAL_UART_ERROR_NONE; /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->State == HAL_UART_STATE_BUSY_TX) { huart->State = HAL_UART_STATE_BUSY_TX_RX; } @@ -812,55 +833,55 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, { huart->State = HAL_UART_STATE_BUSY_RX; } - + /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); - + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Send an amount of data in DMA mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in DMA mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - + if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pTxBuffPtr = pData; huart->TxXferSize = Size; - huart->TxXferCount = Size; - + huart->TxXferCount = Size; + huart->ErrorCode = HAL_UART_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) + if(huart->State == HAL_UART_STATE_BUSY_RX) { huart->State = HAL_UART_STATE_BUSY_TX_RX; } @@ -868,64 +889,67 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat { huart->State = HAL_UART_STATE_BUSY_TX; } - + /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - + /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; /* Enable the UART transmit DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size); - + + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ huart->Instance->CR3 |= USART_CR3_DMAT; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in DMA mode - * @param huart: uart handle - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) + * @brief Receive an amount of data in DMA mode. + * @param huart: UART handle. + * @param pData: pointer to data buffer. + * @param Size: amount of data to be received. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - + if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(huart); - + huart->pRxBuffPtr = pData; huart->RxXferSize = Size; - + huart->ErrorCode = HAL_UART_ERROR_NONE; /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) + if(huart->State == HAL_UART_STATE_BUSY_TX) { huart->State = HAL_UART_STATE_BUSY_TX_RX; } @@ -933,13 +957,13 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData { huart->State = HAL_UART_STATE_BUSY_RX; } - + /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - + /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - + /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; @@ -947,31 +971,31 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ huart->Instance->CR3 |= USART_CR3_DMAR; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Pauses the DMA Transfer. - * @param huart: UART handle - * @retval None + * @brief Pause the DMA Transfer. + * @param huart: UART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + if(huart->State == HAL_UART_STATE_BUSY_TX) { /* Disable the UART DMA Tx request */ @@ -989,23 +1013,23 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request */ huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR); } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Resumes the DMA Transfer. - * @param huart: UART handle - * @retval None + * @brief Resume the DMA Transfer. + * @param huart: UART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - + if(huart->State == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ @@ -1013,42 +1037,49 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) } else if(huart->State == HAL_UART_STATE_BUSY_RX) { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + /* Enable the UART DMA Rx request */ huart->Instance->CR3 |= USART_CR3_DMAR; } else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + /* Enable the UART DMA Rx request before the DMA Tx request */ huart->Instance->CR3 |= USART_CR3_DMAR; + /* Enable the UART DMA Tx request */ huart->Instance->CR3 |= USART_CR3_DMAT; } - /* If the UART peripheral is still not enabled, enable it */ - if ((huart->Instance->CR1 & USART_CR1_UE) == 0) - { - /* Enable UART peripheral */ - __HAL_UART_ENABLE(huart); - } - - /* TEACK and/or REACK to check before moving huart->State to Ready */ - return (UART_CheckIdleState(huart)); + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; } /** - * @brief Stops the DMA Transfer. - * @param huart: UART handle - * @retval None + * @brief Stop the DMA Transfer. + * @param huart: UART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { - /* Process Locked */ - __HAL_LOCK(huart); + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback() / HAL_UART_RxHalfCpltCallback (): + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is + generated if the DMA transfer interruption occurs at the middle or at the end of the stream + and the corresponding call back is executed. + */ /* Disable the UART Tx/Rx DMA requests */ huart->Instance->CR3 &= ~USART_CR3_DMAT; huart->Instance->CR3 &= ~USART_CR3_DMAR; - + /* Abort the UART DMA tx channel */ if(huart->hdmatx != NULL) { @@ -1059,219 +1090,218 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { HAL_DMA_Abort(huart->hdmarx); } - - /* Disable UART peripheral */ - __HAL_UART_DISABLE(huart); - + huart->State = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - + return HAL_OK; } - + /** - * @brief Tx Transfer completed callbacks - * @param huart: uart handle + * @brief Tx Transfer completed callback. + * @param huart: UART handle. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback can be implemented in the user file - */ + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ } /** - * @brief Tx Half Transfer completed callbacks. - * @param huart: UART handle + * @brief Tx Half Transfer completed callback. + * @param huart: UART handle. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback can be implemented in the user file - */ + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ } /** - * @brief Rx Transfer completed callbacks - * @param huart: uart handle + * @brief Rx Transfer completed callback. + * @param huart: UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback can be implemented in the user file + the HAL_UART_RxCpltCallback can be implemented in the user file. */ } /** - * @brief Rx Half Transfer completed callbacks. - * @param huart: UART handle + * @brief Rx Half Transfer completed callback. + * @param huart: UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback can be implemented in the user file + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. */ } /** - * @brief UART error callbacks - * @param huart: uart handle + * @brief UART error callback. + * @param huart: UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback can be implemented in the user file - */ + the HAL_UART_ErrorCallback can be implemented in the user file. + */ } /** * @} - */ + */ -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the UART. - (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral. (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) HAL_UART_EnableStopMode() API enables the UART to wake up the MCU from stop mode - (+) HAL_UART_DisableStopMode() API disables the above functionality - (+) UART_SetConfig() API configures the UART peripheral - (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features - (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters - (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter - (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver @endverbatim * @{ */ /** - * @brief Enable UART in mute mode (doesn't mean UART enters mute mode; - * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called) - * @param huart: UART handle + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart: UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) -{ +{ /* Process Locked */ __HAL_LOCK(huart); - + huart->State = HAL_UART_STATE_BUSY; - + /* Enable USART mute mode by setting the MME bit in the CR1 register */ huart->Instance->CR1 |= USART_CR1_MME; - + huart->State = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } /** - * @brief Disable UART mute mode (doesn't mean it actually wakes up the software, + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode * as it may not have been in mute mode at this very moment). - * @param huart: uart handle + * @param huart: UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) -{ +{ /* Process Locked */ __HAL_LOCK(huart); - + huart->State = HAL_UART_STATE_BUSY; - + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ huart->Instance->CR1 &= ~(USART_CR1_MME); - + huart->State = HAL_UART_STATE_READY; - + return (UART_CheckIdleState(huart)); } /** * @brief Enter UART mute mode (means UART actually enters mute mode). - * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart: uart handle - * @retval HAL status + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart: UART handle. + * @retval None */ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ +{ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); } /** - * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart: UART handle + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart: UART handle. * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); huart->State = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_TE); - + huart->State = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart: UART handle - * @retval HAL status + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart: UART handle. + * @retval HAL status. */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); huart->State = HAL_UART_STATE_BUSY; - + /* Clear TE and RE bits */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RE); - + huart->State = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); - return HAL_OK; + return HAL_OK; } /** * @} - */ - -/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim * @{ */ /** - * @brief return the UART state - * @param huart: uart handle + * @brief Return the UART handle state. + * @param huart : pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) @@ -1280,7 +1310,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) } /** -* @brief Return the UART error code +* @brief Return the UART handle error code. * @param huart : pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code @@ -1289,187 +1319,268 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; } +/** + * @} + */ /** * @} - */ - -/** - * @} - */ - + */ + /** @defgroup UART_Private_Functions UART Private Functions * @{ */ - + /** - * @brief Send an amount of data in interrupt mode - * Function called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT() - * @param huart: UART handle + * @brief Configure the UART peripheral. + * @param huart: UART handle. * @retval HAL status */ -HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - uint16_t* tmp; + uint32_t tmpreg = 0x00000000; + UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; + uint16_t brrtemp = 0x0000; + uint16_t usartdiv = 0x0000; + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ; + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg); + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); - if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) + /* Check UART Over Sampling to set Baud Rate Register */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) { - - if(huart->TxXferCount == 0) + switch (clocksource) { - /* Disable the UART Transmit Data Register Empty Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - - /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); - - return HAL_OK; + case UART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } - else - { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; - } - else - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); - } - huart->TxXferCount--; - - return HAL_OK; - } + brrtemp = usartdiv & 0xFFF0; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); + huart->Instance->BRR = brrtemp; } else { - return HAL_BUSY; + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_HSI: + huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_SYSCLK: + huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_LSE: + huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; + } + } + + return ret; + +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart: UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX/TX pins swap */ + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure RX overrun detection disabling */ + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure auto Baud rate detection scheme */ + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); } } /** - * @brief Receive an amount of data in interrupt mode - * Function called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart: UART handle - * @retval HAL status - */ -HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint16_t uhMask = huart->Mask; - - if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) - { - - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) huart->pRxBuffPtr ; - *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - huart->pRxBuffPtr +=2; - } - else - { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - } - - if(--huart->RxXferCount == 0) - { - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State = HAL_UART_STATE_READY; - } - - HAL_UART_RxCpltCallback(huart); - - return HAL_OK; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Check the UART Idle State - * @param huart: uart handle + * @brief Check the UART Idle State. + * @param huart: UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Check if the Transmitter is enabled */ - if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + + /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices). + Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature. + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) + if (IS_UART_WAKEUP_INSTANCE(huart->Instance)) { - /* Wait until TEACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout Occured */ - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout Occured */ - return HAL_TIMEOUT; + /* Check if the Transmitter is enabled */ + if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } } } +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ /* Initialize the UART State */ - huart->State= HAL_UART_STATE_READY; + huart->State= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } + /** - * @brief This function handles UART Communication Timeout. - * @param huart: UART handle + * @brief Handle UART Communication Timeout. + * @param huart: UART handle. * @param Flag: specifies the UART flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @param Status: the Flag status (SET or RESET). + * @param Timeout: Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); /* Wait until flag is set */ if(Status == RESET) - { + { while(__HAL_UART_GET_FLAG(huart, Flag) == RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); @@ -1494,7 +1605,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); @@ -1512,49 +1623,41 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ } } } - return HAL_OK; + return HAL_OK; } /** - * @brief DMA UART transmit process complete callback - * @param hdma: DMA handle + * @brief DMA UART transmit process complete callback. + * @param hdma: DMA handle. * @retval None */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->TxXferCount = 0; - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + /* DMA Normal mode */ + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + { + huart->TxXferCount = 0; - /* Wait for UART TC Flag */ - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TXDMA_TIMEOUTVALUE) != HAL_OK) - { - /* Timeout Occured */ - huart->State = HAL_UART_STATE_TIMEOUT; - HAL_UART_ErrorCallback(huart); + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); } + /* DMA Circular mode */ else { - /* No Timeout */ - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } HAL_UART_TxCpltCallback(huart); } + } /** - * @brief DMA UART transmit process half complete callback - * @param hdma : DMA handle + * @brief DMA UART transmit process half complete callback. + * @param hdma : DMA handle. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1565,49 +1668,55 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA UART receive process complete callback - * @param hdma: DMA handle + * @brief DMA UART receive process complete callback. + * @param hdma: DMA handle. * @retval None */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0; - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + /* DMA Normal mode */ + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + { + huart->RxXferCount = 0; + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + + /* Check if a transmit Process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } + } - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } HAL_UART_RxCpltCallback(huart); } /** - * @brief DMA UART receive process half complete callback - * @param hdma : DMA handle + * @brief DMA UART receive process half complete callback. + * @param hdma : DMA handle. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - HAL_UART_RxHalfCpltCallback(huart); + HAL_UART_RxHalfCpltCallback(huart); } /** - * @brief DMA UART communication error callback - * @param hdma: DMA handle + * @brief DMA UART communication error callback. + * @param hdma: DMA handle. * @retval None */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) +static void UART_DMAError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; huart->RxXferCount = 0; @@ -1618,187 +1727,147 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief Configure the UART peripheral - * @param huart: uart handle - * @retval None + * @brief Send an amount of data in interrupt mode. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart: UART handle. + * @retval HAL status */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00000000; - UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000; - uint16_t usartdiv = 0x0000; - HAL_StatusTypeDef ret = HAL_OK; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - assert_param(IS_UART_ONEBIT_SAMPLING(huart->Init.OneBitSampling)); + uint16_t* tmp; - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value - * set PCE and PS bits according to huart->Init.Parity value - * set TE and RE bits according to huart->Init.Mode value - * set OVER8 bit according to huart->Init.OverSampling value */ - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value - * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling */ - tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ; - MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg); - - /*-------------------------- USART BRR Configuration -----------------------*/ - __HAL_UART_GETCLOCKSOURCE(huart, clocksource); - - /* Check the Over Sampling to set Baud Rate Register */ - if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) { - switch (clocksource) + + if(huart->TxXferCount == 0) { - case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(__DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(__DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(__DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(__DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + /* Disable the UART Transmit Data Register Empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + + return HAL_OK; + } + else + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + tmp = (uint16_t*) huart->pTxBuffPtr; + huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + huart->pTxBuffPtr += 2; + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); + } + + huart->TxXferCount--; + + return HAL_OK; } - - brrtemp = usartdiv & 0xFFF0; - brrtemp |= (uint16_t) ((usartdiv & (uint16_t)0x000F) >> 1U); - huart->Instance->BRR = brrtemp; } else { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_HSI: - huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_SYSCLK: - huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_LSE: - huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } + return HAL_BUSY; } - - return ret; - } + /** - * @brief Configure the UART peripheral advanced feautures - * @param huart: uart handle - * @retval None + * @brief Wrap up transmission in non-blocking mode. + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status */ -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) -{ - /* Check whether the set of advanced features to configure is properly set */ - assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - - /* if required, configure TX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) +HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { - assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + huart->State = HAL_UART_STATE_BUSY_RX; } - - /* if required, configure RX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + else { - assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_READY; } - - /* if required, configure data inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + + HAL_UART_TxCpltCallback(huart); + + return HAL_OK; +} + + +/** + * @brief Receive an amount of data in interrupt mode. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart: UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +{ + uint16_t* tmp; + uint16_t uhMask = huart->Mask; + + if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX)) { - assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - } - - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - - /* if required, configure RX overrun detection disabling */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - { - assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - } - - /* if required, configure DMA disabling on reception error */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - } - - /* if required, configure auto Baud rate detection scheme */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - { - assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - /* set auto Baudrate detection parameters if detection is enabled */ - if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + tmp = (uint16_t*) huart->pRxBuffPtr ; + *tmp = (uint16_t)(huart->Instance->RDR & uhMask); + huart->pRxBuffPtr +=2; } + else + { + *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + } + + if(--huart->RxXferCount == 0) + { + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + + /* Check if a transmit Process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_READY; + } + + HAL_UART_RxCpltCallback(huart); + + return HAL_OK; + } + + return HAL_OK; } - - /* if required, configure MSB first on communication line */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + else { - assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + return HAL_BUSY; } } /** * @} */ - + #endif /* HAL_UART_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h index 29bf8761b0..7d0d05ab99 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_uart.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of UART HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -52,17 +52,16 @@ /** @addtogroup UART * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup UART_Exported_Types UART Exported Types * @{ - */ + */ - -/** - * @brief UART Init Structure definition - */ +/** + * @brief UART Init Structure definition + */ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. @@ -70,7 +69,7 @@ typedef struct - If oversampling is 16 or in LIN mode (LIN mode not available on F030xx devices), Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */ @@ -86,64 +85,66 @@ typedef struct at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ - + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref UART_Mode */ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref UART_Hardware_Flow_Control */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). - This parameter can be a value of @ref UART_Over_Sampling */ - + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling */ + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ }UART_InitTypeDef; -/** - * @brief UART Advanced Features initalization structure definition +/** + * @brief UART Advanced Features initalization structure definition */ -typedef struct +typedef struct { uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */ - + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. This parameter can be a value of @ref UART_Tx_Inv */ - + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. This parameter can be a value of @ref UART_Rx_Inv */ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic vs negative/inverted logic). This parameter can be a value of @ref UART_Data_Inv */ - - uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. This parameter can be a value of @ref UART_Rx_Tx_Swap */ - - uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. This parameter can be a value of @ref UART_Overrun_Disable */ - - uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */ - - uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. - This parameter can be a value of @ref UART_AutoBaudRate_Enable */ - - uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate - detection is carried out. + + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. This parameter can be a value of @ref UARTEx_AutoBaud_Rate_Mode */ - - uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref UART_MSB_First */ } UART_AdvFeatureInitTypeDef; -/** - * @brief HAL UART State structures definition - */ + + +/** + * @brief HAL UART State structures definition + */ typedef enum { HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ @@ -165,12 +166,12 @@ typedef enum UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */ }UART_ClockSourceTypeDef; -/** - * @brief UART handle Structure definition - */ +/** + * @brief UART handle Structure definition + */ typedef struct { USART_TypeDef *Instance; /*!< UART registers base address */ @@ -199,19 +200,18 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - HAL_UART_StateTypeDef State; /*!< UART communication state */ - - __IO uint32_t ErrorCode; /*!< UART Error code - This parameter can be a value of @ref UART_Error */ - + __IO HAL_UART_StateTypeDef State; /*!< UART communication state */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + }UART_HandleTypeDef; /** * @} */ - + /* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported constants +/** @defgroup UART_Exported_Constants UART Exported Constants * @{ */ @@ -234,60 +234,46 @@ typedef struct #define UART_STOPBITS_1 ((uint32_t)0x0000) #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) #define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) -#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ - ((STOPBITS) == UART_STOPBITS_2) || \ - ((STOPBITS) == UART_STOPBITS_1_5)) /** * @} - */ + */ /** @defgroup UART_Parity UART Parity * @{ - */ -#define UART_PARITY_NONE ((uint32_t)0x0000) -#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ - ((PARITY) == UART_PARITY_EVEN) || \ - ((PARITY) == UART_PARITY_ODD)) + */ +#define UART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ +#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ +#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ /** * @} - */ + */ /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control * @{ - */ -#define UART_HWCONTROL_NONE ((uint32_t)0x0000) -#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) -#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) -#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == UART_HWCONTROL_NONE) || \ - ((CONTROL) == UART_HWCONTROL_RTS) || \ - ((CONTROL) == UART_HWCONTROL_CTS) || \ - ((CONTROL) == UART_HWCONTROL_RTS_CTS)) + */ +#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) /*!< No hardware control */ +#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */ +#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */ /** * @} */ /** @defgroup UART_Mode UART Transfer Mode * @{ - */ -#define UART_MODE_RX ((uint32_t)USART_CR1_RE) -#define UART_MODE_TX ((uint32_t)USART_CR1_TE) -#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00)) + */ +#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */ +#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */ +#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */ /** * @} */ - - /** @defgroup UART_State UART State + +/** @defgroup UART_State UART State * @{ - */ -#define UART_STATE_DISABLE ((uint32_t)0x0000) -#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) -#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ - ((STATE) == UART_STATE_ENABLE)) + */ +#define UART_STATE_DISABLE ((uint32_t)0x00000000) /*!< UART disabled */ +#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */ /** * @} */ @@ -295,55 +281,35 @@ typedef struct /** @defgroup UART_Over_Sampling UART Over Sampling * @{ */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x0000) -#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) -#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ - ((SAMPLING) == UART_OVERSAMPLING_8)) +#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */ /** * @} - */ + */ /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method * @{ */ -#define UART_ONEBIT_SAMPLING_DISABLED ((uint32_t)0x0000) -#define UART_ONEBIT_SAMPLING_ENABLED ((uint32_t)USART_CR3_ONEBIT) -#define IS_UART_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == UART_ONEBIT_SAMPLING_DISABLED) || \ - ((ONEBIT) == UART_ONEBIT_SAMPLING_ENABLED)) +#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */ /** * @} - */ - + */ -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut +/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) -#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) -#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE)) +#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< UART receiver timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */ /** * @} - */ - -/** @defgroup UART_One_Bit UART One Bit sampling - * @{ */ -#define UART_ONE_BIT_SAMPLE_DISABLED ((uint32_t)0x00000000) -#define UART_ONE_BIT_SAMPLE_ENABLED ((uint32_t)USART_CR3_ONEBIT) -#define IS_UART_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLED) || \ - ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLED)) -/** - * @} - */ - + /** @defgroup UART_DMA_Tx UART DMA Tx * @{ */ -#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) -#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) -#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \ - ((DMATX) == UART_DMA_TX_ENABLE)) +#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */ /** * @} */ @@ -351,10 +317,8 @@ typedef struct /** @defgroup UART_DMA_Rx UART DMA Rx * @{ */ -#define UART_DMA_RX_DISABLE ((uint32_t)0x0000) -#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) -#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \ - ((DMARX) == UART_DMA_RX_ENABLE)) +#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */ /** * @} */ @@ -362,21 +326,17 @@ typedef struct /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection * @{ */ -#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000) -#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) -#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \ - ((HDSEL) == UART_HALF_DUPLEX_ENABLE)) +#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000) /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */ /** * @} - */ + */ /** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) -#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) -#define IS_UART_ADDRESSLENGTH_DETECT(ADDRESS) (((ADDRESS) == UART_ADDRESS_DETECT_4B) || \ - ((ADDRESS) == UART_ADDRESS_DETECT_7B)) +#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */ /** * @} */ @@ -384,10 +344,8 @@ typedef struct /** @defgroup UART_WakeUp_Methods UART WakeUp Methods * @{ */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) -#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) -#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */ /** * @} */ @@ -416,24 +374,15 @@ typedef struct /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type * @{ */ -#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) -#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) -#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) -#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) -#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) -#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) -#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \ - UART_ADVFEATURE_TXINVERT_INIT | \ - UART_ADVFEATURE_RXINVERT_INIT | \ - UART_ADVFEATURE_DATAINVERT_INIT | \ - UART_ADVFEATURE_SWAP_INIT | \ - UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ - UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ - UART_ADVFEATURE_MSBFIRST_INIT)) +#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */ /** * @} */ @@ -441,10 +390,8 @@ typedef struct /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) -#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) -#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \ - ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE)) +#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */ /** * @} */ @@ -452,10 +399,8 @@ typedef struct /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion * @{ */ -#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) -#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) -#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \ - ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE)) +#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */ /** * @} */ @@ -463,10 +408,8 @@ typedef struct /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion * @{ */ -#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) -#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) -#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \ - ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE)) +#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */ /** * @} */ @@ -474,10 +417,8 @@ typedef struct /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap * @{ */ -#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) -#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) -#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \ - ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE)) +#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */ /** * @} */ @@ -485,10 +426,8 @@ typedef struct /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable * @{ */ -#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) -#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) -#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ - ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE)) +#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */ /** * @} */ @@ -496,10 +435,8 @@ typedef struct /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */ /** * @} */ @@ -507,10 +444,8 @@ typedef struct /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error * @{ */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) -#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) -#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ - ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */ /** * @} */ @@ -518,10 +453,8 @@ typedef struct /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) -#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) -#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ - ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE)) +#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */ /** * @} */ @@ -529,10 +462,8 @@ typedef struct /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable * @{ */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) -#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) -#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ - ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE)) +#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */ /** * @} */ @@ -548,10 +479,8 @@ typedef struct /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity * @{ */ -#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) -#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) -#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \ - ((POLARITY) == UART_DE_POLARITY_LOW)) +#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */ /** * @} */ @@ -559,7 +488,7 @@ typedef struct /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) +#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) /** * @} */ @@ -567,50 +496,101 @@ typedef struct /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) +#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) /** * @} */ /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask * @{ - */ -#define UART_IT_MASK ((uint32_t)0x001F) + */ +#define UART_IT_MASK ((uint32_t)0x001F) /** * @} */ - + /** @defgroup UART_TimeOut_Value UART polling-based communications time-out value * @{ - */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF /** * @} */ + /** * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup UART_Exported_Macros UART Exported Macros * @{ */ - -/** @brief Reset UART handle state + +/** @brief Reset UART handle state. * @param __HANDLE__: UART handle. * @retval None */ #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) -/** @brief Checks whether the specified UART flag is set or not. +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg UART_CLEAR_PEF, Parity Error Clear Flag + * @arg UART_CLEAR_FEF, Framing Error Clear Flag + * @arg UART_CLEAR_NEF, Noise detected Clear Flag + * @arg UART_CLEAR_OREF, OverRun Error Clear Flag + * @arg UART_CLEAR_IDLEF, IDLE line detected Clear Flag + * @arg UART_CLEAR_TCF, Transmission Complete Clear Flag + * @arg UART_CLEAR_LBDF, LIN Break Detection Clear Flag (not available on all devices) + * @arg UART_CLEAR_CTSF, CTS Interrupt Clear Flag + * @arg UART_CLEAR_RTOF, Receiver Time Out Clear Flag + * @arg UART_CLEAR_EOBF, End Of Block Clear Flag (not available on all devices) + * @arg UART_CLEAR_CMF, Character Match Clear Flag + * @arg UART_CLEAR_WUF, Wake Up from stop mode Clear Flag (not available on all devices) + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + +/** @brief Check whether the specified UART flag is set or not. * @param __HANDLE__: specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or * UART peripheral (datasheet: up to four USART/UARTs) * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg UART_FLAG_REACK: Receive enable ackowledge flag - * @arg UART_FLAG_TEACK: Transmit enable ackowledge flag + * @arg UART_FLAG_REACK: Receive enable acknowledge flag + * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag * @arg UART_FLAG_WUF: Wake up from stop mode flag (not available on F030xx devices) * @arg UART_FLAG_RWU: Receiver wake up flag (not available on F030xx devices) * @arg UART_FLAG_SBKF: Send Break flag @@ -619,7 +599,7 @@ typedef struct * @arg UART_FLAG_ABRF: Auto Baud rate detection flag * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag * @arg UART_FLAG_EOBF: End of block flag (not available on F030xx devices) - * @arg UART_FLAG_RTOF: Receiver timeout flag + * @arg UART_FLAG_RTOF: Receiver timeout flag * @arg UART_FLAG_CTS: CTS Change flag * @arg UART_FLAG_LBD: LIN Break detection flag (not available on F030xx devices) * @arg UART_FLAG_TXE: Transmit data register empty flag @@ -632,9 +612,9 @@ typedef struct * @arg UART_FLAG_PE: Parity Error flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) -/** @brief Enables the specified UART interrupt. +/** @brief Enable the specified UART interrupt. * @param __HANDLE__: specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or * UART peripheral. (datasheet: up to four USART/UARTs) @@ -657,14 +637,14 @@ typedef struct ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) -/** @brief Disables the specified UART interrupt. +/** @brief Disable the specified UART interrupt. * @param __HANDLE__: specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or * UART peripheral. (datasheet: up to four USART/UARTs) * @param __INTERRUPT__: specifies the UART interrupt source to disable. * This parameter can be one of the following values: * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices) - * @arg UART_IT_CM: Character match interrupt + * @arg UART_IT_CM: Character match interrupt * @arg UART_IT_CTS: CTS change interrupt * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices) * @arg UART_IT_TXE: Transmit Data Register empty interrupt @@ -672,21 +652,21 @@ typedef struct * @arg UART_IT_RXNE: Receive Data register not empty interrupt * @arg UART_IT_IDLE: Idle line detection interrupt * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg UART_IT_ERR: Error interrupt (Frame error, noise error, overrun error) * @retval None */ #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) -/** @brief Checks whether the specified UART interrupt has occurred or not. +/** @brief Check whether the specified UART interrupt has occurred or not. * @param __HANDLE__: specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or * UART peripheral. (datasheet: up to four USART/UARTs) * @param __IT__: specifies the UART interrupt to check. * This parameter can be one of the following values: * @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices) - * @arg UART_IT_CM: Character match interrupt + * @arg UART_IT_CM: Character match interrupt * @arg UART_IT_CTS: CTS change interrupt * @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices) * @arg UART_IT_TXE: Transmit Data Register empty interrupt @@ -696,12 +676,12 @@ typedef struct * @arg UART_IT_ORE: OverRun Error interrupt * @arg UART_IT_NE: Noise Error interrupt * @arg UART_IT_FE: Framing Error interrupt - * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) -/** @brief Checks whether the specified UART interrupt source is enabled. +/** @brief Check whether the specified UART interrupt source is enabled or not. * @param __HANDLE__: specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or * UART peripheral. (datasheet: up to four USART/UARTs) @@ -718,34 +698,34 @@ typedef struct * @arg UART_IT_ORE: OverRun Error interrupt * @arg UART_IT_NE: Noise Error interrupt * @arg UART_IT_FE: Framing Error interrupt - * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) -/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag. +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__: specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or * UART peripheral. (datasheet: up to four USART/UARTs) * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: - * @arg UART_CLEAR_PEF: Parity Error Clear Flag - * @arg UART_CLEAR_FEF: Framing Error Clear Flag - * @arg UART_CLEAR_NEF: Noise detected Clear Flag - * @arg UART_CLEAR_OREF: OverRun Error Clear Flag - * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag - * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag + * @arg UART_CLEAR_PEF: Parity Error Clear Flag + * @arg UART_CLEAR_FEF: Framing Error Clear Flag + * @arg UART_CLEAR_NEF: Noise detected Clear Flag + * @arg UART_CLEAR_OREF: OverRun Error Clear Flag + * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag + * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag (not available on F030xx devices) - * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag - * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag - * @arg UART_CLEAR_EOBF: End Of Block Clear Flag (not available on F030xx devices) - * @arg UART_CLEAR_CMF: Character Match Clear Flag + * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag + * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag + * @arg UART_CLEAR_EOBF: End Of Block Clear Flag (not available on F030xx devices) + * @arg UART_CLEAR_CMF: Character Match Clear Flag * @arg UART_CLEAR_WUF: Wake Up from stop mode Clear Flag (not available on F030xx devices) * @retval None */ -#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific UART request flag. * @param __HANDLE__: specifies the UART Handle. @@ -753,29 +733,113 @@ typedef struct * UART peripheral. (datasheet: up to four USART/UARTs) * @param __REQ__: specifies the request flag to set * This parameter can be one of the following values: - * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request - * @arg UART_SENDBREAK_REQUEST: Send Break Request - * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request - * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request - * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request (not available on F030xx devices) + * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request + * @arg UART_SENDBREAK_REQUEST: Send Break Request + * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request + * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request + * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request (not available on F030xx devices) * @retval None */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) -/** @brief Enable UART +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + +/** @brief Enable UART. * @param __HANDLE__: specifies the UART Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral * @retval None - */ + */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) -/** @brief Disable UART +/** @brief Disable UART. * @param __HANDLE__: specifies the UART Handle. * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral * @retval None */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0) + /** * @} */ @@ -785,54 +849,256 @@ typedef struct * @{ */ -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode - * @param _PCLK_: UART clock - * @param _BAUD_: Baud rate set by the user +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__: UART clock. + * @param __BAUD__: Baud rate set by the user. * @retval Division result */ -#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_))) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) (((__PCLK__)*2)/((__BAUD__))) -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode - * @param _PCLK_: UART clock - * @param _BAUD_: Baud rate set by the user +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__: UART clock. + * @param __BAUD__: Baud rate set by the user. * @retval Division result */ -#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_))) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__))/((__BAUD__))) /** @brief Check UART Baud rate - * @param BAUDRATE: Baudrate specified by the user + * @param __BAUDRATE__: Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001) + +/** @brief Check UART assertion time. + * @param __TIME__: 5-bit value assertion time. * @retval Test result (TRUE or FALSE). */ -#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001) +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) -/** @brief Check UART assertion time - * @param TIME: 5-bit value assertion time - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F) - -/** @brief Check UART deassertion time - * @param TIME: 5-bit value deassertion time - * @retval Test result (TRUE or FALSE). +/** @brief Check UART deassertion time. + * @param __TIME__: 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). */ -#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F) +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__: UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) UART_STOPBITS_1_5 + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_2) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5)) + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__: UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__: UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__: UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__: UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__: UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__: UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that Address Length detection parameter is valid. + * @param __ADDRESS__: UART Adress length value. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__: UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__: UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__: UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__: UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__: UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__: UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__: UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__: UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__: UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__: UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__: UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__: UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__: UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__: UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__: UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__: UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) /** * @} */ /* Include UART HAL Extension module */ -#include "stm32f0xx_hal_uart_ex.h" +#include "stm32f0xx_hal_uart_ex.h" /* Exported functions --------------------------------------------------------*/ - /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -848,7 +1114,7 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); * @} */ -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions * @{ */ @@ -862,6 +1128,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); @@ -876,10 +1143,10 @@ void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); * @{ */ -/* Peripheral Control functions ***********************************************/ -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +/* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); @@ -887,22 +1154,23 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); * @} */ -/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions * @{ */ /* Peripheral State and Errors functions **************************************************/ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); /** * @} - */ + */ /** * @} - */ + */ +/* Private functions -----------------------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ */ @@ -910,15 +1178,16 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); /** * @} - */ - + */ + /** * @} - */ + */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c index 0a0121e984..512ead707a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c @@ -2,10 +2,9 @@ ****************************************************************************** * @file stm32f0xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Extended UART HAL module driver. - * * This file provides firmware functions to manage the following extended * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). * + Initialization and de-initialization functions @@ -13,23 +12,21 @@ * * @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The Extended UART HAL driver can be used as follows: - + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + (#) Declare a UART_HandleTypeDef handle structure. - (#) For the UART RS485 Driver Enabled mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -53,7 +50,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -63,7 +60,7 @@ * @{ */ -/** @defgroup UARTEx UARTEx Extended HAL module driver +/** @defgroup UARTEx UARTEx * @brief UART Extended HAL module driver * @{ */ @@ -72,17 +69,15 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - /** @defgroup UARTEx_Private_Functions UARTEx Private Functions * @{ */ #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) -static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); /** * @} @@ -94,7 +89,7 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); * @{ */ -/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions +/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization and de-initialization functions * @brief Extended Initialization and Configuration Functions * @verbatim @@ -104,29 +99,43 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); [..] This subsection provides a set of functions allowing to initialize the USARTx or the UARTy in asynchronous mode. - (+) For the asynchronous mode only these parameters can be configured: + (+) For the asynchronous mode the parameters below can be configured: (++) Baud Rate (++) Word Length (Fixed to 8-bits only for LIN mode) (++) Stop Bit (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible UART frame formats are as listed in the following table: - |-----------|-----------|---------------------------------------| - | M1M0 bits | PCE bit | UART frame | - |-----------------------|---------------------------------------| - | 00 | 0 | | SB | 8-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 00 | 1 | | SB | 7-bit data | PB | STB | | - |-----------|-----------|---------------------------------------| - | 01 | 0 | | SB | 9-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 01 | 1 | | SB | 8-bit data | PB | STB | | - +---------------------------------------------------------------+ - | 10 | 0 | | SB | 7-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 10 | 1 | | SB | 6-bit data | PB | STB | | - +---------------------------------------------------------------+ + According to device capability (support or not of 7-bit word length), + frame length is either defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). + Possible UART frame formats are as listed in the following table: + + (+++) Table 1. UART frame format. + (+++) +-----------------------------------------------------------------------+ + (+++) | M bit | PCE bit | UART frame | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 0 | 0 | | SB | 8-bit data | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 1 | 0 | | SB | 9-bit data | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | | + (+++) +-----------------------------------------------------------------------+ + (+++) | M1 bit | M0 bit | PCE bit | UART frame | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + (+++) +-----------------------------------------------------------------------+ (++) Hardware flow control (++) Receiver/transmitter modes (++) Over Sampling Method @@ -148,30 +157,29 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); * @{ */ -#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** - * @brief Initializes the RS485 Driver enable feature according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: uart handle - * @param UART_DEPolarity: select the driver enable polarity + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart: UART handle. + * @param Polarity: select the driver enable polarity. * This parameter can be one of the following values: * @arg UART_DE_POLARITY_HIGH: DE signal is active high * @arg UART_DE_POLARITY_LOW: DE signal is active low - * @param UART_DEAssertionTime: Driver Enable assertion time + * @param AssertionTime: Driver Enable assertion time: * 5-bit value defining the time between the activation of the DE (Driver Enable) * signal and the beginning of the start bit. It is expressed in sample time - * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param UART_DEDeassertionTime: Driver Enable deassertion time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime: Driver Enable deassertion time: * 5-bit value defining the time between the end of the last stop bit, in a * transmitted message, and the de-activation of the DE (Driver Enable) signal. * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the - * oversampling rate). + * oversampling rate). * @retval HAL status */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime) +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { uint32_t temp = 0x0; - + /* Check the UART handle allocation */ if(huart == NULL) { @@ -179,62 +187,64 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPo } /* Check the Driver Enable UART instance */ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - + /* Check the Driver Enable polarity */ - assert_param(IS_UART_DE_POLARITY(UART_DEPolarity)); - + assert_param(IS_UART_DE_POLARITY(Polarity)); + /* Check the Driver Enable assertion time */ - assert_param(IS_UART_ASSERTIONTIME(UART_DEAssertionTime)); - + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + /* Check the Driver Enable deassertion time */ - assert_param(IS_UART_DEASSERTIONTIME(UART_DEDeassertionTime)); - + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + if(huart->State == HAL_UART_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK */ + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); } - + huart->State = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + } + + if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ - huart->Instance->CR3 |= USART_CR3_DEM; - + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + /* Set the Driver Enable polarity */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, UART_DEPolarity); - + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + /* Set the Driver Enable assertion and deassertion times */ - temp = (UART_DEAssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); - temp |= (UART_DEDeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->State to Ready */ return (UART_CheckIdleState(huart)); } -#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)*/ #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** - * @brief Initializes the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: uart handle + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle . + * @param huart: UART handle. * @param BreakDetectLength: specifies the LIN break detection length. * This parameter can be one of the following values: * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection @@ -248,59 +258,68 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe { return HAL_ERROR; } - - /* Check the parameters */ + + /* Check the LIN UART instance */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - + /* LIN mode limited to 16-bit oversampling only */ if(huart->Init.OverSampling == UART_OVERSAMPLING_8) { return HAL_ERROR; } - - /* in LIN mode, data length is limited to 8-bit only */ - if(huart->Init.WordLength!= UART_WORDLENGTH_8B) + /* LIN mode limited to 8-bit data length */ + if(huart->Init.WordLength != UART_WORDLENGTH_8B) { return HAL_ERROR; } - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_UART_MspInit(huart); - + if(huart->State == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + } + + huart->State = HAL_UART_STATE_BUSY; + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) { return HAL_ERROR; - } - + } + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { UART_AdvFeatureConfig(huart); } - - /* In LIN mode, the following bits must be kept cleared: + + /* In LIN mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ huart->Instance->CR2 &= ~(USART_CR2_CLKEN); huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN); - + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ huart->Instance->CR2 |= USART_CR2_LINEN; - + /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* TEACK and/or REACK to check before moving huart->State to Ready */ return (UART_CheckIdleState(huart)); } #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ + /** * @} */ @@ -320,7 +339,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe (++) HAL_UART_IRQHandler() (#) Callback provided in No_Blocking mode: - (++) HAL_UART_WakeupCallback() + (++) HAL_UARTEx_WakeupCallback() @endverbatim * @{ @@ -328,101 +347,102 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** - * @brief This function handles UART interrupt request. - * @param huart: uart handle + * @brief Handle UART interrupt request. + * @param huart: UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { /* UART parity error interrupt occurred -------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) - { + { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); - + huart->ErrorCode |= HAL_UART_ERROR_PE; /* Set the UART state ready to be able to start again the process */ huart->State = HAL_UART_STATE_READY; } - - /* UART frame error interrupt occured --------------------------------------*/ + + /* UART frame error interrupt occurred --------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { + { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); - + huart->ErrorCode |= HAL_UART_ERROR_FE; /* Set the UART state ready to be able to start again the process */ huart->State = HAL_UART_STATE_READY; } - - /* UART noise error interrupt occured --------------------------------------*/ + + /* UART noise error interrupt occurred --------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { + { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; + + huart->ErrorCode |= HAL_UART_ERROR_NE; /* Set the UART state ready to be able to start again the process */ huart->State = HAL_UART_STATE_READY; } - - /* UART Over-Run interrupt occured -----------------------------------------*/ + + /* UART Over-Run interrupt occurred -----------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) - { + { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); - - huart->ErrorCode |= HAL_UART_ERROR_ORE; + + huart->ErrorCode |= HAL_UART_ERROR_ORE; /* Set the UART state ready to be able to start again the process */ huart->State = HAL_UART_STATE_READY; } - + /* Call UART Error Call back function if need be --------------------------*/ if(huart->ErrorCode != HAL_UART_ERROR_NONE) { HAL_UART_ErrorCallback(huart); } - + #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET)) - { + { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); /* Set the UART state ready to be able to start again the process */ huart->State = HAL_UART_STATE_READY; - HAL_UART_WakeupCallback(huart); + HAL_UARTEx_WakeupCallback(huart); } #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ - + /* UART in mode Receiver ---------------------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET)) - { + { UART_Receive_IT(huart); /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } - + /* UART in mode Transmitter ------------------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET)) { UART_Transmit_IT(huart); - } - - /* UART in mode Transmitter ------------------------------------------------*/ + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) { UART_EndTransmit_IT(huart); - } + } + } #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** - * @brief UART wakeup from Stop mode callback - * @param huart: uart handle + * @brief UART wakeup from Stop mode callback + * @param huart: UART handle * @retval None */ - __weak void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart) + __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_WakeupCallback can be implemented in the user file + the HAL_UARTEx_WakeupCallback can be implemented in the user file */ } #endif /*!defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)*/ @@ -441,12 +461,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) =============================================================================== [..] This subsection provides extended functions allowing to control the UART. - (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address - detection length to more than 4 bits for multiprocessor address mark wake up. (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection (+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as long as UART clock is HSI or LSE (+) HAL_UARTEx_DisableStopMode() API disables the above feature + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. (+) HAL_LIN_SendBreak() API transmits the break characters @endverbatim @@ -455,59 +475,65 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** - * @brief Set Wakeup from Stop mode interrupt flag selection - * @param huart: uart handle, + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @param huart: UART handle. * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg UART_WAKEUP_ON_ADDRESS * @arg UART_WAKEUP_ON_STARTBIT - * @arg UART_WAKEUP_ON_READDATA_NONEMPTY + * @arg UART_WAKEUP_ON_READDATA_NONEMPTY * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { - /* Check parameters */ + HAL_StatusTypeDef status = HAL_OK; + + /* check the wake-up from stop mode UART instance */ assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - + /* Process Locked */ __HAL_LOCK(huart); - + huart->State = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the wake-up selection scheme */ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); - + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) { - UART_Wakeup_AddressConfig(huart, WakeUpSelection); + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); } - + /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - + /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - return HAL_TIMEOUT; + if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; } else { /* Initialize the UART State */ - huart->State= HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; + huart->State = HAL_UART_STATE_READY; } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; } + /** - * @brief Enable UART Stop Mode - * The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE - * @param huart: uart handle + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart: UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) @@ -517,23 +543,23 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - + huart->State = HAL_UART_STATE_BUSY; - - /* Set the USART UESM bit */ - huart->Instance->CR1 |= USART_CR1_UESM; - + + /* Set UESM bit */ + SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + huart->State = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Disable UART Stop Mode - * @param huart: uart handle + * @brief Disable UART Stop Mode. + * @param huart: UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) @@ -543,34 +569,32 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; - /* Clear USART UESM bit */ - huart->Instance->CR1 &= ~(USART_CR1_UESM); - + huart->State = HAL_UART_STATE_BUSY; + + /* Clear UESM bit */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + huart->State = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - - return HAL_OK; -} + return HAL_OK; +} #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ - + /** - * @brief By default in multiprocessor mode, when the wake up method is set - * to address mark, the UART handles only 4-bit long addresses detection. - * This API allows to enable longer addresses detection (6-, 7- or 8-bit - * long): - * - 6-bit address detection in 7-bit data mode - * - 7-bit address detection in 8-bit data mode - * - 8-bit address detection in 9-bit data mode - * @param huart: UART handle + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart: UART handle. * @param AddressLength: this parameter can be one of the following values: * @arg UART_ADDRESS_DETECT_4B: 4-bit long address - * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address + * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) @@ -583,18 +607,18 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua /* Check the address length parameter */ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - + huart->State = HAL_UART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - + /* Set the address length */ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - + /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - + __HAL_UART_ENABLE(huart); + /* TEACK and/or REACK to check before moving huart->State to Ready */ return (UART_CheckIdleState(huart)); } @@ -602,31 +626,30 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** - * @brief Transmits break characters. - * @param huart: UART handle + * @brief Transmit break characters. + * @param huart: UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); - + /* Process Locked */ __HAL_LOCK(huart); - + huart->State = HAL_UART_STATE_BUSY; - + /* Send break characters */ - huart->Instance->RQR |= UART_SENDBREAK_REQUEST; - + huart->Instance->RQR |= UART_SENDBREAK_REQUEST; + huart->State = HAL_UART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - - return HAL_OK; -} + return HAL_OK; +} #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ /** @@ -635,49 +658,20 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /** * @} - */ + */ /** @addtogroup UARTEx_Private_Functions * @{ */ - -/** - * @brief Wraps up transmission in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State = HAL_UART_STATE_READY; - } - - HAL_UART_TxCpltCallback(huart); - - return HAL_OK; -} #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) /** - * @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart: uart handle - * @param WakeUpSelection: UART wake up from stop mode parameters - * @retval HAL status - */ -static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart: UART handle. + * @param WakeUpSelection: UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { /* Check parmeters */ assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance)); diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h index 7a941621bd..968a75cd3a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -52,29 +52,30 @@ /** @addtogroup UARTEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** @defgroup UARTEx_Exported_Types UARTEx Exported Types * @{ - */ - -/** - * @brief UART wake up from stop mode parameters */ -typedef struct + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct { uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF). This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must be filled up. */ - + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. This parameter can be a value of @ref UART_WakeUp_Address_Length */ - + uint8_t Address; /*!< UART/USART node address (7-bit long max) */ } UART_WakeUpTypeDef; + /** * @} */ @@ -84,7 +85,7 @@ typedef struct /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants * @{ */ - + /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ @@ -94,14 +95,9 @@ typedef struct #define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) #define UART_WORDLENGTH_8B ((uint32_t)0x00000000) #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) -#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_7B) || \ - ((LENGTH) == UART_WORDLENGTH_8B) || \ - ((LENGTH) == UART_WORDLENGTH_9B)) #else #define UART_WORDLENGTH_8B ((uint32_t)0x00000000) #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ - ((LENGTH) == UART_WORDLENGTH_9B)) #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ @@ -115,35 +111,26 @@ typedef struct #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000) -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) -#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ - ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ - ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ - ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /*!< Auto Baud rate detection on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */ #else -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000) -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) -#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ - ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE)) +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /*!< Auto Baud rate detection on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */ #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ /** * @} */ - #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** @defgroup UARTEx_LIN UARTEx Local Interconnection Network mode * @{ */ -#define UART_LIN_DISABLE ((uint32_t)0x00000000) -#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) -#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \ - ((LIN) == UART_LIN_ENABLE)) +#define UART_LIN_DISABLE ((uint32_t)0x00000000) /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */ /** * @} */ @@ -151,10 +138,8 @@ typedef struct /** @defgroup UARTEx_LIN_Break_Detection UARTEx LIN Break Detection * @{ */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) -#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) -#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) +#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */ /** * @} */ @@ -165,7 +150,9 @@ typedef struct * - 0xXXXX : Flag mask in the ISR register * @{ */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) #define UART_FLAG_REACK ((uint32_t)0x00400000) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ #define UART_FLAG_TEACK ((uint32_t)0x00200000) #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) #define UART_FLAG_WUF ((uint32_t)0x00100000) @@ -176,9 +163,9 @@ typedef struct #define UART_FLAG_BUSY ((uint32_t)0x00010000) #define UART_FLAG_ABRF ((uint32_t)0x00008000) #define UART_FLAG_ABRE ((uint32_t)0x00004000) -#if !defined(STM32F030x6) && !defined(STM32F030x8) +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) #define UART_FLAG_EOBF ((uint32_t)0x00001000) -#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ #define UART_FLAG_RTOF ((uint32_t)0x00000800) #define UART_FLAG_CTS ((uint32_t)0x00000400) #define UART_FLAG_CTSIF ((uint32_t)0x00000200) @@ -239,7 +226,9 @@ typedef struct #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ #define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) #define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ @@ -255,68 +244,79 @@ typedef struct #define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */ #define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */ #define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#if !defined(STM32F030x6) && !defined(STM32F030x8) +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) #define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ -#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \ - ((PARAM) == UART_SENDBREAK_REQUEST) || \ - ((PARAM) == UART_MUTE_MODE_REQUEST) || \ - ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \ - ((PARAM) == UART_TXDATA_FLUSH_REQUEST)) #else -#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \ - ((PARAM) == UART_SENDBREAK_REQUEST) || \ - ((PARAM) == UART_MUTE_MODE_REQUEST) || \ - ((PARAM) == UART_RXDATA_FLUSH_REQUEST)) -#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ /** * @} */ - + #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) /** @defgroup UART_Stop_Mode_Enable UARTEx Advanced Feature Stop Mode Enable * @{ */ -#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) -#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) -#define IS_UART_ADVFEATURE_STOPMODE(STOPMODE) (((STOPMODE) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ - ((STOPMODE) == UART_ADVFEATURE_STOPMODE_ENABLE)) +#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */ /** * @} */ - + /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ -#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000) -#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) -#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) -#define IS_UART_WAKEUP_SELECTION(WAKE) (((WAKE) == UART_WAKEUP_ON_ADDRESS) || \ - ((WAKE) == UART_WAKEUP_ON_STARTBIT) || \ - ((WAKE) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000) /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */ /** * @} - */ + */ #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ - + /** * @} - */ - -/* Exported macro ------------------------------------------------------------*/ + */ +/* Exported macros ------------------------------------------------------------*/ /** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros * @{ */ -/** @brief Reports the UART clock source. - * @param __HANDLE__: specifies the UART Handle - * @param __CLOCKSOURCE__ : output variable +/** @brief Flush the UART Data registers. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0) +#else +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + } while(0) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__: specifies the UART Handle. + * @param __CLOCKSOURCE__: output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) -#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ switch(__HAL_RCC_GET_USART1_SOURCE()) \ { \ @@ -340,7 +340,7 @@ typedef struct #elif defined (STM32F030x8) || defined (STM32F070x6) || \ defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F051x8) || defined (STM32F058xx) -#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -373,7 +373,7 @@ typedef struct } \ } while(0) #elif defined(STM32F070xB) -#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -414,7 +414,7 @@ typedef struct } \ } while(0) #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) -#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -472,7 +472,7 @@ typedef struct } \ } while(0) #elif defined(STM32F091xC) || defined (STM32F098xx) -#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -563,7 +563,7 @@ typedef struct } \ } while(0) #elif defined(STM32F030xC) -#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -615,19 +615,19 @@ typedef struct #endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */ -/** @brief Computes the UART mask to apply to retrieve the received data +/** @brief Compute the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. - * If PCE = 1, the parity bit is not included in the data extracted + * @note If PCE = 1, the parity bit is not included in the data extracted * by the reception API(). * This masking operation is not carried out in the case of - * DMA transfers. - * @param __HANDLE__: specifies the UART Handle - * @retval none - */ + * DMA transfers. + * @param __HANDLE__: specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) -#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \ +#define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ { \ @@ -662,9 +662,9 @@ typedef struct (__HANDLE__)->Mask = 0x003F ; \ } \ } \ -} while(0) +} while(0) #else -#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \ +#define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ { \ @@ -692,6 +692,100 @@ typedef struct #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__: UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ + defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) +#else +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ + defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__: UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ + defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) +#else +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE)) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ + defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ + + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__: UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__: UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__: UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) +#else +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST)) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ + +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__: UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__: UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ + /** * @} */ @@ -706,8 +800,8 @@ typedef struct * @{ */ /* Initialization and de-initialization functions ****************************/ -#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime); +#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ /** @@ -718,12 +812,10 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe * @brief Extended UART Interrupt handling function * @{ */ - -/* IO operation functions ***************************************************/ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +/* IO operation functions ***************************************************/ #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) -void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ /** * @} @@ -749,16 +841,17 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); /** * @} - */ + */ +/* Private functions ---------------------------------------------------------*/ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c index a5fb466f4b..e61bde7704 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c @@ -2,115 +2,117 @@ ****************************************************************************** * @file stm32f0xx_hal_usart.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief USART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter + * Peripheral (USART). * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions - * + Peripheral State and Errors functions - @verbatim + * + Peripheral State and Error functions + * + @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] - The USART HAL driver can be used as follows: - - (#) Declare a USART_HandleTypeDef handle structure. - (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit ()API: - (##) Enable the USARTx interface clock. - (##) USART pins configuration: + The USART HAL driver can be used as follows: + + (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart). + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) USART pins configuration: (+++) Enable the clock for the USART GPIOs. (+++) Configure these USART pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), - HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): + (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), + HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): (+++) Configure the USARTx interrupt priority. (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() - HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): + (++) USART interrupts handling: + -@@- The specific USART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. + (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() + HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle. + (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the husart Init structure. + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode (Receiver/Transmitter) in the husart handle Init structure. - (#) Initialize the USART registers by calling the HAL_USART_Init() API: - (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_USART_MspInit(&husart) API. + (#) Initialize the USART registers by calling the HAL_USART_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_USART_MspInit(&husart) API. + + (#) Three operation modes are available within this driver : - -@@- The specific USART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. - - (#) Three operation modes are available within this driver : - *** Polling mode IO operation *** ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_USART_Transmit() + [..] + (+) Send an amount of data in blocking mode using HAL_USART_Transmit() (+) Receive an amount of data in blocking mode using HAL_USART_Receive() - - *** Interrupt mode IO operation *** + + *** Interrupt mode IO operation *** =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() - (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can + [..] + (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() + (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_USART_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() - (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback - (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxCpltCallback - (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can + (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() + (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback + (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxCpltCallback + (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_USART_ErrorCallback - - *** DMA mode IO operation *** + + *** DMA mode IO operation *** ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() - (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() + (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_USART_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() - (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback - (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxCpltCallback - (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can + (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() + (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback + (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxCpltCallback + (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_USART_ErrorCallback - (+) Pause the DMA Transfer using HAL_USART_DMAPause() - (+) Resume the DMA Transfer using HAL_USART_DMAResume() - (+) Stop the DMA Transfer using HAL_USART_DMAStop() - + (+) Pause the DMA Transfer using HAL_USART_DMAPause() + (+) Resume the DMA Transfer using HAL_USART_DMAResume() + (+) Stop the DMA Transfer using HAL_USART_DMAStop() + *** USART HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in USART HAL driver. - - (+) __HAL_USART_ENABLE: Enable the USART peripheral - (+) __HAL_USART_DISABLE: Disable the USART peripheral + + (+) __HAL_USART_ENABLE: Enable the USART peripheral + (+) __HAL_USART_DISABLE: Disable the USART peripheral (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt - - [..] + + [..] (@) You can refer to the USART HAL driver header file for more useful macros @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -134,7 +136,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -144,29 +146,31 @@ * @{ */ -/** @defgroup USART USART HAL module driver +/** @defgroup USART USART * @brief HAL USART Synchronous module driver * @{ */ + #ifdef HAL_USART_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup USART_Private_Constants USART Private Constants +/** @defgroup USART_Private_Constants USART Private Constants * @{ */ -#define DUMMY_DATA ((uint16_t) 0xFFFF) -#define TEACK_REACK_TIMEOUT ((uint32_t) 1000) +#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ +#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */ #define USART_TXDMA_TIMEOUTVALUE 22000 #define USART_TIMEOUT_VALUE 22000 -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE)) -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ - USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ + USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ /** * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup USART_Private_Functions USART Private Functions @@ -176,7 +180,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void USART_DMAError(DMA_HandleTypeDef *hdma); +static void USART_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); @@ -188,56 +192,65 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); * @} */ -/* Exported functions ---------------------------------------------------------*/ - +/* Exported functions --------------------------------------------------------*/ /** @defgroup USART_Exported_Functions USART Exported Functions * @{ */ -/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim - ============================================================================== +@verbatim + =============================================================================== ##### Initialization and Configuration functions ##### - ============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to initialize the USART + This subsection provides a set of functions allowing to initialize the USART in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + (+) For the asynchronous mode only these parameters can be configured: (++) Baud Rate - (++) Word Length + (++) Word Length (++) Stop Bit (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits) - or by the M1 and M0 bits (7-bit, 8-bit or 9-bit), - the possible USART frame formats are as listed in the following table: - +---------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |-----------|-----------|---------------------------------------| - | 0 | 0 | | SB | 8-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7-bit data | PB | STB | | - |-----------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8-bit data | PB | STB | | - +---------------------------------------------------------------+ - | M1M0 bits | PCE bit | USART frame | - |-----------------------|---------------------------------------| - | 10 | 0 | | SB | 7-bit data | STB | | - |-----------|-----------|---------------------------------------| - | 10 | 1 | | SB | 6-bit data | PB | STB | | - +---------------------------------------------------------------+ + According to device capability (support or not of 7-bit word length), + frame length is either defined by the M bit (8-bits or 9-bits) + or by the M1 and M0 bits (7-bit, 8-bit or 9-bit). + Possible USART frame formats are as listed in the following table: + (+++) Table 1. USART frame format. + (+++) +-----------------------------------------------------------------------+ + (+++) | M bit | PCE bit | USART frame | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 0 | 0 | | SB | 8-bit data | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 1 | 0 | | SB | 9-bit data | STB | | + (+++) |-------------------|-----------|---------------------------------------| + (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | | + (+++) +-----------------------------------------------------------------------+ + (+++) | M1 bit | M0 bit | PCE bit | USART frame | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | | + (+++) |---------|---------|-----------|---------------------------------------| + (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + (+++) +-----------------------------------------------------------------------+ (++) USART polarity (++) USART phase (++) USART LastBit (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -245,9 +258,9 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); */ /** - * @brief Initializes the USART mode according to the specified - * parameters in the USART_InitTypeDef and create the associated handle . - * @param husart: usart handle + * @brief Initializes the USART mode according to the specified + * parameters in the USART_InitTypeDef and initialize the associated handle. + * @param husart: USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) @@ -257,43 +270,46 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_USART_INSTANCE(husart->Instance)); - + if(husart->State == HAL_USART_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + husart->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_USART_MspInit(husart); } - + husart->State = HAL_USART_STATE_BUSY; - + /* Disable the Peripheral */ __HAL_USART_DISABLE(husart); - + /* Set the Usart Communication parameters */ if (USART_SetConfig(husart) == HAL_ERROR) { return HAL_ERROR; } - - /* In Synchronous mode, the following bits must be kept cleared: + + /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ husart->Instance->CR2 &= ~USART_CR2_LINEN; husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); - - /* Enable the Peripharal */ + + /* Enable the Peripheral */ __HAL_USART_ENABLE(husart); - + /* TEACK and/or REACK to check before moving husart->State to Ready */ return (USART_CheckIdleState(husart)); } /** - * @brief DeInitializes the USART peripheral - * @param husart: usart handle + * @brief DeInitialize the USART peripheral. + * @param husart: USART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) @@ -303,307 +319,305 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_USART_INSTANCE(husart->Instance)); - + husart->State = HAL_USART_STATE_BUSY; - + husart->Instance->CR1 = 0x0; husart->Instance->CR2 = 0x0; husart->Instance->CR3 = 0x0; - + /* DeInit the low level hardware */ HAL_USART_MspDeInit(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_RESET; - + /* Process Unlock */ __HAL_UNLOCK(husart); - + return HAL_OK; } /** - * @brief USART MSP Init - * @param husart: usart handle + * @brief Initialize the USART MSP. + * @param husart: USART handle. * @retval None */ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspInit can be implemented in the user file - */ + */ } /** - * @brief USART MSP DeInit - * @param husart: usart handle + * @brief DeInitialize the USART MSP. + * @param husart: USART handle. * @retval None */ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_USART_MspDeInit can be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART synchronous +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART synchronous data transfers. - - [..] - The USART supports master mode only: it cannot receive or send data related to an input + + [..] The USART supports master mode only: it cannot receive or send data related to an input clock (SCLK is always an output). (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) Non Blocking mode: The communication is performed using Interrupts + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode APIs are : (++) HAL_USART_Transmit()in simplex mode (++) HAL_USART_Receive() in full duplex receive only - (++) HAL_USART_TransmitReceive() in full duplex mode - - (#) Non Blocking mode APIs with Interrupt are : + (++) HAL_USART_TransmitReceive() in full duplex mode + + (#) No-Blocking mode APIs with Interrupt are : (++) HAL_USART_Transmit_IT()in simplex mode (++) HAL_USART_Receive_IT() in full duplex receive only (++) HAL_USART_TransmitReceive_IT()in full duplex mode (++) HAL_USART_IRQHandler() - (#) Non Blocking mode functions with DMA are : + (#) No-Blocking mode APIs with DMA are : (++) HAL_USART_Transmit_DMA()in simplex mode (++) HAL_USART_Receive_DMA() in full duplex receive only (++) HAL_USART_TransmitReceive_DMA() in full duplex mode (++) HAL_USART_DMAPause() (++) HAL_USART_DMAResume() (++) HAL_USART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + + (#) A set of Transfer Complete Callbacks are provided in No-Blocking mode: (++) HAL_USART_TxCpltCallback() (++) HAL_USART_RxCpltCallback() (++) HAL_USART_TxHalfCpltCallback() (++) HAL_USART_RxHalfCpltCallback() (++) HAL_USART_ErrorCallback() (++) HAL_USART_TxRxCpltCallback() - + @endverbatim * @{ */ /** - * @brief Simplex Send an amount of data in blocking mode - * @param husart: USART handle - * @param pTxData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout : Timeout duration + * @brief Simplex send an amount of data in blocking mode. + * @param husart: USART handle. + * @param pTxData: Pointer to data buffer. + * @param Size: Amount of data to be sent. + * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp=0; - + uint16_t* tmp=0; + if(husart->State == HAL_USART_STATE_READY) - { - if((pTxData == NULL) || (Size == 0)) + { + if((pTxData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - + husart->TxXferSize = Size; husart->TxXferCount = Size; - + /* Check the remaining data to be sent */ while(husart->TxXferCount > 0) { husart->TxXferCount--; if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; } - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) pTxData; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); pTxData += 2; } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); - } + husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF); + } } - + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; } - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in blocking mode - * To receive synchronous data, dummy data are simultaneously transmitted - * @param husart: USART handle - * @param pRxData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout : Timeout duration + * @brief Receive an amount of data in blocking mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @param husart: USART handle. + * @param pRxData: Pointer to data buffer. + * @param Size: Amount of data to be received. + * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) -{ +{ uint16_t* tmp=0; - uint16_t uhMask; - + uint16_t uhMask; + if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - - husart->RxXferSize = Size; + + husart->RxXferSize = Size; husart->RxXferCount = Size; /* Computation of USART mask to apply to RDR register */ - __HAL_USART_MASK_COMPUTATION(husart); + USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; - + /* as long as data have to be received */ while(husart->RxXferCount > 0) { husart->RxXferCount--; - - /* Wait until TC flag is set to send dummy byte in order to generate the + + /* Wait until TC flag is set to send dummy byte in order to generate the * clock for the slave to send data. - * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value * can be written for all the cases. */ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FF); - - /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; } - - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); + + /* Wait for RXNE Flag */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) pRxData ; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + pRxData +=2; } else { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - } + *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + } } - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Full-Duplex Send and Receive an amount of data in blocking mode - * @param husart: USART handle - * @param pTxData: pointer to TX data buffer - * @param pRxData: pointer to RX data buffer - * @param Size: amount of data to be sent (same amount to be received) - * @param Timeout : Timeout duration + * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @param husart: USART handle. + * @param pTxData: pointer to TX data buffer. + * @param pRxData: pointer to RX data buffer. + * @param Size: amount of data to be sent (same amount to be received). + * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp=0; - uint16_t uhMask; - + uint16_t uhMask; + if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(husart); - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - + husart->RxXferSize = Size; husart->TxXferSize = Size; husart->TxXferCount = Size; husart->RxXferCount = Size; - + /* Computation of USART mask to apply to RDR register */ - __HAL_USART_MASK_COMPUTATION(husart); + USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; /* Check the remain data to be sent */ while(husart->TxXferCount > 0) { husart->TxXferCount--; - husart->RxXferCount--; - - /* Wait until TC flag is set to send data */ + husart->RxXferCount--; + + /* Wait until TC flag is set to send data */ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; + { + return HAL_TIMEOUT; } - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) pTxData; husart->Instance->TDR = (*tmp & uhMask); @@ -611,404 +625,412 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t } else { - husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); - } - + husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask); + } + /* Wait for RXNE Flag */ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + { return HAL_TIMEOUT; } - - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) pRxData ; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - pRxData +=2; + pRxData +=2; } else { - *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - } + *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + } } - + husart->State = HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Send an amount of data in interrupt mode - * @param husart: USART handle - * @param pTxData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in interrupt mode. + * @param husart: USART handle. + * @param pTxData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) -{ +{ if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->pTxBuffPtr = pTxData; husart->TxXferSize = Size; husart->TxXferCount = Size; - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - - /* The USART Error Interrupts: (Frame error, noise error, overrun error) + + /* The USART Error Interrupts: (Frame error, noise error, overrun error) are not managed by the USART Transmit Process to avoid the overrun interrupt when the usart mode is configured for transmit and receive "USART_MODE_TX_RX" - to benefit for the frame error and noise interrupts the usart mode should be + to benefit for the frame error and noise interrupts the usart mode should be configured only for transmit "USART_MODE_TX" */ - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the USART Transmit Data Register Empty Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Receive an amount of data in blocking mode - * To receive synchronous data, dummy data are simultaneously transmitted - * @param husart: usart handle - * @param pRxData: pointer to data buffer - * @param Size: amount of data to be received + * @brief Receive an amount of data in blocking mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @param husart: USART handle. + * @param pRxData: pointer to data buffer. + * @param Size: amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(husart); - + husart->pRxBuffPtr = pRxData; husart->RxXferSize = Size; husart->RxXferCount = Size; - - __HAL_USART_MASK_COMPUTATION(husart); + + USART_MASK_COMPUTATION(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - + /* Enable the USART Parity Error Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_PE); - + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); - + /* Enable the USART Data Register not empty Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Send dummy byte in order to generate the clock for the Slave to send the next data */ if(husart->Init.WordLength == USART_WORDLENGTH_9B) { - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FF); - } + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FF); + } else { - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF); + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); } - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Full-Duplex Send and Receive an amount of data in interrupt mode - * @param husart: USART handle - * @param pTxData: pointer to TX data buffer - * @param pRxData: pointer to RX data buffer - * @param Size: amount of data to be sent (same amount to be received) + * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @param husart: USART handle. + * @param pTxData: pointer to TX data buffer. + * @param pRxData: pointer to RX data buffer. + * @param Size: amount of data to be sent (same amount to be received). * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { + if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(husart); - + husart->pRxBuffPtr = pRxData; husart->RxXferSize = Size; husart->RxXferCount = Size; husart->pTxBuffPtr = pTxData; husart->TxXferSize = Size; husart->TxXferCount = Size; - + /* Computation of USART mask to apply to RDR register */ - __HAL_USART_MASK_COMPUTATION(husart); - + USART_MASK_COMPUTATION(husart); + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; - + /* Enable the USART Data Register not empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); - + __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); + /* Enable the USART Parity Error Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_PE); - + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_ENABLE_IT(husart, USART_IT_ERR); - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + /* Enable the USART Transmit Data Register Empty Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); - + return HAL_OK; } else { - return HAL_BUSY; - } + return HAL_BUSY; + } + } /** - * @brief Send an amount of data in DMA mode - * @param husart: USART handle - * @param pTxData: pointer to data buffer - * @param Size: amount of data to be sent + * @brief Send an amount of data in DMA mode. + * @param husart: USART handle. + * @param pTxData: pointer to data buffer. + * @param Size: amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) { uint32_t *tmp=0; - + if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } /* Process Locked */ - __HAL_LOCK(husart); - + __HAL_LOCK(husart); + husart->pTxBuffPtr = pTxData; husart->TxXferSize = Size; husart->TxXferCount = Size; - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - + /* Set the USART DMA transfer complete callback */ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - + /* Set the USART DMA Half transfer complete callback */ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - + /* Set the DMA error callback */ husart->hdmatx->XferErrorCallback = USART_DMAError; /* Enable the USART transmit DMA channel */ tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); - + + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ husart->Instance->CR3 |= USART_CR3_DMAT; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Full-Duplex Receive an amount of data in non-blocking mode - * @param husart: USART handle - * @param pRxData: pointer to data buffer - * @param Size: amount of data to be received - * @note When the USART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) + * @brief Receive an amount of data in DMA mode. + * @param husart: USART handle. + * @param pRxData: pointer to data buffer. + * @param Size: amount of data to be received. + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @retval HAL status - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { - uint32_t *tmp=0; - + uint32_t *tmp; + if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(husart); - + husart->pRxBuffPtr = pRxData; husart->RxXferSize = Size; husart->pTxBuffPtr = pRxData; husart->TxXferSize = Size; - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - + /* Set the USART DMA Rx transfer complete callback */ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - + /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + /* Set the USART DMA Rx transfer error callback */ husart->hdmarx->XferErrorCallback = USART_DMAError; - + /* Enable the USART receive DMA channel */ tmp = (uint32_t*)&pRxData; HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); - + /* Enable the USART transmit DMA channel: the transmit channel is used in order - to generate in the non-blocking mode the clock to the slave device, + to generate in the non-blocking mode the clock to the slave device, this mode isn't a simplex receive mode but a full-duplex receive mode */ tmp = (uint32_t*)&pRxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ husart->Instance->CR3 |= USART_CR3_DMAR; - + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ husart->Instance->CR3 |= USART_CR3_DMAT; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode - * @param husart: usart handle - * @param pTxData: pointer to TX data buffer - * @param pRxData: pointer to RX data buffer - * @param Size: amount of data to be received/sent + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @param husart: USART handle. + * @param pTxData: pointer to TX data buffer. + * @param pRxData: pointer to RX data buffer. + * @param Size: amount of data to be received/sent. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t *tmp=0; - + uint32_t *tmp; + if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(husart); - + husart->pRxBuffPtr = pRxData; husart->RxXferSize = Size; husart->pTxBuffPtr = pTxData; husart->TxXferSize = Size; - + husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; - + /* Set the USART DMA Rx transfer complete callback */ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - + /* Set the USART DMA Half transfer complete callback */ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; /* Set the USART DMA Tx transfer complete callback */ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - + /* Set the USART DMA Half transfer complete callback */ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; /* Set the USART DMA Tx transfer error callback */ husart->hdmatx->XferErrorCallback = USART_DMAError; - + /* Set the USART DMA Rx transfer error callback */ husart->hdmarx->XferErrorCallback = USART_DMAError; - + /* Enable the USART receive DMA channel */ tmp = (uint32_t*)&pRxData; HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size); - + /* Enable the USART transmit DMA channel */ tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ husart->Instance->CR3 |= USART_CR3_DMAR; - + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ husart->Instance->CR3 |= USART_CR3_DMAT; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } - + /** - * @brief Pauses the DMA Transfer. - * @param husart: USART handle - * @retval None + * @brief Pause the DMA Transfer. + * @param husart: USART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) { @@ -1036,13 +1058,13 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) /* Process Unlocked */ __HAL_UNLOCK(husart); - return HAL_OK; + return HAL_OK; } /** - * @brief Resumes the DMA Transfer. - * @param husart: USART handle - * @retval None + * @brief Resume the DMA Transfer. + * @param husart: USART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) { @@ -1056,24 +1078,24 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) } else if(husart->State == HAL_USART_STATE_BUSY_RX) { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + /* Enable the USART DMA Rx request */ husart->Instance->CR3 |= USART_CR3_DMAR; } else if(husart->State == HAL_USART_STATE_BUSY_TX_RX) { + /* Clear the Overrun flag before resumming the Rx transfer*/ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + /* Enable the USART DMA Rx request before the DMA Tx request */ husart->Instance->CR3 |= USART_CR3_DMAR; + /* Enable the USART DMA Tx request */ husart->Instance->CR3 |= USART_CR3_DMAT; } - /* If the USART peripheral is still not enabled, enable it */ - if ((husart->Instance->CR1 & USART_CR1_UE) == 0) - { - /* Enable USART peripheral */ - __HAL_USART_ENABLE(husart); - } - /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1081,91 +1103,90 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) } /** - * @brief Stops the DMA Transfer. - * @param husart: USART handle - * @retval None + * @brief Stop the DMA Transfer. + * @param husart: USART handle. + * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) { - /* Process Locked */ - __HAL_LOCK(husart); + /* The Lock is not implemented on this API to allow the user application + to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / + HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback (): + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is + generated if the DMA transfer interruption occurs at the middle or at the end of the stream + and the corresponding call back is executed. + */ /* Disable the USART Tx/Rx DMA requests */ husart->Instance->CR3 &= ~USART_CR3_DMAT; husart->Instance->CR3 &= ~USART_CR3_DMAR; - /* Abort the USART DMA tx Channel */ + /* Abort the USART DMA tx channel */ if(husart->hdmatx != NULL) { HAL_DMA_Abort(husart->hdmatx); } - /* Abort the USART DMA rx Channel */ + /* Abort the USART DMA rx channel */ if(husart->hdmarx != NULL) { HAL_DMA_Abort(husart->hdmarx); } - /* Disable USART peripheral */ - __HAL_USART_DISABLE(husart); - husart->State = HAL_USART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_OK; -} - +} + /** - * @brief This function handles USART interrupt request. - * @param husart: USART handle + * @brief Handle USART interrupt request. + * @param husart: USART handle. * @retval None */ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { - - /* USART parity error interrupt occured ------------------------------------*/ + + /* USART parity error interrupt occurred ------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_IT_PE); + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); husart->ErrorCode |= HAL_USART_ERROR_PE; /* Set the USART state ready to be able to start again the process */ husart->State = HAL_USART_STATE_READY; } - - /* USART frame error interrupt occured -------------------------------------*/ + + /* USART frame error interrupt occurred -------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_IT_FE); + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); husart->ErrorCode |= HAL_USART_ERROR_FE; /* Set the USART state ready to be able to start again the process */ husart->State = HAL_USART_STATE_READY; } - - /* USART noise error interrupt occured -------------------------------------*/ + + /* USART noise error interrupt occurred -------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_IT_NE); + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); husart->ErrorCode |= HAL_USART_ERROR_NE; /* Set the USART state ready to be able to start again the process */ husart->State = HAL_USART_STATE_READY; } - - /* USART Over-Run interrupt occured ----------------------------------------*/ + + /* USART Over-Run interrupt occurred ----------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) - { - __HAL_USART_CLEAR_IT(husart, USART_IT_ORE); + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); husart->ErrorCode |= HAL_USART_ERROR_ORE; /* Set the USART state ready to be able to start again the process */ husart->State = HAL_USART_STATE_READY; } - + /* Call USART Error Call back function if need be --------------------------*/ if(husart->ErrorCode != HAL_USART_ERROR_NONE) { HAL_USART_ErrorCallback(husart); - } - + } + /* USART in mode Receiver --------------------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET)) { @@ -1178,10 +1199,10 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) USART_TransmitReceive_IT(husart); } } - + /* USART in mode Transmitter -----------------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET)) - { + { if(husart->State == HAL_USART_STATE_BUSY_TX) { USART_Transmit_IT(husart); @@ -1191,55 +1212,54 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) USART_TransmitReceive_IT(husart); } } - + /* USART in mode Transmitter (transmission end) -----------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET)) { USART_EndTransmit_IT(husart); - } + } } - /** - * @brief Tx Transfer completed callbacks - * @param husart: usart handle + * @brief Tx Transfer completed callback. + * @param husart: USART handle. * @retval None */ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_TxCpltCallback can be implemented in the user file - */ + the HAL_USART_TxCpltCallback can be implemented in the user file. + */ } /** - * @brief Tx Half Transfer completed callbacks. + * @brief Tx Half Transfer completed callback. * @param husart: USART handle * @retval None */ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) { /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_TxHalfCpltCallback can be implemented in the user file - */ + the HAL_USART_TxHalfCpltCallback can be implemented in the user file. + */ } /** - * @brief Rx Transfer completed callbacks. - * @param husart: USART handle + * @brief Rx Transfer completed callback. + * @param husart: USART handle. * @retval None */ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) { /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_RxCpltCallback can be implemented in the user file + the HAL_USART_RxCpltCallback can be implemented in the user file. */ } /** - * @brief Rx Half Transfer completed callbacks - * @param husart: usart handle + * @brief Rx Half Transfer completed callback. + * @param husart: USART handle. * @retval None */ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) @@ -1250,8 +1270,8 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) } /** - * @brief Tx/Rx Transfers completed callback for the non-blocking process - * @param husart: usart handle + * @brief Tx/Rx Transfers completed callback for the non-blocking process. + * @param husart: USART handle * @retval None */ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) @@ -1262,42 +1282,43 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) } /** - * @brief USART error callbacks - * @param husart: usart handle + * @brief USART error callback. + * @param husart: USART handle. * @retval None */ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) { /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_ErrorCallback can be implemented in the user file - */ + the HAL_USART_ErrorCallback can be implemented in the user file. + */ } /** * @} */ -/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief USART control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== +/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions + * @brief USART Peripheral State and Error functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== [..] - This subsection provides a set of functions allowing to control the USART. - (+) HAL_USART_GetState() API can be helpful to check in run-time the state of the USART peripheral. - (+) USART_SetConfig() API is used to set the USART communication parameters. - (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization - + This subsection provides functions allowing to : + (+) Return the USART handle state + (+) Return the USART handle error code + @endverbatim * @{ */ + /** - * @brief return the USART state - * @param husart: USART handle - * @retval HAL state + * @brief Return the USART handle state. + * @param husart : pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle state */ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) { @@ -1305,10 +1326,10 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) } /** - * @brief Return the USART error code + * @brief Return the USART error code. * @param husart : pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART. - * @retval USART Error Code + * the configuration information for the specified USART. + * @retval USART handle Error Code */ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) { @@ -1323,154 +1344,180 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) * @} */ -/** @defgroup USART_Private_Functions USART Private Functions - * @brief USART Private functions +/** @defgroup USART_Private_Functions USART Private Functions + * @brief USART Private functions + * +@verbatim + [..] + This subsection provides a set of functions allowing to control the USART. + (+) USART_SetConfig() API is used to set the USART communication parameters. + (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization + +@endverbatim * @{ */ /** - * @brief Configure the USART peripheral - * @param husart: USART handle - * @retval None + * @brief Configure the USART peripheral. + * @param husart: USART handle. + * @retval HAL status */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) { uint32_t tmpreg = 0x0; USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; HAL_StatusTypeDef ret = HAL_OK; - + uint16_t brrtemp = 0x0000; + uint16_t usartdiv = 0x0000; + /* Check the parameters */ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); - assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); assert_param(IS_USART_PARITY(husart->Init.Parity)); assert_param(IS_USART_MODE(husart->Init.Mode)); - + /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE and RE bits and configure - * the USART Word Length, Parity and Mode: - * set the M bits according to husart->Init.WordLength value + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value * set PCE and PS bits according to husart->Init.Parity value - * set TE and RE bits according to husart->Init.Mode value */ - tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode; + * set TE and RE bits according to husart->Init.Mode value + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - + /*---------------------------- USART CR2 Configuration ---------------------*/ /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value * set LBCL bit according to husart->Init.CLKLastBit value * set STOP[13:12] bits according to husart->Init.StopBits value */ - tmpreg = (uint32_t)(USART_CLOCK_ENABLED); + tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits); MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); - /*-------------------------- USART CR3 Configuration -----------------------*/ + /*-------------------------- USART CR3 Configuration -----------------------*/ /* no CR3 register configuration */ /*-------------------------- USART BRR Configuration -----------------------*/ - __HAL_USART_GETCLOCKSOURCE(husart, clocksource); + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + USART_GETCLOCKSOURCE(husart, clocksource); switch (clocksource) { - case USART_CLOCKSOURCE_PCLK1: - husart->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / husart->Init.BaudRate); + case USART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate); break; - case USART_CLOCKSOURCE_HSI: - husart->Instance->BRR = (uint16_t)(HSI_VALUE / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_SYSCLK: - husart->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_LSE: - husart->Instance->BRR = (uint16_t)(LSE_VALUE / husart->Init.BaudRate); - break; case USART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - return ret; + brrtemp = usartdiv & 0xFFF0; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); + husart->Instance->BRR = brrtemp; + + return ret; } /** - * @brief Check the USART Idle State - * @param husart: USART handle + * @brief Check the USART Idle State. + * @param husart: USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) { /* Initialize the USART ErrorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; - - /* Check if the Transmitter is enabled */ - if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + + /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices). + Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature. + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) + if (IS_UART_WAKEUP_INSTANCE(husart->Instance)) { - /* Wait until TEACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) - { - husart->State= HAL_USART_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK) - { - husart->State= HAL_USART_STATE_TIMEOUT; - return HAL_TIMEOUT; + /* Check if the Transmitter is enabled */ + if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } } } - +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */ + /* Initialize the USART state*/ - husart->State= HAL_USART_STATE_READY; - + husart->State= HAL_USART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(husart); - - return HAL_OK; + + return HAL_OK; } + /** - * @brief This function handles USART Communication Timeout. - * @param husart: USART handle + * @brief Handle USART Communication Timeout. + * @param husart: USART handle. * @param Flag: specifies the USART flag to check. - * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @param Status: the Flag status (SET or RESET). + * @param Timeout: timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - + /* Wait until flag is set */ if(Status == RESET) - { + { while(__HAL_USART_GET_FLAG(husart, Flag) == RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); __HAL_USART_DISABLE_IT(husart, USART_IT_PE); __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - + husart->State= HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_TIMEOUT; } } @@ -1483,69 +1530,66 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); __HAL_USART_DISABLE_IT(husart, USART_IT_PE); __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - + husart->State= HAL_USART_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(husart); - + return HAL_TIMEOUT; } } } } - return HAL_OK; + return HAL_OK; } /** - * @brief DMA USART transmit process complete callback - * @param hdma : DMA handle + * @brief DMA USART transmit process complete callback. + * @param hdma: DMA handle * @retval None */ -static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - husart->TxXferCount = 0; - - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Wait for USART TC Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TXDMA_TIMEOUTVALUE) != HAL_OK) + /* DMA Normal mode */ + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + { + husart->TxXferCount = 0; + + if(husart->State == HAL_USART_STATE_BUSY_TX) { - /* Timeout Occured */ - husart->State = HAL_USART_STATE_TIMEOUT; - HAL_USART_ErrorCallback(husart); - } - else - { - /* No Timeout */ - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ husart->Instance->CR3 &= ~(USART_CR3_DMAT); - husart->State= HAL_USART_STATE_READY; + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } } - /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + /* DMA Circular mode */ else { - husart->State= HAL_USART_STATE_BUSY_RX; - HAL_USART_TxCpltCallback(husart); -} + if(husart->State == HAL_USART_STATE_BUSY_TX) + { + HAL_USART_TxCpltCallback(husart); + } + } } /** - * @brief DMA USART transmit process half complete callback - * @param hdma : DMA handle + * @brief DMA USART transmit process half complete callback. + * @param hdma : DMA handle. * @retval None */ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1556,46 +1600,71 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA USART receive process complete callback - * @param hdma : DMA handle + * @brief DMA USART receive process complete callback. + * @param hdma: DMA handle. * @retval None */ -static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - husart->RxXferCount = 0; - - /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit - in USART CR3 register */ - husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); - /* similarly, disable the DMA TX transfer that was started to provide the - clock to the slave device */ - husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + /* DMA Normal mode */ + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + { + husart->RxXferCount = 0; + + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + HAL_USART_RxCpltCallback(husart); + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { + HAL_USART_TxRxCpltCallback(husart); + } + husart->State= HAL_USART_STATE_READY; + } + /* DMA circular mode */ + else + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + HAL_USART_RxCpltCallback(husart); + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { + HAL_USART_TxRxCpltCallback(husart); + } + } - husart->State= HAL_USART_STATE_READY; - - HAL_USART_RxCpltCallback(husart); } /** - * @brief DMA USART receive process half complete callback - * @param hdma : DMA handle + * @brief DMA USART receive process half complete callback. + * @param hdma : DMA handle. * @retval None */ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - HAL_USART_RxHalfCpltCallback(husart); + HAL_USART_RxHalfCpltCallback(husart); } /** - * @brief DMA USART communication error callback - * @param hdma : DMA handle + * @brief DMA USART communication error callback. + * @param hdma: DMA handle. * @retval None */ -static void USART_DMAError(DMA_HandleTypeDef *hdma) +static void USART_DMAError(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; @@ -1603,146 +1672,147 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) husart->TxXferCount = 0; husart->ErrorCode |= HAL_USART_ERROR_DMA; husart->State= HAL_USART_STATE_READY; - + HAL_USART_ErrorCallback(husart); } /** - * @brief Simplex Send an amount of data in non-blocking mode. - * Function called under interruption only, once - * interruptions have been enabled by HAL_USART_Transmit_IT() - * @param husart: USART handle - * @retval HAL status + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). * @note The USART errors are not managed to avoid the overrun error. + * @param husart: USART handle. + * @retval HAL status */ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) { uint16_t* tmp=0; - if (husart->State == HAL_USART_STATE_BUSY_TX) + if(husart->State == HAL_USART_STATE_BUSY_TX) { - - if(husart->TxXferCount == 0) + + if(husart->TxXferCount == 0) { /* Disable the USART Transmit Complete Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - - /* Enable the USART Transmit Complete Interrupt */ + + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - + return HAL_OK; } else { - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); + husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); husart->pTxBuffPtr += 2; } else - { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); - } + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + } husart->TxXferCount--; - + return HAL_OK; } } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Wraps up transmission in non blocking mode. + * @brief Wraps up transmission in non-blocking mode. * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) { - /* Disable the USART Transmit Complete Interrupt */ + /* Disable the USART Transmit Complete Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TC); - + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - + husart->State = HAL_USART_STATE_READY; - + HAL_USART_TxCpltCallback(husart); - + return HAL_OK; } /** - * @brief Simplex Receive an amount of data in non-blocking mode. - * Function called under interruption only, once - * interruptions have been enabled by HAL_USART_Receive_IT() - * @param husart: USART handle + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @param husart: USART handle * @retval HAL status */ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) { uint16_t* tmp=0; - uint16_t uhMask = husart->Mask; + uint16_t uhMask = husart->Mask; if(husart->State == HAL_USART_STATE_BUSY_RX) - { - - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - tmp = (uint16_t*) husart->pRxBuffPtr ; + { + + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + tmp = (uint16_t*) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); husart->pRxBuffPtr += 2; - } + } else { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); } + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ - husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF); - + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + if(--husart->RxXferCount == 0) - { - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + { + __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); /* Disable the USART Parity Error Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - + husart->State = HAL_USART_STATE_READY; - + HAL_USART_RxCpltCallback(husart); - + return HAL_OK; } - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * Function called under interruption only, once - * interruptions have been enabled by HAL_USART_TransmitReceive_IT() - * @param husart: USART handle + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_TransmitReceive_IT(). + * @param husart: USART handle. * @retval HAL status */ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { uint16_t* tmp=0; - uint16_t uhMask = husart->Mask; + uint16_t uhMask = husart->Mask; if(husart->State == HAL_USART_STATE_BUSY_TX_RX) { @@ -1751,18 +1821,18 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) { - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { tmp = (uint16_t*) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & uhMask); husart->pTxBuffPtr += 2; - } + } else { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask); + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask); } husart->TxXferCount--; - + /* Check the latest data transmitted */ if(husart->TxXferCount == 0) { @@ -1770,48 +1840,48 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) } } } - + if(husart->RxXferCount != 0x00) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) { - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - tmp = (uint16_t*) husart->pRxBuffPtr ; + tmp = (uint16_t*) husart->pRxBuffPtr; *tmp = (uint16_t)(husart->Instance->RDR & uhMask); husart->pRxBuffPtr += 2; } else - { - *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + { + *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); } husart->RxXferCount--; } } - + /* Check the latest data received */ if(husart->RxXferCount == 0) { __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - + /* Disable the USART Parity Error Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - + husart->State = HAL_USART_STATE_READY; - + HAL_USART_TxRxCpltCallback(husart); - + return HAL_OK; } - + return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h index cabbd30263..5a30afb258 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_usart.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of USART HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -52,28 +52,27 @@ /** @addtogroup USART * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup USART_Exported_Types USART Exported Types * @{ - */ + */ - -/** - * @brief USART Init Structure definition - */ +/** + * @brief USART Init Structure definition + */ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */ + Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USARTEx_Word_Length */ + This parameter can be a value of @ref USARTEx_Word_Length. */ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ + This parameter can be a value of @ref USART_Stop_Bits. */ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_Parity @@ -81,37 +80,37 @@ typedef struct at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ - + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ + This parameter can be a value of @ref USART_Mode. */ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ + This parameter can be a value of @ref USART_Clock_Polarity. */ uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ + This parameter can be a value of @ref USART_Clock_Phase. */ uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ + This parameter can be a value of @ref USART_Last_Bit. */ }USART_InitTypeDef; -/** - * @brief HAL State structures definition - */ +/** + * @brief HAL USART State structures definition + */ typedef enum { - HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ - HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_USART_STATE_ERROR = 0x04 /*!< Error */ + HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04 /*!< Error */ }HAL_USART_StateTypeDef; -/** +/** * @brief USART clock sources definitions */ typedef enum @@ -120,43 +119,43 @@ typedef enum USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */ USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */ - USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */ }USART_ClockSourceTypeDef; -/** - * @brief USART handle Structure definition - */ + +/** + * @brief USART handle Structure definition + */ typedef struct { USART_TypeDef *Instance; /*!< USART registers base address */ - + USART_InitTypeDef Init; /*!< USART communication parameters */ - + uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ - + uint16_t TxXferSize; /*!< USART Tx Transfer size */ - + uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ - + uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ - + uint16_t RxXferSize; /*!< USART Rx Transfer size */ - + uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ - + uint16_t Mask; /*!< USART Rx RDR register mask */ - + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ - + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - HAL_USART_StateTypeDef State; /*!< USART communication state */ - - __IO uint32_t ErrorCode; /*!< USART Error code - This parameter can be a value of @ref USART_Error */ - + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + + __IO uint32_t ErrorCode; /*!< USART Error code */ + }USART_HandleTypeDef; /** @@ -164,7 +163,7 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_Exported_Constants USART Exported constants +/** @defgroup USART_Exported_Constants USART Exported Constants * @{ */ @@ -187,64 +186,53 @@ typedef struct #define USART_STOPBITS_1 ((uint32_t)0x0000) #define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) #define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ - ((STOPBITS) == USART_STOPBITS_1_5) || \ - ((STOPBITS) == USART_STOPBITS_2)) /** * @} */ /** @defgroup USART_Parity USART Parity * @{ - */ -#define USART_PARITY_NONE ((uint32_t)0x0000) -#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ - ((PARITY) == USART_PARITY_EVEN) || \ - ((PARITY) == USART_PARITY_ODD)) -/** - * @} - */ - -/** @defgroup USART_Mode USART Mode - * @{ - */ -#define USART_MODE_RX ((uint32_t)USART_CR1_RE) -#define USART_MODE_TX ((uint32_t)USART_CR1_TE) -#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && ((MODE) != (uint32_t)0x00)) + */ +#define USART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */ +#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */ +#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */ /** * @} */ - -/** @defgroup USART_Clock USART Clock + +/** @defgroup USART_Mode USART Mode * @{ - */ -#define USART_CLOCK_DISABLED ((uint32_t)0x0000) -#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \ - ((CLOCK) == USART_CLOCK_ENABLED)) + */ +#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */ +#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */ +#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */ /** * @} - */ + */ + +/** @defgroup USART_Clock USART Clock + * @{ + */ +#define USART_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< USART clock disable */ +#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */ +/** + * @} + */ /** @defgroup USART_Clock_Polarity USART Clock Polarity * @{ */ -#define USART_POLARITY_LOW ((uint32_t)0x0000) -#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) -#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH)) +#define USART_POLARITY_LOW ((uint32_t)0x00000000) /*!< USART Clock signal is steady Low */ +#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */ /** * @} - */ + */ /** @defgroup USART_Clock_Phase USART Clock Phase * @{ */ -#define USART_PHASE_1EDGE ((uint32_t)0x0000) -#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) -#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE)) +#define USART_PHASE_1EDGE ((uint32_t)0x00000000) /*!< USART frame phase on first clock transition */ +#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */ /** * @} */ @@ -252,34 +240,8 @@ typedef struct /** @defgroup USART_Last_Bit USART Last Bit * @{ */ -#define USART_LASTBIT_DISABLE ((uint32_t)0x0000) -#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ - ((LASTBIT) == USART_LASTBIT_ENABLE)) -/** - * @} - */ - - -/** @defgroup USART_Flags USART Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#define USART_FLAG_REACK ((uint32_t)0x00400000) -#define USART_FLAG_TEACK ((uint32_t)0x00200000) -#define USART_FLAG_BUSY ((uint32_t)0x00010000) -#define USART_FLAG_CTS ((uint32_t)0x00000400) -#define USART_FLAG_CTSIF ((uint32_t)0x00000200) -#define USART_FLAG_LBDF ((uint32_t)0x00000100) -#define USART_FLAG_TXE ((uint32_t)0x00000080) -#define USART_FLAG_TC ((uint32_t)0x00000040) -#define USART_FLAG_RXNE ((uint32_t)0x00000020) -#define USART_FLAG_IDLE ((uint32_t)0x00000010) -#define USART_FLAG_ORE ((uint32_t)0x00000008) -#define USART_FLAG_NE ((uint32_t)0x00000004) -#define USART_FLAG_FE ((uint32_t)0x00000002) -#define USART_FLAG_PE ((uint32_t)0x00000001) +#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< USART frame last data bit clock pulse not output to SCLK pin */ +#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */ /** * @} */ @@ -294,17 +256,16 @@ typedef struct * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE ((uint16_t)0x0300) -#define USART_IT_NE ((uint16_t)0x0200) -#define USART_IT_FE ((uint16_t)0x0100) +#define USART_IT_PE ((uint16_t)0x0028) /*!< USART parity error interruption */ +#define USART_IT_TXE ((uint16_t)0x0727) /*!< USART transmit data register empty interruption */ +#define USART_IT_TC ((uint16_t)0x0626) /*!< USART transmission complete interruption */ +#define USART_IT_RXNE ((uint16_t)0x0525) /*!< USART read data register not empty interruption */ +#define USART_IT_IDLE ((uint16_t)0x0424) /*!< USART idle interruption */ +#define USART_IT_ERR ((uint16_t)0x0060) /*!< USART error interruption */ +#define USART_IT_ORE ((uint16_t)0x0300) /*!< USART overrun error interruption */ +#define USART_IT_NE ((uint16_t)0x0200) /*!< USART noise error interruption */ +#define USART_IT_FE ((uint16_t)0x0100) /*!< USART frame error interruption */ /** * @} */ @@ -312,32 +273,21 @@ typedef struct /** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags * @{ */ -#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ +#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ /** * @} - */ + */ -/** @defgroup USART_Request_Parameters USART Request Parameters +/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask * @{ */ -#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ -#define IS_USART_REQUEST_PARAMETER(PARAM) (((PARAM) == USART_RXDATA_FLUSH_REQUEST) || \ - ((PARAM) == USART_TXDATA_FLUSH_REQUEST)) -/** - * @} - */ - -/** @defgroup USART_Interruption_Mask USART interruptions flag mask - * @{ - */ -#define USART_IT_MASK ((uint16_t)0x001F) +#define USART_IT_MASK ((uint16_t)0x001F) /*!< USART interruptions flags mask */ /** * @} */ @@ -345,27 +295,26 @@ typedef struct /** * @} */ - -/* Exported macro ------------------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ /** @defgroup USART_Exported_Macros USART Exported Macros * @{ - */ + */ - -/** @brief Reset USART handle state +/** @brief Reset USART handle state. * @param __HANDLE__: USART handle. * @retval None */ -#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) -/** @brief Checks whether the specified USART flag is set or not. +/** @brief Check whether the specified USART flag is set or not. * @param __HANDLE__: specifies the USART Handle * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg USART_FLAG_REACK: Receive enable ackowledge flag - * @arg USART_FLAG_TEACK: Transmit enable ackowledge flag - * @arg USART_FLAG_BUSY: Busy flag - * @arg USART_FLAG_CTS: CTS Change flag + * @arg USART_FLAG_REACK: Receive enable acknowledge flag + * @arg USART_FLAG_TEACK: Transmit enable acknowledge flag + * @arg USART_FLAG_BUSY: Busy flag + * @arg USART_FLAG_CTS: CTS Change flag * @arg USART_FLAG_TXE: Transmit data register empty flag * @arg USART_FLAG_TC: Transmission Complete flag * @arg USART_FLAG_RXNE: Receive data register not empty flag @@ -378,9 +327,57 @@ typedef struct */ #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) +/** @brief Clear the specified USART pending flag. + * @param __HANDLE__: specifies the USART Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg USART_CLEAR_PEF + * @arg USART_CLEAR_FEF + * @arg USART_CLEAR_NEF + * @arg USART_CLEAR_OREF + * @arg USART_CLEAR_IDLEF + * @arg USART_CLEAR_TCF + * @arg USART_CLEAR_CTSF + * @arg USART_CLEAR_RTOF + * @arg USART_CLEAR_EOBF + * @arg USART_CLEAR_CMF + * @arg USART_CLEAR_WUF + * @retval None + */ +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) -/** @brief Enables the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle +/** @brief Clear the USART PE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) + +/** @brief Clear the USART FE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) + +/** @brief Clear the USART NE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) + +/** @brief Clear the USART ORE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) + +/** @brief Clear the USART IDLE pending flag. + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) + +/** @brief Enable the specified USART interrupt. + * @param __HANDLE__: specifies the USART Handle. * @param __INTERRUPT__: specifies the USART interrupt source to enable. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt @@ -395,7 +392,7 @@ typedef struct ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) -/** @brief Disables the specified USART interrupt. +/** @brief Disable the specified USART interrupt. * @param __HANDLE__: specifies the USART Handle. * @param __INTERRUPT__: specifies the USART interrupt source to disable. * This parameter can be one of the following values: @@ -411,9 +408,9 @@ typedef struct ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) - -/** @brief Checks whether the specified USART interrupt has occurred or not. - * @param __HANDLE__: specifies the USART Handle + +/** @brief Check whether the specified USART interrupt has occurred or not. + * @param __HANDLE__: specifies the USART Handle. * @param __IT__: specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt @@ -426,9 +423,9 @@ typedef struct * @arg USART_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) +#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) -/** @brief Checks whether the specified USART interrupt source is enabled. +/** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__: specifies the USART Handle. * @param __IT__: specifies the USART interrupt source to check. * This parameter can be one of the following values: @@ -447,48 +444,60 @@ typedef struct (((uint16_t)(__IT__)) & USART_IT_MASK))) -/** @brief Clears the specified USART ISR flag, in setting the proper ICR register flag. +/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__: specifies the USART Handle. * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt + * to clear the corresponding interrupt. * This parameter can be one of the following values: - * @arg USART_CLEAR_PEF: Parity Error Clear Flag - * @arg USART_CLEAR_FEF: Framing Error Clear Flag - * @arg USART_CLEAR_NEF: Noise detected Clear Flag - * @arg USART_CLEAR_OREF: OverRun Error Clear Flag - * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag - * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag - * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag + * @arg USART_CLEAR_PEF: Parity Error Clear Flag + * @arg USART_CLEAR_FEF: Framing Error Clear Flag + * @arg USART_CLEAR_NEF: Noise detected Clear Flag + * @arg USART_CLEAR_OREF: OverRun Error Clear Flag + * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag + * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag + * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag * @retval None */ -#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) +#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific USART request flag. * @param __HANDLE__: specifies the USART Handle. - * @param __REQ__: specifies the request flag to set + * @param __REQ__: specifies the request flag to set. * This parameter can be one of the following values: - * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request - * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request + * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request + * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request * * @retval None - */ -#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + */ +#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) -/** @brief Enable USART +/** @brief Enable the USART one bit sample method. + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the USART one bit sample method. + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + +/** @brief Enable USART. * @param __HANDLE__: specifies the USART Handle. * @retval None - */ -#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + */ +#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) -/** @brief Disable USART +/** @brief Disable USART. * @param __HANDLE__: specifies the USART Handle. * @retval None - */ -#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + */ +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) /** * @} - */ + */ /* Private macros --------------------------------------------------------*/ /** @defgroup USART_Private_Macros USART Private Macros @@ -496,45 +505,99 @@ typedef struct */ /** @brief Check USART Baud rate - * @param BAUDRATE: Baudrate specified by the user + * @param __BAUDRATE__: Baudrate specified by the user. * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval Test result (TRUE or FALSE) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval Test result (TRUE or FALSE). */ -#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001) +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001) + +/** + * @brief Ensure that USART frame number of stop bits is valid. + * @param __STOPBITS__: USART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \ + ((__STOPBITS__) == USART_STOPBITS_1_5) || \ + ((__STOPBITS__) == USART_STOPBITS_2)) + +/** + * @brief Ensure that USART frame parity is valid. + * @param __PARITY__: USART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ + ((__PARITY__) == USART_PARITY_EVEN) || \ + ((__PARITY__) == USART_PARITY_ODD)) + +/** + * @brief Ensure that USART communication mode is valid. + * @param __MODE__: USART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00)) + +/** + * @brief Ensure that USART clock state is valid. + * @param __CLOCK__: USART clock state. + * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) + */ +#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ + ((__CLOCK__) == USART_CLOCK_ENABLE)) + +/** + * @brief Ensure that USART frame polarity is valid. + * @param __CPOL__: USART frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) + +/** + * @brief Ensure that USART frame phase is valid. + * @param __CPHA__: USART frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) + +/** + * @brief Ensure that USART frame last bit clock pulse setting is valid. + * @param __LASTBIT__: USART frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == USART_LASTBIT_ENABLE)) + /** * @} */ - -/* Include USART HAL Extension module */ -#include "stm32f0xx_hal_usart_ex.h" - -/* Exported functions --------------------------------------------------------*/ +/* Include USART HAL Extension module */ +#include "stm32f0xx_hal_usart_ex.h" + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup USART_Exported_Functions USART Exported Functions * @{ */ - -/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ -/* Initialization and de-initialization functions ******************************/ +/* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); void HAL_USART_MspInit(USART_HandleTypeDef *husart); void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); -HAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart); /** * @} */ -/** @addtogroup USART_Exported_Functions_Group2 IO operation functions +/** @addtogroup USART_Exported_Functions_Group2 IO operation functions * @{ */ -/* IO operation functions *******************************************************/ +/* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); @@ -561,25 +624,25 @@ void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); /* Peripheral Control functions ***********************************************/ -/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions +/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); - -/** - * @} - */ +uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); /** * @} */ - + /** * @} - */ + */ + +/** + * @} + */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h index 9f244f9298..1ea4219107 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention - * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -50,7 +50,7 @@ * @{ */ -/** @defgroup USARTEx USARTEx Extended HAL module driver +/** @defgroup USARTEx USARTEx * @{ */ @@ -59,48 +59,104 @@ /** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants * @{ */ - + /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_7B) || \ - ((LENGTH) == USART_WORDLENGTH_8B) || \ - ((LENGTH) == USART_WORDLENGTH_9B)) +#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ #else -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \ - ((LENGTH) == USART_WORDLENGTH_9B)) +#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */ #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ /** * @} */ - + +/** @defgroup USART_Request_Parameters USARTEx Request Parameters + * @{ + */ +#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#else +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ /** * @} - */ - -/* Exported macro ------------------------------------------------------------*/ + */ +/** @defgroup USART_Flags USART Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define USART_FLAG_REACK ((uint32_t)0x00400000) /*!< USART receive enable acknowledge flag */ +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ +#define USART_FLAG_TEACK ((uint32_t)0x00200000) /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY ((uint32_t)0x00010000) /*!< USART busy flag */ +#define USART_FLAG_CTS ((uint32_t)0x00000400) /*!< USART clear to send flag */ +#define USART_FLAG_CTSIF ((uint32_t)0x00000200) /*!< USART clear to send interrupt flag */ +#define USART_FLAG_TXE ((uint32_t)0x00000080) /*!< USART transmit data register empty */ +#define USART_FLAG_TC ((uint32_t)0x00000040) /*!< USART transmission complete */ +#define USART_FLAG_RXNE ((uint32_t)0x00000020) /*!< USART read data register not empty */ +#define USART_FLAG_IDLE ((uint32_t)0x00000010) /*!< USART idle flag */ +#define USART_FLAG_ORE ((uint32_t)0x00000008) /*!< USART overrun error */ +#define USART_FLAG_NE ((uint32_t)0x00000004) /*!< USART noise error */ +#define USART_FLAG_FE ((uint32_t)0x00000002) /*!< USART frame error */ +#define USART_FLAG_PE ((uint32_t)0x00000001) /*!< USART parity error */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ /** @defgroup USARTEx_Exported_Macros USARTEx Exported Macros * @{ */ +/** @brief Flush the USART Data registers. + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \ + } while(0) +#else +#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \ + } while(0) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Macros USARTEx Private Macros + * @{ + */ + /** @brief Reports the USART clock source. * @param __HANDLE__: specifies the USART Handle * @param __CLOCKSOURCE__ : output variable * @retval the USART clocking source, written in __CLOCKSOURCE__. */ #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) -#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ switch(__HAL_RCC_GET_USART1_SOURCE()) \ { \ @@ -124,7 +180,7 @@ #elif defined (STM32F030x8) || defined (STM32F070x6) || \ defined (STM32F042x6) || defined (STM32F048xx) || \ defined (STM32F051x8) || defined (STM32F058xx) -#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -155,9 +211,9 @@ { \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0) #elif defined (STM32F070xB) -#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -196,9 +252,9 @@ { \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0) #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) -#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -254,9 +310,9 @@ { \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0) #elif defined(STM32F091xC) || defined (STM32F098xx) -#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -347,7 +403,7 @@ } \ } while(0) #elif defined(STM32F030xC) -#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -394,23 +450,23 @@ { \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ - } while(0) + } while(0) #endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */ - -/** @brief Reports the USART mask to apply to retrieve the received data + +/** @brief Compute the USART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. - * If PCE = 1, the parity bit is not included in the data extracted + * @note If PCE = 1, the parity bit is not included in the data extracted * by the reception API(). * This masking operation is not carried out in the case of - * DMA transfers. - * @param __HANDLE__: specifies the USART Handle - * @retval none - */ + * DMA transfers. + * @param __HANDLE__: specifies the USART Handle. + * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. + */ #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) -#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \ +#define USART_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ { \ @@ -445,9 +501,9 @@ (__HANDLE__)->Mask = 0x003F ; \ } \ } \ -} while(0) +} while(0) #else -#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \ +#define USART_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ { \ @@ -471,28 +527,56 @@ (__HANDLE__)->Mask = 0x007F ; \ } \ } \ -} while(0) +} while(0) #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ + + +/** + * @brief Ensure that USART frame length is valid. + * @param __LENGTH__: USART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \ + defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) +#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ + ((__LENGTH__) == USART_WORDLENGTH_8B) || \ + ((__LENGTH__) == USART_WORDLENGTH_9B)) +#else +#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \ + ((__LENGTH__) == USART_WORDLENGTH_9B)) +#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \ + defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ + defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */ + +/** + * @brief Ensure that USART request parameter is valid. + * @param __PARAM__: USART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) +#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) +#else +#define IS_USART_REQUEST_PARAMETER(__PARAM__) ((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) +#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */ + /** * @} */ /* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions ****************************/ -/* I/O operation functions ***************************************************/ -/* Peripheral Control functions **********************************************/ -/* Peripheral State functions ************************************************/ /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c index 946ecad9f4..c41db51b69 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c @@ -2,22 +2,21 @@ ****************************************************************************** * @file stm32f0xx_hal_wwdg.c * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State functions - * @verbatim ============================================================================== ##### WWDG specific features ##### ============================================================================== [..] Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the Counter (T[6;0] downcounter) + time period, unless the program refreshes the counter (T[6;0] downcounter) before reaching 0x3F value (i.e. a reset is generated when the counter value rolls over from 0x40 to 0x3F). @@ -25,8 +24,8 @@ before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. (+) Once enabled the WWDG cannot be disabled except by a system reset. - (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - reset occurs. + (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has + occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)). (+) The WWDG counter input clock is derived from the APB clock divided by a programmable prescaler. (+) WWDG clock (Hz) = PCLK / (4096 * Prescaler) @@ -35,13 +34,12 @@ (+) WWDG Counter refresh is allowed between the following limits : (++) min time (mS) = 1000 * (Counter-Window) / WWDG clock (++) max time (mS) = 1000 * (Counter-0x40) / WWDG clock - (+) Min-max timeout value @48 MHz(PCLK): ~85,3us / ~5,46 ms ##### How to use this driver ##### =============================================================================== [..] - (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE(). + (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). (+) Set the WWDG prescaler, refresh window and counter value using HAL_WWDG_Init() function. (+) Start the WWDG using HAL_WWDG_Start() function. @@ -49,11 +47,11 @@ a value greater than 0x40 to prevent generating an immediate reset. (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is generated when the counter reaches 0x40, and then start the WWDG using - HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can - add his own code by customization of function pointer HAL_WWDG_WakeupCallback + HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback() is executed and user can + add his own code by customization of function pointer HAL_WWDG_WakeupCallback(). Once enabled, EWI interrupt cannot be disabled except by a system reset. - (+) Then the application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset, using + (+) The application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset using HAL_WWDG_Refresh() function. This operation must occur only when the counter is lower than the refresh window value already programmed. @@ -63,15 +61,16 @@ Below the list of most used macros in WWDG HAL driver. (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral + (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt + (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags - (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt @endverbatim ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -105,7 +104,7 @@ * @{ */ -/** @defgroup WWDG WWDG HAL module driver +/** @defgroup WWDG WWDG * @brief WWDG HAL module driver. * @{ */ @@ -133,18 +132,18 @@ [..] This section provides functions allowing to: (+) Initialize the WWDG according to the specified parameters - in the WWDG_InitTypeDef and create the associated handle - (+) DeInitialize the WWDG peripheral - (+) Initialize the WWDG MSP - (+) DeInitialize the WWDG MSP + in the WWDG_InitTypeDef and initialize the associated handle. + (+) DeInitialize the WWDG peripheral. + (+) Initialize the WWDG MSP. + (+) DeInitialize the WWDG MSP. @endverbatim * @{ */ /** - * @brief Initializes the WWDG according to the specified - * parameters in the WWDG_InitTypeDef and creates the associated handle. + * @brief Initialize the WWDG according to the specified + * parameters in the WWDG_InitTypeDef and initialize the associated handle. * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL status @@ -165,6 +164,9 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) if(hwwdg->State == HAL_WWDG_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hwwdg->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); } @@ -186,13 +188,19 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) } /** - * @brief DeInitializes the WWDG peripheral. + * @brief DeInitialize the WWDG peripheral. * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) { + /* Check the WWDG handle allocation */ + if(hwwdg == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); @@ -222,27 +230,27 @@ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) } /** - * @brief Initializes the WWDG MSP. + * @brief Initialize the WWDG MSP. * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval None */ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_WWDG_MspInit could be implemented in the user file */ } /** - * @brief DeInitializes the WWDG MSP. + * @brief DeInitialize the WWDG MSP. * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval None */ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_WWDG_MspDeInit could be implemented in the user file */ } @@ -262,14 +270,14 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) This section provides functions allowing to: (+) Start the WWDG. (+) Refresh the WWDG. - (+) Handle WWDG interrupt request. + (+) Handle WWDG interrupt request and associated function callback. @endverbatim * @{ */ /** - * @brief Starts the WWDG. + * @brief Start the WWDG. * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL status @@ -296,7 +304,7 @@ HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) } /** - * @brief Starts the WWDG with interrupt enabled. + * @brief Start the WWDG with interrupt enabled. * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL status @@ -320,7 +328,7 @@ HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) } /** - * @brief Refreshes the WWDG. + * @brief Refresh the WWDG. * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @param Counter: value of counter to put in WWDG counter @@ -351,7 +359,7 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) } /** - * @brief Handles WWDG interrupt request. + * @brief Handle WWDG interrupt request. * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations * or data logging must be performed before the actual reset is generated. * The EWI interrupt is enabled when calling HAL_WWDG_Start_IT function. @@ -368,7 +376,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) /* Check if Early Wakeup Interrupt is enable */ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) { - /* Wheck if WWDG Early Wakeup Interrupt occurred */ + /* Check if WWDG Early Wakeup Interrupt occurred */ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) { /* Early Wakeup callback */ @@ -394,7 +402,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) */ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_WWDG_WakeupCallback could be implemented in the user file */ } @@ -419,7 +427,7 @@ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) */ /** - * @brief Returns the WWDG state. + * @brief Return the WWDG handle state. * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL state diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h index 155f5448d5..2ad8cd8699 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_wwdg.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -102,7 +102,6 @@ typedef struct __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */ } WWDG_HandleTypeDef; - /** * @} */ @@ -137,56 +136,52 @@ typedef struct #define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ #define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ #define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup WWDG_Private_Macros WWDG Private Macros + * @{ + */ #define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ ((__PRESCALER__) == WWDG_PRESCALER_2) || \ ((__PRESCALER__) == WWDG_PRESCALER_4) || \ ((__PRESCALER__) == WWDG_PRESCALER_8)) -/** - * @} - */ -/** @defgroup WWDG_Window WWDG Window - * @{ - */ #define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) -/** - * @} - */ -/** @defgroup WWDG_Counter WWDG Counter - * @{ - */ #define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) /** * @} */ -/** - * @} - */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros ------------------------------------------------------------*/ /** @defgroup WWDG_Exported_Macros WWDG Exported Macros * @{ */ -/** @brief Reset WWDG handle state +/** @brief Reset WWDG handle state. * @param __HANDLE__: WWDG handle * @retval None */ #define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET) /** - * @brief Enables the WWDG peripheral. + * @brief Enable the WWDG peripheral. * @param __HANDLE__: WWDG handle * @retval None */ #define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= WWDG_CR_WDGA) /** - * @brief Disables the WWDG peripheral. + * @brief Disable the WWDG peripheral. * @param __HANDLE__: WWDG handle * @note WARNING: This is a dummy macro for HAL code alignment. * Once enable, WWDG Peripheral cannot be disabled except by a system reset. @@ -195,7 +190,7 @@ typedef struct #define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */ /** - * @brief Enables the WWDG early wakeup interrupt. + * @brief Enable the WWDG early wakeup interrupt. * @param __HANDLE__: WWDG handle * @param __INTERRUPT__: specifies the interrupt to enable. * This parameter can be one of the following values: @@ -206,7 +201,7 @@ typedef struct #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CFR |= (__INTERRUPT__)) /** - * @brief Disables the WWDG early wakeup interrupt. + * @brief Disable the WWDG early wakeup interrupt. * @param __HANDLE__: WWDG handle * @param __INTERRUPT__: specifies the interrupt to disable. * This parameter can be one of the following values: @@ -218,7 +213,7 @@ typedef struct #define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */ /** - * @brief Gets the selected WWDG's it status. + * @brief Check whether the selected WWDG interrupt has occurred or not. * @param __HANDLE__: WWDG handle * @param __INTERRUPT__: specifies the it to check. * This parameter can be one of the following values: @@ -227,7 +222,7 @@ typedef struct */ #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) -/** @brief Clear the WWDG's interrupt pending bits +/** @brief Clear the WWDG interrupt pending bits. * bits to clear the selected interrupt pending bits. * @param __HANDLE__: WWDG handle * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @@ -237,7 +232,7 @@ typedef struct #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) /** - * @brief Gets the selected WWDG's flag status. + * @brief Check whether the specified WWDG flag is set or not. * @param __HANDLE__: WWDG handle * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: @@ -247,7 +242,7 @@ typedef struct #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** - * @brief Clears the WWDG's pending flags. + * @brief Clear the WWDG's pending flags. * @param __HANDLE__: WWDG handle * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: @@ -256,7 +251,7 @@ typedef struct */ #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) -/** @brief Checks if the specified WWDG interrupt source is enabled or disabled. +/** @brief Check whether the specified WWDG interrupt source is enabled or not. * @param __HANDLE__: WWDG Handle. * @param __INTERRUPT__: specifies the WWDG interrupt source to check. * This parameter can be one of the following values: @@ -283,8 +278,6 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); - /** * @} */ @@ -297,7 +290,7 @@ HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg); HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg); HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter); void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); - +void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); /** * @} */ @@ -307,7 +300,6 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); */ /* Peripheral State functions **************************************************/ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); - /** * @} */ @@ -331,4 +323,3 @@ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); #endif /* __STM32F0xx_HAL_WWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_MICRO/startup_stm32f303x8.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_MICRO/startup_stm32f303x8.S new file mode 100644 index 0000000000..53ac9e71bc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_MICRO/startup_stm32f303x8.S @@ -0,0 +1,342 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f303x8.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 12-Sept-2014 +;* Description : STM32F303x6/x8 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20003000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23 + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 and EXTI Line 25 + DCD USART2_IRQHandler ; USART2 and EXTI Line 26 + DCD USART3_IRQHandler ; USART3 and EXTI Line 28 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors + DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP2_IRQHandler ; COMP2 + DCD COMP4_6_IRQHandler ; COMP4 and COMP6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TSC_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN_TX_IRQHandler [WEAK] + EXPORT CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM6_DAC1_IRQHandler [WEAK] + EXPORT TIM7_DAC2_IRQHandler [WEAK] + EXPORT COMP2_IRQHandler [WEAK] + EXPORT COMP4_6_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TSC_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN_TX_IRQHandler +CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM6_DAC1_IRQHandler +TIM7_DAC2_IRQHandler +COMP2_IRQHandler +COMP4_6_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_MICRO/stm32f303x8.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_MICRO/stm32f303x8.sct new file mode 100644 index 0000000000..64a32c381d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_MICRO/stm32f303x8.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F303K8: 64KB FLASH (0x10000) + 12KB SRAM (0x3000) +LR_IROM1 0x08000000 0x10000 { ; load region size_region + + ER_IROM1 0x08000000 0x10000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x20000000+0x188) (0x3000-0x188) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_STD/startup_stm32f303x8.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_STD/startup_stm32f303x8.S new file mode 100644 index 0000000000..b878001b17 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_STD/startup_stm32f303x8.S @@ -0,0 +1,315 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f303x8.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 12-Sept-2014 +;* Description : STM32F303x6/x8 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20003000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23 + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 and EXTI Line 25 + DCD USART2_IRQHandler ; USART2 and EXTI Line 26 + DCD USART3_IRQHandler ; USART3 and EXTI Line 28 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors + DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP2_IRQHandler ; COMP2 + DCD COMP4_6_IRQHandler ; COMP4 and COMP6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_TSC_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN_TX_IRQHandler [WEAK] + EXPORT CAN_RX0_IRQHandler [WEAK] + EXPORT CAN_RX1_IRQHandler [WEAK] + EXPORT CAN_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM6_DAC1_IRQHandler [WEAK] + EXPORT TIM7_DAC2_IRQHandler [WEAK] + EXPORT COMP2_IRQHandler [WEAK] + EXPORT COMP4_6_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_TSC_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN_TX_IRQHandler +CAN_RX0_IRQHandler +CAN_RX1_IRQHandler +CAN_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM6_DAC1_IRQHandler +TIM7_DAC2_IRQHandler +COMP2_IRQHandler +COMP4_6_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_STD/stm32f303x8.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_STD/stm32f303x8.sct new file mode 100644 index 0000000000..64a32c381d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_STD/stm32f303x8.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F303K8: 64KB FLASH (0x10000) + 12KB SRAM (0x3000) +LR_IROM1 0x08000000 0x10000 { ; load region size_region + + ER_IROM1 0x08000000 0x10000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x20000000+0x188) (0x3000-0x188) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_GCC_ARM/STM32F303X8.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_GCC_ARM/STM32F303X8.ld new file mode 100644 index 0000000000..e1fb24442a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_GCC_ARM/STM32F303X8.ld @@ -0,0 +1,155 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K + CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 4K + RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 12K - 0x188 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_GCC_ARM/startup_stm32f303x8.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_GCC_ARM/startup_stm32f303x8.S new file mode 100644 index 0000000000..d31da878a3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_GCC_ARM/startup_stm32f303x8.S @@ -0,0 +1,409 @@ +/** + ****************************************************************************** + * @file startup_stm32f303x8.s + * @author MCD Application Team + * @version + * @date 12-Sept-2014 + * @brief STM32F303x6/STM32F303x8 devices vector table for + * Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2014 STMicroelectronics

      + * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main +/** + * Calling the crt0 'cold-start' entry point. There __libc_init_array is called + * and when existing hardware_init_hook() and software_init_hook() before + * starting main(). software_init_hook() is available and has to be called due + * to initializsation when using rtos. +*/ + bl _start + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TSC_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN_TX_IRQHandler + .word CAN_RX0_IRQHandler + .word CAN_RX1_IRQHandler + .word CAN_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word 0 + .word 0 + .word SPI1_IRQHandler + .word 0 + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_DAC1_IRQHandler + .word TIM7_DAC2_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word COMP2_IRQHandler + .word COMP4_6_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TSC_IRQHandler + .thumb_set EXTI2_TSC_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN_TX_IRQHandler + .thumb_set CAN_TX_IRQHandler,Default_Handler + + .weak CAN_RX0_IRQHandler + .thumb_set CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM6_DAC1_IRQHandler + .thumb_set TIM6_DAC1_IRQHandler,Default_Handler + + .weak TIM7_DAC2_IRQHandler + .thumb_set TIM7_DAC2_IRQHandler,Default_Handler + + .weak COMP2_IRQHandler + .thumb_set COMP2_IRQHandler,Default_Handler + + .weak COMP4_6_IRQHandler + .thumb_set COMP4_6_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_IAR/startup_stm32f303x8.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_IAR/startup_stm32f303x8.S new file mode 100644 index 0000000000..92e695fc3d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_IAR/startup_stm32f303x8.S @@ -0,0 +1,450 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f303x8.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 12-Sept-2014 +;* Description : STM32F303x6/STM32F303x8 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;*

      © COPYRIGHT(c) 2014 STMicroelectronics

      +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN_TX_IRQHandler ; CAN TX + DCD CAN_RX0_IRQHandler ; CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors + DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP2_IRQHandler ; COMP2 + DCD COMP4_6_IRQHandler ; COMP4 and COMP6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_TSC_IRQHandler + B EXTI2_TSC_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_TX_IRQHandler + B CAN_TX_IRQHandler + + PUBWEAK CAN_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_RX0_IRQHandler + B CAN_RX0_IRQHandler + + PUBWEAK CAN_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_RX1_IRQHandler + B CAN_RX1_IRQHandler + + PUBWEAK CAN_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_SCE_IRQHandler + B CAN_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM6_DAC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC1_IRQHandler + B TIM6_DAC1_IRQHandler + + PUBWEAK TIM7_DAC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_DAC2_IRQHandler + B TIM7_DAC2_IRQHandler + + PUBWEAK COMP2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP2_IRQHandler + B COMP2_IRQHandler + + PUBWEAK COMP4_6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP4_6_IRQHandler + B COMP4_6_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_IAR/stm32f303x8.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_IAR/stm32f303x8.icf new file mode 100644 index 0000000000..98af5cefcf --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/TOOLCHAIN_IAR/stm32f303x8.icf @@ -0,0 +1,35 @@ +/* [ROM = 64kb = 0x10000] */ +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x0800FFFF; + +define symbol __region_CCMRAM_start__ = 0x10000000; +define symbol __region_CCMRAM_end__ = 0x10000FFF; + +/* [RAM = 12kb = 0x3000] Vector table dynamic copy: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000187; /* No need to add 4 more bytes to be aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000188; +define symbol __region_RAM_end__ = 0x20002FFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define region CCMRAM_region = mem:[from __region_CCMRAM_start__ to __region_CCMRAM_end__]; + +/* Stack and Heap */ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __size_cstack__ = 0x600; +define symbol __size_heap__ = 0xC00; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/cmsis.h new file mode 100644 index 0000000000..8b9ba0fc38 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f3xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/cmsis_nvic.c new file mode 100644 index 0000000000..2da63fc9af --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/cmsis_nvic.h new file mode 100644 index 0000000000..eb09b74d89 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/cmsis_nvic.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F303RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to 0x193 +// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM +#define NVIC_NUM_VECTORS 101 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/hal_tick.c new file mode 100644 index 0000000000..e326cdcecd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/hal_tick.c @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/hal_tick.h new file mode 100644 index 0000000000..e8acd8c64b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f3xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __TIM2_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/stm32f303x8.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/stm32f303x8.h new file mode 100644 index 0000000000..4a41089bd2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/stm32f303x8.h @@ -0,0 +1,6265 @@ +/** + ****************************************************************************** + * @file stm32f303x8.h + * @author MCD Application Team + * @version $VERSION$ + * @date 12-Sept-2014 + * @brief CMSIS STM32F303x6/STM32F303x8 Devices Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f303x8 + * @{ + */ + +#ifndef __STM32F303x8_H +#define __STM32F303x8_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< STM32F303x6/STM32F303x8 devices do not provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F303x6/STM32F303x8 devices use 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F303x6/STM32F303x8 devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F303x6/STM32F303x8 device Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ + CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */ + CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */ + CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ + CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ + USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ + TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */ + TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */ + COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */ + COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */ + FPU_IRQn = 81 /*!< Floating point Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f3xx.h" /* STM32F3xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, 0x010 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1/3 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ +}EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, 0x18 */ + __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ + __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ + +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ +typedef struct +{ + __IO uint16_t RDP; /*!
      © COPYRIGHT(c) 2014 STMicroelectronics
      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f3xx + * @{ + */ + +#ifndef __STM32F3xx_H +#define __STM32F3xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \ + !defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \ + !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \ + !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \ + !defined (STM32F373xC) && !defined (STM32F378xx) + + /* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8, + STM32F301R6 and STM32F301R8 Devices */ + /* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8, + STM32F302R6 and STM32F302R8 Devices */ + /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB and STM32F302VC Devices */ + /* #define STM32F302xE */ /*!< STM32F302CE, STM32F302RE, and STM32F302VE Devices */ + #define STM32F303x8 /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8, + STM32F303R6 and STM32F303R8 Devices */ + /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */ + /* #define STM32F303xE */ /*!< STM32F303RE, STM32F303VE and STM32F303ZE Devices */ + /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC, + STM32F373V8, STM32F373VB and STM32F373VC Devices */ + /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */ + /* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */ + /* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */ + /* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */ + /* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */ + /* #define STM32F398xx */ /*!< STM32F398CE, STM32F398RE, STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.1.0 + */ +#define __STM32F3xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F3xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F3xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ + |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ + |(__CMSIS_DEVICE_HAL_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F301x8) + #include "stm32f301x8.h" +#elif defined(STM32F302x8) + #include "stm32f302x8.h" +#elif defined(STM32F302xC) + #include "stm32f302xc.h" +#elif defined(STM32F302xE) + #include "stm32f302xe.h" +#elif defined(STM32F303x8) + #include "stm32f303x8.h" +#elif defined(STM32F303xC) + #include "stm32f303xc.h" +#elif defined(STM32F303xE) + #include "stm32f303xe.h" +#elif defined(STM32F373xC) + #include "stm32f373xc.h" +#elif defined(STM32F334x8) + #include "stm32f334x8.h" +#elif defined(STM32F318xx) + #include "stm32f318xx.h" +#elif defined(STM32F328xx) + #include "stm32f328xx.h" +#elif defined(STM32F358xx) + #include "stm32f358xx.h" +#elif defined(STM32F378xx) + #include "stm32f378xx.h" +#elif defined(STM32F398xx) + #include "stm32f398xx.h" +#else + #error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +#if defined (USE_HAL_DRIVER) + #include "stm32f3xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F3xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/system_stm32f3xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/system_stm32f3xx.c new file mode 100644 index 0000000000..e1c77d52d7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/system_stm32f3xx.c @@ -0,0 +1,456 @@ +/** + ****************************************************************************** + * @file system_stm32f3xx.c + * @author MCD Application Team + * @version V2.1.0 + * @date 12-Sept-2014 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f3xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 8 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 36 | 32 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | NO | NO + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f3xx_system + * @{ + */ + +/** @addtogroup STM32F3xx_System_Private_Includes + * @{ + */ + +#include "stm32f3xx.h" +#include "hal_tick.h" + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (1) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock there is no need to + call the 2 first functions listed above, since SystemCoreClock variable is + updated automatically. + */ +uint32_t SystemCoreClock = 72000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes + * @{ + */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and the PLL configuration is reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR &= 0xF87FC00C; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + + /* Reset PREDIV1[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; + + /* Reset USARTSW[1:0], I2CSW and TIMs bits */ + RCC->CFGR3 &= (uint32_t)0xFF00FCCC; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 8000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + +#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + } + else + { + /* HSI oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; + } +#else + if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + } +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/system_stm32f3xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/system_stm32f3xx.h new file mode 100644 index 0000000000..d91ace096d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/system_stm32f3xx.h @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file system_stm32f3xx.h + * @author MCD Application Team + * @version V2.1.0 + * @date 12-Sept-2014 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f3xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F3XX_H +#define __SYSTEM_STM32F3XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F3xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F3xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F3XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/Release_Notes_stm32f4xx_hal.html b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/Release_Notes_stm32f4xx_hal.html index 42e71c45bf..cc0c80baa2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/Release_Notes_stm32f4xx_hal.html +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/Release_Notes_stm32f4xx_hal.html @@ -922,7 +922,41 @@ ul
      -

      Update History

      V1.3.2 / 26-June-2015

      +

      Update History

      V1.4.1 / 09-October-2015

      + +

      Main Changes

      + + + + + + +
      • HAL DSI update
        • Update TCCR register assigned value in HAL_DSI_ConfigHostTimeouts() function
        • Update WPCR register assigned value +in HAL_DSI_Init(), HAL_DSI_SetSlewRateAndDelayTuning(), +HAL_DSI_SetSlewRateAndDelayTuning(), HAL_DSI_SetLowPowerRXFilter() / +HAL_DSI_SetSDD(), HAL_DSI_SetLanePinsConfiguration(), +HAL_DSI_SetPHYTimings(), HAL_DSI_ForceTXStopMode(), +HAL_DSI_ForceRXLowPower(), HAL_DSI_ForceDataLanesInRX(), +HAL_DSI_SetPullDown() and HAL_DSI_SetContentionDetectionOff() functions
        • Update DSI_HS_PM_ENABLE define value
        • Implement +workaround for the hardware limitation: The time to activate the clock +between HS transmissions is not calculated correctly

      V1.4.0 / 14-August-2015

      + +

      Main Changes

      + + + + + + +
      • Add support of STM32F469xx, STM32F479xx, STM32F410Cx, STM32F410Rx and STM32F410Tx  devices
      • General updates to fix known defects and enhancements implementation
      • Add new HAL drivers for DSI and LPTIM peripherals
      • HAL ADC update
        • Rename ADC_CLOCKPRESCALER_PCLK_DIV2 define to ADC_CLOCK_SYNC_PCLK_DIV2
        • Rename ADC_CLOCKPRESCALER_PCLK_DIV4 define to ADC_CLOCK_SYNC_PCLK_DIV4
        • Rename ADC_CLOCKPRESCALER_PCLK_DIV6 define to ADC_CLOCK_SYNC_PCLK_DIV6
        • Rename ADC_CLOCKPRESCALER_PCLK_DIV8 define to ADC_CLOCK_SYNC_PCLK_DIV8
      • HAL CORTEX update
        • Add specific API for MPU management
          • add MPU_Region_InitTypeDef structure
          • add new function HAL_MPU_ConfigRegion()
      • HAL DMA update
        • Overall driver update for code optimization
          • add StreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef structure
          • add DMA_Base_Registers private structure
          • add static function DMA_CalcBaseAndBitshift()
          • update HAL_DMA_Init() function to use the new added static function
          • update HAL_DMA_DeInit() function to optimize clear flag operations
          • update HAL_DMA_Start_IT() function to optimize interrupts enable
          • update HAL_DMA_PollForTransfer() function to optimize check on flags
          • update HAL_DMA_IRQHandler() function to optimize interrupt flag management
      • HAL FLASH update
        • update HAL_FLASH_Program_IT() function by removing the pending flag clear
        • update HAL_FLASH_IRQHandler() function to improve erase operation procedure
        • update FLASH_WaitForLastOperation() function by checking on end of operation flag
      • HAL GPIO update
        • Rename GPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW
        • Rename GPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM
        • Rename GPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH
        • Rename GPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH
      • HAL I2S update
        • Move I2S_Clock_Source defines to extension file to properly add the support of STM32F410xx devices
      • HAL LTDC update
        • rename HAL_LTDC_LineEvenCallback() function to HAL_LTDC_LineEventCallback()
        • add new function HAL_LTDC_SetPitch()
        • add +new functions HAL_LTDC_StructInitFromVideoConfig() and +HAL_LTDC_StructInitFromAdaptedCommandConfig() applicable only to +STM32F469xx and STM32F479xx devices
      • HAL PWR update
        • move __HAL_PWR_VOLTAGESCALING_CONFIG() macro to extension file
        • move PWR_WAKEUP_PIN2 define to extension file
        • add PWR_WAKEUP_PIN3 define, applicable only to STM32F10xx devices
        • add +new functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() and +HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), applicable only to STM32F469xx and STM32F479xx devices
      • HAL RTC update
        • Update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on the WUTWF flag
      • HAL TIM update
        • add +new defines TIM_SYSTEMBREAKINPUT_HARDFAULT,  +TIM_SYSTEMBREAKINPUT_PVD and TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, +applicable only to STM32F410xx devices

      V1.3.2 / 26-June-2015

      Main Changes

      diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx_hal_conf.h index 7d4cec5f8b..689cf11847 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx_hal_conf.h @@ -101,7 +101,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx_hal_conf.h index 8f67be411c..98e3f379c0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx_hal_conf.h @@ -101,7 +101,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.s new file mode 100644 index 0000000000..196df1b811 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.s @@ -0,0 +1,449 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Version : V2.4.1 +;* Date : 09-October-2015 +;* Description : STM32F469x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20050000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +QUADSPI_IRQHandler +DSI_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_MICRO/stm32f469xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_MICRO/stm32f469xx.sct new file mode 100644 index 0000000000..cc685ff89c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_MICRO/stm32f469xx.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 2 MB FLASH (0x200000) + 320 KB SRAM (0x50000) +LR_IROM1 0x08000000 0x200000 { ; load region size_region + + ER_IROM1 0x08000000 0x200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1B4) (0x50000-0x1B4) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..4362e30478 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_STD/startup_stm32f469xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_STD/startup_stm32f469xx.s new file mode 100644 index 0000000000..01f2bbc1e3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_STD/startup_stm32f469xx.s @@ -0,0 +1,422 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Version : V2.4.1 +;* Date : 09-October-2015 +;* Description : STM32F469x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20050000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +QUADSPI_IRQHandler +DSI_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_STD/stm32f469xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_STD/stm32f469xx.sct new file mode 100644 index 0000000000..cc685ff89c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_STD/stm32f469xx.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 2 MB FLASH (0x200000) + 320 KB SRAM (0x50000) +LR_IROM1 0x08000000 0x200000 { ; load region size_region + + ER_IROM1 0x08000000 0x200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1B4) (0x50000-0x1B4) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..4362e30478 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_GCC_ARM/STM32F469XI.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_GCC_ARM/STM32F469XI.ld new file mode 100644 index 0000000000..9cdb87a990 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_GCC_ARM/STM32F469XI.ld @@ -0,0 +1,153 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2M + RAM (rwx) : ORIGIN = 0x200001B4, LENGTH = 320k - 0x1B4 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.s new file mode 100644 index 0000000000..1925d08b37 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.s @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file startup_stm32f469xx.s + * @author MCD Application Team + * @version V2.4.1 + * @date 09-October-2015 + * @brief STM32F469xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word DSI_IRQHandler /* DSI */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + + + + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_IAR/startup_stm32f469xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_IAR/startup_stm32f469xx.s new file mode 100644 index 0000000000..f0fc3e3f70 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_IAR/startup_stm32f469xx.s @@ -0,0 +1,704 @@ +;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Version : V2.4.1 +;* Date : 09-October-2015 +;* Description : STM32F469xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI Controller + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSI_IRQHandler + B DSI_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_IAR/stm32f469xx.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_IAR/stm32f469xx.icf new file mode 100644 index 0000000000..4c2aa1be12 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/TOOLCHAIN_IAR/stm32f469xx.icf @@ -0,0 +1,31 @@ +/* [ROM = 2mb = 0x200000] */ +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x081FFFFF; + +/* [RAM = 384kb = 0x60000] Vector table dynamic copy: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x200001B3; /* Aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x200001B4; +define symbol __region_RAM_end__ = 0x2004FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __size_cstack__ = 0x4000; +define symbol __size_heap__ = 0x8000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/cmsis.h new file mode 100644 index 0000000000..f0c2b2a907 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/cmsis_nvic.c new file mode 100644 index 0000000000..2da63fc9af --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/cmsis_nvic.h new file mode 100644 index 0000000000..4f2fbf9b5d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/cmsis_nvic.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F429ZI +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 93 vectors = 372 bytes from 0x40 to 0x1B3 +// Total: 109 vectors = 436 bytes (0x1B4) to be reserved in RAM +#define NVIC_NUM_VECTORS 109 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/hal_tick.c new file mode 100644 index 0000000000..7a7eeaeb44 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/hal_tick.c @@ -0,0 +1,124 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + if ( SystemCoreClock == 16000000 ) { + TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 1000000) - 1; // 1 s tick + } else { + TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 2 / 1000000) - 1; // 1 s tick + } + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/hal_tick.h new file mode 100644 index 0000000000..8e3519afb0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __TIM2_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f469xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f469xx.h new file mode 100644 index 0000000000..e37bf9a9dd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f469xx.h @@ -0,0 +1,10141 @@ +/** + ****************************************************************************** + * @file stm32f469xx.h + * @author MCD Application Team + * @version V2.4.1 + * @date 09-October-2015 + * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f469xx + * @{ + */ + +#ifndef __STM32F469xx_H +#define __STM32F469xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */ + DSI_IRQn = 92 /*!< DSI global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED9; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ + uint32_t RESERVED10; /*!< Reserved, 0x42C */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(160 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x20028000) /*!< SRAM2(32 KB) base address in the alias region */ +#define SRAM3_BASE ((uint32_t)0x20030000) /*!< SRAM3(128 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ +#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */ +#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) +#define DSI_BASE (APB2PERIPH_BASE + 0x6C00) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) + +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000) +#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) + +#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) +#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) +#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) +#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) +#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) +#define USB_OTG_HOST_BASE ((uint32_t )0x400) +#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) +#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) +#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) +#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) +#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) +#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define DSI ((DSI_TypeDef *)DSI_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!
      © COPYRIGHT(c) 2015 STMicroelectronics
      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F4) +#define STM32F4 +#endif /* STM32F4 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \ + !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \ + !defined (STM32F479xx) + /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ + /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */ + /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */ + /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */ + /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ + /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, + and STM32F446ZE Devices */ + #define STM32F469xx /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, + STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */ + /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG + and STM32F479NG Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.4.1 + */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F410Tx) + #include "stm32f410tx.h" +#elif defined(STM32F410Cx) + #include "stm32f410cx.h" +#elif defined(STM32F410Rx) + #include "stm32f410rx.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#elif defined(STM32F446xx) + #include "stm32f446xx.h" +#elif defined(STM32F469xx) + #include "stm32f469xx.h" +#elif defined(STM32F479xx) + #include "stm32f479xx.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000..cf0101d86c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/stm32f4xx_hal_conf.h @@ -0,0 +1,434 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf.h + * @author MCD Application Team + * @version V1.4.1 + * @date 09-October-2015 + * @brief HAL configuration template file. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CEC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DMA2D_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_PCCARD_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_DSI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_FMPI2C_MODULE_ENABLED +#define HAL_SPDIFRX_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 1 +#define DATA_CACHE_ENABLE 1 + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.c new file mode 100644 index 0000000000..d1f256ee26 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.c @@ -0,0 +1,658 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.4.1 + * @date 09-October-2015 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * This file configures the system clock as follows: + *-------------------------------------------------------------------------------------- + * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL + * | (external 8 MHz clock) | (external 8 MHz clock) + *-------------------------------------------------------------------------------------- + * SYSCLK(MHz) | 168 | 180 + *-------------------------------------------------------------------------------------- + * AHBCLK (MHz) | 168 | 180 + *-------------------------------------------------------------------------------------- + * APB1CLK (MHz) | 42 | 45 + *-------------------------------------------------------------------------------------- + * APB2CLK (MHz) | 84 | 90 + *-------------------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | YES | NO + *-------------------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" +#include "hal_tick.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) + #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/* Select the SYSCLOCK to start with (0=OFF, 1=ON) */ +#define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */ +#define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 168000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +void SystemClock_Config(void); +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 16000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SystemClock_Config(); + SystemCoreClockUpdate(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E0; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** System Clock Configuration +*/ +#if USE_SYSCLOCK_168 != 0 +/* + * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery + * and SYSCLK=168MHZ + */ +void SystemClock_Config(void) +{ + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + __PWR_CLK_ENABLE(); + + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 + |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); + +} + +#elif USE_SYSCLOCK_180 != 0 +/* + * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery + * and SYSCLK=180MHZ + */ +void SystemClock_Config(void) +{ + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + __PWR_CLK_ENABLE(); + + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 360; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + HAL_PWREx_ActivateOverDrive(); + + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 + |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); + +} +#endif + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + SystemClock_Config(); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.h new file mode 100644 index 0000000000..5be60e4334 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.h @@ -0,0 +1,123 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V2.4.1 + * @date 09-October-2015 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S new file mode 100644 index 0000000000..aa7d51ad14 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S @@ -0,0 +1,373 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct new file mode 100644 index 0000000000..c018724bf7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) +LR_IROM1 0x08000000 0x80000 { ; load region size_region + + ER_IROM1 0x08000000 0x80000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM + RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S new file mode 100644 index 0000000000..effaaf1e52 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S @@ -0,0 +1,346 @@ +;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct new file mode 100644 index 0000000000..c018724bf7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2014, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000) +LR_IROM1 0x08000000 0x80000 { ; load region size_region + + ER_IROM1 0x08000000 0x80000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM + RW_IRAM1 (0x20000000+0x198) (0x20000-0x198) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld new file mode 100644 index 0000000000..c028371d60 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld @@ -0,0 +1,153 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K + RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S new file mode 100644 index 0000000000..8950a21b6b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file startup_stm32f411xe.s + * @author MCD Application Team + * @version V2.3.0 + * @date 02-March-2015 + * @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_IAR/startup_stm32f411xe.S b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_IAR/startup_stm32f411xe.S new file mode 100644 index 0000000000..1b782c36dc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_IAR/startup_stm32f411xe.S @@ -0,0 +1,523 @@ +;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.1.0 +;* Date : 19-June-2014 +;* Description : STM32F411xExx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf new file mode 100644 index 0000000000..f481cdbf14 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf @@ -0,0 +1,31 @@ +/* [ROM = 512kb = 0x80000] */ +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x0807FFFF; + +/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x20000198; +define symbol __region_RAM_end__ = 0x2001FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +/*Heap 1/4 of ram and stack 1/8*/ +define symbol __size_cstack__ = 0x4000; +define symbol __size_heap__ = 0x8000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis.h new file mode 100644 index 0000000000..f0c2b2a907 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis_nvic.c new file mode 100644 index 0000000000..2da63fc9af --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis_nvic.h new file mode 100644 index 0000000000..a98d56f154 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/cmsis_nvic.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// STM32F411RE +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 86 vectors = 344 bytes from 0x40 to 0x197 +// Total: 102 vectors = 408 bytes (0x198) to be reserved in RAM +#define NVIC_NUM_VECTORS 102 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/hal_tick.c new file mode 100644 index 0000000000..bd400d4379 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/hal_tick.c @@ -0,0 +1,122 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Update the SystemCoreClock variable + SystemCoreClockUpdate(); + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 s tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimMasterHandle.Init.RepetitionCounter = 0; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/hal_tick.h new file mode 100644 index 0000000000..2e6f01b8a6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f4xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f411xe.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f411xe.h new file mode 100644 index 0000000000..9ba378ecc8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f411xe.h @@ -0,0 +1,4803 @@ +/** + ****************************************************************************** + * @file stm32f411xe.h + * @author MCD Application Team + * @version V2.3.0 + * @date 02-March-2015 + * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f401xe + * @{ + */ + +#ifndef __STM32F401xE_H +#define __STM32F401xE_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief __USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */ + uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */ + __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */ + uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} +USB_OTG_GlobalTypeDef; + + + +/** + * @brief __device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */ + __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */ + uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */ + __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */ + uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */ + uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */ + __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ + uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */ + uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ +} +USB_OTG_DeviceTypeDef; + + +/** + * @brief __IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} +USB_OTG_INEndpointTypeDef; + + +/** + * @brief __OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} +USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief __Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} +USB_OTG_HostTypeDef; + + +/** + * @brief __Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} +USB_OTG_HostChannelTypeDef; + + +/** + * @brief Peripheral_memory_map + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ +#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) + +#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) +#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) +#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) +#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) +#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) +#define USB_OTG_HOST_BASE ((uint32_t )0x400) +#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) +#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) +#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) +#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) +#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) +#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!
      © COPYRIGHT(c) 2015 STMicroelectronics
      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx + * @{ + */ + +#ifndef __STM32F4xx_H +#define __STM32F4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F4) +#define STM32F4 +#endif /* STM32F4 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \ + !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \ + !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx) + /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */ + /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */ + /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */ + /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ + /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */ + /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */ + /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, + STM32F439NI, STM32F429IG and STM32F429II Devices */ + /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, + STM32F439NI, STM32F439IG and STM32F439II Devices */ + /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */ + /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */ + #define STM32F411xE /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */ + /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, + and STM32F446ZE Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V2.3.0 + */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\ + |(__STM32F4xx_CMSIS_DEVICE_VERSION)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F405xx) + #include "stm32f405xx.h" +#elif defined(STM32F415xx) + #include "stm32f415xx.h" +#elif defined(STM32F407xx) + #include "stm32f407xx.h" +#elif defined(STM32F417xx) + #include "stm32f417xx.h" +#elif defined(STM32F427xx) + #include "stm32f427xx.h" +#elif defined(STM32F437xx) + #include "stm32f437xx.h" +#elif defined(STM32F429xx) + #include "stm32f429xx.h" +#elif defined(STM32F439xx) + #include "stm32f439xx.h" +#elif defined(STM32F401xC) + #include "stm32f401xc.h" +#elif defined(STM32F401xE) + #include "stm32f401xe.h" +#elif defined(STM32F411xE) + #include "stm32f411xe.h" +#elif defined(STM32F446xx) + #include "stm32f446xx.h" +#else + #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f4xx_hal_conf.h new file mode 100644 index 0000000000..54dbf8871d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/stm32f4xx_hal_conf.h @@ -0,0 +1,405 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf.h + * @author MCD Application Team + * @version V1.1.0 + * @date 26-December-2014 + * @brief HAL configuration file + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_PCCARD_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +/* #define HAL_SDRAM_MODULE_ENABLED */ +#define HAL_HASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 1 +#define DATA_CACHE_ENABLE 1 + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.c new file mode 100644 index 0000000000..fd3b198505 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.c @@ -0,0 +1,711 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.1.0 + * @date 19-June-2014 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 96 | 96 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 96 | 96 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 48 | 48 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 96 | 96 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | YES | YES + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2014 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" +#include "hal_tick.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) + #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (0) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 16000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E0; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384) + //RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) + //RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) + + RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 2 MHz (8 MHz / 4) + RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (2 MHz * 192) + + + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = 16; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384) + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.h new file mode 100644 index 0000000000..ea2f070a6b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/system_stm32f4xx.h @@ -0,0 +1,123 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.h + * @author MCD Application Team + * @version V2.3.0 + * @date 02-March-2015 + * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F4XX_H +#define __SYSTEM_STM32F4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_conf.h index 9d286f18ff..2a68d8595c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_conf.h @@ -101,7 +101,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_conf.h index 7b7b992010..42e8b6e9d1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_conf.h @@ -107,7 +107,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_conf.h index 9d286f18ff..2a68d8595c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_conf.h @@ -101,7 +101,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h index 3a7ecf5313..d57f7fe498 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h @@ -101,7 +101,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx_hal_conf.h index 9d286f18ff..2a68d8595c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx_hal_conf.h @@ -101,7 +101,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h index d4a2710b24..37f01d40b1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h @@ -107,7 +107,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx_hal_conf.h index 637cd7ce76..53cfbe4034 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx_hal_conf.h @@ -101,7 +101,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx_hal_conf.h index 8d902c9084..9ede6a7661 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx_hal_conf.h @@ -101,7 +101,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h index 3c1a907e0e..33d5b9b72b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** @@ -87,6 +87,11 @@ #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO @@ -250,7 +255,14 @@ #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS #define OB_WDG_SW OB_IWDG_SW #define OB_WDG_HW OB_IWDG_HW - +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 /** * @} */ @@ -259,14 +271,15 @@ * @{ */ -#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 - +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 /** * @} */ @@ -325,6 +338,13 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 +#if defined(STM32L0) || defined(STM32F4) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32F4 */ + /** * @} */ @@ -2010,39 +2030,202 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE /* alias define maintained for legacy */ #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + #if defined(STM32F4) #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET @@ -2081,28 +2264,75 @@ #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 #define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER #define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER - +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS @@ -2123,6 +2353,8 @@ #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c index 32ae35feb6..34f6ad5824 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -68,17 +68,17 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.3.2 + * @brief STM32F4xx HAL Driver version number V1.4.1 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16)\ |(__STM32F4xx_HAL_VERSION_SUB2 << 8 )\ |(__STM32F4xx_HAL_VERSION_RC)) - + #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) /* ------------ RCC registers bit address in the alias region ----------- */ @@ -87,7 +87,7 @@ /* Alias word address of UFB_MODE bit */ #define MEMRMP_OFFSET SYSCFG_OFFSET #define UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE) -#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BIT_NUMBER * 4)) +#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BIT_NUMBER * 4)) /* --- CMPCR Register ---*/ /* Alias word address of CMP_PD bit */ @@ -479,7 +479,8 @@ void HAL_DisableCompensationCell(void) *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE; } -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Enables the Internal FLASH Bank Swapping. * @@ -510,7 +511,7 @@ void HAL_DisableMemorySwappingBank(void) *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE; } -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h index a0cc063424..7d03dcb4c6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -134,7 +134,8 @@ }while(0); #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */ #define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ @@ -146,7 +147,37 @@ #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\ }while(0); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable + * @{ + */ +/** @brief SYSCFG Break Lockup lock + * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ + }while(0) +/** + * @} + */ + +/** @defgroup PVD_Lock_Enable PVD Lock + * @{ + */ +/** @brief SYSCFG Break PVD lock + * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ /** * @} */ @@ -188,10 +219,11 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void); void HAL_DBGMCU_DisableDBGStandbyMode(void); void HAL_EnableCompensationCell(void); void HAL_DisableCompensationCell(void); -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) void HAL_EnableMemorySwappingBank(void); void HAL_DisableMemorySwappingBank(void); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c index 1b4dce2a70..3a4942af56 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h index 74a2f159c9..5bdb0e1407 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 - * @brief Header file of ADC HAL extension module. + * @version V1.4.1 + * @date 09-October-2015 + * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention * @@ -201,10 +201,10 @@ typedef struct /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler * @{ */ -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000) -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000) +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) +#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) +#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) /** * @} */ @@ -565,10 +565,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ -#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \ - ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \ - ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \ - ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8)) +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8)) #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c index ee889939b8..73efd3d53d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions @@ -639,7 +639,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); } - + /* Process locked */ __HAL_LOCK(hadc); diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h index 24a010a320..01c9cb4c60 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -188,14 +188,16 @@ typedef struct * @{ */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ + defined(STM32F410Rx) || defined(STM32F412xG) #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412xG */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT ((uint32_t)0x10000000) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -262,14 +264,16 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ * @{ */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412xG) #define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18) -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412xG */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c index e6ad694515..9fc383db39 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_can.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: * + Initialization and de-initialization functions @@ -115,7 +115,7 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -1424,7 +1424,8 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM3F412xE */ #endif /* HAL_CAN_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h index 210d89f10f..24ee78e356 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_can.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -45,7 +45,7 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -755,7 +755,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c index 9516bf2bd2..c91629ed4d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cec.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief CEC HAL module driver. * * This file provides firmware functions to manage the following @@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) * @verbatim =============================================================================== - ##### I/O operation functions ##### + ##### IO operation functions ##### =============================================================================== This subsection provides a set of functions allowing to manage the CEC data transfers. @@ -317,14 +317,14 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) * @param pData: pointer to input byte data buffer * @param Size: amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). - * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). + * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout) { - uint8_t temp = 0; - uint32_t tempisr = 0; + uint8_t temp = 0; + uint32_t tempisr = 0; uint32_t tickstart = 0; if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) @@ -333,32 +333,32 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA if((pData == NULL ) && (Size > 0)) { hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; + return HAL_ERROR; } - assert_param(IS_CEC_ADDRESS(DestinationAddress)); + assert_param(IS_CEC_ADDRESS(DestinationAddress)); assert_param(IS_CEC_MSGSIZE(Size)); - + /* Process Locked */ __HAL_LOCK(hcec); hcec->State = HAL_CEC_STATE_BUSY_TX; hcec->TxXferCount = Size; - + /* case no data to be sent, sender is only pinging the system */ if (Size == 0) { /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ __HAL_CEC_LAST_BYTE_TX_SET(hcec); } - + /* send header block */ temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress; hcec->Instance->TXDR = temp; /* Set TX Start of Message (TXSOM) bit */ __HAL_CEC_FIRST_BYTE_TX_SET(hcec); - + while (hcec->TxXferCount > 0) { hcec->TxXferCount--; @@ -366,16 +366,16 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR)) { - if(Timeout != HAL_MAX_DELAY) + if(Timeout != HAL_MAX_DELAY) { - if((HAL_GetTick() - tickstart) > Timeout) + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) { - hcec->State = HAL_CEC_STATE_TIMEOUT; + hcec->State = HAL_CEC_STATE_TIMEOUT; /* Process Unlocked */ - __HAL_UNLOCK(hcec); + __HAL_UNLOCK(hcec); return HAL_TIMEOUT; } - } + } /* check whether error occured while waiting for TXBR to be set: * has Tx underrun occurred ? @@ -391,9 +391,9 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); hcec->State = HAL_CEC_STATE_ERROR; __HAL_UNLOCK(hcec); - return HAL_ERROR; + return HAL_ERROR; } - } + } /* TXBR to clear BEFORE writing TXDR register */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); if (hcec->TxXferCount == 0) @@ -402,7 +402,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA __HAL_CEC_LAST_BYTE_TX_SET(hcec); } hcec->Instance->TXDR = *pData++; - + /* error check after TX byte write up */ tempisr = hcec->Instance->ISR; if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0) @@ -413,18 +413,17 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)); hcec->State = HAL_CEC_STATE_ERROR; __HAL_UNLOCK(hcec); - return HAL_ERROR; + return HAL_ERROR; } } /* end while (while (hcec->TxXferCount > 0)) */ - - + /* if no error up to this point, check that transmission is * complete, that is wait until TXEOM is reset */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM)) { - if(Timeout != HAL_MAX_DELAY) + if(Timeout != HAL_MAX_DELAY) { if((HAL_GetTick() - tickstart) > Timeout) { @@ -445,8 +444,8 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)); hcec->State = HAL_CEC_STATE_ERROR; __HAL_UNLOCK(hcec); - return HAL_ERROR; - } + return HAL_ERROR; + } hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); @@ -455,7 +454,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA } else { - return HAL_BUSY; + return HAL_BUSY; } } @@ -471,9 +470,9 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout) -{ +{ uint32_t temp; - uint32_t tickstart = 0; + uint32_t tickstart = 0; if (hcec->State == HAL_CEC_STATE_READY) { @@ -481,14 +480,13 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3 if (pData == NULL ) { hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; + return HAL_ERROR; } - + hcec->RxXferSize = 0; /* Process Locked */ __HAL_LOCK(hcec); - - + /* Rx loop until CEC_ISR_RXEND is set */ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) { @@ -496,12 +494,12 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3 /* Wait for next byte to be received */ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) { - if(Timeout != HAL_MAX_DELAY) + if(Timeout != HAL_MAX_DELAY) { - if((HAL_GetTick() - tickstart) > Timeout) + if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) { hcec->State = HAL_CEC_STATE_TIMEOUT; - __HAL_UNLOCK(hcec); + __HAL_UNLOCK(hcec); return HAL_TIMEOUT; } } @@ -509,7 +507,7 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3 * has Rx Missing Acknowledge occurred ? * has Rx Long Bit Period error occurred ? * has Rx Short Bit Period error occurred ? - * has Rx Bit Rising error occurred ? + * has Rx Bit Rising error occurred ? * has Rx Overrun error occurred ? */ temp = (uint32_t) (hcec->Instance->ISR); if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0) @@ -520,57 +518,56 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3 __HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)); hcec->State = HAL_CEC_STATE_ERROR; __HAL_UNLOCK(hcec); - return HAL_ERROR; + return HAL_ERROR; } } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */ - /* read received data */ *pData++ = hcec->Instance->RXDR; temp = (uint32_t) (hcec->Instance->ISR); /* end of message ? */ - if ((temp & CEC_ISR_RXEND) != 0) + if ((temp & CEC_ISR_RXEND) != 0) { assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize)); __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND); - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); + hcec->State = HAL_CEC_STATE_READY; + __HAL_UNLOCK(hcec); return HAL_OK; } - + /* clear Rx-Byte Received flag */ - __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR); + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR); /* increment payload byte counter */ hcec->RxXferSize++; } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */ - + /* if the instructions below are executed, it means RXEND was set when RXBR was * set for the first time: * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))" * loop has not been executed and this means a single byte has been sent */ *pData++ = hcec->Instance->RXDR; - /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */ + /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */ hcec->RxXferSize = 0; __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); + + hcec->State = HAL_CEC_STATE_READY; + __HAL_UNLOCK(hcec); return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** * @brief Send data in interrupt mode * @param hcec: CEC handle - * @param DestinationAddress: destination logical address + * @param DestinationAddress: destination logical address * @param pData: pointer to input byte data buffer * @param Size: amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). - * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). + * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) @@ -580,25 +577,25 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati already pending due to arbitration lost */ if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX)) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) - { + { if((pData == NULL) && (Size > 0)) { hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; + return HAL_ERROR; } assert_param(IS_CEC_ADDRESS(DestinationAddress)); assert_param(IS_CEC_MSGSIZE(Size)); - + /* Process Locked */ __HAL_LOCK(hcec); hcec->pTxBuffPtr = pData; hcec->State = HAL_CEC_STATE_BUSY_TX; hcec->ErrorCode = HAL_CEC_ERROR_NONE; - + /* Disable Peripheral to write CEC_IER register */ __HAL_CEC_DISABLE(hcec); - + /* Enable the following two CEC Transmission interrupts as * well as the following CEC Transmission Errors interrupts: * Tx Byte Request IT @@ -608,36 +605,35 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati * Tx-Buffer Underrun IT * Tx arbitration lost */ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR); - + /* Enable the Peripheral */ __HAL_CEC_ENABLE(hcec); - + /* initialize the number of bytes to send, * 0 means only one header is sent (ping operation) */ hcec->TxXferCount = Size; - + /* Process Unlocked */ __HAL_UNLOCK(hcec); - + /* in case of no payload (Size = 0), sender is only pinging the system; * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ if (Size == 0) { __HAL_CEC_LAST_BYTE_TX_SET(hcec); } - + /* send header block */ temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress; hcec->Instance->TXDR = temp; /* Set TX Start of Message (TXSOM) bit */ __HAL_CEC_FIRST_BYTE_TX_SET(hcec); - + return HAL_OK; } /* if the IP is already busy or if there is a previous transmission already pending due to arbitration loss */ - else if ((hcec->State == HAL_CEC_STATE_BUSY_TX) - || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) + else if ((hcec->State == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) { __HAL_LOCK(hcec); /* set state to BUSY TX, in case it wasn't set already (case @@ -652,17 +648,17 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati { /* Disable Peripheral to write CEC_IER register */ __HAL_CEC_DISABLE(hcec); - + /* Disable the CEC Transmission Interrupts */ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); /* Disable the CEC Transmission Error Interrupts */ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); - + /* Enable the Peripheral */ __HAL_CEC_ENABLE(hcec); - + __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND); - + hcec->State = HAL_CEC_STATE_READY; /* Call the Process Unlocked before calling the Tx call back API to give the possibility to start again the Transmission under the Tx call back API */ @@ -683,16 +679,16 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); hcec->Instance->TXDR = *hcec->pTxBuffPtr++; hcec->TxXferCount--; - + /* Process Unlocked */ __HAL_UNLOCK(hcec); - + return HAL_OK; } } else { - return HAL_BUSY; + return HAL_BUSY; } } @@ -713,7 +709,7 @@ HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) if(pData == NULL) { hcec->State = HAL_CEC_STATE_ERROR; - return HAL_ERROR; + return HAL_ERROR; } /* Process Locked */ @@ -807,28 +803,28 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX bit rising error interrupt occured --------------------------------------*/ + /* CEC RX bit rising error interrupt occured -------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE); hcec->State = HAL_CEC_STATE_ERROR; - } + } - /* CEC RX short bit period error interrupt occured --------------------------------------*/ + /* CEC RX short bit period error interrupt occured -------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE); hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX long bit period error interrupt occured --------------------------------------*/ + /* CEC RX long bit period error interrupt occured --------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE); hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/ + /* CEC RX missing acknowledge error interrupt occured ----------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE); @@ -840,34 +836,33 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) HAL_CEC_ErrorCallback(hcec); } - /* CEC RX byte received interrupt ---------------------------------------------------*/ + /* CEC RX byte received interrupt -----------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET)) { /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ CEC_Receive_IT(hcec); } - - /* CEC RX end received interrupt ---------------------------------------------------*/ + + /* CEC RX end received interrupt ------------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET)) { /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */ CEC_Receive_IT(hcec); } - - - /* CEC TX byte request interrupt ------------------------------------------------*/ + + /* CEC TX byte request interrupt -------------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET)) { /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */ CEC_Transmit_IT(hcec); } - - /* CEC TX end interrupt ------------------------------------------------*/ + + /* CEC TX end interrupt ----------------------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET)) { /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */ CEC_Transmit_IT(hcec); - } + } } /** @@ -915,7 +910,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) @verbatim =============================================================================== ##### Peripheral Control function ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the CEC. (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. @@ -979,12 +974,12 @@ static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND); /* Disable the CEC Transmission Error Interrupts */ __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR); - + /* Enable the Peripheral */ __HAL_CEC_ENABLE(hcec); - + __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND); - + hcec->State = HAL_CEC_STATE_READY; /* Call the Process Unlocked before calling the Tx call back API to give the possibility to start again the Transmission under the Tx call back API */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h index 14cb738b1d..64646f4142 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cec.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c index 59209d028e..f0382cd377 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -261,13 +261,60 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK) functionalities. + (NVIC, SYSTICK, MPU) functionalities. @endverbatim * @{ */ +#if (__MPU_PRESENT == 1) +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != RESET) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00; + MPU->RASR = 0x00; + } +} +#endif /* __MPU_PRESENT */ + /** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h index 71807bfda9..93b2d5c9e2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention @@ -54,6 +54,48 @@ * @{ */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants @@ -87,6 +129,137 @@ * @} */ +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + /** * @} */ @@ -140,6 +313,9 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); * @{ */ /* Peripheral Control functions ***********************************************/ +#if (__MPU_PRESENT == 1) +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); @@ -178,9 +354,123 @@ void HAL_SYSTICK_Callback(void); #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Functions CORTEX Private Functions + * @brief CORTEX private functions + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** + * @brief Disables the MPU + * @retval None + */ +__STATIC_INLINE void HAL_MPU_Disable(void) +{ + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** + * @brief Enables the MPU + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +} +#endif /* __MPU_PRESENT */ + /** * @} - */ + */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c index 6db9a2773e..504134a7bc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h index 24a4aeda91..8e8fc3da1b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c index 74b3a9b0eb..a6e81aeef7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -111,7 +111,7 @@ #ifdef HAL_CRYP_MODULE_ENABLED -#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) +#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -3799,7 +3799,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) * @} */ -#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */ +#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */ #endif /* HAL_CRYP_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h index e0219cea7e..0a39eb2338 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) +#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -517,7 +517,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */ +#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c index a16078800e..fe7b672f8a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Extended CRYP HAL module driver * This file provides firmware functions to manage the following * functionalities of CRYP extension peripheral: @@ -110,7 +110,7 @@ #ifdef HAL_CRYP_MODULE_ENABLED -#if defined(STM32F437xx) || defined(STM32F439xx) +#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -3029,7 +3029,7 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp) /** * @} */ -#endif /* STM32F437xx || STM32F439xx */ +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ #endif /* HAL_CRYP_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h index e73ed536d9..9d005ff6a0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of CRYP HAL Extension module. ****************************************************************************** * @attention @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F437xx) || defined(STM32F439xx) +#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -203,7 +203,7 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* STM32F437xx || STM32F439xx */ +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c index 9a7ccef878..efe9a54a43 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -20,7 +20,7 @@ [..] *** DAC Channels *** ==================== - [..] + [..] The device integrates two 12-bit Digital Analog Converters that can be used independently or simultaneously (dual mode): (#) DAC channel1 with DAC_OUT1 (PA4) as output @@ -185,7 +185,8 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -938,8 +939,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx - */ + STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_DAC_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h index bfc12597df..9a0493b69e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention @@ -45,7 +45,8 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -393,7 +394,7 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx */ + STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c index a8d3e7d857..65918291d4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -69,7 +69,8 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -366,8 +367,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx - */ + STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_DAC_MODULE_ENABLED */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h index 10a118b07f..a5c50fc037 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention @@ -45,7 +45,8 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -180,7 +181,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx */ + STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c index 5713a86162..de0c7096a5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: @@ -104,7 +104,8 @@ #ifdef HAL_DCMI_MODULE_ENABLED #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */ @@ -607,10 +608,10 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) * @brief Configure the DCMI CROP coordinate. * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @param YSize: DCMI Line number - * @param XSize: DCMI Pixel per line * @param X0: DCMI window X offset * @param Y0: DCMI window Y offset + * @param XSize: DCMI Pixel per line + * @param YSize: DCMI Line number * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) @@ -817,7 +818,8 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) * @} */ #endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx */ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ #endif /* HAL_DCMI_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h index 644f7a8afa..f59ae38e9e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of DCMI HAL module. ****************************************************************************** * @attention @@ -44,7 +44,8 @@ #endif #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -496,7 +497,8 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); */ #endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx */ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c index 4cc2d45bbe..cf64725632 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief DCMI Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of DCMI extension peripheral: @@ -60,14 +60,15 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ -/** @defgroup DCMI DCMI - * @brief DCMI HAL module driver +/** @defgroup DCMIEx DCMIEx + * @brief DCMI Extended HAL module driver * @{ */ #ifdef HAL_DCMI_MODULE_ENABLED -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) ||\ + defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -118,12 +119,12 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate)); assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode)); assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode)); -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode)); assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart)); assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode)); assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart)); -#endif +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ if(hdcmi->State == HAL_DCMI_STATE_RESET) { /* Init the low level hardware */ @@ -136,20 +137,20 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\ DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\ DCMI_CR_ESS -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\ DCMI_CR_LSM | DCMI_CR_OELS -#endif +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ ); hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\ hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\ hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\ hdcmi->Init.JPEGMode -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | hdcmi->Init.ByteSelectMode |\ hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\ hdcmi->Init.LineSelectStart -#endif +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ ); if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) { @@ -199,7 +200,8 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /** * @} */ -#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx ||\ + STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_DCMI_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h index 6355fb50f5..ddf687b28d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of DCMI Extension HAL module. ****************************************************************************** * @attention @@ -44,7 +44,8 @@ #endif #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -54,13 +55,13 @@ * @{ */ -/** @addtogroup DCMIEx DCMI Extended +/** @addtogroup DCMIEx * @brief DCMI HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup DCMIEx_Exported_Types DCMI Extende Exported Types +/** @defgroup DCMIEx_Exported_Types DCMI Extended Exported Types * @{ */ /** @@ -101,7 +102,7 @@ typedef struct uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. This parameter can be a value of @ref DCMI_MODE_JPEG */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */ @@ -114,7 +115,7 @@ typedef struct uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd This parameter can be a value of @ref DCMIEx_Line_Select_Start */ -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ }DCMI_InitTypeDef; /** @@ -122,7 +123,7 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants * @{ */ @@ -196,14 +197,15 @@ typedef struct #define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \ ((POLARITY) == DCMI_OELS_EVEN)) -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ /* Private functions ---------------------------------------------------------*/ #endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx */ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h index d700336790..7903aab26b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_def.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c index 2e2757cfda..02fb1d5fd1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -128,6 +128,14 @@ #ifdef HAL_DMA_MODULE_ENABLED /* Private types -------------------------------------------------------------*/ + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @addtogroup DMA_Private_Constants @@ -143,6 +151,8 @@ * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); + /** * @} */ @@ -178,9 +188,9 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ +{ uint32_t tmp = 0; - + /* Check the DMA peripheral state */ if(hdma == NULL) { @@ -254,6 +264,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + DMA_CalcBaseAndBitshift(hdma); + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -271,6 +285,8 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { + DMA_Base_Registers *regs; + /* Check the DMA peripheral state */ if(hdma == NULL) { @@ -297,19 +313,18 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Reset DMA Streamx memory 0 address register */ hdma->Instance->M0AR = 0; - + /* Reset DMA Streamx memory 1 address register */ hdma->Instance->M1AR = 0; - + /* Reset DMA Streamx FIFO control register */ hdma->Instance->FCR = (uint32_t)0x00000021; - - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3F << hdma->StreamIndex; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -403,20 +418,9 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - /* Enable the transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); - - /* Enable the Half transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); - - /* Enable the transfer Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); - - /* Enable the FIFO Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE); - - /* Enable the direct mode Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); + /* Enable all interrupts */ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); @@ -484,28 +488,33 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp, tmp, tmp1, tmp2; - uint32_t tickstart = 0; + uint32_t tickstart = 0; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs; + + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Transfer Complete flag */ - temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); + temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; } else { /* Half Transfer Complete flag */ - temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); + temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; } /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) + while((regs->ISR & temp) == RESET) { - tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + tmp = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex); + tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex); + tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex); if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET)) { if(tmp != RESET) @@ -514,15 +523,15 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp hdma->ErrorCode |= HAL_DMA_ERROR_TE; /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; } if(tmp1 != RESET) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; - + /* Clear the FIFO error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; } if(tmp2 != RESET) { @@ -530,16 +539,16 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp hdma->ErrorCode |= HAL_DMA_ERROR_DME; /* Clear the Direct Mode error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; } /* Change the DMA state */ hdma->State= HAL_DMA_STATE_ERROR; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; - } + } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { @@ -553,7 +562,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_TIMEOUT; } } @@ -561,14 +570,12 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == 0) { @@ -584,11 +591,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp } else { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY_MEM0; @@ -597,13 +599,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp __HAL_UNLOCK(hdma); } else - { + { + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == 0) { @@ -619,9 +621,6 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp } else { - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; } @@ -637,8 +636,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs; + + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + /* Transfer Error Interrupt management ***************************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) + if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) { @@ -646,7 +650,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; @@ -655,7 +659,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->State = HAL_DMA_STATE_ERROR; /* Process Unlocked */ - __HAL_UNLOCK(hdma); + __HAL_UNLOCK(hdma); if(hdma->XferErrorCallback != NULL) { @@ -665,7 +669,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } /* FIFO Error Interrupt management ******************************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET) + if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) { @@ -673,7 +677,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE); /* Clear the FIFO error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; @@ -692,7 +696,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } /* Direct Mode Error Interrupt management ***********************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET) + if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) { @@ -700,7 +704,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME); /* Clear the direct mode error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; @@ -719,15 +723,15 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } /* Half Transfer Complete Interrupt management ******************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) + if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) - { + { /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) { /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == 0) @@ -751,7 +755,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); } /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; @@ -765,14 +769,14 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } /* Transfer Complete Interrupt management ***********************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) + if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) { if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) { /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; /* Current memory buffer used is Memory 1 */ if((hdma->Instance->CR & DMA_SxCR_CT) == 0) @@ -784,7 +788,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } /* Current memory buffer used is Memory 0 */ - else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) + else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) { if(hdma->XferCpltCallback != NULL) { @@ -802,7 +806,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); } /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_NONE; @@ -811,7 +815,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->State = HAL_DMA_STATE_READY_MEM0; /* Process Unlocked */ - __HAL_UNLOCK(hdma); + __HAL_UNLOCK(hdma); if(hdma->XferCpltCallback != NULL) { @@ -912,6 +916,34 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t hdma->Instance->M0AR = DstAddress; } } + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + + if (stream_number > 3) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)); + } + + return hdma->StreamBaseAddress; +} /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h index d4585b1305..7e9783e0b8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -165,7 +165,11 @@ typedef struct __DMA_HandleTypeDef void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - __IO uint32_t ErrorCode; /*!< DMA Error code */ + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ }DMA_HandleTypeDef; /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c index a41cb31a58..ad900f25a6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma2d.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief DMA2D HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: @@ -127,7 +127,7 @@ #ifdef HAL_DMA2D_MODULE_ENABLED -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private types -------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -1253,7 +1253,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #endif /* HAL_DMA2D_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h index fc3ff1e4ab..089d8e0538 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma2d.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention @@ -43,7 +43,8 @@ extern "C" { #endif -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -543,7 +544,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c index bf293fb005..73d53d5f74 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h index 9cf760b352..b5427e0a5f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.c new file mode 100644 index 0000000000..30e7ade189 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.c @@ -0,0 +1,2244 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dsi.c + * @author MCD Application Team + * @version V1.4.1 + * @date 09-October-2015 + * @brief DSI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the DSI peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ +/** @addtogroup DSI + * @{ + */ + +#ifdef HAL_DSI_MODULE_ENABLED + +#if defined(STM32F469xx) || defined(STM32F479xx) + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup DSI_Private_Constants + * @{ + */ +#define DSI_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */ + +#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ + DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ + DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ + DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) +#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) +#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX +#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX +#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) +#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE +#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE +#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE +#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE +#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1); + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Generic DSI packet header configuration + * @param DSIx: Pointer to DSI register base + * @param ChannelID: Virtual channel ID of the header packet + * @param DataType: Packet data type of the header packet + * This parameter can be any value of : + * @ref DSI_SHORT_WRITE_PKT_Data_Type + * or @ref DSI_LONG_WRITE_PKT_Data_Type + * or @ref DSI_SHORT_READ_PKT_Data_Type + * or DSI_MAX_RETURN_PKT_SIZE + * @param Data0: Word count LSB + * @param Data1: Word count MSB + * @retval None + */ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, + uint32_t ChannelID, + uint32_t DataType, + uint32_t Data0, + uint32_t Data1) +{ + /* Update the DSI packet header with new information */ + DSIx->GHCR = (DataType | (ChannelID<<6) | (Data0<<8) | (Data1<<16)); +} + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DSI_Exported_Functions + * @{ + */ + +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DSI + (+) De-initialize the DSI + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DSI according to the specified + * parameters in the DSI_InitTypeDef and create the associated handle. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) +{ + uint32_t tickstart = 0; + uint32_t unitIntervalx4 = 0; + uint32_t tempIDF = 0; + + /* Check the DSI handle allocation */ + if(hdsi == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); + assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); + assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); + assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); + assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); + + if(hdsi->State == HAL_DSI_STATE_RESET) + { + /* Initialize the low level hardware */ + HAL_DSI_MspInit(hdsi); + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /**************** Turn on the regulator and enable the DSI PLL ****************/ + + /* Enable the regulator */ + __HAL_DSI_REG_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the regulator is ready */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the PLL division factors */ + hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2) | ((PLLInit->PLLIDF)<<11) | ((PLLInit->PLLODF)<<16)); + + /* Enable the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /*************************** Set the PHY parameters ***************************/ + + /* D-PHY clock and digital enable*/ + hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Clock lane configuration */ + hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); + hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); + + /* Configure the number of active data lanes */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; + hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; + + /************************ Set the DSI clock parameters ************************/ + + /* Set the TX escape clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; + hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv; + + /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ + /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ + /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ + tempIDF = (PLLInit->PLLIDF > 0) ? PLLInit->PLLIDF : 1; + unitIntervalx4 = (4000000 * tempIDF * (1 << PLLInit->PLLODF)) / ((HSE_VALUE/1000) * PLLInit->PLLNDIV); + + /* Set the bit period in high-speed mode */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_UIX4; + hdsi->Instance->WPCR[0] |= unitIntervalx4; + + /****************************** Error management *****************************/ + + /* Disable all error interrupts and reset the Error Mask */ + hdsi->Instance->IER[0] = 0; + hdsi->Instance->IER[1] = 0; + hdsi->ErrorMsk = 0; + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initializes the DSI peripheral registers to their default reset + * values. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) +{ + /* Check the DSI handle allocation */ + if(hdsi == NULL) + { + return HAL_ERROR; + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* D-PHY clock and digital disable */ + hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Disable the regulator */ + __HAL_DSI_REG_DISABLE(hdsi); + + /* DeInit the low level hardware */ + HAL_DSI_MspDeInit(hdsi); + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Return the DSI error code + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval DSI Error Code + */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +{ + /* Get the error code */ + return hdsi->ErrorCode; +} + +/** + * @brief Enable the error monitor flags + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ActiveErrors: indicates which error interrupts will be enabled. + * This parameter can be any combination of @ref DSI_Error_Data_Type. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + hdsi->Instance->IER[0] = 0; + hdsi->Instance->IER[1] = 0; + + /* Store active errors to the handle */ + hdsi->ErrorMsk = ActiveErrors; + + if(ActiveErrors & HAL_DSI_ERROR_ACK) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0] |= DSI_ERROR_ACK_MASK; + } + + if(ActiveErrors & HAL_DSI_ERROR_PHY) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0] |= DSI_ERROR_PHY_MASK; + } + + if(ActiveErrors & HAL_DSI_ERROR_TX) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_TX_MASK; + } + + if(ActiveErrors & HAL_DSI_ERROR_RX) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_RX_MASK; + } + + if(ActiveErrors & HAL_DSI_ERROR_ECC) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_ECC_MASK; + } + + if(ActiveErrors & HAL_DSI_ERROR_CRC) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_CRC_MASK; + } + + if(ActiveErrors & HAL_DSI_ERROR_PSE) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_PSE_MASK; + } + + if(ActiveErrors & HAL_DSI_ERROR_EOT) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_EOT_MASK; + } + + if(ActiveErrors & HAL_DSI_ERROR_OVF) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_OVF_MASK; + } + + if(ActiveErrors & HAL_DSI_ERROR_GEN) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1] |= DSI_ERROR_GEN_MASK; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Initializes the DSI MSP. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initializes the DSI MSP. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle DSI interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handles DSI interrupt request. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) +{ + uint32_t ErrorStatus0, ErrorStatus1; + + /* Tearing Effect Interrupt management ***************************************/ + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET) + { + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET) + { + /* Clear the Tearing Effect Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); + + /* Tearing Effect Callback */ + HAL_DSI_TearingEffectCallback(hdsi); + } + } + + /* End of Refresh Interrupt management ***************************************/ + if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET) + { + if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET) + { + /* Clear the End of Refresh Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); + + /* End of Refresh Callback */ + HAL_DSI_EndOfRefreshCallback(hdsi); + } + } + + /* Error Interrupts management ***********************************************/ + if(hdsi->ErrorMsk != 0) + { + ErrorStatus0 = hdsi->Instance->ISR[0]; + ErrorStatus0 &= hdsi->Instance->IER[0]; + ErrorStatus1 = hdsi->Instance->ISR[1]; + ErrorStatus1 &= hdsi->Instance->IER[1]; + + if(ErrorStatus0 & DSI_ERROR_ACK_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; + } + + if(ErrorStatus0 & DSI_ERROR_PHY_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; + } + + if(ErrorStatus1 & DSI_ERROR_TX_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_TX; + } + + if(ErrorStatus1 & DSI_ERROR_RX_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_RX; + } + + if(ErrorStatus1 & DSI_ERROR_ECC_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; + } + + if(ErrorStatus1 & DSI_ERROR_CRC_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; + } + + if(ErrorStatus1 & DSI_ERROR_PSE_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; + } + + if(ErrorStatus1 & DSI_ERROR_EOT_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; + } + + if(ErrorStatus1 & DSI_ERROR_OVF_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; + } + + if(ErrorStatus1 & DSI_ERROR_GEN_MASK) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; + } + + /* Check only selected errors */ + if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) + { + /* DSI error interrupt user callback */ + HAL_DSI_ErrorCallback(hdsi); + } + } +} + +/** + * @brief Tearing Effect DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_TearingEffectCallback could be implemented in the user file + */ +} + +/** + * @brief End of Refresh DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_EndOfRefreshCallback could be implemented in the user file + */ +} + +/** + * @brief Operation Error DSI callback. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) + (+) + (+) + +@endverbatim + * @{ + */ + +/** + * @brief Configure the Generic interface read-back Virtual Channel ID. + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VirtualChannelID: Virtual channel ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the GVCID register */ + hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; + hdsi->Instance->GVCIDR |= VirtualChannelID; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select video mode and configure the corresponding parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); + assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); + assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); + assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); + assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); + assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); + assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); + assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); + assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); + assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); + assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); + /* Check the LooselyPacked variant only in 18-bit mode */ + if(VidCfg->ColorCoding == DSI_RGB666) + { + assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); + } + + /* Select video mode by resetting CMDM and DSIM bits */ + hdsi->Instance->MCR &= ~DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + + /* Configure the video mode transmission type */ + hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; + hdsi->Instance->VMCR |= VidCfg->Mode; + + /* Configure the video packet size */ + hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; + hdsi->Instance->VPCR |= VidCfg->PacketSize; + + /* Set the chunks number to be transmitted through the DSI link */ + hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; + hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; + + /* Set the size of the null packet */ + hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; + hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1); + + /* Enable/disable the loosely packed variant to 18-bit configuration */ + if(VidCfg->ColorCoding == DSI_RGB666) + { + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; + hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; + } + + /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ + hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; + hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; + + /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ + hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; + hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; + + /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ + hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; + hdsi->Instance->VLCR |= VidCfg->HorizontalLine; + + /* Set the Vertical Synchronization Active (VSA) */ + hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; + hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; + + /* Set the Vertical Back Porch (VBP)*/ + hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; + hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; + + /* Set the Vertical Front Porch (VFP)*/ + hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; + hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; + + /* Set the Vertical Active period*/ + hdsi->Instance->VVACR &= ~DSI_VVACR_VA; + hdsi->Instance->VVACR |= VidCfg->VerticalActive; + + /* Configure the command transmission mode */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; + hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; + + /* Low power largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; + hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16); + + /* Low power VACT largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; + hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; + + /* Enable LP transition in HFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; + + /* Enable LP transition in HBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; + + /* Enable LP transition in VACT period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; + + /* Enable LP transition in VFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; + + /* Enable LP transition in VBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; + + /* Enable LP transition in vertical sync period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; + + /* Enable the request for an acknowledge response at the end of a frame */ + hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; + hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select adapted command mode and configure the corresponding parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); + assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); + assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); + assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); + assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); + assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); + assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); + + /* Select command mode by setting CMDM and DSIM bits */ + hdsi->Instance->MCR |= DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1); + + /* Configure the maximum allowed size for write memory command */ + hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; + hdsi->Instance->LCCR |= CmdCfg->CommandSize; + + /* Configure the tearing effect source and polarity and select the refresh mode */ + hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); + hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol); + + /* Configure the tearing effect acknowledge request */ + hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; + hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; + + /* Enable the Tearing Effect interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); + + /* Enable the End of Refresh interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure command transmission mode: High-speed or Low-power + * and enable/disable acknowledge request after packet transmission + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains + * the DSI command transmission mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); + assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); + assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); + assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); + assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); + assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); + assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); + assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); + assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); + assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); + assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); + assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); + assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); + + /* Select High-speed or Low-power for command transmission */ + hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\ + DSI_CMCR_GSW1TX |\ + DSI_CMCR_GSW2TX |\ + DSI_CMCR_GSR0TX |\ + DSI_CMCR_GSR1TX |\ + DSI_CMCR_GSR2TX |\ + DSI_CMCR_GLWTX |\ + DSI_CMCR_DSW0TX |\ + DSI_CMCR_DSW1TX |\ + DSI_CMCR_DSR0TX |\ + DSI_CMCR_DLWTX |\ + DSI_CMCR_MRDPS); + hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\ + LPCmd->LPGenShortWriteOneP |\ + LPCmd->LPGenShortWriteTwoP |\ + LPCmd->LPGenShortReadNoP |\ + LPCmd->LPGenShortReadOneP |\ + LPCmd->LPGenShortReadTwoP |\ + LPCmd->LPGenLongWrite |\ + LPCmd->LPDcsShortWriteNoP |\ + LPCmd->LPDcsShortWriteOneP |\ + LPCmd->LPDcsShortReadNoP |\ + LPCmd->LPDcsLongWrite |\ + LPCmd->LPMaxReadPacket); + + /* Configure the acknowledge request after each packet transmission */ + hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; + hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the flow control parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param FlowControl: flow control feature(s) to be enabled. + * This parameter can be any combination of @ref DSI_FlowControl. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); + + /* Set the DSI Host Protocol Configuration Register */ + hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; + hdsi->Instance->PCR |= FlowControl; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI PHY timer parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains + * the DSI PHY timing parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) +{ + uint32_t maxTime; + /* Process locked */ + __HAL_LOCK(hdsi); + + maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime; + + /* Clock lane timer configuration */ + + /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two + High-Speed transmission. + To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed + to Low-Power and from Low-Power to High-Speed. + This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). + But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. + + Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. + */ + hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); + hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16)); + + /* Data lane timer configuration */ + hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); + hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16) | ((PhyTimers->DataLaneHS2LPTime)<<24)); + + /* Configure the wait period to request HS transmission after a stop state */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; + hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI HOST timeout parameters + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains + * the DSI host timeout parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Set the timeout clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; + hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8); + + /* High-speed transmission timeout */ + hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT; + hdsi->Instance->TCCR[0] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16); + + /* Low-power reception timeout */ + hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_LPRX_TOCNT; + hdsi->Instance->TCCR[0] |= HostTimeouts->LowPowerReceptionTimeout; + + /* High-speed read timeout */ + hdsi->Instance->TCCR[1] &= ~DSI_TCCR1_HSRD_TOCNT; + hdsi->Instance->TCCR[1] |= HostTimeouts->HighSpeedReadTimeout; + + /* Low-power read timeout */ + hdsi->Instance->TCCR[2] &= ~DSI_TCCR2_LPRD_TOCNT; + hdsi->Instance->TCCR[2] |= HostTimeouts->LowPowerReadTimeout; + + /* High-speed write timeout */ + hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_HSWR_TOCNT; + hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWriteTimeout; + + /* High-speed write presp mode */ + hdsi->Instance->TCCR[3] &= ~DSI_TCCR3_PM; + hdsi->Instance->TCCR[3] |= HostTimeouts->HighSpeedWritePrespMode; + + /* Low-speed write timeout */ + hdsi->Instance->TCCR[4] &= ~DSI_TCCR4_LPWR_TOCNT; + hdsi->Instance->TCCR[4] |= HostTimeouts->LowPowerWriteTimeout; + + /* BTA timeout */ + hdsi->Instance->TCCR[5] &= ~DSI_TCCR5_BTA_TOCNT; + hdsi->Instance->TCCR[5] |= HostTimeouts->BTATimeout; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start the DSI module + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Enable the DSI host */ + __HAL_DSI_ENABLE(hdsi); + + /* Enable the DSI wrapper */ + __HAL_DSI_WRAPPER_ENABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop the DSI module + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Refresh the display in command mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the display */ + hdsi->Instance->WCR |= DSI_WCR_LTDCEN; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Controls the display color mode in Video mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ColorMode: Color mode (full or 8-colors). + * This parameter can be any value of @ref DSI_Color_Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_MODE(ColorMode)); + + /* Update the display color mode */ + hdsi->Instance->WCR &= ~DSI_WCR_COLM; + hdsi->Instance->WCR |= ColorMode; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Control the display shutdown in Video mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Shutdown: Shut-down (Display-ON or Display-OFF). + * This parameter can be any value of @ref DSI_ShutDown + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHUT_DOWN(Shutdown)); + + /* Update the display Shutdown */ + hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; + hdsi->Instance->WCR |= Shutdown; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief DCS or Generic short write command + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID: Virtual channel ID. + * @param Mode: DSI short packet data type. + * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1: DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code. + * @param Param2: DSC parameter or second generic parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Configure the packet to send a short DCS command with 0 or 1 parameter */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + Param1, + Param2); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief DCS or Generic long write command + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID: Virtual channel ID. + * @param Mode: DSI long packet data type. + * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. + * @param NbParams: Number of parameters. + * @param Param1: DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code + * @param ParametersTable: Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t* ParametersTable) +{ + uint32_t uicounter = 0; + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Set the DCS code hexadecimal on payload byte 1, and the other parameters on the write FIFO command*/ + while(uicounter < NbParams) + { + if(uicounter == 0x00) + { + hdsi->Instance->GPDR=(Param1 | \ + ((*(ParametersTable+uicounter))<<8) | \ + ((*(ParametersTable+uicounter+1))<<16) | \ + ((*(ParametersTable+uicounter+2))<<24)); + uicounter += 3; + } + else + { + hdsi->Instance->GPDR=((*(ParametersTable+uicounter)) | \ + ((*(ParametersTable+uicounter+1))<<8) | \ + ((*(ParametersTable+uicounter+2))<<16) | \ + ((*(ParametersTable+uicounter+3))<<24)); + uicounter+=4; + } + } + + /* Configure the packet to send a long DCS command */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + ((NbParams+1)&0x00FF), + (((NbParams+1)&0xFF00)>>8)); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Read command (DCS or generic) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelNbr: Virtual channel ID + * @param Array: pointer to a buffer to store the payload of a read back operation. + * @param Size: Data size to be read (in byte). + * @param Mode: DSI read packet data type. + * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. + * @param DCSCmd: DCS get/read command. + * @param ParametersTable: Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t* Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t* ParametersTable) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); + + if(Size > 2) + { + /* set max return packet size */ + HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFF), (((Size)>>8)&0xFF)); + } + + /* Configure the packet to read command */ + if (Mode == DSI_DCS_SHORT_PKT_READ) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0, 0); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], 0); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0], ParametersTable[1]); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check that the payload read FIFO is not empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Get the first byte */ + *((uint32_t *)Array) = (hdsi->Instance->GPDR); + if (Size > 4) + { + Size -= 4; + Array += 4; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Get the remaining bytes if any */ + while(((int)(Size)) > 0) + { + if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0) + { + *((uint32_t *)Array) = (hdsi->Instance->GPDR); + Size -= 4; + Array += 4; + } + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* ULPS Request on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_URDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the D-PHY active lanes enter into ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Exit ULPS on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_UEDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Clock lane configuration: no more HS request */ + hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; + + /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR); + + /* ULPS Request on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Exit ULPS on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0; + + /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); + + /* Restore clock lane configuration to HS */ + hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start test pattern generation + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Mode: Pattern generator mode + * This parameter can be one of the following values: + * 0 : Color bars (horizontal or vertical) + * 1 : BER pattern (vertical only) + * @param Orientation: Pattern generator orientation + * This parameter can be one of the following values: + * 0 : Vertical color bars + * 1 : Horizontal color bars + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Configure pattern generator mode and orientation */ + hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); + hdsi->Instance->VMCR |= ((Mode<<20) | (Orientation<<24)); + + /* Enable pattern generator by setting PGE bit */ + hdsi->Instance->VMCR |= DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop test pattern generation + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable pattern generator by clearing PGE bit */ + hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set Slew-Rate And Delay Tuning + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CommDelay: Communication delay to be adjusted. + * This parameter can be any value of @ref DSI_Communication_Delay + * @param Lane: select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param Value: Custom value of the slew-rate or delay + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); + assert_param(IS_DSI_LANE_GROUP(Lane)); + + switch(CommDelay) + { + case DSI_SLEW_RATE_HSTX: + if(Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Slew Rate Control on Clock Lane */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCCL; + hdsi->Instance->WPCR[1] |= Value<<16; + } + else if(Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Slew Rate Control on Data Lanes */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXSRCDL; + hdsi->Instance->WPCR[1] |= Value<<18; + } + break; + case DSI_SLEW_RATE_LPTX: + if(Lane == DSI_CLOCK_LANE) + { + /* Low-Power transmission Slew Rate Compensation on Clock Lane */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCCL; + hdsi->Instance->WPCR[1] |= Value<<6; + } + else if(Lane == DSI_DATA_LANES) + { + /* Low-Power transmission Slew Rate Compensation on Data Lanes */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPSRCDL; + hdsi->Instance->WPCR[1] |= Value<<8; + } + break; + case DSI_HS_DELAY: + if(Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Delay on Clock Lane */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDCL; + hdsi->Instance->WPCR[1] |= Value; + } + else if(Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Delay on Data Lanes */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_HSTXDDL; + hdsi->Instance->WPCR[1] |= Value<<2; + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Low-Power Reception Filter Tuning + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Low-Power RX low-pass Filtering Tuning */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_LPRXFT; + hdsi->Instance->WPCR[1] |= Frequency<<25; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Activate an additional current path on all lanes to meet the SDDTx parameter + * defined in the MIPI D-PHY specification + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Activate/Disactivate additional current path on all lanes */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_SDDC; + hdsi->Instance->WPCR[1] |= State<<12; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Custom lane pins configuration + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CustomLane: Function to be applyed on selected lane. + * This parameter can be any value of @ref DSI_CustomLane + * @param Lane: select between clock or data lane 0 or data lane 1. + * This parameter can be any value of @ref DSI_Lane_Select + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); + assert_param(IS_DSI_LANE(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch(CustomLane) + { + case DSI_SWAP_LANE_PINS: + if(Lane == DSI_CLOCK_LANE) + { + /* Swap pins on clock lane */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWCL; + hdsi->Instance->WPCR[0] |= (State<<6); + } + else if(Lane == DSI_DATA_LANE0) + { + /* Swap pins on data lane 0 */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL0; + hdsi->Instance->WPCR[0] |= (State<<7); + } + else if(Lane == DSI_DATA_LANE1) + { + /* Swap pins on data lane 1 */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_SWDL1; + hdsi->Instance->WPCR[0] |= (State<<8); + } + break; + case DSI_INVERT_HS_SIGNAL: + if(Lane == DSI_CLOCK_LANE) + { + /* Invert HS signal on clock lane */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSICL; + hdsi->Instance->WPCR[0] |= (State<<9); + } + else if(Lane == DSI_DATA_LANE0) + { + /* Invert HS signal on data lane 0 */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL0; + hdsi->Instance->WPCR[0] |= (State<<10); + } + else if(Lane == DSI_DATA_LANE1) + { + /* Invert HS signal on data lane 1 */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_HSIDL1; + hdsi->Instance->WPCR[0] |= (State<<11); + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set custom timing for the PHY + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Timing: PHY timing to be adjusted. + * This parameter can be any value of @ref DSI_PHY_Timing + * @param State: ENABLE or DISABLE + * @param Value: Custom value of the timing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_PHY_TIMING(Timing)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch(Timing) + { + case DSI_TCLK_POST: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPOSTEN; + hdsi->Instance->WPCR[0] |= (State<<27); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[4] &= ~DSI_WPCR4_TCLKPOST; + hdsi->Instance->WPCR[4] |= Value; + } + + break; + case DSI_TLPX_CLK: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXCEN; + hdsi->Instance->WPCR[0] |= (State<<26); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXC; + hdsi->Instance->WPCR[3] |= Value; + } + + break; + case DSI_THS_EXIT: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSEXITEN; + hdsi->Instance->WPCR[0] |= (State<<25); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSEXIT; + hdsi->Instance->WPCR[3] |= Value; + } + + break; + case DSI_TLPX_DATA: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TLPXDEN; + hdsi->Instance->WPCR[0] |= (State<<24); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_TLPXD; + hdsi->Instance->WPCR[3] |= Value; + } + + break; + case DSI_THS_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSZEROEN; + hdsi->Instance->WPCR[0] |= (State<<23); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[3] &= ~DSI_WPCR3_THSZERO; + hdsi->Instance->WPCR[3] |= Value; + } + + break; + case DSI_THS_TRAIL: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSTRAILEN; + hdsi->Instance->WPCR[0] |= (State<<22); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSTRAIL; + hdsi->Instance->WPCR[2] |= Value; + } + + break; + case DSI_THS_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_THSPREPEN; + hdsi->Instance->WPCR[0] |= (State<<21); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_THSPREP; + hdsi->Instance->WPCR[2] |= Value; + } + + break; + case DSI_TCLK_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKZEROEN; + hdsi->Instance->WPCR[0] |= (State<<20); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKZERO; + hdsi->Instance->WPCR[2] |= Value; + } + + break; + case DSI_TCLK_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TCLKPREPEN; + hdsi->Instance->WPCR[0] |= (State<<19); + + if(State) + { + /* Set custom value */ + hdsi->Instance->WPCR[2] &= ~DSI_WPCR2_TCLKPREP; + hdsi->Instance->WPCR[2] |= Value; + } + + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force the Clock/Data Lane in TX Stop Mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Lane: select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_LANE_GROUP(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + if(Lane == DSI_CLOCK_LANE) + { + /* Force/Unforce the Clock Lane in TX Stop Mode */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMCL; + hdsi->Instance->WPCR[0] |= (State<<12); + } + else if(Lane == DSI_DATA_LANES) + { + /* Force/Unforce the Data Lanes in TX Stop Mode */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_FTXSMDL; + hdsi->Instance->WPCR[0] |= (State<<13); + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Forces LP Receiver in Low-Power Mode + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force/Unforce LP Receiver in Low-Power Mode */ + hdsi->Instance->WPCR[1] &= ~DSI_WPCR1_FLPRXLPM; + hdsi->Instance->WPCR[1] |= State<<22; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force Data Lanes in RX Mode after a BTA + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force Data Lanes in RX Mode */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_TDDL; + hdsi->Instance->WPCR[0] |= State<<16; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enable a pull-down on the lanes to prevent from floating states when unused + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Enable/Disable pull-down on lanes */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_PDEN; + hdsi->Instance->WPCR[0] |= State<<18; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Switch off the contention detection on data lanes + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State: ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Contention Detection on Data Lanes OFF */ + hdsi->Instance->WPCR[0] &= ~DSI_WPCR0_CDOFFDL; + hdsi->Instance->WPCR[0] |= State<<14; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DSI state. + (+) Get error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the DSI state + * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL state + */ +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +{ + return hdsi->State; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F469xx || STM32F479xx */ +#endif /* HAL_DSI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.h new file mode 100644 index 0000000000..a7d558db9c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dsi.h @@ -0,0 +1,1242 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dsi.h + * @author MCD Application Team + * @version V1.4.1 + * @date 09-October-2015 + * @brief Header file of DSI HAL module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DSI_H +#define __STM32F4xx_HAL_DSI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F469xx) || defined(STM32F479xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup DSI DSI + * @brief DSI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief DSI Init Structure definition + */ +typedef struct +{ + uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control + This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ + + uint32_t TXEscapeCkdiv; /*!< TX Escape clock division + The values 0 and 1 stop the TX_ESC clock generation */ + + uint32_t NumberOfLanes; /*!< Number of lanes + This parameter can be any value of @ref DSI_Number_Of_Lanes */ + +}DSI_InitTypeDef; + +/** + * @brief DSI PLL Clock structure definition + */ +typedef struct +{ + uint32_t PLLNDIV; /*!< PLL Loop Division Factor + This parameter must be a value between 10 and 125 */ + + uint32_t PLLIDF; /*!< PLL Input Division Factor + This parameter can be any value of @ref DSI_PLL_IDF */ + + uint32_t PLLODF; /*!< PLL Output Division Factor + This parameter can be any value of @ref DSI_PLL_ODF */ + +}DSI_PLLInitTypeDef; + +/** + * @brief DSI Video mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using + 18-bit configuration). + This parameter can be any value of @ref DSI_LooselyPacked */ + + uint32_t Mode; /*!< Video mode type + This parameter can be any value of @ref DSI_Video_Mode_Type */ + + uint32_t PacketSize; /*!< Video packet size */ + + uint32_t NumberOfChunks; /*!< Number of chunks */ + + uint32_t NullPacketSize; /*!< Null packet size */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ + + uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ + + uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ + + uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ + + uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ + + uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ + + uint32_t VerticalActive; /*!< Vertical active duration */ + + uint32_t LPCommandEnable; /*!< Low-power command enable + This parameter can be any value of @ref DSI_LP_Command */ + + uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VSA, VBP and VFP regions */ + + uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VACT region */ + + uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable + This parameter can be any value of @ref DSI_LP_HFP */ + + uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable + This parameter can be any value of @ref DSI_LP_HBP */ + + uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable + This parameter can be any value of @ref DSI_LP_VACT */ + + uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable + This parameter can be any value of @ref DSI_LP_VFP */ + + uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable + This parameter can be any value of @ref DSI_LP_VBP */ + + uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable + This parameter can be any value of @ref DSI_LP_VSYNC */ + + uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable + This parameter can be any value of @ref DSI_FBTA_acknowledge */ + +}DSI_VidCfgTypeDef; + +/** + * @brief DSI Adapted command mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in + pixels. This parameter can be any value between 0x00 and 0xFFFF */ + + uint32_t TearingEffectSource; /*!< Tearing effect source + This parameter can be any value of @ref DSI_TearingEffectSource */ + + uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity + This parameter can be any value of @ref DSI_TearingEffectPolarity */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted + This parameter can be any value of @ref DSI_Vsync_Polarity */ + + uint32_t AutomaticRefresh; /*!< Automatic refresh mode + This parameter can be any value of @ref DSI_AutomaticRefresh */ + + uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable + This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ + +}DSI_CmdCfgTypeDef; + +/** + * @brief DSI command transmission mode configuration + */ +typedef struct +{ + uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ + + uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ + + uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ + + uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ + + uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ + + uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ + + uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ + + uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ + + uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ + + uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ + + uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ + + uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission + This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ + + uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable + This parameter can be any value of @ref DSI_AcknowledgeRequest */ + +}DSI_LPCmdTypeDef; + +/** + * @brief DSI PHY Timings definition + */ +typedef struct +{ + uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed + to low-power transmission */ + + uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed + to low-power transmission */ + + uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ + + uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the + Stop state */ + +}DSI_PHY_TimerTypeDef; + +/** + * @brief DSI HOST Timeouts definition + */ +typedef struct +{ + uint32_t TimeoutCkdiv; /*!< Time-out clock division */ + + uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ + + uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ + + uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ + + uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ + + uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ + + uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode + This parameter can be any value of @ref DSI_HS_PrespMode */ + + uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ + + uint32_t BTATimeout; /*!< BTA time-out */ + +}DSI_HOST_TimeoutTypeDef; + +/** + * @brief DSI States Structure definition + */ +typedef enum +{ + HAL_DSI_STATE_RESET = 0x00, + HAL_DSI_STATE_READY = 0x01, + HAL_DSI_STATE_ERROR = 0x02, + HAL_DSI_STATE_BUSY = 0x03, + HAL_DSI_STATE_TIMEOUT = 0x04 +}HAL_DSI_StateTypeDef; + +/** + * @brief DSI Handle Structure definition + */ +typedef struct +{ + DSI_TypeDef *Instance; /*!< Register base address */ + DSI_InitTypeDef Init; /*!< DSI required parameters */ + HAL_LockTypeDef Lock; /*!< DSI peripheral status */ + __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ + __IO uint32_t ErrorCode; /*!< DSI Error code */ + uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ +}DSI_HandleTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DSI_DCS_Command DSI DCS Command + * @{ + */ +#define DSI_ENTER_IDLE_MODE 0x39 +#define DSI_ENTER_INVERT_MODE 0x21 +#define DSI_ENTER_NORMAL_MODE 0x13 +#define DSI_ENTER_PARTIAL_MODE 0x12 +#define DSI_ENTER_SLEEP_MODE 0x10 +#define DSI_EXIT_IDLE_MODE 0x38 +#define DSI_EXIT_INVERT_MODE 0x20 +#define DSI_EXIT_SLEEP_MODE 0x11 +#define DSI_GET_3D_CONTROL 0x3F +#define DSI_GET_ADDRESS_MODE 0x0B +#define DSI_GET_BLUE_CHANNEL 0x08 +#define DSI_GET_DIAGNOSTIC_RESULT 0x0F +#define DSI_GET_DISPLAY_MODE 0x0D +#define DSI_GET_GREEN_CHANNEL 0x07 +#define DSI_GET_PIXEL_FORMAT 0x0C +#define DSI_GET_POWER_MODE 0x0A +#define DSI_GET_RED_CHANNEL 0x06 +#define DSI_GET_SCANLINE 0x45 +#define DSI_GET_SIGNAL_MODE 0x0E +#define DSI_NOP 0x00 +#define DSI_READ_DDB_CONTINUE 0xA8 +#define DSI_READ_DDB_START 0xA1 +#define DSI_READ_MEMORY_CONTINUE 0x3E +#define DSI_READ_MEMORY_START 0x2E +#define DSI_SET_3D_CONTROL 0x3D +#define DSI_SET_ADDRESS_MODE 0x36 +#define DSI_SET_COLUMN_ADDRESS 0x2A +#define DSI_SET_DISPLAY_OFF 0x28 +#define DSI_SET_DISPLAY_ON 0x29 +#define DSI_SET_GAMMA_CURVE 0x26 +#define DSI_SET_PAGE_ADDRESS 0x2B +#define DSI_SET_PARTIAL_COLUMNS 0x31 +#define DSI_SET_PARTIAL_ROWS 0x30 +#define DSI_SET_PIXEL_FORMAT 0x3A +#define DSI_SET_SCROLL_AREA 0x33 +#define DSI_SET_SCROLL_START 0x37 +#define DSI_SET_TEAR_OFF 0x34 +#define DSI_SET_TEAR_ON 0x35 +#define DSI_SET_TEAR_SCANLINE 0x44 +#define DSI_SET_VSYNC_TIMING 0x40 +#define DSI_SOFT_RESET 0x01 +#define DSI_WRITE_LUT 0x2D +#define DSI_WRITE_MEMORY_CONTINUE 0x3C +#define DSI_WRITE_MEMORY_START 0x2C +/** + * @} + */ + +/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type + * @{ + */ +#define DSI_VID_MODE_NB_PULSES 0 +#define DSI_VID_MODE_NB_EVENTS 1 +#define DSI_VID_MODE_BURST 2 +/** + * @} + */ + +/** @defgroup DSI_Color_Mode DSI Color Mode + * @{ + */ +#define DSI_COLOR_MODE_FULL 0 +#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM +/** + * @} + */ + +/** @defgroup DSI_ShutDown DSI ShutDown + * @{ + */ +#define DSI_DISPLAY_ON 0 +#define DSI_DISPLAY_OFF DSI_WCR_SHTDN +/** + * @} + */ + +/** @defgroup DSI_LP_Command DSI LP Command + * @{ + */ +#define DSI_LP_COMMAND_DISABLE 0 +#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE +/** + * @} + */ + +/** @defgroup DSI_LP_HFP DSI LP HFP + * @{ + */ +#define DSI_LP_HFP_DISABLE 0 +#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE +/** + * @} + */ + +/** @defgroup DSI_LP_HBP DSI LP HBP + * @{ + */ +#define DSI_LP_HBP_DISABLE 0 +#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VACT DSI LP VACT + * @{ + */ +#define DSI_LP_VACT_DISABLE 0 +#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE +/** + * @} + */ + +/** @defgroup DSI_LP_VFP DSI LP VFP + * @{ + */ +#define DSI_LP_VFP_DISABLE 0 +#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE +/** + * @} + */ + +/** @defgroup DSI_LP_VBP DSI LP VBP + * @{ + */ +#define DSI_LP_VBP_DISABLE 0 +#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VSYNC DSI LP VSYNC + * @{ + */ +#define DSI_LP_VSYNC_DISABLE 0 +#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE +/** + * @} + */ + +/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge + * @{ + */ +#define DSI_FBTAA_DISABLE 0 +#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE +/** + * @} + */ + +/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source + * @{ + */ +#define DSI_TE_DSILINK 0 +#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC +/** + * @} + */ + +/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity + * @{ + */ +#define DSI_TE_RISING_EDGE 0 +#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL +/** + * @} + */ + +/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity + * @{ + */ +#define DSI_VSYNC_FALLING 0 +#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL +/** + * @} + */ + +/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh + * @{ + */ +#define DSI_AR_DISABLE 0 +#define DSI_AR_ENABLE DSI_WCFGR_AR +/** + * @} + */ + +/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request + * @{ + */ +#define DSI_TE_ACKNOWLEDGE_DISABLE 0 +#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE +/** + * @} + */ + +/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request + * @{ + */ +#define DSI_ACKNOWLEDGE_DISABLE 0 +#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP + * @{ + */ +#define DSI_LP_GSW0P_DISABLE 0 +#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP + * @{ + */ +#define DSI_LP_GSW1P_DISABLE 0 +#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP + * @{ + */ +#define DSI_LP_GSW2P_DISABLE 0 +#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP + * @{ + */ +#define DSI_LP_GSR0P_DISABLE 0 +#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP + * @{ + */ +#define DSI_LP_GSR1P_DISABLE 0 +#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP + * @{ + */ +#define DSI_LP_GSR2P_DISABLE 0 +#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite + * @{ + */ +#define DSI_LP_GLW_DISABLE 0 +#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP + * @{ + */ +#define DSI_LP_DSW0P_DISABLE 0 +#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP + * @{ + */ +#define DSI_LP_DSW1P_DISABLE 0 +#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP + * @{ + */ +#define DSI_LP_DSR0P_DISABLE 0 +#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write + * @{ + */ +#define DSI_LP_DLW_DISABLE 0 +#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet + * @{ + */ +#define DSI_LP_MRDP_DISABLE 0 +#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS +/** + * @} + */ + +/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode + * @{ + */ +#define DSI_HS_PM_DISABLE 0 +#define DSI_HS_PM_ENABLE DSI_TCCR3_PM +/** + * @} + */ + + +/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control + * @{ + */ +#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0 +#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR +/** + * @} + */ + +/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes + * @{ + */ +#define DSI_ONE_DATA_LANE 0 +#define DSI_TWO_DATA_LANES 1 +/** + * @} + */ + +/** @defgroup DSI_FlowControl DSI Flow Control + * @{ + */ +#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE +#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE +#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE +#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE +#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE +#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ + DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ + DSI_FLOW_CONTROL_EOTP_TX) +/** + * @} + */ + +/** @defgroup DSI_Color_Coding DSI Color Coding + * @{ + */ +#define DSI_RGB565 ((uint32_t)0x00000000) /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ +#define DSI_RGB666 ((uint32_t)0x00000003) /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ +#define DSI_RGB888 ((uint32_t)0x00000005) +/** + * @} + */ + +/** @defgroup DSI_LooselyPacked DSI Loosely Packed + * @{ + */ +#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE +#define DSI_LOOSELY_PACKED_DISABLE 0 +/** + * @} + */ + +/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity + * @{ + */ +#define DSI_HSYNC_ACTIVE_HIGH 0 +#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP +/** + * @} + */ + +/** @defgroup DSI_VSYNC_Polarity DSI VSYNC Polarity + * @{ + */ +#define DSI_VSYNC_ACTIVE_HIGH 0 +#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP +/** + * @} + */ + +/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity + * @{ + */ +#define DSI_DATA_ENABLE_ACTIVE_HIGH 0 +#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP +/** + * @} + */ + +/** @defgroup DSI_PLL_IDF DSI PLL IDF + * @{ + */ +#define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001) +#define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002) +#define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003) +#define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004) +#define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005) +#define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006) +#define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007) +/** + * @} + */ + +/** @defgroup DSI_PLL_ODF DSI PLL ODF + * @{ + */ +#define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000) +#define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001) +#define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002) +#define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003) +/** + * @} + */ + +/** @defgroup DSI_Flags DSI Flags + * @{ + */ +#define DSI_FLAG_TE DSI_WISR_TEIF +#define DSI_FLAG_ER DSI_WISR_ERIF +#define DSI_FLAG_BUSY DSI_WISR_BUSY +#define DSI_FLAG_PLLLS DSI_WISR_PLLLS +#define DSI_FLAG_PLLL DSI_WISR_PLLLIF +#define DSI_FLAG_PLLU DSI_WISR_PLLUIF +#define DSI_FLAG_RRS DSI_WISR_RRS +#define DSI_FLAG_RR DSI_WISR_RRIF +/** + * @} + */ + +/** @defgroup DSI_Interrupts DSI Interrupts + * @{ + */ +#define DSI_IT_TE DSI_WIER_TEIE +#define DSI_IT_ER DSI_WIER_ERIE +#define DSI_IT_PLLL DSI_WIER_PLLLIE +#define DSI_IT_PLLU DSI_WIER_PLLUIE +#define DSI_IT_RR DSI_WIER_RRIE +/** + * @} + */ + +/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005) /*!< DCS short write, no parameters */ +#define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015) /*!< DCS short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003) /*!< Generic short write, no parameters */ +#define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013) /*!< Generic short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023) /*!< Generic short write, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039) /*!< DCS long write */ +#define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029) /*!< Generic long write */ +/** + * @} + */ + +/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006) /*!< DCS short read */ +#define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004) /*!< Generic short read, no parameters */ +#define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014) /*!< Generic short read, one parameter */ +#define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024) /*!< Generic short read, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_Error_Data_Type DSI Error Data Type + * @{ + */ +#define HAL_DSI_ERROR_NONE 0 +#define HAL_DSI_ERROR_ACK ((uint32_t)0x00000001) /*!< acknowledge errors */ +#define HAL_DSI_ERROR_PHY ((uint32_t)0x00000002) /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX ((uint32_t)0x00000004) /*!< transmission error */ +#define HAL_DSI_ERROR_RX ((uint32_t)0x00000008) /*!< reception error */ +#define HAL_DSI_ERROR_ECC ((uint32_t)0x00000010) /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC ((uint32_t)0x00000020) /*!< CRC error */ +#define HAL_DSI_ERROR_PSE ((uint32_t)0x00000040) /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT ((uint32_t)0x00000080) /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF ((uint32_t)0x00000100) /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN ((uint32_t)0x00000200) /*!< Generic FIFO related errors */ +/** + * @} + */ + +/** @defgroup DSI_Lane_Group DSI Lane Group + * @{ + */ +#define DSI_CLOCK_LANE ((uint32_t)0x00000000) +#define DSI_DATA_LANES ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup DSI_Communication_Delay DSI Communication Delay + * @{ + */ +#define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000) +#define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001) +#define DSI_HS_DELAY ((uint32_t)0x00000002) +/** + * @} + */ + +/** @defgroup DSI_CustomLane DSI CustomLane + * @{ + */ +#define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000) +#define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup DSI_Lane_Select DSI Lane Select + * @{ + */ +#define DSI_CLOCK_LANE ((uint32_t)0x00000000) +#define DSI_DATA_LANE0 ((uint32_t)0x00000001) +#define DSI_DATA_LANE1 ((uint32_t)0x00000002) +/** + * @} + */ + +/** @defgroup DSI_PHY_Timing DSI PHY Timing + * @{ + */ +#define DSI_TCLK_POST ((uint32_t)0x00000000) +#define DSI_TLPX_CLK ((uint32_t)0x00000001) +#define DSI_THS_EXIT ((uint32_t)0x00000002) +#define DSI_TLPX_DATA ((uint32_t)0x00000003) +#define DSI_THS_ZERO ((uint32_t)0x00000004) +#define DSI_THS_TRAIL ((uint32_t)0x00000005) +#define DSI_THS_PREPARE ((uint32_t)0x00000006) +#define DSI_TCLK_ZERO ((uint32_t)0x00000007) +#define DSI_TCLK_PREPARE ((uint32_t)0x00000008) +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** + * @brief Enables the DSI host. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN) + +/** + * @brief Disables the DSI host. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN) + +/** + * @brief Enables the DSI wrapper. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN) + +/** + * @brief Disable the DSI wrapper. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN) + +/** + * @brief Enables the DSI PLL. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN) + +/** + * @brief Disables the DSI PLL. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN) + +/** + * @brief Enables the DSI regulator. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN) + +/** + * @brief Disables the DSI regulator. + * @param __HANDLE__: DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN) + +/** + * @brief Get the DSI pending flags. + * @param __HANDLE__: DSI handle. + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_BUSY : Busy Flag + * @arg DSI_FLAG_PLLLS: PLL Lock Status + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RRS : Regulator Ready Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) + +/** + * @brief Clears the DSI pending flags. + * @param __HANDLE__: DSI handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval None + */ +#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) + +/** + * @brief Enables the specified DSI interrupts. + * @param __HANDLE__: DSI handle. + * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified DSI interrupts. + * @param __HANDLE__: DSI handle + * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DSI interrupt has occurred or not. + * @param __HANDLE__: DSI handle + * @param __INTERRUPT__: specifies the DSI interrupt source to check. + * This parameter can be one of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WISR & (__INTERRUPT__)) + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DSI_Exported_Functions DSI Exported Functions + * @{ + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); + +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); +void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimings); +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Nbparams, + uint32_t Param1, + uint8_t* ParametersTable); +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t* Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t* ParametersTable); +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value); +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); + +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup DSI_Private_Types DSI Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup DSI_Private_Defines DSI Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Variables DSI Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Constants DSI Private Constants + * @{ + */ +#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037) /*!< Maximum return packet configuration */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DSI_Private_Macros DSI Private Macros + * @{ + */ +#define IS_DSI_PLL_NDIV(NDIV) ((10 <= (NDIV)) && ((NDIV) <= 125)) +#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ + ((IDF) == DSI_PLL_IN_DIV2) || \ + ((IDF) == DSI_PLL_IN_DIV3) || \ + ((IDF) == DSI_PLL_IN_DIV4) || \ + ((IDF) == DSI_PLL_IN_DIV5) || \ + ((IDF) == DSI_PLL_IN_DIV6) || \ + ((IDF) == DSI_PLL_IN_DIV7)) +#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ + ((ODF) == DSI_PLL_OUT_DIV2) || \ + ((ODF) == DSI_PLL_OUT_DIV4) || \ + ((ODF) == DSI_PLL_OUT_DIV8)) +#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) +#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) +#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) +#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5) +#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) +#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ + ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ + ((VideoModeType) == DSI_VID_MODE_BURST)) +#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) +#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) +#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) +#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) +#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) +#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) +#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) +#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) +#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) +#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) +#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) +#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) +#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) +#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) +#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) +#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) +#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) +#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) +#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) +#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) +#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) +#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) +#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) +#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) +#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) +#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) +#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) +#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ + ((MODE) == DSI_GEN_LONG_PKT_WRITE)) +#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) +#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) +#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) +#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) +#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) +#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ + ((Timing) == DSI_TLPX_CLK ) || \ + ((Timing) == DSI_THS_EXIT ) || \ + ((Timing) == DSI_TLPX_DATA ) || \ + ((Timing) == DSI_THS_ZERO ) || \ + ((Timing) == DSI_THS_TRAIL ) || \ + ((Timing) == DSI_THS_PREPARE ) || \ + ((Timing) == DSI_TCLK_ZERO ) || \ + ((Timing) == DSI_TCLK_PREPARE)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Functions DSI Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* STM32F469xx || STM32F479xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_DSI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c index e458ede97e..f57c994483 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_eth.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: @@ -112,7 +112,8 @@ #ifdef HAL_ETH_MODULE_ENABLED -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -2004,7 +2005,8 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ + STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #endif /* HAL_ETH_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h index 79e936e96c..d6647c3caf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_eth.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of ETH HAL module. ****************************************************************************** * @attention @@ -43,7 +43,8 @@ extern "C" { #endif -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -2090,7 +2091,7 @@ typedef struct * @brief Disables the rising edge trigger to the ETH External interrupt line. * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) /** * @brief Enables falling edge trigger to the ETH External interrupt line. @@ -2205,7 +2206,8 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ + STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c index 4492f55d5e..94fe4f84be 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -111,7 +111,6 @@ /** @addtogroup FLASH_Private_Constants * @{ */ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ /** * @} @@ -137,6 +136,7 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data); static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); static void FLASH_SetErrorCode(void); +extern void FLASH_FlushCaches(void); HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** @@ -178,10 +178,10 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* Process Locked */ __HAL_LOCK(&pFlash); - + /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); @@ -190,7 +190,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint if(TypeProgram == FLASH_TYPEPROGRAM_BYTE) { /*Program byte (8-bit) at a specified address.*/ - FLASH_Program_Byte(Address, (uint8_t) Data); + FLASH_Program_Byte(Address, (uint8_t) Data); } else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { @@ -207,17 +207,17 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /*Program double word (64-bit) at a specified address.*/ FLASH_Program_DoubleWord(Address, Data); } - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); + FLASH->CR &= (~FLASH_CR_PG); } - + /* Process Unlocked */ __HAL_UNLOCK(&pFlash); - + return status; } @@ -245,10 +245,6 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* Enable Error source interrupt */ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR); pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; pFlash.Address = Address; @@ -283,59 +279,84 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u */ void HAL_FLASH_IRQHandler(void) { - uint32_t temp; + uint32_t addresstmp = 0; + + /* Check FLASH operation error flags */ + if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) + { + /*return the faulty sector*/ + addresstmp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFF; + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /*return the faulty bank*/ + addresstmp = pFlash.Bank; + } + else + { + /*return the faulty address*/ + addresstmp = pFlash.Address; + } + + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } - /* If the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - - /* If the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_MER_BIT); - /* Check FLASH End of Operation flag */ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) { /*Nb of sector to erased can be decreased*/ pFlash.NbSectorsToErase--; - + /* Check if there are still sectors to erase*/ if(pFlash.NbSectorsToErase != 0) { - temp = pFlash.Sector; + addresstmp = pFlash.Sector; /*Indicate user which sector has been erased*/ - HAL_FLASH_EndOfOperationCallback(temp); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR); - + HAL_FLASH_EndOfOperationCallback(addresstmp); + /*Increment sector number*/ pFlash.Sector++; - temp = pFlash.Sector; - FLASH_Erase_Sector(temp, pFlash.VoltageForErase); + addresstmp = pFlash.Sector; + FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase); } else { /*No more sectors to Erase, user callback can be called.*/ /*Reset Sector and stop Erase sectors procedure*/ - pFlash.Sector = temp = 0xFFFFFFFF; + pFlash.Sector = addresstmp = 0xFFFFFFFF; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches() ; + /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(temp); - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + HAL_FLASH_EndOfOperationCallback(addresstmp); } } else { if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) { - /*MassErase ended. Return the selected bank*/ + /* MassErase ended. Return the selected bank */ + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches() ; + /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Bank); } @@ -346,58 +367,23 @@ void HAL_FLASH_IRQHandler(void) HAL_FLASH_EndOfOperationCallback(pFlash.Address); } pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } - - } - - /* Check FLASH operation error flags */ - if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ - FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) - { - /*return the faulty sector*/ - temp = pFlash.Sector; - pFlash.Sector = 0xFFFFFFFF; - } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) - { - /*return the faulty bank*/ - temp = pFlash.Bank; - } - else - { - /*return the faulty address*/ - temp = pFlash.Address; - } - - /*Save the Error code*/ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(temp); - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR |\ - FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR); - - /*Stop the procedure ongoing*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { + /* Operation is completed, disable the PG, SER, SNB and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT)); + /* Disable End of FLASH Operation interrupt */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); - + /* Disable Error source interrupt */ __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); - + /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } - } /** @@ -592,6 +578,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) } } } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) @@ -601,7 +594,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) return HAL_ERROR; } - /* If there is an error flag set */ + /* If there is no error flag set */ return HAL_OK; } @@ -624,7 +617,7 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) assert_param(IS_FLASH_ADDRESS(Address)); /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; FLASH->CR |= FLASH_CR_PG; @@ -650,7 +643,7 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) assert_param(IS_FLASH_ADDRESS(Address)); /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= FLASH_PSIZE_WORD; FLASH->CR |= FLASH_CR_PG; @@ -675,7 +668,7 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) assert_param(IS_FLASH_ADDRESS(Address)); /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= FLASH_PSIZE_HALF_WORD; FLASH->CR |= FLASH_CR_PG; @@ -700,7 +693,7 @@ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) assert_param(IS_FLASH_ADDRESS(Address)); /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= FLASH_PSIZE_BYTE; FLASH->CR |= FLASH_CR_PG; @@ -716,31 +709,49 @@ static void FLASH_SetErrorCode(void) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + + /* Clear FLASH write protection error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR); } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) { pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + + /* Clear FLASH Programming alignment error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR); } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) { pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; + + /* Clear FLASH Programming parallelism error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR); } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET) { pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; + + /* Clear FLASH Programming sequence error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR); } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) { pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + + /* Clear FLASH Proprietary readout protection error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR); } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) { pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; + + /* Clear FLASH Operation error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR); } } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h index 1060645e13..0a92241b3d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention @@ -187,7 +187,7 @@ typedef struct */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency + * @param __LATENCY__: FLASH Latency * The value of this parameter depend on device used within the same series * @retval none */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c index 97ee094278..d51fcc1045 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: @@ -25,7 +25,8 @@ ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure and program the FLASH memory - of all STM32F427xx/437xx andSTM32F429xx/439xx devices. It includes + of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx + devices. It includes (#) FLASH Memory Erase functions: (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions @@ -96,7 +97,6 @@ /** @addtogroup FLASHEx_Private_Constants * @{ */ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ /** * @} @@ -118,6 +118,7 @@ extern FLASH_ProcessTypeDef pFlash; */ /* Option bytes control */ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); +void FLASH_FlushCaches(void); static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks); static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks); static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); @@ -128,16 +129,17 @@ static uint16_t FLASH_OB_GetWRP(void); static uint8_t FLASH_OB_GetRDP(void); static uint8_t FLASH_OB_GetBOR(void); -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector); static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector); -#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); -static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** @@ -158,7 +160,7 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); =============================================================================== [..] This subsection provides a set of functions allowing to manage the Extension FLASH - programming operations Operations. + programming operations. @endverbatim * @{ @@ -217,9 +219,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - /* If the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; + /* If the erase operation is completed, disable the SER and SNB Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); if(status != HAL_OK) { @@ -229,6 +230,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t } } } + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); } /* Process Unlocked */ @@ -349,6 +352,35 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) return status; } +/** + * @brief Flush the instruction and data caches + * @retval None + */ +void FLASH_FlushCaches(void) +{ + /* Flush instruction cache */ + if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)) + { + /* Disable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + /* Reset instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + /* Enable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + } + + /* Flush data cache */ + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN)) + { + /* Disable data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + /* Reset data cache */ + __HAL_FLASH_DATA_CACHE_RESET(); + /* Enable data cache */ + __HAL_FLASH_DATA_CACHE_ENABLE(); + } +} + /** * @brief Get the Option byte configuration * @param pOBInit: pointer to an FLASH_OBInitStruct structure that @@ -362,10 +394,10 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) /*Get WRP*/ pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP(); - + /*Get RDP Level*/ pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP(); - + /*Get USER*/ pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser(); @@ -373,8 +405,10 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR(); } -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /** * @brief Program option bytes * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that @@ -397,30 +431,32 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE) { /*Enable of Write protection on the selected Sector*/ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors); -#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); -#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */ } else { /*Disable of Write protection on the selected Sector*/ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors); -#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); -#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */ } } -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /*Program BOOT config option byte*/ if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) { status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); } -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ return status; } @@ -434,10 +470,11 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO */ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) { -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) /*Get Sector*/ pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ /*Get Sector for Bank1*/ pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); @@ -446,7 +483,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) /*Get Boot config OB*/ pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS; -#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */ } /** @@ -456,7 +493,8 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) * Global Read Out Protection modification (from level1 to level0) * @note Once SPRMOD bit is active unprotection of a protected sector is not possible * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx devices. + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ + * STM32F469xx/STM32F479xx devices. * * @retval HAL Status */ @@ -480,7 +518,8 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) * Global Read Out Protection modification (from level1 to level0) * @note Once SPRMOD bit is active unprotection of a protected sector is not possible * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx devices. + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ + * STM32F469xx/STM32F479xx devices. * * @retval HAL Status */ @@ -496,12 +535,13 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) return HAL_OK; } -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\ + STM32F411xE || STM32F469xx || STM32F479xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Returns the FLASH Write Protection Option Bytes value for Bank 2 - * @note This function can be used only for STM32F427X and STM32F429X devices. + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices. * @retval The FLASH Write Protection Option Bytes value */ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) @@ -509,13 +549,13 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) /* Return the FLASH write protection Register value */ return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); } -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ /** * @} */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Full erase of FLASH memory sectors * @param VoltageRange: The device voltage range which defines the erase parallelism. @@ -546,7 +586,7 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) assert_param(IS_FLASH_BANK(Banks)); /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= tmp_psize; if(Banks == FLASH_BANK_BOTH) { @@ -614,9 +654,9 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) Sector += 4; } /* If the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); FLASH->CR |= FLASH_CR_STRT; } @@ -631,7 +671,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) * * @param WRPSector: specifies the sector(s) to be write protected. * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 * @arg OB_WRP_SECTOR_All * @note BANK2 starts from OB_WRP_SECTOR_12 * @@ -702,7 +742,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) * * @param WRPSector: specifies the sector(s) to be write protected. * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 * @arg OB_WRP_Sector_All * @note BANK2 starts from OB_WRP_SECTOR_12 * @@ -924,10 +964,11 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se } -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) /** * @brief Mass erase of FLASH memory * @param VoltageRange: The device voltage range which defines the erase parallelism. @@ -954,12 +995,12 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /* Check the parameters */ assert_param(IS_VOLTAGERANGE(VoltageRange)); assert_param(IS_FLASH_BANK(Banks)); - + /* If the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= tmp_psize; + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT; } /** @@ -1005,9 +1046,9 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) } /* If the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); FLASH->CR |= FLASH_CR_STRT; } @@ -1083,9 +1124,10 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) return status; } -#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F411xE || STM32F446xx */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) /** * @brief Enable the read/write protection (PCROP) of the desired sectors. * @note This function can be used only for STM32F401xx devices. @@ -1141,7 +1183,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) return status; } -#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ /** * @brief Set the read protection level. @@ -1233,7 +1275,8 @@ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level; - return HAL_OK; + return HAL_OK; + } /** @@ -1281,7 +1324,7 @@ static uint8_t FLASH_OB_GetRDP(void) { readstatus = OB_RDP_LEVEL_0; } - + return readstatus; } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h index a917577f73..7930977c73 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention @@ -111,8 +111,10 @@ typedef struct /** * @brief FLASH Advanced Option Bytes Program structure definition */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) typedef struct { uint32_t OptionType; /*!< Option byte to be configured for extension. @@ -121,12 +123,12 @@ typedef struct uint32_t PCROPState; /*!< PCROP activation or deactivation. This parameter can be a value of @ref FLASHEx_PCROP_State */ -#if defined (STM32F401xC) || defined (STM32F401xE) || defined (STM32F411xE) || defined (STM32F446xx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) uint16_t Sectors; /*!< specifies the sector(s) set for PCROP. This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ -#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors. This parameter must be a value of @ref FLASHEx_Banks */ @@ -139,9 +141,9 @@ typedef struct uint8_t BootConfig; /*!< Specifies Option bytes for boot config. This parameter can be a value of @ref FLASHEx_Dual_Boot */ -#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ } FLASH_AdvOBProgramInitTypeDef; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -243,7 +245,9 @@ typedef struct */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /** @defgroup FLASHEx_PCROP_State FLASH PCROP State * @{ */ @@ -252,19 +256,22 @@ typedef struct /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ /** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) #define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!< PCROP option byte configuration */ #define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02) /*!< BOOTConfig option byte configuration */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) #define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFF000000) == 0x00000000) && ((SECTOR) != 0x00000000)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) @@ -808,30 +883,42 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void); #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) #endif /* STM32F401xC */ -#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) #define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -#endif /* STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #if defined(STM32F401xC) #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) #endif /* STM32F401xC */ -#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -#endif /* STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) #define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c index 1bfb475347..1ad8018abd 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief FLASH RAMFUNC module driver. * This file provides a FLASH firmware functions which should be * executed from internal SRAM @@ -74,10 +74,8 @@ * @brief FLASH functions executed from RAM * @{ */ - #ifdef HAL_FLASH_MODULE_ENABLED - -#if defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -181,7 +179,7 @@ __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void) * @} */ -#endif /* STM32F411xE || STM32F446xx */ +#endif /* STM32F410xx || STM32F411xE || STM32F446xx */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h index db308ac4c2..40d204e9ea 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention @@ -42,8 +42,7 @@ #ifdef __cplusplus extern "C" { #endif - -#if defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -54,7 +53,7 @@ /** @addtogroup FLASHRAMFUNC * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ @@ -77,7 +76,6 @@ __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void); /** * @} */ -#endif /* STM32F411xE */ /** * @} @@ -86,7 +84,8 @@ __RAM_FUNC HAL_FLASHEx_DisableFlashSleepMode(void); /** * @} */ - + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx */ #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c index 79b1c5bdf3..6890d21f78 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_fmpi2c.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief FMPI2C HAL module driver. * * This file provides firmware functions to manage the following @@ -193,7 +193,7 @@ #ifdef HAL_FMPI2C_MODULE_ENABLED -#if defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -253,12 +253,12 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAd * @{ */ -/** @defgroup FMPI2C_Exported_Functions_Group1 Initialization/de-initialization functions +/** @defgroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== - ##### Initialization/de-initialization functions ##### + ##### Initialization and de-initialization functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to initialize and de-initialiaze the FMPI2Cx peripheral: @@ -4085,7 +4085,7 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAd /** * @} */ -#endif /* STM32F446xx */ +#endif /* STM32F410xx || STM32F446xx */ #endif /* HAL_FMPI2C_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h index dff8815506..73a2f35340 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_fmpi2c.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of FMPI2C HAL module. ****************************************************************************** * @attention @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -566,7 +566,7 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hFMPI2C); /** * @} */ -#endif /* STM32F446xx */ +#endif /* STM32F410xx || STM32F446xx */ #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c index 431b1a16c0..73caf96074 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_fmpi2c_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Extended FMPI2C HAL module driver. * * This file provides firmware functions to manage the following @@ -71,7 +71,7 @@ #ifdef HAL_FMPI2C_MODULE_ENABLED -#if defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -313,7 +313,7 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ -#endif /* STM32F446xx */ +#endif /* STM32F410xx || STM32F446xx */ #endif /* HAL_FMPI2C_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h index b485c9733b..79d8813d6a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_fmpi2c_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of FMPI2C HAL Extension module. ****************************************************************************** * @attention @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -140,7 +140,7 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** * @} */ -#endif /* STM32F446xx */ +#endif /* STM32F410xx || STM32F446xx */ #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c index 56275fea9a..9614d586d0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h index f31c0ad75b..1408571c43 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -156,11 +156,11 @@ typedef enum /** @defgroup GPIO_speed_define GPIO speed define * @brief GPIO Output Maximum frequency * @{ - */ -#define GPIO_SPEED_LOW ((uint32_t)0x00000000) /*!< Low speed */ -#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */ -#define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */ -#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */ + */ +#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< IO works at 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */ /** * @} */ @@ -293,8 +293,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); ((MODE) == GPIO_MODE_EVT_FALLING) ||\ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ ((MODE) == GPIO_MODE_ANALOG)) -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \ - ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ ((PULL) == GPIO_PULLDOWN)) /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h index ddd191dd36..38e39f4e41 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention @@ -62,10 +62,10 @@ /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection * @{ - */ - -/*------------------------------------------ STM32F429xx/STM32F439xx --------------------------------------*/ -#if defined (STM32F429xx) || defined (STM32F439xx) + */ + +/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/ +#if defined(STM32F429xx) || defined(STM32F439xx) /** * @brief AF 0 selection */ @@ -181,10 +181,10 @@ */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F429xx || STM32F439xx */ -/*------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*---------------------------------- STM32F427xx/STM32F437xx--------------------------------*/ -#if defined (STM32F427xx) || defined (STM32F437xx) +/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) /** * @brief AF 0 selection */ @@ -296,10 +296,10 @@ */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F427xx || STM32F437xx */ -/*------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*---------------------------------- STM32F407xx/STM32F417xx--------------------------------*/ -#if defined (STM32F407xx) || defined (STM32F417xx) +/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ +#if defined(STM32F407xx) || defined(STM32F417xx) /** * @brief AF 0 selection */ @@ -402,10 +402,10 @@ */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F407xx || STM32F417xx */ -/*------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*---------------------------------- STM32F405xx/STM32F415xx--------------------------------*/ -#if defined (STM32F405xx) || defined (STM32F415xx) +/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) /** * @brief AF 0 selection */ @@ -499,9 +499,9 @@ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F405xx || STM32F415xx */ -/*------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*---------------------------------------- STM32F401xx--------------------------------------*/ +/*---------------------------------------- STM32F401xx------------------------*/ #if defined(STM32F401xC) || defined(STM32F401xE) /** * @brief AF 0 selection @@ -545,7 +545,7 @@ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ /** * @brief AF 6 selection @@ -588,9 +588,8 @@ */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F401xC || STM32F401xE */ -/*------------------------------------------------------------------------------------------*/ - -/*---------------------------------------- STM32F411xx--------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/*---------------------------------------- STM32F411xx------------------------*/ #if defined(STM32F411xE) /** * @brief AF 0 selection @@ -640,11 +639,12 @@ /** * @brief AF 6 selection */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ #define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ #define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + /** * @brief AF 7 selection */ @@ -665,7 +665,6 @@ #define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ #define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ - /** * @brief AF 10 selection */ @@ -681,8 +680,83 @@ */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F411xE */ -/*---------------------------------------- STM32F446xx -------------------------------------------*/ -#if defined (STM32F446xx) + +/*---------------------------------------- STM32F410xx------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#if defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#endif /* STM32F410Cx || STM32F410Rx */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ +#if defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#endif /* STM32F410Cx || STM32F410Rx */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/*---------------------------------------- STM32F446xx -----------------------*/ +#if defined(STM32F446xx) /** * @brief AF 0 selection */ @@ -748,7 +822,7 @@ #define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ #define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */ +#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */ /** * @brief AF 8 selection @@ -756,7 +830,7 @@ #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */ #define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ /** @@ -800,7 +874,132 @@ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ +/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0xA) /* QSPI Alternate Function mapping */ + + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ /** * @} */ @@ -817,7 +1016,7 @@ * @} */ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions * @{ */ @@ -842,7 +1041,7 @@ /** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index * @{ */ -#if defined (STM32F405xx) || defined (STM32F415xx) || defined (STM32F407xx) || defined (STM32F417xx) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -854,7 +1053,8 @@ ((__GPIOx__) == (GPIOI))? 8U : 9U) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -#if defined (STM32F427xx) || defined (STM32F437xx) || defined (STM32F429xx) || defined (STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -865,9 +1065,16 @@ ((__GPIOx__) == (GPIOH))? 7U :\ ((__GPIOx__) == (GPIOI))? 8U :\ ((__GPIOx__) == (GPIOJ))? 9U : 10U) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#if defined (STM32F401xC) || defined (STM32F401xE) || defined (STM32F411xE) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -875,7 +1082,7 @@ ((__GPIOx__) == (GPIOE))? 4U : 5U) #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ -#if defined (STM32F446xx) +#if defined(STM32F446xx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -883,7 +1090,7 @@ ((__GPIOx__) == (GPIOE))? 4U :\ ((__GPIOx__) == (GPIOF))? 5U :\ ((__GPIOx__) == (GPIOG))? 6U : 8U) -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ /** * @} @@ -892,8 +1099,8 @@ /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function * @{ */ -/*------------------------- STM32F429xx/STM32F439xx---------------------------*/ -#if defined (STM32F429xx) || defined (STM32F439xx) +/*------------------------- STM32F429xx/STM32F439xx---------------------------*/ +#if defined(STM32F429xx) || defined(STM32F439xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ @@ -918,10 +1125,10 @@ ((AF) == GPIO_AF14_LTDC)) #endif /* STM32F429xx || STM32F439xx */ -/*------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*---------------------------------- STM32F427xx/STM32F437xx--------------------------------*/ -#if defined (STM32F427xx) || defined (STM32F437xx) +/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ @@ -945,10 +1152,10 @@ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1)) #endif /* STM32F427xx || STM32F437xx */ -/*------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*---------------------------------- STM32F407xx/STM32F417xx--------------------------------*/ -#if defined (STM32F407xx) || defined (STM32F417xx) +/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ +#if defined(STM32F407xx) || defined(STM32F417xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ @@ -969,10 +1176,10 @@ ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT)) #endif /* STM32F407xx || STM32F417xx */ -/*------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*---------------------------------- STM32F405xx/STM32F415xx--------------------------------*/ -#if defined (STM32F405xx) || defined (STM32F415xx) +/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ @@ -993,9 +1200,9 @@ #endif /* STM32F405xx || STM32F415xx */ -/*------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*---------------------------------------- STM32F401xx--------------------------------------*/ +/*---------------------------------------- STM32F401xx------------------------*/ #if defined(STM32F401xC) || defined(STM32F401xE) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ @@ -1012,9 +1219,13 @@ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT)) #endif /* STM32F401xC || STM32F401xE */ -/*------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ +/*---------------------------------------- STM32F410xx------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_GPIO_AF(AF) (((AF) < 10) || ((AF) == 15)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ -/*---------------------------------------- STM32F411xx--------------------------------------*/ +/*---------------------------------------- STM32F411xx------------------------*/ #if defined(STM32F411xE) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ @@ -1033,9 +1244,9 @@ ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT)) #endif /* STM32F411xE */ -/*----------------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*----------------------------------------------- STM32F446xx ----------------------------------------*/ +/*----------------------------------------------- STM32F446xx ----------------*/ #if defined(STM32F446xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ @@ -1058,13 +1269,43 @@ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI2) || \ - ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_SPI3) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF9_QSPI) || \ + ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_SPI3) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF9_QSPI) || \ ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QSPI)) #endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------------------- STM32F469xx/STM32F479xx --------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI) || \ + ((AF) == GPIO_AF9_QSPI) || ((AF) == GPIO_AF10_QSPI)) + +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c index 1dc145a6e8..cdfd97ad6c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hash.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: @@ -109,7 +109,7 @@ #ifdef HAL_HASH_MODULE_ENABLED -#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) +#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -177,7 +177,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) } /* Configure the number of valid bits in last word of the message */ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4)); - + /* Set the HASH DMA transfer complete */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; @@ -719,10 +719,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf */ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - /* Check the parameters */ assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size)); - + /* Process Locked */ __HAL_LOCK(hhash); @@ -923,12 +922,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB __HAL_HASH_START_DIGEST(); /* Reset buffer counter */ hhash->HashInCount = 0; - /* Call Input data transfer complete callback */ HAL_HASH_InCpltCallback(hhash); } } - + /* Process Unlocked */ __HAL_UNLOCK(hhash); @@ -975,7 +973,6 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn the message digest of a new message */ HASH->CR |= HASH_CR_INIT; } - /* Reset interrupt counter */ hhash->HashITCounter = 0; @@ -1084,7 +1081,6 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn __HAL_HASH_START_DIGEST(); /* Reset buffer counter */ hhash->HashInCount = 0; - /* Call Input data transfer complete callback */ HAL_HASH_InCpltCallback(hhash); } @@ -1849,7 +1845,7 @@ HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) * @} */ -#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */ +#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */ #endif /* HAL_HASH_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h index fb39cdd772..f88b95e094 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hash.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) +#if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -243,6 +243,7 @@ typedef struct */ #define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\ ((HASH->SR & (__FLAG__)) == (__FLAG__))) + /** * @brief Enable the multiple DMA mode. * This feature is available only in STM32F429x and STM32F439x devices. @@ -431,7 +432,7 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); * @} */ -#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */ +#endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c index 1daa4b54c1..156b744381 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hash_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief HASH HAL Extension module driver. * This file provides firmware functions to manage the following * functionalities of HASH peripheral: @@ -106,7 +106,7 @@ #ifdef HAL_HASH_MODULE_ENABLED -#if defined(STM32F437xx) || defined(STM32F439xx) +#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -266,7 +266,7 @@ static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma) } /* Configure the number of valid bits in last word of the message */ MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4)); - + /* Set the HASH DMA transfer complete */ hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt; @@ -944,7 +944,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t the message digest of a new message */ HASH->CR |= HASH_CR_INIT; } - /* Reset interrupt counter */ hhash->HashITCounter = 0; @@ -1045,9 +1044,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t __HAL_HASH_START_DIGEST(); /* Reset buffer counter */ hhash->HashInCount = 0; - - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); + /* Call Input data transfer complete callback */ + HAL_HASH_InCpltCallback(hhash); } } @@ -1097,7 +1095,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t the message digest of a new message */ HASH->CR |= HASH_CR_INIT; } - /* Reset interrupt counter */ hhash->HashITCounter = 0; @@ -1198,9 +1195,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t __HAL_HASH_START_DIGEST(); /* Reset buffer counter */ hhash->HashInCount = 0; - - /* Call Input data transfer complete callback */ - HAL_HASH_InCpltCallback(hhash); + /* Call Input data transfer complete callback */ + HAL_HASH_InCpltCallback(hhash); } } @@ -1628,7 +1624,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @} */ -#endif /* STM32F437xx || STM32F439xx */ +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ #endif /* HAL_HASH_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h index b4d2625b2d..d29a62f7cb 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F437xx) || defined(STM32F439xx) +#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -182,7 +182,7 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash); * @} */ -#endif /* STM32F437xx || STM32F439xx */ +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c index 2395983cdd..dc5745bb0d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hcd.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -84,7 +84,10 @@ */ #ifdef HAL_HCD_MODULE_ENABLED - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -1198,11 +1201,8 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) /** * @} */ - -/** - * @} - */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_HCD_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h index 5627d56f6a..a85178d079 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hcd.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention @@ -42,7 +42,10 @@ #ifdef __cplusplus extern "C" { #endif - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_ll_usb.h" @@ -177,7 +180,7 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); */ /* I/O operation functions ***************************************************/ -/** @addtogroup HCD_Exported_Functions_Group2 IO operation functions +/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions * @{ */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, @@ -238,10 +241,11 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); * @{ */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) ||\ - defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) + defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ ((INSTANCE) == USB_OTG_HS)) -#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS)) #endif /** @@ -259,7 +263,8 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** * @} */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c index 179b608b7a..982e72d12e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h index dc58d5fa78..bcf13b8dcf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c index b829d3b62a..f30277472b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief I2C Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C extension peripheral: @@ -72,7 +72,8 @@ #ifdef HAL_I2C_MODULE_ENABLED #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -190,7 +191,8 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ /** * @} */ -#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F446xx */ +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ + STM32F401xE || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_I2C_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h index b3646208f3..23ace7a954 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention @@ -44,7 +44,8 @@ #endif #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -124,7 +125,8 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ * @} */ -#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F401xC ||\ + STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c index 487b12bad7..7ad67ee08e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -480,7 +480,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin { return HAL_TIMEOUT; } - } + } /* Check if Slave mode is selected */ if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) { diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h index 18e6c2d17c..630b0cfc95 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -162,17 +162,6 @@ typedef struct * @} */ -/** @defgroup I2S_Clock_Source I2S Clock Source - * @{ - */ -#define I2S_CLOCK_PLL ((uint32_t)0x00000000) -#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001) -#define I2S_CLOCK_PLLR ((uint32_t)0x00000002) -#define I2S_CLOCK_PLLSRC ((uint32_t)0x00000003) -/** - * @} - */ - /** @defgroup I2S_Mode I2S Mode * @{ */ @@ -438,11 +427,6 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); /** @defgroup I2S_Private_Macros I2S Private Macros * @{ */ -#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \ - ((CLOCK) == I2S_CLOCK_PLLR) ||\ - ((CLOCK) == I2S_CLOCK_PLLSRC) ||\ - ((CLOCK) == I2S_CLOCK_PLL)) - #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ ((MODE) == I2S_MODE_SLAVE_RX) || \ ((MODE) == I2S_MODE_MASTER_TX) || \ @@ -471,8 +455,7 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ ((CPOL) == I2S_CPOL_HIGH)) - -#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE)) + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c index 7b9032412a..67c3374941 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2S extension peripheral: @@ -114,11 +114,6 @@ */ #ifdef HAL_I2S_MODULE_ENABLED - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -175,6 +170,10 @@ @endverbatim * @{ */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /** * @brief Initializes the I2S according to the specified parameters * in the I2S_InitTypeDef and create the associated handle. @@ -1004,7 +1003,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR; tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR; - /* I2Sext Overrun error interrupt occurred ------------------------------*/ + /* I2Sext Overrun error interrupt occurred -----------------------------*/ if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR)) { /* Clear I2Sext OVR Flag */ @@ -1031,7 +1030,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR); tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); - /* I2S Underrun error interrupt occurred --------------------------------*/ + /* I2S Underrun error interrupt occurred -------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { __HAL_I2S_CLEAR_UDRFLAG(hi2s); @@ -1058,7 +1057,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR); tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); - /* I2S Overrun error interrupt occurred ---------------------------------*/ + /* I2S Overrun error interrupt occurred --------------------------------*/ if((tmp1 != RESET) && (tmp2 != RESET)) { __HAL_I2S_CLEAR_OVRFLAG(hi2s); @@ -1082,7 +1081,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR; tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR; - /* I2Sext Underrun error interrupt occurred -----------------------------*/ + /* I2Sext Underrun error interrupt occurred ----------------------------*/ if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR)) { /* Clear I2Sext UDR Flag */ @@ -1106,7 +1105,6 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) * @} */ - /** * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains @@ -1220,7 +1218,8 @@ HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s) return HAL_BUSY; } } -#endif /* STM32F40xxx/ STM32F41xxx/ STM32F42xxx/ STM32F43xxx/ STM32F401xx/ STM32F411xx */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx ||\ + STM32F411xx || STM32F469xx || STM32F479xx */ /** * @brief DMA I2S transmit process complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains @@ -1239,13 +1238,15 @@ void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ + defined(STM32F479xx) if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) { /* Disable Rx DMA Request for the slave*/ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); } -#endif /* STM32F40xxx/ STM32F41xxx/ STM32F42xxx/ STM32F43xxx/ STM32F401xx/ STM32F411xx */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\ + STM32F469xx || STM32F479xx */ if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) { if(hi2s->RxXferCount == 0) @@ -1277,13 +1278,15 @@ void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ + defined(STM32F479xx) if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) { /* Disable Tx DMA Request for the slave*/ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); } -#endif /* STM32F40xxx/ STM32F41xxx/ STM32F42xxx/ STM32F43xxx/ STM32F401xx/ STM32F411xx */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\ + STM32F469xx || STM32F479xx */ hi2s->RxXferCount = 0; if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) { @@ -1315,8 +1318,8 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s) /* This variable used to store the I2S_CK_x (value in Hz) */ uint32_t i2ssourceclock = 0; - /* Configure SAI Clock based on SAI source clock selection */ -#if defined(STM32F446xx) + /* Configure 12S Clock based on I2S source clock selection */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) switch(hi2s->Init.ClockSource) { case I2S_CLOCK_EXTERNAL : @@ -1325,6 +1328,7 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s) i2ssourceclock = EXTERNAL_CLOCK_VALUE; break; } +#if defined(STM32F446xx) case I2S_CLOCK_PLL : { /* Configure the PLLI2S division factor */ @@ -1346,6 +1350,7 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s) i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28))); break; } +#endif /* STM32F446xx */ case I2S_CLOCK_PLLR : { /* Configure the PLLI2S division factor */ @@ -1388,18 +1393,16 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s) break; } } -#endif /* STM32F446xx */ +#endif /* STM32F410xx || STM32F446xx */ + #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F469xx) || defined(STM32F479xx) /* If an external I2S clock has to be used, the specific define should be set in the project configuration or in the stm32f4xx_conf.h file */ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL) { - /* Enable the External Clock selection */ - __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT); - /* Set the I2S clock to the external clock value */ i2ssourceclock = EXTERNAL_CLOCK_VALUE; } @@ -1423,7 +1426,7 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s) /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28))); } -#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ #if defined(STM32F411xE) @@ -1431,9 +1434,6 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s) in the project configuration or in the stm32f4xx_conf.h file */ if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL) { - /* Enable the External Clock selection */ - __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT); - /* Set the I2S clock to the external clock value */ i2ssourceclock = EXTERNAL_CLOCK_VALUE; } @@ -1461,12 +1461,15 @@ uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s) /* the return result is the value of SAI clock */ return i2ssourceclock; - } /** * @} */ +/** + * @} + */ + #endif /* HAL_I2S_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h index 81cdc624a5..85796dbd0e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -65,7 +65,37 @@ /* Exported constants --------------------------------------------------------*/ /** @defgroup I2SEx_Exported_Constants I2S Exported Constants * @{ - */ + */ + +/** @defgroup I2S_Clock_Source I2S Clock Source + * @{ + */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ + defined(STM32F479xx) +#define I2S_CLOCK_PLL ((uint32_t)0x00000000) +#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) +#define I2S_CLOCK_PLL ((uint32_t)0x00000000) +#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001) +#define I2S_CLOCK_PLLR ((uint32_t)0x00000002) +#define I2S_CLOCK_PLLSRC ((uint32_t)0x00000003) +#endif /* STM32F446xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define I2S_CLOCK_PLLSRC ((uint32_t)0x00000000) +#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001) +#define I2S_CLOCK_PLLR ((uint32_t)0x00000002) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/** + * @} + */ + /** * @} */ @@ -116,6 +146,36 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ /** @defgroup I2SEx_Private_Macros I2S Private Macros * @{ */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ + defined(STM32F479xx) +#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ + ((CLOCK) == I2S_CLOCK_PLL)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) +#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ + ((CLOCK) == I2S_CLOCK_PLL) ||\ + ((CLOCK) == I2S_CLOCK_PLLSRC) ||\ + ((CLOCK) == I2S_CLOCK_PLLR)) +#endif /* STM32F446xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ + ((CLOCK) == I2S_CLOCK_PLLSRC) ||\ + ((CLOCK) == I2S_CLOCK_PLLR)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Cx) || defined(STM32F410Rx) || \ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F410Cx || STM32F410Rx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c index 17d6f48161..aac88963f9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_irda.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA SIR ENDEC block (IrDA): diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h index 2516f7c50e..168fa46dd6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_irda.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c index 9ac08fb728..071940ff85 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h index f71195705c..83bd252216 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.c new file mode 100644 index 0000000000..db73e12236 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.c @@ -0,0 +1,1655 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_lptim.c + * @author MCD Application Team + * @version V1.4.1 + * @date 09-October-2015 + * @brief LPTIM HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Low Power Timer (LPTIM) peripheral: + * + Initialization and de-initialization functions. + * + Start/Stop operation functions in polling mode. + * + Start/Stop operation functions in interrupt mode. + * + Reading operation functions. + * + Peripheral State functions. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LPTIM HAL driver can be used as follows: + + (#)Initialize the LPTIM low level resources by implementing the + HAL_LPTIM_MspInit(): + (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE(). + (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()): + (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority(). + (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ(). + (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler(). + + (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function + configures mainly: + (##) The instance: LPTIM1. + (##) Clock: the counter clock. + - Source : it can be either the ULPTIM input (IN1) or one of + the internal clock; (APB, LSE, LSI or MSI). + - Prescaler: select the clock divider. + (##) UltraLowPowerClock : To be used only if the ULPTIM is selected + as counter clock source. + - Polarity: polarity of the active edge for the counter unit + if the ULPTIM input is selected. + - SampleTime: clock sampling time to configure the clock glitch + filter. + (##) Trigger: How the counter start. + - Source: trigger can be software or one of the hardware triggers. + - ActiveEdge : only for hardware trigger. + - SampleTime : trigger sampling time to configure the trigger + glitch filter. + (##) OutputPolarity : 2 opposite polarities are possibles. + (##) UpdateMode: specifies whether the update of the autoreload and + the compare values is done immediately or after the end of current + period. + + (#)Six modes are available: + + (##) PWM Mode: To generate a PWM signal with specified period and pulse, + call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption + mode. + + (##) One Pulse Mode: To generate pulse with specified width in response + to a stimulus, call HAL_LPTIM_OnePulse_Start() or + HAL_LPTIM_OnePulse_Start_IT() for interruption mode. + + (##) Set once Mode: In this mode, the output changes the level (from + low level to high level if the output polarity is configured high, else + the opposite) when a compare match occurs. To start this mode, call + HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for + interruption mode. + + (##) Encoder Mode: To use the encoder interface call + HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for + interruption mode. + + (##) Time out Mode: an active edge on one selected trigger input rests + the counter. The first trigger event will start the timer, any + successive trigger event will reset the counter and the timer will + restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or + HAL_LPTIM_TimeOut_Start_IT() for interruption mode. + + (##) Counter Mode: counter can be used to count external events on + the LPTIM Input1 or it can be used to count internal clock cycles. + To start this mode, call HAL_LPTIM_Counter_Start() or + HAL_LPTIM_Counter_Start_IT() for interruption mode. + + (#) User can stop any process by calling the corresponding API: + HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is + already started in interruption mode. + + (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral. + + @endverbatim + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup LPTIM LPTIM + * @brief LPTIM HAL module driver. + * @{ + */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/* Private types -------------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Types LPTIM Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Defines LPTIM Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** @defgroup LPTIM_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the LPTIM according to the specified parameters in the + LPTIM_InitTypeDef and creates the associated handle. + (+) DeInitialize the LPTIM peripheral. + (+) Initialize the LPTIM MSP. + (+) DeInitialize LPTIM MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the LPTIM according to the specified parameters in the + * LPTIM_InitTypeDef and creates the associated handle. + * @param hlptim: LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpcfgr = 0; + + /* Check the LPTIM handle allocation */ + if(hlptim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); + if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + { + assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); + } + assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); + assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); + } + assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); + assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); + assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); + + if(hlptim->State == HAL_LPTIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hlptim->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_LPTIM_MspInit(hlptim); + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + + if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); + } + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + } + + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE )); + + /* Set initialization parameters */ + tmpcfgr |= (hlptim->Init.Clock.Source | + hlptim->Init.Clock.Prescaler | + hlptim->Init.OutputPolarity | + hlptim->Init.UpdateMode | + hlptim->Init.CounterSource); + + if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + { + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + hlptim->Init.UltraLowPowerClock.SampleTime); + } + + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Enable External trigger and set the trigger source */ + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge | + hlptim->Init.Trigger.SampleTime); + } + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the LPTIM peripheral. + * @param hlptim: LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if(hlptim == NULL) + { + return HAL_ERROR; + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the LPTIM Peripheral Clock */ + __HAL_LPTIM_DISABLE(hlptim); + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_LPTIM_MspDeInit(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hlptim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the LPTIM MSP. + * @param hlptim: LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LPTIM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes LPTIM MSP. + * @param hlptim: LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LPTIM_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions + * @brief Start-Stop operation functions. + * +@verbatim + ============================================================================== + ##### LPTIM Start Stop operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start the PWM mode. + (+) Stop the PWM mode. + (+) Start the One pulse mode. + (+) Stop the One pulse mode. + (+) Start the Set once mode. + (+) Stop the Set once mode. + (+) Start the Encoder mode. + (+) Stop the Encoder mode. + (+) Start the Timeout mode. + (+) Stop the Timeout mode. + (+) Start the Counter mode. + (+) Stop the Counter mode. + + +@endverbatim + * @{ + */ + +/** + * @brief Starts the LPTIM PWM generation. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Pulse : Specifies the compare value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Pulse)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Reset WAVE bit to set PWM mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM PWM generation. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM PWM generation in interrupt mode. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF + * @param Pulse : Specifies the compare value. + * This parameter must be a value between 0x0000 and 0xFFFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Pulse)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Reset WAVE bit to set PWM mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable Autoreload write complete interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); + + /* Enable Compare write complete interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); + + /* Enable Autoreload match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); + + /* Enable Compare match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Enable external trigger interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + } + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM PWM generation in interrupt mode. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Disable Autoreload write complete interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); + + /* Disable Compare write complete interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); + + /* Disable Autoreload match interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); + + /* Disable Compare match interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* If external trigger source is used, then disable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Disable external trigger interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + } + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM One pulse generation. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Pulse : Specifies the compare value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Pulse)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Reset WAVE bit to set one pulse mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM One pulse generation. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM One pulse generation in interrupt mode. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Pulse : Specifies the compare value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Pulse)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Reset WAVE bit to set one pulse mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable Autoreload write complete interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); + + /* Enable Compare write complete interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); + + /* Enable Autoreload match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); + + /* Enable Compare match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Enable external trigger interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + } + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM One pulse generation in interrupt mode. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Disable Autoreload write complete interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); + + /* Disable Compare write complete interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); + + /* Disable Autoreload match interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); + + /* Disable Compare match interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* If external trigger source is used, then disable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Disable external trigger interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + } + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM in Set once mode. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Pulse : Specifies the compare value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Pulse)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Set WAVE bit to enable the set once mode */ + hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Start timer in single mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM Set once mode. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM Set once mode in interrupt mode. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Pulse : Specifies the compare value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Pulse)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Set WAVE bit to enable the set once mode */ + hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + + /* Enable Autoreload write complete interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); + + /* Enable Compare write complete interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); + + /* Enable Autoreload match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); + + /* Enable Compare match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Enable external trigger interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + } + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Start timer in single mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM Set once mode in interrupt mode. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Disable Autoreload write complete interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); + + /* Disable Compare write complete interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); + + /* Disable Autoreload match interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); + + /* Disable Compare match interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* If external trigger source is used, then disable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Disable external trigger interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + } + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the Encoder interface. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) +{ + uint32_t tmpcfgr = 0; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); + assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); + assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + + /* Clear CKPOL bits */ + tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); + + /* Set Input polarity */ + tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + + /* Set ENC bit to enable the encoder interface */ + hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the Encoder interface. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset ENC bit to disable the encoder interface */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the Encoder interface in interrupt mode. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) +{ + uint32_t tmpcfgr = 0; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); + assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); + assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Configure edge sensitivity for encoder mode */ + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + + /* Clear CKPOL bits */ + tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); + + /* Set Input polarity */ + tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + + /* Set ENC bit to enable the encoder interface */ + hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + + /* Enable "switch to down direction" interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); + + /* Enable "switch to up direction" interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the Encoder interface in interrupt mode. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset ENC bit to disable the encoder interface */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; + + /* Disable "switch to down direction" interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN); + + /* Disable "switch to up direction" interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the Timeout function. The first trigger event will start the + * timer, any successive trigger event will reset the counter and + * the timer restarts. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Timeout : Specifies the TimeOut value to rest the counter. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Timeout)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Set TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Load the Timeout value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the Timeout function. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the Timeout function in interrupt mode. The first trigger + * event will start the timer, any successive trigger event will reset + * the counter and the timer restarts. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Timeout : Specifies the TimeOut value to rest the counter. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Timeout)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Set TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; + + /* Enable Compare match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Load the Timeout value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the Timeout function in interrupt mode. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; + + /* Disable Compare match interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the Counter mode. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ + if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + /* Check if clock is prescaled */ + assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); + /* Set clock prescaler to 0 */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; + } + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the Counter mode. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the Counter mode in interrupt mode. + * @param hlptim : LPTIM handle + * @param Period : Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(Period)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ + if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + /* Check if clock is prescaled */ + assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); + /* Set clock prescaler to 0 */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; + } + + /* Enable Autoreload write complete interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); + + /* Enable Autoreload match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the Counter mode in interrupt mode. + * @param hlptim : LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State= HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Disable Autoreload write complete interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); + + /* Disable Autoreload match interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); + + /* Change the TIM state*/ + hlptim->State= HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup LPTIM_Group3 LPTIM Read operation functions + * @brief Read operation functions. + * +@verbatim + ============================================================================== + ##### LPTIM Read operation functions ##### + ============================================================================== +[..] This section provides LPTIM Reading functions. + (+) Read the counter value. + (+) Read the period (Auto-reload) value. + (+) Read the pulse (Compare)value. +@endverbatim + * @{ + */ + +/** + * @brief This function returns the current counter value. + * @param hlptim: LPTIM handle + * @retval Counter value. + */ +uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + return (hlptim->Instance->CNT); +} + +/** + * @brief This function return the current Autoreload (Period) value. + * @param hlptim: LPTIM handle + * @retval Autoreload value. + */ +uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + return (hlptim->Instance->ARR); +} + +/** + * @brief This function return the current Compare (Pulse) value. + * @param hlptim: LPTIM handle + * @retval Compare value. + */ +uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + return (hlptim->Instance->CMP); +} + +/** + * @} + */ + + + +/** @defgroup LPTIM_Group4 LPTIM IRQ handler + * @brief LPTIM IRQ handler. + * +@verbatim + ============================================================================== + ##### LPTIM IRQ handler ##### + ============================================================================== +[..] This section provides LPTIM IRQ handler function. + +@endverbatim + * @{ + */ + +/** + * @brief This function handles LPTIM interrupt request. + * @param hlptim: LPTIM handle + * @retval None + */ +void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) +{ + /* Compare match interrupt */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET) + { + /* Clear Compare match flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM); + /* Compare match Callback */ + HAL_LPTIM_CompareMatchCallback(hlptim); + } + } + + /* Autoreload match interrupt */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET) + { + /* Clear Autoreload match flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); + /* Autoreload match Callback */ + HAL_LPTIM_AutoReloadMatchCallback(hlptim); + } + } + + /* Trigger detected interrupt */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET) + { + /* Clear Trigger detected flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); + /* Trigger detected callback */ + HAL_LPTIM_TriggerCallback(hlptim); + } + } + + /* Compare write interrupt */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET) + { + /* Clear Compare write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Compare write Callback */ + HAL_LPTIM_CompareWriteCallback(hlptim); + } + } + + /* Autoreload write interrupt */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET) + { + /* Clear Autoreload write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Autoreload write Callback */ + HAL_LPTIM_AutoReloadWriteCallback(hlptim); + } + } + + /* Direction counter changed from Down to Up interrupt */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET) + { + /* Clear Direction counter changed from Down to Up flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); + /* Direction counter changed from Down to Up Callback */ + HAL_LPTIM_DirectionUpCallback(hlptim); + } + } + + /* Direction counter changed from Up to Down interrupt */ + if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) + { + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET) + { + /* Clear Direction counter changed from Up to Down flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); + /* Direction counter changed from Up to Down Callback */ + HAL_LPTIM_DirectionDownCallback(hlptim); + } + } + __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG(); +} + +/** + * @brief Compare match callback in non blocking mode + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LPTIM_CompareMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Autoreload match callback in non blocking mode + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Trigger detected callback in non blocking mode + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LPTIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Compare write callback in non blocking mode + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LPTIM_CompareWriteCallback could be implemented in the user file + */ +} + +/** + * @brief Autoreload write callback in non blocking mode + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file + */ +} + +/** + * @brief Direction counter changed from Down to Up callback in non blocking mode + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LPTIM_DirectionUpCallback could be implemented in the user file + */ +} + +/** + * @brief Direction counter changed from Up to Down callback in non blocking mode + * @param hlptim : LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_LPTIM_DirectionDownCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LPTIM_Group5 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the LPTIM state. + * @param hlptim: LPTIM handle + * @retval HAL state + */ +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) +{ + return hlptim->State; +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +#endif /* HAL_LPTIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.h new file mode 100644 index 0000000000..545ae6d3c3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_lptim.h @@ -0,0 +1,759 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_lptim.h + * @author MCD Application Team + * @version V1.4.1 + * @date 09-October-2015 + * @brief Header file of LPTIM HAL module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_LPTIM_H +#define __STM32F4xx_HAL_LPTIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup LPTIM LPTIM + * @brief LPTIM HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Types LPTIM Exported Types + * @{ + */ + +/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line + * @{ + */ +#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */ +/** + * @} + */ + +/** + * @brief LPTIM Clock configuration definition + */ +typedef struct +{ + uint32_t Source; /*!< Selects the clock source. + This parameter can be a value of @ref LPTIM_Clock_Source */ + + uint32_t Prescaler; /*!< Specifies the counter clock Prescaler. + This parameter can be a value of @ref LPTIM_Clock_Prescaler */ + +}LPTIM_ClockConfigTypeDef; + +/** + * @brief LPTIM Clock configuration definition + */ +typedef struct +{ + uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit + if the ULPTIM input is selected. + Note: This parameter is used only when Ultra low power clock source is used. + Note: If the polarity is configured on 'both edges', an auxiliary clock + (one of the Low power oscillator) must be active. + This parameter can be a value of @ref LPTIM_Clock_Polarity */ + + uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter. + Note: This parameter is used only when Ultra low power clock source is used. + This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ + +}LPTIM_ULPClockConfigTypeDef; + +/** + * @brief LPTIM Trigger configuration definition + */ +typedef struct +{ + uint32_t Source; /*!< Selects the Trigger source. + This parameter can be a value of @ref LPTIM_Trigger_Source */ + + uint32_t ActiveEdge; /*!< Selects the Trigger active edge. + Note: This parameter is used only when an external trigger is used. + This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */ + + uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter. + Note: This parameter is used only when an external trigger is used. + This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ +}LPTIM_TriggerConfigTypeDef; + +/** + * @brief LPTIM Initialization Structure definition + */ +typedef struct +{ + LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ + + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */ + + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ + + uint32_t OutputPolarity; /*!< Specifies the Output polarity. + This parameter can be a value of @ref LPTIM_Output_Polarity */ + + uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare + values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_Updating_Mode */ + + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + This parameter can be a value of @ref LPTIM_Counter_Source */ + +}LPTIM_InitTypeDef; + +/** + * @brief HAL LPTIM State structure definition + */ +typedef enum __HAL_LPTIM_StateTypeDef +{ + HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ + HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ + HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ + HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */ +}HAL_LPTIM_StateTypeDef; + +/** + * @brief LPTIM handle Structure definition + */ +typedef struct +{ + LPTIM_TypeDef *Instance; /*!< Register base address */ + + LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ + + HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ + + HAL_LockTypeDef Lock; /*!< LPTIM locking object */ + + __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ + +}LPTIM_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants + * @{ + */ + +/** @defgroup LPTIM_Clock_Source LPTIM Clock Source + * @{ + */ +#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00) +#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler + * @{ + */ +#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000) +#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 +#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 +#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)) +#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 +#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)) +#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)) +#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC) +/** + * @} + */ + +/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity + * @{ + */ + +#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) +#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL) +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time + * @{ + */ +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 +#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 +#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity + * @{ + */ + +#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000) +#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 +#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 +/** + * @} + */ + +/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source + * @{ + */ +#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF) +#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000) +#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0) +#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 +#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) +#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 +#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) +/** + * @} + */ + +/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity + * @{ + */ +#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0 +#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1 +#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN +/** + * @} + */ + +/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time + * @{ + */ +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 +#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 +#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT +/** + * @} + */ + +/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode + * @{ + */ + +#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000) +#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD +/** + * @} + */ + +/** @defgroup LPTIM_Counter_Source LPTIM Counter Source + * @{ + */ + +#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000) +#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE +/** + * @} + */ + +/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition + * @{ + */ + +#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN +#define LPTIM_FLAG_UP LPTIM_ISR_UP +#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK +#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK +#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG +#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM +#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM +/** + * @} + */ + +/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition + * @{ + */ + +#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE +#define LPTIM_IT_UP LPTIM_IER_UPIE +#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE +#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE +#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE +#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE +#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE +/** + * @} + */ + +/** @defgroup LPTIM_Option Register Definition + * @{ + */ +#define LPTIM_OP_PAD_AF ((uint32_t)0x00000000) +#define LPTIM_OP_PAD_PA4 LPTIM_OR_OR_0 +#define LPTIM_OP_PAD_PB9 LPTIM_OR_OR_1 +#define LPTIM_OP_TIM_DAC LPTIM_OR_OR + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros + * @{ + */ + +/** @brief Reset LPTIM handle state + * @param __HANDLE__: LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) + +/** + * @brief Enable/Disable the LPTIM peripheral. + * @param __HANDLE__: LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) +#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE)) + +/** + * @brief Starts the LPTIM peripheral in Continuous or in single mode. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) +#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) + + +/** + * @brief Writes the passed parameter in the Autoreload register. + * @param __HANDLE__: LPTIM handle + * @param __VALUE__ : Autoreload value + * @retval None + */ +#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) + +/** + * @brief Writes the passed parameter in the Compare register. + * @param __HANDLE__: LPTIM handle + * @param __VALUE__ : Compare value + * @retval None + */ +#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) + +/** + * @brief Checks whether the specified LPTIM flag is set or not. + * @param __HANDLE__: LPTIM handle + * @param __FLAG__ : LPTIM flag to check + * This parameter can be a value of: + * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. + * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. + * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. + * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. + * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. + * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. + * @arg LPTIM_FLAG_CMPM : Compare match Flag. + * @retval The state of the specified flag (SET or RESET). + */ +#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the specified LPTIM flag. + * @param __HANDLE__: LPTIM handle. + * @param __FLAG__ : LPTIM flag to clear. + * This parameter can be a value of: + * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. + * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. + * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. + * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. + * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. + * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. + * @arg LPTIM_FLAG_CMPM : Compare match Flag. + * @retval None. + */ +#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enable the specified LPTIM interrupt. + * @param __HANDLE__ : LPTIM handle. + * @param __INTERRUPT__ : LPTIM interrupt to set. + * This parameter can be a value of: + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CMPM : Compare match Interrupt. + * @retval None. + */ +#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + + /** + * @brief Disable the specified LPTIM interrupt. + * @param __HANDLE__ : LPTIM handle. + * @param __INTERRUPT__ : LPTIM interrupt to set. + * This parameter can be a value of: + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CMPM : Compare match Interrupt. + * @retval None. + */ +#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + + /** + * @brief Checks whether the specified LPTIM interrupt is set or not. + * @param __HANDLE__ : LPTIM handle. + * @param __INTERRUPT__ : LPTIM interrupt to check. + * This parameter can be a value of: + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CMPM : Compare match Interrupt. + * @retval Interrupt status. + */ + +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief LPTIM Option Register + * @param __HANDLE__: LPTIM handle + * @param __VALUE__: This parameter can be a value of : + * @arg LPTIM_OP_PAD_AF + * @arg LPTIM_OP_PAD_PA4 + * @arg LPTIM_OP_PAD_PB9 + * @arg LPTIM_OP_TIM_DAC + * @retval None + */ +#define __HAL_LPTIM_OPTR_CONFIG(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->OR = (__VALUE__)) + +/** + * @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Clear the LPTIM Wake-up Timer associated Exti line flag. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line. + * @retval None. + */ +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); + +/* MSP functions *************************************************************/ +void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); + +/* Start/Stop operation functions *********************************************/ +/* ################################# PWM Mode ################################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################# One Pulse Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################## Set once Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################### Encoder Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period); +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################# Time out Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout); +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout); +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################## Counter Mode ###############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period); +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* Reading operation functions ************************************************/ +uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); + +/* LPTIM IRQ functions *******************************************************/ +void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); + +/* CallBack functions ********************************************************/ +void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); + +/* Peripheral State functions ************************************************/ +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Types LPTIM Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Variables LPTIM Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Constants LPTIM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Macros LPTIM Private Macros + * @{ + */ + +#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ + ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) + +#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV128)) +#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1) + +#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \ + ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH)) + +#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) + +#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) + +#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_5)) + +#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \ + ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \ + ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING )) + +#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) + +#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \ + ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) + +#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ + ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) + +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF) + +#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF) + +#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFF) + +#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFF) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_LPTIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c index 596a896ae9..d5d7de5793 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief LTDC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LTDC peripheral: @@ -109,7 +109,7 @@ #ifdef HAL_LTDC_MODULE_ENABLED -#if defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -372,7 +372,7 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) __HAL_UNLOCK(hltdc); /* Line interrupt Callback */ - HAL_LTDC_LineEvenCallback(hltdc); + HAL_LTDC_LineEventCallback(hltdc); } } } @@ -396,10 +396,10 @@ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) * the configuration information for the LTDC. * @retval None */ -__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc) +__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_LTDC_LineEvenCallback could be implemented in the user file + the HAL_LTDC_LineEventCallback could be implemented in the user file */ } @@ -872,7 +872,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); /* Sets the Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; + hltdc->Instance->SRCR = LTDC_SRCR_VBR; /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; @@ -1016,6 +1016,80 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres return HAL_OK; } +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx: LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t pitchUpdate = 0; + uint32_t pixelFormat = 0; + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Sets the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Sets the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + /** * @brief Define the position of the line interrupt . * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains @@ -1178,7 +1252,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /** * @} */ -#endif /* STM32F429xx || STM32F439xx */ +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #endif /* HAL_LTDC_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h index 096364c5d7..a3334ba1e5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of LTDC HAL module. ****************************************************************************** * @attention @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -467,6 +467,9 @@ typedef struct * @} */ +/* Include LTDC HAL Extension module */ +#include "stm32f4xx_hal_ltdc_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup LTDC_Exported_Functions * @{ @@ -480,7 +483,7 @@ HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc); void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc); void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); -void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); /** * @} */ @@ -504,6 +507,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); @@ -620,7 +624,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); * @} */ -#endif /* STM32F429xx || STM32F439xx */ +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.c new file mode 100644 index 0000000000..815a8a9ac9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.c @@ -0,0 +1,164 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_ltdc_ex.c + * @author MCD Application Team + * @version V1.4.1 + * @date 09-October-2015 + * @brief LTDC Extension HAL module driver. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ +/** @defgroup LTDCEx LTDCEx + * @brief LTDC HAL module driver + * @{ + */ + +#ifdef HAL_LTDC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ + +/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + +@endverbatim + * @{ + */ +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Retrieve common parameters from DSI Video mode configuration structure + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ + + /* Retrieve vertical timing parameters from DSI */ + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1; + + return HAL_OK; +} + +/** + * @brief Retrieve common parameters from DSI Adapted command mode configuration structure + * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ + + return HAL_OK; +} +#endif /* STM32F469xx || STM32F479xx */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DCMI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.h new file mode 100644 index 0000000000..9d517280ec --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc_ex.h @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_ltdc_ex.h + * @author MCD Application Team + * @version V1.4.1 + * @date 09-October-2015 + * @brief Header file of LTDC HAL Extension module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_LTDC_EX_H +#define __STM32F4xx_HAL_LTDC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F469xx) || defined(STM32F479xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" +#include "stm32f4xx_hal_dsi.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup LTDCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Constants LTDCEx Exported Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LTDCEx_Exported_Macros LTDC Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ +HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg); +/** + * @} + */ + + + /* Private types -------------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Types LTDCEx Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Variables LTDCEx Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Constants LTDCEx Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Macros LTDCEx Private Macros + * @{ + */ + + /** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LTDCEx_Private_Functions LTDCEx Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F469xx || STM32F479xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_LTDC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c index 0a78d6a5ab..de5694f144 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_nand.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -94,7 +94,7 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup NAND NAND * @brief NAND HAL module driver @@ -1114,8 +1114,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx */ - + STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_NAND_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h index 6cf3ae3705..a057393db6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_nand.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -48,9 +48,11 @@ #include "stm32f4xx_ll_fsmc.h" #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -60,10 +62,10 @@ * @{ */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + /* Exported typedef ----------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /** @defgroup NAND_Exported_Types NAND Exported Types @@ -274,7 +276,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** * @brief NAND memory address computation. * @param __ADDRESS__: NAND memory address. - * @param __HANDLE__ : NAND handle. + * @param __HANDLE__: NAND handle. * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ @@ -294,7 +296,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx */ + STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c index 754aafb60b..3b47afc8c3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_nor.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -96,7 +96,7 @@ #ifdef HAL_NOR_MODULE_ENABLED #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -994,7 +994,8 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @} */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ - STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ + STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ #endif /* HAL_NOR_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h index 55f8690c6d..5bcf6acc23 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_nor.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention @@ -44,13 +44,14 @@ #endif /* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -62,7 +63,7 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Exported typedef ----------------------------------------------------------*/ /** @defgroup NOR_Exported_Types NOR Exported Types @@ -283,7 +284,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx */ + STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c index c8e54e3984..f1f21404cd 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pccard.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief PCCARD HAL module driver. * This file provides a generic firmware to drive PCCARD memories mounted * as external device. diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h index a67f54f391..dcbfe4c5d3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pccard.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of PCCARD HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c index bbf1d13171..8b532b5e7b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -85,7 +85,10 @@ */ #ifdef HAL_PCD_MODULE_ENABLED - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -200,6 +203,14 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) } #endif /* USB_OTG_GLPMCFG_LPMEN */ +#ifdef USB_OTG_GCCFG_BCDEN + /* Activate Battery charging */ + if (hpcd->Init.battery_charging_enable ==1) + { + HAL_PCDEx_ActivateBCD(hpcd); + } +#endif /* USB_OTG_GCCFG_BCDEN */ + USB_DevDisconnect (hpcd->Instance); return HAL_OK; } @@ -1195,7 +1206,8 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t /** * @} */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_PCD_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h index ad6ae87bab..fb81f4567a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -42,7 +42,10 @@ #ifdef __cplusplus extern "C" { #endif - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_ll_usb.h" @@ -104,6 +107,10 @@ typedef struct uint32_t lpm_active; /*!< Enable or disable the Link Power Management . This parameter can be set to ENABLE or DISABLE */ #endif /* USB_OTG_GLPMCFG_LPMEN */ +#ifdef USB_OTG_GCCFG_BCDEN + uint32_t battery_charging_active; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ +#endif /* USB_OTG_GCCFG_BCDEN */ void *pData; /*!< Pointer to upper stack Handler */ } PCD_HandleTypeDef; @@ -137,7 +144,7 @@ typedef struct /** * @} */ - + /** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value * @{ */ @@ -164,7 +171,7 @@ typedef struct #define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) @@ -221,10 +228,10 @@ typedef struct EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup PCD_Exported_Functions PCD Exported Functions @@ -245,7 +252,7 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); /* I/O operation functions ***************************************************/ /* Non-Blocking mode: Interrupt */ -/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* Non-Blocking mode: Interrupt */ @@ -310,18 +317,15 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @{ */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ ((INSTANCE) == USB_OTG_HS)) -#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS)) #endif /** * @} */ -/** - * @} - */ /** * @} @@ -331,6 +335,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @} */ +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c index 2d14dd4272..83f38d69d2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -51,7 +51,10 @@ * @{ */ #ifdef HAL_PCD_MODULE_ENABLED - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -114,7 +117,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin } /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); + hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset); } return HAL_OK; @@ -133,7 +136,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) return HAL_OK; } -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Activate LPM feature * @param hpcd: PCD handle @@ -176,7 +179,7 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { } -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} @@ -186,6 +189,8 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m * @} */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_PCD_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h index 7d4b0c3274..22ec48df5a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -42,7 +42,10 @@ #ifdef __cplusplus extern "C" { #endif - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -54,18 +57,18 @@ * @{ */ /* Exported types ------------------------------------------------------------*/ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) typedef enum { PCD_LPM_L0_ACTIVE = 0x00, /* on */ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ }PCD_LPM_MsgTypeDef; -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ /* Exported constants --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions +/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions * @{ */ /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions @@ -73,11 +76,11 @@ typedef enum */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} @@ -94,7 +97,8 @@ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /** * @} */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c index 5834418e0a..bd565ba684 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -167,7 +167,8 @@ void HAL_PWR_DisableBkUpAccess(void) (+) Wake-up pin is used to wake up the system from Standby mode. This pin is forced in input pull-down configuration and is active on rising edges. (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. - Only for STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin 2 on PC.13 + (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 + (++) For STM32F410xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 *** Low Power modes configuration *** ===================================== @@ -328,7 +329,8 @@ void HAL_PWR_DisablePVD(void) * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 only available in case of STM32F446xx devices + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) @@ -345,7 +347,8 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 only available in case of STM32F446xx devices + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx devices * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h index 0532721e94..664a07944c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -85,7 +85,6 @@ typedef struct * @{ */ #define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100) -#define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080) /** * @} */ @@ -169,43 +168,6 @@ typedef struct * @{ */ -#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) -/** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ - __IO uint32_t tmpreg; \ - MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ - UNUSED(tmpreg); \ - } while(0) -#else -/** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ - __IO uint32_t tmpreg; \ - MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ - /** @brief Check PWR flag is set or not. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: @@ -445,7 +407,6 @@ void HAL_PWR_DisableSEVOnPend(void); /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters * @{ */ -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2)) #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c index a1e469148d..55526a10e5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: @@ -122,7 +122,7 @@ is in power down mode, an additional startup delay is incurred when waking up from Stop mode. - (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL is OFF and the HSI or HSE clock source is selected as system clock. The new value programmed is active only when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically selected. @@ -131,7 +131,7 @@ *** Over-Drive and Under-Drive configuration **** ================================================= [..] - (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has 2 operating modes available: (++) Normal mode: The CPU and core logic operate at maximum frequency at a given voltage scaling (scale 1, scale 2 or scale 3) @@ -141,7 +141,7 @@ disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow the sequence described in Reference manual. - (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator supplies a low power voltage to the 1.2V domain, thus preserving the content of registers and internal SRAM. 2 operating modes are available: (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only @@ -275,7 +275,9 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) } #elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \ + defined(STM32F479xx) /** * @brief Configures the main internal regulator output voltage. * @param VoltageScaling: specifies the regulator output voltage to achieve @@ -364,10 +366,31 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) } #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Enables Wakeup Pin Detection on high level (rising edge). + * @retval None + */ +void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void) +{ + *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables Wakeup Pin Detection on low level (falling edge). + * @retval None + */ +void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void) +{ + *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE; +} +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) /** * @brief Enables Main Regulator low voltage mode. - * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices. * @retval None */ void HAL_PWREx_EnableMainRegulatorLowVoltage(void) @@ -377,7 +400,7 @@ void HAL_PWREx_EnableMainRegulatorLowVoltage(void) /** * @brief Disables Main Regulator low voltage mode. - * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices. * @retval None */ void HAL_PWREx_DisableMainRegulatorLowVoltage(void) @@ -387,7 +410,7 @@ void HAL_PWREx_DisableMainRegulatorLowVoltage(void) /** * @brief Enables Low Power Regulator low voltage mode. - * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices. * @retval None */ void HAL_PWREx_EnableLowRegulatorLowVoltage(void) @@ -397,7 +420,7 @@ void HAL_PWREx_EnableLowRegulatorLowVoltage(void) /** * @brief Disables Low Power Regulator low voltage mode. - * @note This mode is only available for STM32F401xx/STM32F411xx devices. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices. * @retval None */ void HAL_PWREx_DisableLowRegulatorLowVoltage(void) @@ -405,12 +428,13 @@ void HAL_PWREx_DisableLowRegulatorLowVoltage(void) *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; } -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Activates the Over-Drive mode. - * @note This function can be used only for STM32F42xx/STM32F43xx devices. + * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. * This mode allows the CPU and the core logic to operate at a higher frequency * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). * @note It is recommended to enter or exit Over-drive mode when the application is not running @@ -457,7 +481,7 @@ HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) /** * @brief Deactivates the Over-Drive mode. - * @note This function can be used only for STM32F42xx/STM32F43xx devices. + * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. * This mode allows the CPU and the core logic to operate at a higher frequency * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). * @note It is recommended to enter or exit Over-drive mode when the application is not running @@ -506,7 +530,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) /** * @brief Enters in Under-Drive STOP mode. * - * @note This mode is only available for STM32F42xxx/STM324F3xxx devices. + * @note This mode is only available for STM32F42xxx/STM324F3xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. * * @note This mode can be selected only when the Under-Drive is already active * @@ -603,7 +627,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t return HAL_OK; } -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h index 17032d6185..29513e9080 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention @@ -59,8 +59,8 @@ /** @defgroup PWREx_Exported_Constants PWREx Exported Constants * @{ */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode * @{ @@ -80,9 +80,9 @@ /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale * @{ */ #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) @@ -98,7 +98,19 @@ /** * @} */ - +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) +/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins + * @{ + */ +#define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define PWR_WAKEUP_PIN3 ((uint32_t)0x00000040) +#endif /* STM32F410xx */ +/** + * @} + */ +#endif /* STM32F410xx || STM32F446xx */ + /** * @} */ @@ -107,7 +119,46 @@ /** @defgroup PWREx_Exported_Constants PWREx Exported Constants * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) + +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__: specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg; \ + MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ + UNUSED(tmpreg); \ + } while(0) +#else +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__: specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg; \ + MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macros to enable or disable the Over drive mode. * @note These macros can be used only for STM32F42xx/STM3243xx devices. */ @@ -152,7 +203,7 @@ */ #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -172,18 +223,25 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); uint32_t HAL_PWREx_GetVoltageRange(void); HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#if defined(STM32F469xx) || defined(STM32F479xx) +void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void); +void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void); +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ + defined(STM32F401xE) || defined(STM32F411xE) void HAL_PWREx_EnableMainRegulatorLowVoltage(void); void HAL_PWREx_DisableMainRegulatorLowVoltage(void); void HAL_PWREx_EnableLowRegulatorLowVoltage(void); void HAL_PWREx_DisableLowRegulatorLowVoltage(void); -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} @@ -234,7 +292,13 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /* --- CSR Register ---*/ /* Alias word address of BRE bit */ #define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE) -#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4)) +#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4)) + +#if defined(STM32F469xx) || defined(STM32F479xx) +/* Alias word address of WUPP bit */ +#define WUPP_BIT_NUMBER POSITION_VAL(PWR_CSR_WUPP) +#define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (WUPP_BIT_NUMBER * 4)) +#endif /* STM32F469xx || STM32F479xx */ /** * @} */ @@ -251,10 +315,11 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ @@ -265,6 +330,14 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ +#if defined(STM32F446xx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2)) +#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1) +#endif /* STM32F446xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c index 526a048ca6..2d09a55c95 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_qspi.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief QSPI HAL module driver. * * This file provides firmware functions to manage the following @@ -166,7 +166,7 @@ */ #ifdef HAL_QSPI_MODULE_ENABLED -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -377,7 +377,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) * @verbatim =============================================================================== - ##### I/O operation functions ##### + ##### IO operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to : @@ -1311,28 +1311,31 @@ if(hqspi->State == HAL_QSPI_STATE_READY) /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); - if (status == HAL_OK) - { - /* Configure QSPI: PSMAR register with the status match value */ - WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); + if (status == HAL_OK) + { + /* Configure QSPI: PSMAR register with the status match value */ + WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); - /* Configure QSPI: PSMKR register with the status mask value */ - WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); + /* Configure QSPI: PSMKR register with the status mask value */ + WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); - /* Configure QSPI: PIR register with the interval value */ - WRITE_REG(hqspi->Instance->PIR, cfg->Interval); + /* Configure QSPI: PIR register with the interval value */ + WRITE_REG(hqspi->Instance->PIR, cfg->Interval); - /* Configure QSPI: CR register with Match mode and Automatic stop mode */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), + /* Configure QSPI: CR register with Match mode and Automatic stop mode */ + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), (cfg->MatchMode | cfg->AutomaticStop)); + + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); - /* Call the configuration function */ - cmd->NbData = cfg->StatusBytesSize; - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); - - /* Enable the QSPI Transfer Error, FIFO threshold and status match Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_FT | QSPI_IT_SM | QSPI_IT_TE)); - } + /* Enable the QSPI Transfer Error and status match Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); + + /* Call the configuration function */ + cmd->NbData = cfg->StatusBytesSize; + QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + } } else { @@ -1928,7 +1931,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @} */ -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_QSPI_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h index bd76eeb0ea..88377e4f4a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_qspi.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention @@ -43,7 +43,7 @@ extern "C" { #endif -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -777,7 +777,7 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Ti /** * @} */ -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c index 343ce74057..f2db87fc1f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -214,6 +214,12 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz, + PCLK2 100 MHz and PCLK1 50 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + @endverbatim * @{ */ @@ -222,7 +228,7 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF + * - HSE and PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled @@ -231,31 +237,8 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, * - LSI, LSE and RTC clocks * @retval None */ -void HAL_RCC_DeInit(void) -{ - /* Set HSION bit */ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Reset HSEON, CSSON, PLLON, PLLI2S */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); - - /* Reset PLLCFGR register */ - CLEAR_REG(RCC->PLLCFGR); - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); - - /* Reset PLLI2SCFGR register */ - CLEAR_REG(RCC->PLLI2SCFGR); - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1); - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); -} +__weak void HAL_RCC_DeInit(void) +{} /** * @brief Initializes the RCC Oscillators according to the specified parameters in the @@ -882,7 +865,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source * @param RCC_MCODiv: specifies the MCOx prescaler. @@ -892,6 +876,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have + * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5). * @retval None */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) @@ -918,6 +904,11 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + + /* This RCC MCO1 enable feature is available only on STM32F410xx devices */ +#if defined(RCC_CFGR_MCO1EN) + __HAL_RCC_MCO1_ENABLE(); +#endif /* RCC_CFGR_MCO1EN */ } else { @@ -936,6 +927,11 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3))); + + /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */ +#if defined(RCC_CFGR_MCO2EN) + __HAL_RCC_MCO2_ENABLE(); +#endif /* RCC_CFGR_MCO2EN */ } } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h index 596f7efc40..cb1d7066ff 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -301,15 +301,6 @@ typedef struct * @} */ -/** @defgroup RCC_I2S_Clock_Source I2S Clock Source - * @{ - */ -#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000) -#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001) -/** - * @} - */ - /** @defgroup RCC_MCO_Index MCO Index * @{ */ @@ -330,17 +321,6 @@ typedef struct * @} */ -/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source - * @{ - */ -#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000) -#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 -#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 -#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 -/** - * @} - */ - /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler * @{ */ @@ -435,20 +415,6 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0) #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ @@ -456,27 +422,6 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ - UNUSED(tmpreg); \ - } while(0) #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ @@ -495,37 +440,10 @@ typedef struct #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) -#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) -#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) -/** - * @} - */ - -/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ - }while(0) - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\ - __HAL_RCC_SYSCFG_CLK_DISABLE();\ - }while(0) - -#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN)) -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) - /** * @} */ @@ -537,27 +455,6 @@ typedef struct * using it. * @{ */ -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0) #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ @@ -579,13 +476,6 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ @@ -607,13 +497,6 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - UNUSED(tmpreg); \ - } while(0) #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ @@ -621,17 +504,13 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) + #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) /** * @} @@ -672,13 +551,6 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - UNUSED(tmpreg); \ - } while(0) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ @@ -686,13 +558,6 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - UNUSED(tmpreg); \ - } while(0) #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ @@ -707,13 +572,6 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0) #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ @@ -726,12 +584,9 @@ typedef struct #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) /** * @} @@ -745,10 +600,7 @@ typedef struct #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) @@ -756,65 +608,33 @@ typedef struct #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) -#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) /** * @} */ -/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) - -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) - -#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) -/** - * @} - */ - /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) /** * @} @@ -829,12 +649,9 @@ typedef struct #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) -#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) @@ -842,27 +659,14 @@ typedef struct #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) -#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) /** * @} */ -/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) -/** - * @} - */ - /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -874,50 +678,20 @@ typedef struct #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) /** * @} */ -/** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) - -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) -/** - * @} - */ - /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -926,30 +700,20 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) /** * @} @@ -967,24 +731,18 @@ typedef struct #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) /** * @} @@ -1162,9 +920,6 @@ typedef struct */ #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) -/** - * @} - */ /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. @@ -1186,20 +941,10 @@ typedef struct * */ #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) - -/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration - * @{ - */ - -/** @brief Macros to enable or disable the PLLI2S. - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) -#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) /** * @} - */ - + */ + /** @defgroup RCC_Get_Clock_source Get Clock source * @{ */ @@ -1235,6 +980,54 @@ typedef struct * @} */ +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have + * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5). + */ + +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (__MCOCLKSOURCE__ | (__MCODIV__ << 3))); +/** + * @} + */ + /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ @@ -1395,15 +1188,6 @@ void HAL_RCC_CSSCallback(void); /* Alias word address of PLLON bit */ #define RCC_PLLON_BIT_NUMBER 0x18 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4)) -/* Alias word address of PLLI2SON bit */ -#define RCC_PLLI2SON_BIT_NUMBER 0x1A -#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4)) - -/* --- CFGR Register ---*/ -/* Alias word address of I2SSRC bit */ -#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08) -#define RCC_I2SSRC_BIT_NUMBER 0x17 -#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4)) /* --- BDCR Register ---*/ /* Alias word address of RTCEN bit */ @@ -1439,8 +1223,6 @@ void HAL_RCC_CSSCallback(void); #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */ -#define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */ /** * @} */ @@ -1504,9 +1286,6 @@ void HAL_RCC_CSSCallback(void); #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) - #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ ((DIV) == RCC_MCODIV_5)) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c index 87ebc8bd09..599ffdba0a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Extension RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -75,7 +75,7 @@ @verbatim =============================================================================== ##### Extended Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the RCC Clocks frequencies. @@ -88,6 +88,88 @@ @endverbatim * @{ */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL and PLLI2S OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +void HAL_RCC_DeInit(void) +{ + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Reset HSEON, CSSON, PLLON, PLLI2S */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); + + /* Reset PLLCFGR register */ + CLEAR_REG(RCC->PLLCFGR); + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); + + /* Reset PLLI2SCFGR register */ + CLEAR_REG(RCC->PLLI2SCFGR); + SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); +} +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +void HAL_RCC_DeInit(void) +{ + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Reset HSEON, CSSON, PLLON */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); + + /* Reset PLLCFGR register */ + CLEAR_REG(RCC->PLLCFGR); + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); +} +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + #if defined(STM32F446xx) /** * @brief Initializes the RCC extended peripherals clocks according to the specified @@ -117,8 +199,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*----------------------------------- I2S APB1 configuration ----------------------------------*/ + + /*------------------------ I2S APB1 configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) { /* Check the parameters */ @@ -132,8 +214,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk plli2sused = 1; } } - - /*----------------------------------- I2S APB2 configuration -----------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*---------------------------- I2S APB2 configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) { /* Check the parameters */ @@ -147,8 +230,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk plli2sused = 1; } } - - /*------------------------------------ SAI1 configuration --------------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*--------------------------- SAI1 configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) { /* Check the parameters */ @@ -167,8 +251,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk pllsaiused = 1; } } - - /*------------------------------------ SAI2 configuration --------------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*-------------------------- SAI2 configuration ----------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) { /* Check the parameters */ @@ -188,10 +273,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk pllsaiused = 1; } } - - /*------------------------------------ RTC configuration --------------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*----------------------------- RTC configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { + { /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); @@ -210,7 +296,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /* Reset the Backup domain only if the RTC Clock source selction is modified */ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) - { + { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); /* RTC Clock selection can be changed only if the Backup Domain is reset */ @@ -218,7 +304,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; - + /* Wait for LSERDY if LSE was enabled */ if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY)) { @@ -237,15 +323,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } } - - /*------------------------------------ TIM configuration --------------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) { /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } - - /*------------------------------------- FMPI2C1 Configuration ----------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*---------------------------- FMPI2C1 Configuration -----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) { /* Check the parameters */ @@ -254,8 +342,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); } - - /*--------------------------------------- CEC Configuration -----------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*------------------------------ CEC Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) { /* Check the parameters */ @@ -264,14 +353,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); } - - /*-------------------------------------- CK48 Configuration -----------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*------------------------------ CK48 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) { /* Check the parameters */ assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - /* Configure the SDIO clock source */ + /* Configure the CK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); /* Enable the PLLSAI when it's used as clock source for CK48 */ @@ -280,8 +370,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk pllsaiused = 1; } } - - /*------------------------------------- SDIO Configuration ------------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*----------------------------- SDIO Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) { /* Check the parameters */ @@ -290,8 +381,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); } - - /*------------------------------------- SPDIFRX Configuration --------------*/ + /*--------------------------------------------------------------------------*/ + + /*------------------------------ SPDIFRX Configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) { /* Check the parameters */ @@ -305,8 +397,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk plli2sused = 1; } } - - /*-------------------------------------- PLLI2S Configuration --------------*/ + /*--------------------------------------------------------------------------*/ + + /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) @@ -329,7 +422,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) { @@ -340,12 +433,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1); plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) (PLLI2SN/PLLI2SM) */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); } - - /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) { @@ -367,7 +460,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); } - /*----------------- In Case of PLLI2S is selected as source clock for SPDIFRX -------------------*/ + /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) { /* check for Parameters */ @@ -376,7 +469,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1); plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) (PLLI2SN/PLLI2SM) */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr); } @@ -390,7 +483,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) (PLLI2SN/PLLI2SM) */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } @@ -408,7 +501,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /*--------------------------------------------------------------------------*/ + + /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CK48 or SDIO */ if(pllsaiused == 1) { @@ -430,7 +525,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) { @@ -450,7 +545,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); } - /*----------------- In Case of PLLSAI is selected as source clock for CK48 -------------------*/ + /*------ In Case of PLLSAI is selected as source clock for CK48 ----------*/ /* In Case of PLLI2S is selected as source clock for CK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)) { @@ -459,7 +554,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); /* Configure the PLLSAI division factors */ - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) (PLLI2SN/PLLSAIM) */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0); } @@ -500,53 +595,53 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_CK48 | RCC_PERIPHCLK_SDIO |\ RCC_PERIPHCLK_SPDIFRX; - /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + /* Get the PLLI2S Clock configuration --------------------------------------*/ PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM)); PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1); PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + /* Get the PLLSAI Clock configuration --------------------------------------*/ PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM)); PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1); PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); - /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ + /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); - /* Get the SAI1 clock configuration ----------------------------------------------*/ + /* Get the SAI1 clock configuration ----------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - /* Get the SAI2 clock configuration ----------------------------------------------*/ + /* Get the SAI2 clock configuration ----------------------------------------*/ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - /* Get the I2S APB1 clock configuration ------------------------------------------*/ + /* Get the I2S APB1 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); - /* Get the I2S APB2 clock configuration ------------------------------------------*/ + /* Get the I2S APB2 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); - /* Get the RTC Clock configuration -----------------------------------------------*/ + /* Get the RTC Clock configuration -----------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - /* Get the CEC clock configuration -----------------------------------------------*/ + /* Get the CEC clock configuration -----------------------------------------*/ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); - /* Get the FMPI2C1 clock configuration -----------------------------------------------*/ + /* Get the FMPI2C1 clock configuration -------------------------------------*/ PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); - /* Get the CK48 clock configuration -----------------------------------------------*/ + /* Get the CK48 clock configuration ----------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - /* Get the SDIO clock configuration -----------------------------------------------*/ + /* Get the SDIO clock configuration ----------------------------------------*/ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - /* Get the SPDIFRX clock configuration ----------------------------------------------*/ + /* Get the SPDIFRX clock configuration -------------------------------------*/ PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); - /* Get the TIM Prescaler configuration --------------------------------------------*/ + /* Get the TIM Prescaler configuration -------------------------------------*/ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) { PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; @@ -683,6 +778,492 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) #endif /* STM32F446xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC, RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg1 = 0; + uint32_t pllsaip = 0; + uint32_t pllsaiq = 0; + uint32_t pllsair = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*--------------------------- CLK48 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ SDIO Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ + /*------------------- Common configuration SAI/I2S -------------------------*/ + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------- I2S configuration -------------------------------*/ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) + { + /* Check the PLLI2S division factors */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Configure the PLLI2S multiplication and division factors */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ + /*----------------------- Common configuration SAI/LTDC --------------------*/ + /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division + factor is common parameters for these peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && + (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))) + { + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) + { + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1); + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair); + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*---------------------------- LTDC configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1); + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR); + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } + + /*---------------------------- CLK48 configuration ------------------------*/ + /* Configure the PLLSAI when it is used as clock source for CLK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == (RCC_PERIPHCLK_CK48)) && + (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)) + { + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*--------------------------------------------------------------------------*/ + + /*---------------------------- RTC configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSERDY if LSE was enabled */ + if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + return HAL_OK; +} + +/** + * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\ + RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CK48 | RCC_PERIPHCLK_SDIO; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); + /* Get the PLLSAI Clock configuration --------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); + PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the CK48 clock configuration --------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg1 = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while((PWR->CR & PWR_CR_DBP) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSERDY if LSE was enabled */ + if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- FMPI2C1 Configuration -----------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- LPTIM1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*---------------------------- I2S Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection)); + + /* Configure the I2S clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection); + } + + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; + + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the I2S clock configuration -----------------------------------------*/ + PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE(); + + +} +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** * @brief Initializes the RCC extended peripherals clocks according to the specified @@ -706,9 +1287,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/ - - /*----------------------- Common configuration SAI/I2S ---------------------------*/ + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ + /*----------------------- Common configuration SAI/I2S ----------------------*/ /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division factor is common parameters for both peripherals */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || @@ -739,7 +1319,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) (PLLI2SN/PLLM) */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); } @@ -778,9 +1358,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - + /*--------------------------------------------------------------------------*/ + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ - /*----------------------- Common configuration SAI/LTDC --------------------*/ /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division factor is common parameters for both peripherals */ @@ -851,30 +1431,31 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - - + /*--------------------------------------------------------------------------*/ + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Enable Power Clock*/ + { + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) { - return HAL_TIMEOUT; - } - } + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified */ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) - { + { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); /* RTC Clock selection can be changed only if the Backup Domain is reset */ @@ -882,6 +1463,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; + /* Wait for LSERDY if LSE was enabled */ if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY)) { @@ -900,7 +1482,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } } - + /*--------------------------------------------------------------------------*/ + /*---------------------------- TIM configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) { @@ -910,7 +1493,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the PeriphClkInit according to the internal * RCC configuration registers. * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. @@ -998,12 +1581,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(STM32F411xE) /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) (PLLI2SN/PLLI2SM) */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); #else /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) (PLLI2SN/PLLM) */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); #endif /* STM32F411xE */ @@ -1025,23 +1608,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Enable Power Clock*/ + { + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) { - return HAL_TIMEOUT; - } - } + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified */ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) { @@ -1052,6 +1636,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; + /* Wait for LSERDY if LSE was enabled */ if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY)) { @@ -1070,7 +1655,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } } - + return HAL_OK; } @@ -1088,55 +1673,28 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC; - /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + /* Get the PLLI2S Clock configuration --------------------------------------*/ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); #if defined(STM32F411xE) PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM); -#endif /* STM32F411xE */ - /* Get the RTC Clock configuration -----------------------------------------------*/ +#endif /* STM32F411xE */ + /* Get the RTC Clock configuration -----------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); } -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ -#if defined(STM32F411xE) || defined(STM32F446xx) -/** - * @brief Select LSE mode - * - * @note This mode is only available for STM32F411xx devices. - * - * @param Mode: specifies the LSE mode. - * This parameter can be one of the following values: - * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection - * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection - * @retval None - */ -void HAL_RCCEx_SelectLSEMode(uint8_t Mode) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE_MODE(Mode)); - if(Mode == RCC_LSE_HIGHDRIVE_MODE) - { - SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); - } - else - { - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); - } -} - -#endif /* STM32F411xE || STM32F446xx */ - -#if defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. - * @note This function add the PLL/PLLR factor management during PLL configuration this feature is only available in STM32F446xx devices + * @note This function add the PLL/PLLR factor management during PLL configuration this feature + * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) @@ -1151,9 +1709,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ +#if defined(STM32F446xx) if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) +#else + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) +#endif /* STM32F446xx */ { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { @@ -1219,9 +1782,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ +#if defined(STM32F446xx) if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) +#else + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) +#endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) @@ -1319,7 +1887,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } - /*------------------------------ LSE Configuration -------------------------*/ + /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { /* Check the parameters */ @@ -1476,7 +2044,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * RCC configuration registers. * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured. * - * @note This function is only available in case of STM32F446xx devices. + * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx devices. * @note This function add the PLL/PLLR factor management * @retval None */ @@ -1551,11 +2119,41 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)); RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); } +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Select LSE mode + * + * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * + * @param Mode: specifies the LSE mode. + * This parameter can be one of the following values: + * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection + * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection + * @retval None + */ +void HAL_RCCEx_SelectLSEMode(uint8_t Mode) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_MODE(Mode)); + if(Mode == RCC_LSE_HIGHDRIVE_MODE) + { + SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } +} + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) /** * @brief Returns the SYSCLK frequency * - * @note This function is only available in case of STM32F446xx devices. + * @note This function implementation is valide only for STM32F446xx devices. * @note This function add the PLL/PLLR System clock source * * @note The system frequency computed by this function is not the real @@ -1563,7 +2161,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations @@ -1639,7 +2237,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) else { /* HSI used as PLL clock source */ - pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); } pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h index 3f7722a2fd..0076b4a95b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -68,10 +68,10 @@ typedef struct This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ + This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ @@ -81,11 +81,13 @@ typedef struct uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. This parameter must be a number between Min_Data = 4 and Max_Data = 15 */ -#if defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. - This parameter is only available in STM32F446xx devices. + This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx and STM32F479xx + devices. This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ -#endif /* STM32F446xx */ +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */ }RCC_PLLInitTypeDef; #if defined(STM32F446xx) @@ -95,7 +97,7 @@ typedef struct typedef struct { uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ @@ -105,7 +107,7 @@ typedef struct uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. This parameter must be a number between Min_Data = 2 and Max_Data = 7. @@ -118,10 +120,10 @@ typedef struct typedef struct { uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ + This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ @@ -187,7 +189,32 @@ typedef struct }RCC_PeriphCLKInitTypeDef; #endif /* STM32F446xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief PLLI2S Clock structure definition @@ -215,6 +242,11 @@ typedef struct uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. This parameter must be a number between Min_Data = 192 and Max_Data = 432. This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ +#if defined(STM32F469xx) || defined(STM32F479xx) + uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. + This parameter is only available in STM32F469xx/STM32F479xx devices. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ +#endif /* STM32F469xx || STM32F479xx */ uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. This parameter must be a number between Min_Data = 2 and Max_Data = 15. @@ -255,18 +287,24 @@ typedef struct uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +#if defined(STM32F469xx) || defined(STM32F479xx) + uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CK48_Clock_Source */ + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ +#endif /* STM32F469xx || STM32F479xx */ }RCC_PeriphCLKInitTypeDef; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /** * @brief PLLI2S Clock structure definition */ typedef struct { -#if defined(STM32F411xE) +#if defined(STM32F411xE) uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ #endif /* STM32F411xE */ @@ -294,7 +332,7 @@ typedef struct This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ + This parameter can be a value of @ref RCC_RTC_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ @@ -310,7 +348,17 @@ typedef struct /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection * @{ */ -/*------------------------------- Peripheral Clock source for STM32F446xx -----------------------------*/ +/*------------------- Peripheral Clock source for STM32F410xx ----------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) +#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004) +#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008) +#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- Peripheral Clock source for STM32F446xx ----------------*/ #if defined(STM32F446xx) #define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001) #define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002) @@ -325,9 +373,23 @@ typedef struct #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400) #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800) #endif /* STM32F446xx */ -/*-----------------------------------------------------------------------------------------------------*/ +/*-----------------------------------------------------------------------------*/ + +/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) +#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002) +#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004) +#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008) +#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) +#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040) +#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000080) +#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000100) +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ -/*--------------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------------*/ +/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002) @@ -337,29 +399,44 @@ typedef struct #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040) #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -/*-----------------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*------------------------ Peripheral Clock source for STM32F40xxx/STM32F41xxx ------------------------*/ +/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002) #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ -/*-----------------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ /** * @} */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000) +#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001) +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000) #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000) #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000) #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -367,12 +444,12 @@ typedef struct /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider * @{ */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002) #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004) #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006) #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008) -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ /** * @} */ @@ -380,17 +457,17 @@ typedef struct /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider * @{ */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002) #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004) #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006) #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008) -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source * @{ */ @@ -410,7 +487,36 @@ typedef struct /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source + * @{ + */ +#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000) +#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000) +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) +/** + * @} + */ + +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000) +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) +/** + * @} + */ +#endif /* STM32F469xx || STM32F479xx */ #if defined(STM32F446xx) /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source @@ -502,11 +608,42 @@ typedef struct /** * @} */ - + #endif /* STM32F446xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + +/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source + * @{ + */ +#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000) +#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) +#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000) +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) +#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) +#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) +/** + * @} + */ + /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection * @{ */ @@ -515,9 +652,24 @@ typedef struct /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ -#if defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection + * @{ + */ +#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) +#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection * @{ */ @@ -526,7 +678,38 @@ typedef struct /** * @} */ -#endif /* STM32F411xE || STM32F446xx */ +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000) +#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000) +#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ /** * @} @@ -536,13 +719,49 @@ typedef struct /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros * @{ */ -/*------------------------------- STM32F42xxx/STM32F43xxx ----------------------------------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -/** @brief Enables or disables the AHB1 peripheral clock. +/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ @@ -627,7 +846,8 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ UNUSED(tmpreg); \ } while(0) - +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) @@ -640,6 +860,9 @@ typedef struct #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) /** * @brief Enable ETHERNET clock. @@ -657,14 +880,17 @@ typedef struct __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while(0) - -/** @brief Enable or disable the AHB2 peripheral clock. +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ - -#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ /* Delay after an RCC peripheral clock enabling */ \ @@ -673,7 +899,7 @@ typedef struct } while(0) #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) -#if defined(STM32F437xx)|| defined(STM32F439xx) +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ @@ -691,9 +917,40 @@ typedef struct #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F437xx || STM32F439xx */ +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +/** + * @} + */ -/** @brief Enables or disables the AHB3 peripheral clock. +/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_DISABLE();\ + }while(0) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -706,8 +963,22 @@ typedef struct UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ -/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -810,7 +1081,46 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ UNUSED(tmpreg); \ } while(0) - +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) @@ -824,8 +1134,12 @@ typedef struct #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +/** + * @} + */ -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -872,22 +1186,69 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ UNUSED(tmpreg); \ } while(0) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) -#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) -#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) -#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) - -#if defined(STM32F429xx)|| defined(STM32F439xx) -#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN)) +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F429xx || STM32F439xx */ +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -/** @brief Force or release AHB1 peripheral reset. - */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) @@ -896,7 +1257,10 @@ typedef struct #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) @@ -905,26 +1269,55 @@ typedef struct #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) - -/** @brief Force or release AHB2 peripheral reset. +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -#if defined(STM32F437xx)|| defined(STM32F439xx) +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F437xx || STM32F439xx */ +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +/** + * @} + */ -/** @brief Force or release AHB3 peripheral reset +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) - -/** @brief Force or release APB1 peripheral reset. + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. */ #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) @@ -939,7 +1332,17 @@ typedef struct #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) @@ -953,30 +1356,51 @@ typedef struct #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) +/** + * @} + */ -/** @brief Force or release APB2 peripheral reset. +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. */ #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) - +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) -#if defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F429xx|| STM32F439xx */ +#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ -/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) @@ -991,7 +1415,13 @@ typedef struct #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) @@ -1005,25 +1435,44 @@ typedef struct #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) - -/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) -#if defined(STM32F437xx)|| defined(STM32F439xx) +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F437xx || STM32F439xx */ - -/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. @@ -1032,7 +1481,16 @@ typedef struct #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) -/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. @@ -1051,7 +1509,17 @@ typedef struct #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) @@ -1065,8 +1533,12 @@ typedef struct #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) - -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. @@ -1078,7 +1550,13 @@ typedef struct #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) @@ -1086,22 +1564,65 @@ typedef struct #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) -#if defined(STM32F429xx)|| defined(STM32F439xx) +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F429xx || STM32F439xx */ +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */ -/*---------------------------------------------------------------------------------------------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ -/*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/ +/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) -/** @brief Enables or disables the AHB1 peripheral clock. +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ @@ -1137,13 +1658,16 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ UNUSED(tmpreg); \ } while(0) - +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) - +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) #if defined(STM32F407xx)|| defined(STM32F417xx) /** * @brief Enable ETHERNET clock. @@ -1195,12 +1719,33 @@ typedef struct __HAL_RCC_ETHMAC_CLK_DISABLE(); \ } while(0) #endif /* STM32F407xx || STM32F417xx */ - -/** @brief Enable or disable the AHB2 peripheral clock. +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_DISABLE();\ + }while(0) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + #if defined(STM32F407xx)|| defined(STM32F417xx) #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1230,8 +1775,12 @@ typedef struct #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) #endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ -/** @brief Enables or disables the AHB3 peripheral clock. +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -1244,8 +1793,12 @@ typedef struct UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) +/** + * @} + */ -/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -1327,7 +1880,46 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ UNUSED(tmpreg); \ } while(0) - +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) @@ -1339,8 +1931,12 @@ typedef struct #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -1366,27 +1962,68 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ UNUSED(tmpreg); \ } while(0) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0) -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) -#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +/** + * @} + */ -/** @brief Force or release AHB1 peripheral reset. - */ +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) - -/** @brief Force or release AHB2 peripheral reset. +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) + #if defined(STM32F407xx)|| defined(STM32F417xx) #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) @@ -1398,15 +2035,32 @@ typedef struct #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) - #endif /* STM32F415xx || STM32F417xx */ + +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) -/** @brief Force or release AHB3 peripheral reset +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +/** + * @} */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) + #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) +/** + * @} + */ -/** @brief Force or release APB1 peripheral reset. +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. */ #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) @@ -1419,7 +2073,17 @@ typedef struct #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) @@ -1431,18 +2095,35 @@ typedef struct #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ -/** @brief Force or release APB2 peripheral reset. +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. */ #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) - -/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) @@ -1453,7 +2134,13 @@ typedef struct #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) @@ -1464,13 +2151,28 @@ typedef struct #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ -/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + #if defined(STM32F407xx)|| defined(STM32F417xx) #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) @@ -1483,8 +2185,12 @@ typedef struct #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) #endif /* STM32F415xx || STM32F417xx */ - -/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. @@ -1492,8 +2198,12 @@ typedef struct */ #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) - -/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. @@ -1510,7 +2220,17 @@ typedef struct #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) @@ -1522,8 +2242,12 @@ typedef struct #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) - -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. @@ -1532,16 +2256,421 @@ typedef struct #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +/** + * @} + */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -/*---------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -/*------------------------------------------ STM32F411xx --------------------------------------*/ -#if defined(STM32F411xE) -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. +/*------------------------- STM32F401xE/STM32F401xC --------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_DISABLE();\ + }while(0) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +/** + * @} + */ +#endif /* STM32F401xC || STM32F401xE*/ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F410xx -------------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB1) peripheral clock. + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. */ #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1550,28 +2679,471 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ UNUSED(tmpreg); \ } while(0) -#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) - -/** @brief Force or release APB2 peripheral reset. +#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) +/** + * @} */ -#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) -#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + */ +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() +#define __HAL_RCC_AHB2_RELEASE_RESET() +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ */ -#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_AHB3_FORCE_RESET() +#define __HAL_RCC_AHB3_RELEASE_RESET() +/** + * @} + */ -#endif /* STM32F411xE */ -/*---------------------------------------------------------------------------------------------*/ +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + */ +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -/*----------------------------------------- STM32F446xx ---------------------------------------*/ -#if defined(STM32F446xx) -/** @brief Enables or disables the AHB1 peripheral clock. +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + */ +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) + +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + */ +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) +/** + * @} + */ + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F411xx -------------------------------*/ +#if defined(STM32F411xE) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_DISABLE();\ + }while(0) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +/** + * @} + */ +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + */ +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + */ +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + */ +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +/** + * @} + */ +#endif /* STM32F411xE */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F446xx -----------------------------*/ +#if defined(STM32F446xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ @@ -1600,13 +3172,21 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ UNUSED(tmpreg); \ } while(0) - +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) - -/** @brief Enable or disable the AHB2 peripheral clock. +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -1619,8 +3199,28 @@ typedef struct UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_DISABLE();\ + }while(0) -/** @brief Enables or disables the AHB3 peripheral clock. +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -1642,8 +3242,12 @@ typedef struct #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +/** + * @} + */ -/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -1746,7 +3350,46 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ UNUSED(tmpreg); \ } while(0) - +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) @@ -1761,8 +3404,12 @@ typedef struct #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. @@ -1802,44 +3449,101 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ UNUSED(tmpreg); \ } while(0) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) +/** + * @} + */ -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) -#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) -#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) - -/** @brief Force or release AHB1 peripheral reset. - */ +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) - -/** @brief Force or release AHB2 peripheral reset. +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} */ -#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) -#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -/** @brief Force or release AHB3 peripheral reset +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) + #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) - -/** @brief Force or release APB1 peripheral reset. +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. */ #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) @@ -1848,7 +3552,17 @@ typedef struct #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) - +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) @@ -1863,44 +3577,86 @@ typedef struct #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) - -/** @brief Force or release APB2 peripheral reset. +/** + * @} */ -#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) -#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) -#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + */ +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) -/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) -/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +/** + * @} + */ -/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. @@ -1911,8 +3667,12 @@ typedef struct #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +/** + * @} + */ -/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. @@ -1923,7 +3683,7 @@ typedef struct #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) @@ -1932,23 +3692,37 @@ typedef struct #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. @@ -1959,18 +3733,27 @@ typedef struct #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) +/** + * @} + */ #endif /* STM32F446xx */ -/*------------------------------------------------------------------------------------------------------------*/ - -/*------------------------------------------------- PLL Configuration ----------------------------------------*/ -#if defined(STM32F446xx) +/*----------------------------------------------------------------------------*/ +/*------------------------------- PLL Configuration --------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. * @param __RCC_PLLSource__: specifies the PLL entry clock source. @@ -1992,7 +3775,7 @@ typedef struct * This parameter must be a number in the range {2, 4, 6, or 8}. * * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work @@ -2000,7 +3783,7 @@ typedef struct * * @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note This parameter is only available in STM32F446xx devices. + * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx devices. * */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ @@ -2031,7 +3814,7 @@ typedef struct * This parameter must be a number in the range {2, 4, 6, or 8}. * * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work @@ -2043,10 +3826,23 @@ typedef struct ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) - #endif /* STM32F446xx */ -/*-------------------------------------------------------------------------------------------------------*/ + #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------PLLI2S Configuration ---------------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) -/*------------------------------------------- PLLI2S Configuration --------------------------------------*/ +/** @brief Macros to enable or disable the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) +#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #if defined(STM32F446xx) /** @brief Macro to configure the PLLI2S clock multiplication and division factors . * @note This macro must be used only when the PLLI2S is disabled. @@ -2057,8 +3853,7 @@ typedef struct * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 1 MHz to limit PLLI2S jitter. - * @note The PLLI2SM parameter is only used with STM32F411xE and STM32F446xx Devices - * + * * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between Min_Data = 192 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO @@ -2075,15 +3870,13 @@ typedef struct * * @param __PLLI2SQ__: specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note the PLLI2SQ parameter is only available with STM32F427/437/429x/439xx Devices - * */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\ - ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ + ((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\ + ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ + ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) #else /** @brief Macro to configure the PLLI2S clock multiplication and division factors . * @note This macro must be used only when the PLLI2S is disabled. @@ -2093,19 +3886,19 @@ typedef struct * This parameter must be a number between Min_Data = 192 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. + * * @param __PLLI2SR__: specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. - * + * */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | \ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) #endif /* STM32F446xx */ #if defined(STM32F411xE) - /** @brief Macro to configure the PLLI2S clock multiplication and division factors . * @note This macro must be used only when the PLLI2S is disabled. * @note This macro must be used only when the PLLI2S is disabled. @@ -2113,7 +3906,7 @@ typedef struct * HAL_RCC_ClockConfig() API). * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note The PLLI2SM parameter is only used with STM32F411xE Devices + * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLLI2S jitter. @@ -2131,7 +3924,7 @@ typedef struct ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) #endif /* STM32F411xE */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in @@ -2142,8 +3935,8 @@ typedef struct * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. * @param __PLLI2SQ__: specifies the division factor for SAI1 clock. * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx Devices - * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro + * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx + * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro * @param __PLLI2SR__: specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz @@ -2152,13 +3945,13 @@ typedef struct #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) |\ ((__PLLI2SQ__) << 24) |\ ((__PLLI2SR__) << 28)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -/*----------------------------------------------------------------------------------------------------------------*/ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ -/*--------------------------------------------------- PLLSAI Configuration ---------------------------------------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +/*------------------------------ PLLSAI Configuration ------------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macros to Enable or Disable the PLLISAI. - * @note The PLLSAI is only available with STM32F429x/439x Devices. + * @note The PLLSAI is only available with STM32F429x/439x Devices. * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) @@ -2196,6 +3989,30 @@ typedef struct ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \ ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)))) #endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 192 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. + * + * @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLSAIQ__: specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__: specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\ + ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\ + ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\ + ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))) +#endif /* STM32F469xx || STM32F479xx */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** @brief Macro to configure the PLLSAI clock multiplication and division factors. @@ -2218,14 +4035,15 @@ typedef struct ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))) #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ -/*----------------------------------------------------------------------------------------------------------------------*/ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ -/*----------------------------------------- PLLSAI/PLLI2S Dividers Configuration ---------------------------------------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) -/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. - * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock . +/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock. * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ */ @@ -2238,25 +4056,26 @@ typedef struct * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. * - * @note The LTDC peripheral is only available with STM32F427/437/429/439xx Devices. + * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. * @note This function must be called before enabling the PLLSAI. * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . * This parameter must be a number between Min_Data = 2 and Max_Data = 16. * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ - */ + */ #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -/*-----------------------------------------------------------------------------------------------------------------------------------*/ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ -/*-------------------------------------------------- Peripheral Clock selection -----------------------------------------------------*/ +/*------------------------- Peripheral Clock selection -----------------------*/ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /** @brief Macro to configure the I2S clock source (I2SCLK). * @note This function must be called before enabling the I2S APB clock. * @param __SOURCE__: specifies the I2S clock source. @@ -2266,12 +4085,12 @@ typedef struct * used as I2S clock source. */ #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) -#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro to configure SAI1BlockA clock source selection. - * @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices. + * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param __SOURCE__: specifies the SAI Block A clock source. @@ -2286,7 +4105,7 @@ typedef struct #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) /** @brief Macro to configure SAI1BlockB clock source selection. - * @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices. + * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param __SOURCE__: specifies the SAI Block B clock source. @@ -2299,11 +4118,11 @@ typedef struct * used as SAI1 Block B clock. */ #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #if defined(STM32F446xx) /** @brief Macro to configure SAI1 clock source selection. - * @note This configuration is only available with STM32F446xx Devices. + * @note This configuration is only available with STM32F446xx Devices. * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and * the SAI clock. * @param __SOURCE__: specifies the SAI1 clock source. @@ -2349,7 +4168,6 @@ typedef struct #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) /** @brief Macro to configure I2S APB1 clock source selection. - * @note This configuration is only available with STM32F446xx Devices. * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. * @param __SOURCE__: specifies the I2S APB1 clock source. * This parameter can be one of the following values: @@ -2361,7 +4179,6 @@ typedef struct #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) /** @brief Macro to Get I2S APB1 clock source selection. - * @note This configuration is only available with STM32F446xx Devices. * @retval The clock source can be one of the following values: * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. @@ -2371,7 +4188,6 @@ typedef struct #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) /** @brief Macro to configure I2S APB2 clock source selection. - * @note This configuration is only available with STM32F446xx Devices. * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. * @param __SOURCE__: specifies the SAI Block A clock source. * This parameter can be one of the following values: @@ -2383,7 +4199,6 @@ typedef struct #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) /** @brief Macro to Get I2S APB2 clock source selection. - * @note This configuration is only available with STM32F446xx Devices. * @retval The clock source can be one of the following values: * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. @@ -2406,21 +4221,21 @@ typedef struct * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock */ #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) - + /** @brief Macro to configure the FMPI2C1 clock. * @param __SOURCE__: specifies the FMPI2C1 clock source. * This parameter can be one of the following values: - * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock - * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock - * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock + * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock */ #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) /** @brief Macro to Get the FMPI2C1 clock. * @retval The clock source can be one of the following values: - * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock - * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock - * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock + * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock */ #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) @@ -2469,10 +4284,115 @@ typedef struct */ #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) #endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__: specifies the CK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock. + * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) - +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock. + * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock. + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__: specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) + +/** @brief Macro to configure the DSI clock. + * @param __SOURCE__: specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) + +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @brief Macro to configure I2S clock source selection. + * @param __SOURCE__: specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. + * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) + +/** @brief Macro to Get I2S clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. + * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. + */ +#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__: specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the LPTIM1 clock. + * @param __SOURCE__: specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the LPTIM1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /** @brief Macro to configure the Timers clocks prescalers * @note This feature is only available with STM32F429x/439x Devices. * @param __PRESC__ : specifies the Timers clocks prescalers selection @@ -2488,11 +4408,12 @@ typedef struct */ #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ + STM32F446xx || STM32F469xx || STM32F479xx */ -/*-------------------------------------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @brief Enable PLLSAI_RDY interrupt. */ #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) @@ -2515,7 +4436,27 @@ typedef struct */ #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup RCCEx_MCO1_Enable MCO1 Enable + * @brief Macros to enable or disable the RCC MCO1 feature. + */ +#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) +#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) +/** + * @} + */ + +/** @defgroup RCCEx_MCO2_Enable MCO2 Enable + * @brief Macros to enable or disable the RCC MCO2 feature. + */ +#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) +#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ /** * @} @@ -2536,9 +4477,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); #endif /* STM32F446xx */ -#if defined(STM32F411xE) || defined(STM32F446xx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) void HAL_RCCEx_SelectLSEMode(uint8_t Mode); -#endif /* STM32F411xE || STM32F446xx */ +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -2558,20 +4500,60 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode); * @{ */ /* --- CR Register ---*/ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Alias word address of PLLSAION bit */ #define RCC_PLLSAION_BIT_NUMBER 0x1C #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4)) +#define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) +/* Alias word address of PLLI2SON bit */ +#define RCC_PLLI2SON_BIT_NUMBER 0x1A +#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + /* --- DCKCFGR Register ---*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /* Alias word address of TIMPRE bit */ #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) #define RCC_TIMPRE_BIT_NUMBER 0x18 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +/* --- CFGR Register ---*/ +#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) +/* Alias word address of I2SSRC bit */ +#define RCC_I2SSRC_BIT_NUMBER 0x17 +#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4)) + +#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/* Alias word address of MCO1EN bit */ +#define RCC_MCO1EN_BIT_NUMBER 0x8 +#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4)) + +/* Alias word address of MCO2EN bit */ +#define RCC_MCO2EN_BIT_NUMBER 0x9 +#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ - /** * @} */ @@ -2589,23 +4571,32 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode); */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F)) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007F)) #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003)) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007)) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001F)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + #if defined(STM32F446xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000007FF)) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000FFF)) #endif /* STM32F446xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FF)) +#endif /* STM32F469xx || STM32F479xx */ + #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432)) @@ -2622,14 +4613,34 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode); ((VALUE) == RCC_PLLSAIDIVR_4) ||\ ((VALUE) == RCC_PLLSAIDIVR_8) ||\ ((VALUE) == RCC_PLLSAIDIVR_16)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -#if defined(STM32F446xx) || defined(STM32F411xE) +#if defined(STM32F411xE) || defined(STM32F446xx) #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63) #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) -#endif /* STM32F446xx || STM32F411xE */ +#endif /* STM32F411xE || STM32F446xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ #if defined(STM32F446xx) #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) @@ -2679,10 +4690,46 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode); #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\ ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) -#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ +#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) + +#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c index 136c5d657d..a7a966fae3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rng.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -70,7 +70,9 @@ #ifdef HAL_RNG_MODULE_ENABLED #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /* Private types -------------------------------------------------------------*/ @@ -500,7 +502,8 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx */ #endif /* HAL_RNG_MODULE_ENABLED */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h index e4890fd41a..b70a463491 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rng.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention @@ -44,7 +44,9 @@ #endif #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -352,7 +354,8 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F410xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c index 735205eb6b..44f914f570 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: * + Initialization and de-initialization functions * + RTC Time and Date functions * + RTC Alarm functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions * @verbatim @@ -565,10 +565,10 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Get subseconds structure field from the corresponding register */ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); - - /* Get SecondFraction structure field from the corresponding register field */ - sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); + /* Get SecondFraction structure field from the corresponding register field*/ + sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); + /* Get the TR register */ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h index 76bf948ba1..dbbfa2906c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -110,10 +110,10 @@ typedef struct uint8_t Seconds; /*!< Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - + uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ - + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity */ @@ -122,8 +122,8 @@ typedef struct corresponding to Synchronous pre-scaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. - This field will be used only by HAL_RTC_GetTime function */ - + This field will be used only by HAL_RTC_GetTime function */ + uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation. This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c index 11d046d93d..7e6e1deb53 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: @@ -210,7 +210,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS * falling edge of the related pin. * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx devices) * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices * @retval HAL status @@ -744,10 +744,32 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - + + /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ + if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + { + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* Get tick */ tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ @@ -757,14 +779,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Process Unlocked */ __HAL_UNLOCK(hrtc); - + return HAL_TIMEOUT; - } + } } /* Clear the Wake-up Timer clock source bits in CR register */ @@ -813,10 +835,32 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - + + /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ + if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + { + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* Get tick */ tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ @@ -826,14 +870,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - + hrtc->State = HAL_RTC_STATE_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(hrtc); - + return HAL_TIMEOUT; - } + } } /* Configure the Wake-up Timer counter */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h index dcc820e591..8a497f81eb 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention @@ -68,7 +68,7 @@ typedef struct This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ uint32_t PinSelection; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */ + This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */ uint32_t Trigger; /*!< Specifies the Tamper Trigger. This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ @@ -147,7 +147,6 @@ typedef struct */ #define RTC_TAMPERPIN_DEFAULT ((uint32_t)0x00000000) #define RTC_TAMPERPIN_POS1 ((uint32_t)0x00010000) - /** * @} */ @@ -157,7 +156,6 @@ typedef struct */ #define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) #define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00020000) - /** * @} */ @@ -397,7 +395,7 @@ typedef struct * @arg RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) /** * @brief Enable interrupt on the RTC Wake-up Timer associated Exti line. @@ -921,10 +919,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \ ((PIN) == RTC_TAMPERPIN_POS1)) - + #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \ ((PIN) == RTC_TIMESTAMPPIN_POS1)) - + #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c index 187c45bf70..57102f1995 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sai.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief SAI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI) peripheral: @@ -173,7 +173,8 @@ #ifdef HAL_SAI_MODULE_ENABLED -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /** @defgroup SAI_Private_Typedefs SAI Private Typedefs @@ -420,7 +421,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); /* SAI Block_x SLOT Configuration ------------------------------------------*/ - /* This register has no meaning in AC97 and SPDIF audio protocol */ + /* This register has no meaning in AC 97 and SPDIF audio protocol */ hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN )); @@ -1603,7 +1604,7 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) } /** - * @brief disabled the SAI and wait the disabling + * @brief Disable the SAI and wait the disabling * @param hsai : pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None. @@ -1895,7 +1896,7 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma) * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_SAI_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h index 13d9d2fc7a..668a774bff 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sai.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention @@ -49,7 +49,8 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @addtogroup SAI * @{ @@ -670,7 +671,7 @@ typedef struct __SAI_HandleTypeDef /** @addtogroup SAI_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); +HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai); void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); @@ -889,8 +890,8 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); /** * @} */ - -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c index 275c27c15d..3123d8bc3b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sai_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief SAI Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of SAI extension peripheral: @@ -68,7 +68,8 @@ #ifdef HAL_SAI_MODULE_ENABLED -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -142,7 +143,8 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) SAI2->GCR = tmpregisterGCR; } #endif /* STM32F446xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) /* This setting must be done with both audio block (A & B) disabled */ switch(hsai->Init.SynchroExt) { @@ -157,7 +159,7 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) break; } SAI1->GCR = tmpregisterGCR; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ } /** * @brief Get SAI Input Clock based on SAI source clock selection @@ -180,7 +182,8 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) saiclocksource = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); } #endif /* STM32F446xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) uint32_t vcoinput = 0, tmpreg = 0; /* Check the SAI Block parameters */ @@ -243,7 +246,7 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) saiclocksource = EXTERNAL_CLOCK_VALUE; } -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ /* the return result is the value of SAI clock */ return saiclocksource; } @@ -256,7 +259,7 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_SAI_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h index 638bfd77ee..699380d0ea 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sai_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of SAI Extension HAL module. ****************************************************************************** * @attention @@ -54,10 +54,11 @@ * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SAIEx_Exported_Functions * @{ @@ -68,7 +69,7 @@ */ /* Extended features functions ************************************************/ -void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai); +void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai); uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai); /** * @} @@ -83,7 +84,7 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai); /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c index c9e9a46605..5329810e6c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sd.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -180,7 +180,10 @@ #include "stm32f4xx_hal.h" #ifdef HAL_SD_MODULE_ENABLED - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /** @addtogroup STM32F4xx_HAL_Driver * @{ */ @@ -3474,7 +3477,8 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t * /** * @} */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_SD_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h index 8d8a1ac21e..753fac98ef 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sd.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of SD HAL module. ****************************************************************************** * @attention @@ -42,7 +42,10 @@ #ifdef __cplusplus extern "C" { #endif - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_ll_sdmmc.h" @@ -779,7 +782,8 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); /** * @} */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c index bcf1dfe15b..8f8c2dd180 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sdram.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief SDRAM HAL module driver. * This file provides a generic firmware to drive SDRAM memories mounted * as external device. @@ -102,7 +102,8 @@ * @{ */ #ifdef HAL_SDRAM_MODULE_ENABLED -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -829,7 +830,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_SDRAM_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h index ab7782e4dc..a0dd701c35 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sdram.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of SDRAM HAL module. ****************************************************************************** * @attention @@ -43,7 +43,8 @@ extern "C" { #endif -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_ll_fmc.h" @@ -181,7 +182,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c index b3bc7e3182..a8c1f5c261 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_smartcard.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h index 43fec1f631..17c2354b13 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_smartcard.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c index 63a40954c9..015f1f755b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_spdifrx.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief This file provides firmware functions to manage the following * functionalities of the SPDIFRX audio interface: * + Initialization and Configuration diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h index c0d84bc40f..6c2a5e117a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_spdifrx.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of SPDIFRX HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c index 541dae00eb..1777d3521e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief SPI HAL module driver. * * This file provides firmware functions to manage the following @@ -2110,7 +2110,7 @@ static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi) /** * @brief DMA SPI transmit receive process complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h index 145846ce8d..95ab593d61 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c index 77f6fd3512..ecc68c1cee 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sram.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -106,7 +106,7 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -669,7 +669,8 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_SRAM_MODULE_ENABLED */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h index a77d4c8c55..7bb8dc48a3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sram.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention @@ -44,13 +44,14 @@ #endif /* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** @addtogroup STM32F4xx_HAL_Driver @@ -59,7 +60,8 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + /** @addtogroup SRAM * @{ */ @@ -189,7 +191,8 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c index 7c8eaf8c15..189bd70aea 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h index e60782528a..b68bc97eb7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c index 9feb385fa0..049dc30909 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -1723,6 +1723,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) return HAL_OK; } + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h index 81cf0769b7..cf62ff3f18 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention @@ -136,12 +136,23 @@ typedef struct #endif /* STM32F446xx */ /** * @} - */ - + */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup TIMEx_SystemBreakInput TIM System Break Input + * @{ + */ +#define TIM_SYSTEMBREAKINPUT_HARDFAULT ((uint32_t)0x00000001) /* Core Lockup lock output(Hardfault) is connected to Break Input of TIM1 and TIM8 */ +#define TIM_SYSTEMBREAKINPUT_PVD ((uint32_t)0x00000004) /* PVD Interrupt is connected to Break Input of TIM1 and TIM8 */ +#define TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD ((uint32_t)0x00000005) /* Core Lockup lock output(Hardfault) and PVD Interrupt are connected to Break Input of TIM1 and TIM8 */ +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + /** * @} */ - /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIMEx_Exported_Functions @@ -293,6 +304,12 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim); ((TIM_REMAP) == TIM_TIM11_HSE)) #endif /* STM32F446xx */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_TIM_SYSTEMBREAKINPUT(BREAKINPUT) (((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT)||\ + ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_PVD)||\ + ((BREAKINPUT) == TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD)) + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c index 786b79842e..7a4ca19b51 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_uart.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h index f3f8c0a622..2826e2465c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_uart.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of UART HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c index 6eb31b1524..a296d95071 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_usart.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h index f6a135a4c0..c026ce3777 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_usart.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of USART HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c index 01a6186d21..7114039c21 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_wwdg.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h index 37d99426a9..e2d1ae3bd7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_wwdg.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c index ef1055ded3..bf28b4b9c5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fmc.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -87,7 +87,7 @@ #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -160,9 +160,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); -#if !defined (STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); -#endif /* !defined (STM32F446xx) */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); @@ -170,10 +170,10 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); -#if defined (STM32F446xx) +#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); assert_param(IS_FMC_PAGESIZE(Init->PageSize)); -#endif /* defined (STM32F446xx) */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ /* Get the BTCR register value */ tmpr = Device->BTCR[Init->NSBank]; @@ -201,7 +201,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini Init->AsynchronousWait |\ Init->WriteBurst |\ Init->ContinuousClock); -#else /* defined(STM32F446xx) */ +#else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN, WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */ tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ @@ -243,12 +243,12 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini Init->ContinuousClock); } -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) if(Init->NSBank != FMC_NORSRAM_BANK1) { Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); } -#endif /* defined(STM32F446xx) */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ return HAL_OK; } @@ -365,10 +365,10 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); -#if !defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); -#endif /* !defined(STM32F446xx) */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); @@ -388,7 +388,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef (((Timing->CLKDivision)-1) << 20) |\ (((Timing->DataLatency)-2) << 24) |\ (Timing->AccessMode)); -#else /* defined(STM32F446xx) */ +#else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); @@ -496,7 +496,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @{ */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @@ -1108,7 +1108,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui * @} */ -#endif /* defined(STM32F446xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ /** * @} */ @@ -1635,16 +1635,16 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com { return HAL_TIMEOUT; } - } + } } - - return HAL_OK; + + return HAL_OK; } /** * @brief Program the SDRAM Memory Refresh rate. * @param Device: Pointer to SDRAM device instance - * @param RefreshRate: The SDRAM refresh rate value. + * @param RefreshRate: The SDRAM refresh rate value. * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) @@ -1719,7 +1719,7 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h index 3386a27134..03fb06d6b2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fmc.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention @@ -53,7 +53,8 @@ /** @addtogroup FMC_LL * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private types -------------------------------------------------------------*/ /** @defgroup FMC_LL_Private_Types FMC Private Types * @{ @@ -89,7 +90,7 @@ typedef struct uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FMC_Wrap_Mode - This mode is not available for the STM32F446xx devices */ + This mode is not available for the STM32F446/467/479xx devices */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, @@ -122,7 +123,7 @@ typedef struct This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. This parameter can be a value of @ref FMC_Write_FIFO - This mode is available only for the STM32F446xx devices */ + This mode is available only for the STM32F446/469/479xx devices */ uint32_t PageSize; /*!< Specifies the memory page size. This parameter can be a value of @ref FMC_Page_Size @@ -420,7 +421,7 @@ typedef struct /** @defgroup FMC_Wrap_Mode FMC Wrap Mode * @{ */ -/** @note This mode is not available for the STM32F446xx devices +/** @note This mode is not available for the STM32F446/469/479xx devices */ #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400) @@ -474,7 +475,7 @@ typedef struct */ /** @defgroup FMC_Page_Size FMC Page Size - * @note These values are available only for the STM32F446xx devices. + * @note These values are available only for the STM32F446/469/479xx devices. * @{ */ #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) @@ -486,7 +487,7 @@ typedef struct */ /** @defgroup FMC_Write_FIFO FMC Write FIFO - * @note These values are available only for the STM32F446xx devices. + * @note These values are available only for the STM32F446/469/479xx devices. * @{ */ #define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000) @@ -760,23 +761,23 @@ typedef struct /** @defgroup FMC_LL_Alias_definition FMC Alias definition * @{ */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define FMC_NAND_TypeDef FMC_Bank3_TypeDef #else #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef -#endif /* defined(STM32F446xx) */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define FMC_NAND_DEVICE FMC_Bank3 #else #define FMC_NAND_DEVICE FMC_Bank2_3 #define FMC_PCCARD_DEVICE FMC_Bank4 -#endif /* defined(STM32F446xx) */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ #define FMC_NORSRAM_DEVICE FMC_Bank1 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E #define FMC_SDRAM_DEVICE FMC_Bank5_6 @@ -820,7 +821,7 @@ typedef struct * @brief macros to handle NAND device enable/disable * @{ */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Enable the NAND device access. * @param __INSTANCE__: FMC_NAND Instance @@ -855,7 +856,7 @@ typedef struct #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \ ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN)) -#endif /* defined(STM32F446xx)*/ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ /** * @} */ @@ -886,7 +887,7 @@ typedef struct * @brief macros to handle FMC flags and interrupts * @{ */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Enable the NAND device interrupt. * @param __INSTANCE__: FMC_NAND instance @@ -996,7 +997,7 @@ typedef struct */ #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ ((__INSTANCE__)->SR3 &= ~(__FLAG__))) -#endif /* defined(STM32F446xx) */ +#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** @@ -1164,10 +1165,10 @@ typedef struct #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) -#if !defined (STM32F446xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FMC_WRAP_MODE_ENABLE)) -#endif /* !defined (STM32F446xx) */ + ((__MODE__) == FMC_WRAP_MODE_ENABLE)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) @@ -1275,7 +1276,7 @@ typedef struct #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) -#if defined (STM32F446xx) +#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \ ((SIZE) == FMC_PAGE_SIZE_128) || \ ((SIZE) == FMC_PAGE_SIZE_256) || \ @@ -1283,7 +1284,7 @@ typedef struct #define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \ ((FIFO) == FMC_WRITE_FIFO_ENABLE)) -#endif /* defined (STM32F446xx) */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} @@ -1404,7 +1405,7 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t B * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c index 005d5e1700..65ac3ea682 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fsmc.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief FSMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -84,7 +84,7 @@ */ #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -377,7 +377,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi /** * @} */ - + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /** @addtogroup FSMC_LL_NAND * @brief NAND Controller functions * @@ -938,11 +939,12 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) /** * @} */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */ /** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h index 56b3ebd422..1ffaacb554 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fsmc.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of FSMC HAL module. ****************************************************************************** * @attention @@ -54,7 +54,7 @@ * @{ */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /* Private types -------------------------------------------------------------*/ /** @defgroup FSMC_LL_Private_Types FSMC Private Types * @{ @@ -159,6 +159,7 @@ typedef struct }FSMC_NORSRAM_TimingTypeDef; +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /** * @brief FSMC NAND Configuration Structure definition */ @@ -241,6 +242,7 @@ typedef struct /** * @} */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ /* Private constants ---------------------------------------------------------*/ /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants @@ -403,6 +405,7 @@ typedef struct * @} */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller * @{ */ @@ -466,7 +469,8 @@ typedef struct /** * @} */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition * @{ */ @@ -494,13 +498,17 @@ typedef struct */ #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #define FSMC_NORSRAM_DEVICE FSMC_Bank1 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define FSMC_NAND_DEVICE FSMC_Bank2_3 #define FSMC_PCCARD_DEVICE FSMC_Bank4 +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef @@ -517,6 +525,7 @@ typedef struct #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef @@ -546,18 +555,23 @@ typedef struct #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define FMC_NAND_TypeDef FSMC_NAND_TypeDef #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE -#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE +#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define FMC_NAND_DEVICE FSMC_NAND_DEVICE #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE #define FMC_NAND_BANK2 FSMC_NAND_BANK2 +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 @@ -612,6 +626,7 @@ typedef struct * @brief macros to handle NAND device enable/disable * @{ */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /** * @brief Enable the NAND device access. * @param __INSTANCE__: FSMC_NAND Instance @@ -766,6 +781,7 @@ typedef struct /** * @} */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros * @{ @@ -911,6 +927,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev * @} */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /** @defgroup FSMC_LL_NAND NAND * @{ */ @@ -955,11 +972,12 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); /** * @} */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c index fb61e41c3e..8cfd007f7f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -177,8 +177,11 @@ * @{ */ -#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) - +#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -492,7 +495,8 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) /** * @} */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h index 801a9f8178..6a920cc93f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention @@ -42,7 +42,10 @@ #ifdef __cplusplus extern "C" { #endif - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -792,7 +795,9 @@ typedef struct */ #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) -#if !defined(STM32F446xx) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) /** * @brief Enable the command completion signal. * @retval None @@ -828,7 +833,8 @@ typedef struct * @retval None */ #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) -#endif /* !defined(STM32F446xx) */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\ + STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** * @} */ @@ -898,7 +904,8 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); /** * @} */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c index a094e0c963..b1ab9f8963 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.c * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -62,8 +62,11 @@ * @{ */ -#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) - +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -203,7 +206,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c uint32_t i = 0; /*Activate VBUS Sensing B */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; if (cfg.vbus_sensing_enable == 0) @@ -222,7 +225,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; } -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ /* Restart the Phy Clock */ USBx_PCGCCTL = 0; @@ -1135,13 +1138,13 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef USBx_PCGCCTL = 0; /* Activate VBUS Sensing B */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; #else USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN); USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN); USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; -#endif /* STM32F446xx */ +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ /* Disable the FS/LS support mode only */ if((cfg.speed == USB_OTG_SPEED_FULL)&& @@ -1695,8 +1698,9 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) /** * @} */ - -#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ +#endif /* defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) */ /** * @} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h index 9f43ca830a..27c8c5a208 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.h * @author MCD Application Team - * @version V1.3.2 - * @date 26-June-2015 + * @version V1.4.1 + * @date 09-October-2015 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention @@ -42,7 +42,10 @@ #ifdef __cplusplus extern "C" { #endif - +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -125,6 +128,8 @@ typedef struct uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ @@ -452,7 +457,8 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); /** * @} */ - +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ #ifdef __cplusplus } #endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.s index f584368489..919f1d969e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.s +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.s @@ -52,8 +52,7 @@ Stack_Size EQU 0x00000400 Stack_Mem SPACE Stack_Size -;FAIL __initial_sp EQU 0x20020000 ; Top of RAM -__initial_sp +__initial_sp EQU 0x10008000 ; Top of RAM, L4-ECC-SRAM2 retained in standby ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct index 4b652c4753..59fe0fc151 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct @@ -37,11 +37,11 @@ LR_IROM1 0x08000000 0x100000 { ; load region size_region } ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM - RW_IRAM1 (0x20000000+0x188) (0x20000-0x188) { ; RW data + RW_IRAM1 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby .ANY (+RW +ZI) } - RW_IRAM2 0x10000000 0x00008000 { + RW_IRAM2 0x20000000 0x00018000 { ; RW data 96k L4-SRAM1 .ANY (+RW +ZI) } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_STD/startup_stm32l476xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_STD/startup_stm32l476xx.s index 7e7747a02e..9fca91d026 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_STD/startup_stm32l476xx.s +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_STD/startup_stm32l476xx.s @@ -39,7 +39,7 @@ ; ;******************************************************************************* -__initial_sp EQU 0x20020000 ; Top of RAM +__initial_sp EQU 0x10008000 ; Top of RAM, L4-ECC-SRAM2 retained in standby PRESERVE8 THUMB diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_STD/stm32l476xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_STD/stm32l476xx.sct index 4b652c4753..59fe0fc151 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_STD/stm32l476xx.sct +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_ARM_STD/stm32l476xx.sct @@ -37,11 +37,11 @@ LR_IROM1 0x08000000 0x100000 { ; load region size_region } ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM - RW_IRAM1 (0x20000000+0x188) (0x20000-0x188) { ; RW data + RW_IRAM1 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby .ANY (+RW +ZI) } - RW_IRAM2 0x10000000 0x00008000 { + RW_IRAM2 0x20000000 0x00018000 { ; RW data 96k L4-SRAM1 .ANY (+RW +ZI) } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_GCC_ARM/STM32L476XX.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_GCC_ARM/STM32L476XX.ld index 5bc54cd929..3d73c57997 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_GCC_ARM/STM32L476XX.ld +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_GCC_ARM/STM32L476XX.ld @@ -2,7 +2,8 @@ MEMORY { FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - RAM (rwx) : ORIGIN = 0x20000188, LENGTH = 128K - 0x188 + SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188 + SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k } /* Linker script to place sections and symbol values. Should be used together @@ -111,7 +112,7 @@ SECTIONS __data_end__ = .; _edata = .; - } > RAM + } > SRAM2 .bss : { @@ -123,7 +124,7 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; _ebss = .; - } > RAM + } > SRAM2 .heap (COPY): { @@ -131,7 +132,7 @@ SECTIONS end = __end__; *(.heap*) __HeapLimit = .; - } > RAM + } > SRAM2 /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign @@ -139,11 +140,11 @@ SECTIONS .stack_dummy (COPY): { *(.stack*) - } > RAM + } > SRAM2 /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2); _estack = __StackTop; __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_IAR/stm32l476xx.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_IAR/stm32l476xx.icf index 0b25af6ef9..9571587029 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_IAR/stm32l476xx.icf +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/TOOLCHAIN_IAR/stm32l476xx.icf @@ -3,20 +3,20 @@ define symbol __intvec_start__ = 0x08000000; define symbol __region_ROM_start__ = 0x08000000; define symbol __region_ROM_end__ = 0x080FFFFF; -/* [RAM = 128kb = 0x20000] */ +/* [RAM = 96kb + 32kb = 0x20000] */ /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */ -define symbol __region_RAM_start__ = 0x20000188; -define symbol __region_RAM_end__ = 0x2001FFFF; -define symbol __region_SRAM2_start__ = 0x10000000; +define symbol __NVIC_start__ = 0x10000000; +define symbol __NVIC_end__ = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */ +define symbol __region_SRAM2_start__ = 0x10000188; define symbol __region_SRAM2_end__ = 0x10007FFF; +define symbol __region_SRAM1_start__ = 0x20000000; +define symbol __region_SRAM1_end__ = 0x20017FFF; /* Memory regions */ define memory mem with size = 4G; define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__]; +define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__]; /* Stack 1/8 and Heap 1/4 of RAM */ define symbol __size_cstack__ = 0x4000; @@ -31,5 +31,5 @@ do not initialize { section .noinit }; place at address mem:__intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; -place in SRAM2_region { }; \ No newline at end of file +place in SRAM2_region { readwrite, block STACKHEAP }; +place in SRAM1_region { }; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.s new file mode 100644 index 0000000000..919f1d969e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_MICRO/startup_stm32l476xx.s @@ -0,0 +1,417 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32l476xx.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 26-June-2015 +;* Description : STM32L476xx Ultra Low Power devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size + +__initial_sp EQU 0x10008000 ; Top of RAM, L4-ECC-SRAM2 retained in standby + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM3_IRQHandler ; SD Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM0_IRQHandler ; SD Filter 0 global Interrupt + DCD DFSDM1_IRQHandler ; SD Filter 1 global Interrupt + DCD DFSDM2_IRQHandler ; SD Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM0_IRQHandler [WEAK] + EXPORT DFSDM1_IRQHandler [WEAK] + EXPORT DFSDM2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM0_IRQHandler +DFSDM1_IRQHandler +DFSDM2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct new file mode 100644 index 0000000000..59fe0fc151 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct @@ -0,0 +1,49 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 1MB FLASH (0x100000) + 128KB SRAM (0x20000) +LR_IROM1 0x08000000 0x100000 { ; load region size_region + + ER_IROM1 0x08000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby + .ANY (+RW +ZI) + } + + RW_IRAM2 0x20000000 0x00018000 { ; RW data 96k L4-SRAM1 + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_STD/startup_stm32l476xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_STD/startup_stm32l476xx.s new file mode 100644 index 0000000000..9fca91d026 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_STD/startup_stm32l476xx.s @@ -0,0 +1,389 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32l476xx.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 26-June-2015 +;* Description : STM32L476xx Ultra Low Power devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x10008000 ; Top of RAM, L4-ECC-SRAM2 retained in standby + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM3_IRQHandler ; SD Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM0_IRQHandler ; SD Filter 0 global Interrupt + DCD DFSDM1_IRQHandler ; SD Filter 1 global Interrupt + DCD DFSDM2_IRQHandler ; SD Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM0_IRQHandler [WEAK] + EXPORT DFSDM1_IRQHandler [WEAK] + EXPORT DFSDM2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM0_IRQHandler +DFSDM1_IRQHandler +DFSDM2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_STD/stm32l476xx.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_STD/stm32l476xx.sct new file mode 100644 index 0000000000..59fe0fc151 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_STD/stm32l476xx.sct @@ -0,0 +1,49 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 1MB FLASH (0x100000) + 128KB SRAM (0x20000) +LR_IROM1 0x08000000 0x100000 { ; load region size_region + + ER_IROM1 0x08000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x10000000+0x188) (0x08000-0x188) { ; RW data 32k L4-ECC-SRAM2 retained in standby + .ANY (+RW +ZI) + } + + RW_IRAM2 0x20000000 0x00018000 { ; RW data 96k L4-SRAM1 + .ANY (+RW +ZI) + } + +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..bb665909b9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_GCC_ARM/STM32L476XX.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_GCC_ARM/STM32L476XX.ld new file mode 100644 index 0000000000..3d73c57997 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_GCC_ARM/STM32L476XX.ld @@ -0,0 +1,154 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188 + SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > SRAM2 + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > SRAM2 + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > SRAM2 + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM2 + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.s new file mode 100644 index 0000000000..c006305dc9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_GCC_ARM/startup_stm32l476xx.s @@ -0,0 +1,529 @@ +/** + ****************************************************************************** + * @file startup_stm32l476xx.s + * @author MCD Application Team + * @version V1.0.0 + * @date 26-June-2015 + * @brief STM32L476xx devices vector table for Atollic + * TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word DFSDM3_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word SDMMC1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DFSDM0_IRQHandler + .word DFSDM1_IRQHandler + .word DFSDM2_IRQHandler + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word OTG_FS_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word SAI2_IRQHandler + .word SWPMI1_IRQHandler + .word TSC_IRQHandler + .word LCD_IRQHandler + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DFSDM3_IRQHandler + .thumb_set DFSDM3_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DFSDM0_IRQHandler + .thumb_set DFSDM0_IRQHandler,Default_Handler + + .weak DFSDM1_IRQHandler + .thumb_set DFSDM1_IRQHandler,Default_Handler + + .weak DFSDM2_IRQHandler + .thumb_set DFSDM2_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_IAR/startup_stm32l476xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_IAR/startup_stm32l476xx.s new file mode 100644 index 0000000000..57bbda040c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_IAR/startup_stm32l476xx.s @@ -0,0 +1,637 @@ +;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32l476xx.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 26-June-2015 +;* Description : STM32L476xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM3_IRQHandler ; SD Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM0_IRQHandler ; SD Filter 0 global Interrupt + DCD DFSDM1_IRQHandler ; SD Filter 1 global Interrupt + DCD DFSDM2_IRQHandler ; SD Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK DFSDM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM3_IRQHandler + B DFSDM3_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DFSDM0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM0_IRQHandler + B DFSDM0_IRQHandler + + PUBWEAK DFSDM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_IRQHandler + B DFSDM1_IRQHandler + + PUBWEAK DFSDM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM2_IRQHandler + B DFSDM2_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_IAR/stm32l476xx.icf b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_IAR/stm32l476xx.icf new file mode 100644 index 0000000000..9571587029 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/TOOLCHAIN_IAR/stm32l476xx.icf @@ -0,0 +1,35 @@ +/* [ROM = 1024kb = 0x100000] */ +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x080FFFFF; + +/* [RAM = 96kb + 32kb = 0x20000] */ +/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x10000000; +define symbol __NVIC_end__ = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */ +define symbol __region_SRAM2_start__ = 0x10000188; +define symbol __region_SRAM2_end__ = 0x10007FFF; +define symbol __region_SRAM1_start__ = 0x20000000; +define symbol __region_SRAM1_end__ = 0x20017FFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__]; +define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__]; + +/* Stack 1/8 and Heap 1/4 of RAM */ +define symbol __size_cstack__ = 0x4000; +define symbol __size_heap__ = 0x8000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in SRAM2_region { readwrite, block STACKHEAP }; +place in SRAM1_region { }; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis.h new file mode 100644 index 0000000000..41a1233f3b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32l4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.c new file mode 100644 index 0000000000..9263c748e7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.h new file mode 100644 index 0000000000..2af8d33e21 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/cmsis_nvic.h @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187 +// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM +#define NVIC_NUM_VECTORS 98 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/hal_tick.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/hal_tick.c new file mode 100644 index 0000000000..48e22d387b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/hal_tick.c @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file hal_tick.c + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "hal_tick.h" + +TIM_HandleTypeDef TimMasterHandle; +uint32_t PreviousVal = 0; + +void us_ticker_irq_handler(void); + +void timer_irq_handler(void) { + // Channel 1 for mbed timeout + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) { + us_ticker_irq_handler(); + } + + // Channel 2 for HAL tick + if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) { + __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); + uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + if ((val - PreviousVal) >= HAL_TICK_DELAY) { + // Increment HAL variable + HAL_IncTick(); + // Prepare next interrupt + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + PreviousVal = val; +#if 0 // For DEBUG only + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); +#endif + } + } +} + +// Reconfigure the HAL tick using a standard timer instead of systick. +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { + // Enable timer clock + TIM_MST_RCC; + + // Reset timer + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; + + // Update the SystemCoreClock variable + SystemCoreClockUpdate(); + + // Configure time base + TimMasterHandle.Instance = TIM_MST; + TimMasterHandle.Init.Period = 0xFFFFFFFF; + TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick + TimMasterHandle.Init.ClockDivision = 0; + TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + HAL_TIM_OC_Init(&TimMasterHandle); + + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); + + // Channel 1 for mbed timeout + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1); + + // Channel 2 for HAL tick + HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); + PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); + __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); + +#if 0 // For DEBUG only + __GPIOB_CLK_ENABLE(); + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +#endif + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/hal_tick.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/hal_tick.h new file mode 100644 index 0000000000..1fe17e9f84 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/hal_tick.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32l4xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/stm32l476xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/stm32l476xx.h new file mode 100644 index 0000000000..b37d205849 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/stm32l476xx.h @@ -0,0 +1,9784 @@ +/** + ****************************************************************************** + * @file stm32l476xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 26-June-2015 + * @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32l476xx + * @{ + */ + +#ifndef __STM32L476xx_H +#define __STM32L476xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M4 Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + DFSDM3_IRQn = 42, /*!< SD Filter 3 global Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + DFSDM0_IRQn = 61, /*!< SD Filter 0 global Interrupt */ + DFSDM1_IRQn = 62, /*!< SD Filter 1 global Interrupt */ + DFSDM2_IRQn = 63, /*!< SD Filter 2 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ + LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ + LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ + QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ + SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ + TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ + LCD_IRQn = 78, /*!< LCD global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32l4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t CR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t ISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t ICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t JCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t JDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t RDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t AWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t AWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t AWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t AWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t EXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t EXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t CNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t AWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA option register, Address offset: 0x00 */ +} DMA_request_TypeDef; + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + + +/** + * @brief Firewall + */ + +typedef struct +{ + __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ + __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ + __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ + __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ + __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ + __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ +} FIREWALL_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ +} FLASH_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */ + +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ +} PWR_TypeDef; + + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration register, Address offset: 0x0C */ + __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 Configuration Register, Address offset: 0x10 */ + __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 Configuration Register, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC LowSpeed APB1 macrocells resets Low Word, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC LowSpeed APB1 macrocells resets High Word, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC High Speed APB macrocells resets, Address offset: 0x40 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock enable register, Address offset: 0x50 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC LowSpeed APB1 macrocells clock enables Low Word, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC LowSpeed APB1 macrocells clock enables High Word, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC High Speed APB macrocells clock enabled, Address offset: 0x60 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 macrocells clocks enables in sleep mode, Address offset: 0x60 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 macrocells clock enables in sleep mode, Address offset: 0x64 */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 macrocells clock enables in sleep mode, Address offset: 0x70 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC LowSpeed APB1 macrocells clock enables in sleep mode Low Word, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC LowSpeed APB1 macrocells clock enables in sleep mode High Word, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC High Speed APB macrocells clock enabled in sleep mode, Address offset: 0x80 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC IPs Clocks Configuration Register, Address offset: 0x88 */ + __IO uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ +} SPI_TypeDef; + + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ + __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ +} TIM_TypeDef; + + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ + uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + uint16_t RESERVED4; /*!< Reserved, 0x26 */ + __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + uint16_t RESERVED5; /*!< Reserved, 0x2A */ +} USART_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ + uint32_t Reserved30[2]; /* Reserved 030h*/ + __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ + __IO uint32_t CID; /* User ID Register 03Ch*/ + uint32_t Reserved5[3]; /* Reserved 040h-048h*/ + __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ + uint32_t Reserved6; /* Reserved 050h*/ + __IO uint32_t GLPMCFG; /* LPM Register 054h*/ + __IO uint32_t GPWRDN; /* Power Down Register 058h*/ + __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ + __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ + uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ + __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /* dev Configuration Register 800h*/ + __IO uint32_t DCTL; /* dev Control Register 804h*/ + __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ + uint32_t Reserved0C; /* Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ + __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ + __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ + __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved9; /* Reserved 824h*/ + __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ + __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ + __IO uint32_t DTHRCTL; /* dev thr 830h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ + __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ + uint32_t Reserved40; /* dedicated EP mask 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(96 KB) base address*/ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address */ +#define FMC_BASE ((uint32_t)0x60000000) /*!< FMC base address */ +#define SRAM2_BASE ((uint32_t)0x10000000) /*!< SRAM2(32 KB) base address*/ +#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC control registers base address */ +#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x12000000) /*!< SRAM2(32 KB) base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX ((uint32_t)0x00018000) /*!< maximum SRAM1 size (up to 96 KBytes) */ +#define SRAM2_SIZE ((uint32_t)0x00008000) /*!< SRAM2 size (32 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000) +#define FMC_BANK3 (FMC_BASE + 0x20000000) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400) + + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) +#define DFSDM_BASE (APB2PERIPH_BASE + 0x6000) +#define DFSDM_Channel0_BASE (DFSDM_BASE + 0x00) +#define DFSDM_Channel1_BASE (DFSDM_BASE + 0x20) +#define DFSDM_Channel2_BASE (DFSDM_BASE + 0x40) +#define DFSDM_Channel3_BASE (DFSDM_BASE + 0x60) +#define DFSDM_Channel4_BASE (DFSDM_BASE + 0x80) +#define DFSDM_Channel5_BASE (DFSDM_BASE + 0xA0) +#define DFSDM_Channel6_BASE (DFSDM_BASE + 0xC0) +#define DFSDM_Channel7_BASE (DFSDM_BASE + 0xE0) +#define DFSDM_Filter0_BASE (DFSDM_BASE + 0x100) +#define DFSDM_Filter1_BASE (DFSDM_BASE + 0x180) +#define DFSDM_Filter2_BASE (DFSDM_BASE + 0x200) +#define DFSDM_Filter3_BASE (DFSDM_BASE + 0x280) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8) + + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006C) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8) + + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00) + +#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200) +#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) +#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t )0xE0042000) + +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) + +#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) +#define USB_OTG_DEVICE_BASE ((uint32_t )0x800) +#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) +#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) +#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) +#define USB_OTG_HOST_BASE ((uint32_t )0x400) +#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) +#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) +#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) +#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) +#define USB_OTG_FIFO_BASE ((uint32_t )0x1000) +#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN ((CAN_TypeDef *) CAN1_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC1_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE) +#define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE) +#define DFSDM_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM_Channel2_BASE) +#define DFSDM_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM_Channel3_BASE) +#define DFSDM_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM_Channel4_BASE) +#define DFSDM_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM_Channel5_BASE) +#define DFSDM_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM_Channel6_BASE) +#define DFSDM_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM_Channel7_BASE) +#define DFSDM_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM_Filter0_BASE) +#define DFSDM_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM_Filter1_BASE) +#define DFSDM_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM_Filter2_BASE) +#define DFSDM_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM_Filter3_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE) + + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */ +#define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */ +#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */ +#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD ((uint32_t)0x20000000) /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */ +#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */ + +#define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */ +#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */ + +#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */ + +#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */ +#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */ +#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */ +#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */ + +#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */ +#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */ + +#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */ +#define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */ +#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */ +#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */ + +#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */ +#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */ +#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */ +#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */ +#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */ + +#define ADC_CFGR_JQDIS ((uint32_t)0x80000000) /*!< ADC Injected queue disable */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE ((uint32_t)0x00000001) /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE ((uint32_t)0x00000002) /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /*!< ADC OVSR bit 0 */ +#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /*!< ADC OVSR bit 1 */ +#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /*!< ADC OVSR bit 2 */ + +#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /*!< ADC OVSS bit 0 */ +#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /*!< ADC OVSS bit 1 */ +#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /*!< ADC OVSS bit 2 */ +#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /*!< ADC OVSS bit 3 */ + +#define ADC_CFGR2_TROVS ((uint32_t)0x00000200) /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM ((uint32_t)0x00000400) /*!< ADC Regular oversampling mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */ +#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */ +#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */ + +#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */ +#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */ +#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */ + +#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */ +#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */ +#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */ + +#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */ +#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */ +#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */ + +#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */ +#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */ +#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */ + +#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */ +#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */ +#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */ + +#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */ +#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */ +#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */ + +#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */ +#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */ +#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */ + +#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */ +#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */ +#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */ + +#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */ +#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */ +#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */ + +/******************** Bit definition for ADC_TR1 register ********************/ +#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */ +#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */ +#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */ +#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */ +#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */ +#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */ +#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */ +#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */ +#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */ +#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */ +#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */ +#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */ +#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */ + +#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */ +#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */ +#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */ +#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */ +#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */ +#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */ +#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */ +#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */ +#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */ +#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */ +#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */ +#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */ +#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */ + +/******************** Bit definition for ADC_TR2 register ********************/ +#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */ +#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ +#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ +#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ +#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ +#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ +#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ +#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ +#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ + +#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */ +#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */ +#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */ +#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */ +#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */ +#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */ +#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */ +#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */ +#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */ + +/******************** Bit definition for ADC_TR3 register ********************/ +#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */ +#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ +#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ +#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ +#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ +#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ +#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ +#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ +#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ + +#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */ +#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */ +#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */ +#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */ +#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */ +#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */ +#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */ +#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */ +#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */ +#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */ + +#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */ +#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */ +#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */ +#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */ +#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */ + +#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */ +#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */ +#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */ +#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */ +#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */ + +#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */ +#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */ +#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */ +#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */ +#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */ + +#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */ +#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */ +#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */ +#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */ +#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */ +#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */ +#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */ +#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */ +#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */ + +#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */ +#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */ +#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */ +#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */ +#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */ + +#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */ + +#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */ + +#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */ +#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */ +#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */ +#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */ +#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */ + +#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */ +#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */ +#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */ +#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */ +#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */ + +#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */ +#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */ +#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */ +#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */ +#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */ + +#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */ +#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */ +#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */ +#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */ +#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */ + +#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */ +#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */ +#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */ +#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */ +#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */ +#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */ +#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */ +#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */ +#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */ +#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */ +#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */ +#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */ +#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */ +#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */ +#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */ +#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */ +#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */ +#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */ +#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */ +#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */ +#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */ + +#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */ +#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */ +#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */ +#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */ + +#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */ +#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */ + +#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */ + + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */ +#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */ +#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */ +#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */ +#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */ +#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */ +#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */ +#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */ +#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */ +#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */ +#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */ +#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */ + +#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */ +#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */ +#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */ +#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */ +#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */ + +#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */ +#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */ +#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */ +#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */ +#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */ +#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */ +#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */ +#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */ +#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */ +#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */ +#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */ +#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */ + +#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */ +#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */ +#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */ +#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */ +#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */ + +#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */ +#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */ +#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */ +#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */ +#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */ +#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */ +#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */ +#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */ +#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */ +#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */ +#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */ +#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */ + +#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */ +#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */ +#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */ +#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */ +#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */ + +#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */ +#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */ +#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */ +#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */ +#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */ +#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */ +#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */ +#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */ +#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */ +#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */ +#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */ +#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */ + +#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */ +#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */ +#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */ +#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */ +#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */ + +#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ +#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ +#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ +#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ +#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ +#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ +#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ +#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ +#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ +#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ +#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ +#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ +#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ +#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ +#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ +#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ +#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ +#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ +#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ +#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ +#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ +#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ +#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ +#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ +#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ +#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ +#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ +#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ +#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ +#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ +#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ +#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ +#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ +#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ +#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ +#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ +#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ +#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ +#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ +#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ +#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ +#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ +#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ +#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ +#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ +#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ +#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ +#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ +#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ +#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ +#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ +#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ +#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ +#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ +#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ +#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ +#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ +#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ +#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ +#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ +#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFF) /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000001) /*!< ADC AWD2CH bit 0 */ +#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 1 */ +#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 2 */ +#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 3 */ +#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 4 */ +#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 5 */ +#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 6 */ +#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 7 */ +#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 8 */ +#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 9 */ +#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 10 */ +#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 11 */ +#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 12 */ +#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 13 */ +#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 14 */ +#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 15 */ +#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 16 */ +#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 17 */ +#define ADC_AWD2CR_AWD2CH_18 ((uint32_t)0x00040000) /*!< ADC AWD2CH bit 18 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFF) /*!< ADC Analog watchdog 3 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000001) /*!< ADC AWD3CH bit 0 */ +#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 1 */ +#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 2 */ +#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 3 */ +#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 4 */ +#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 5 */ +#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 6 */ +#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 7 */ +#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 8 */ +#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 9 */ +#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 10 */ +#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 11 */ +#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 12 */ +#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 13 */ +#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 14 */ +#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 15 */ +#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 16 */ +#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 17 */ +#define ADC_AWD3CR_AWD3CH_18 ((uint32_t)0x00040000) /*!< ADC AWD3CH bit 18 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFF) /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000001) /*!< ADC DIFSEL bit 0 */ +#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 1 */ +#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 2 */ +#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 3 */ +#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 4 */ +#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 5 */ +#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 6 */ +#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 7 */ +#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 8 */ +#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 9 */ +#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 10 */ +#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 11 */ +#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 12 */ +#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 13 */ +#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 14 */ +#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 15 */ +#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 16 */ +#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 17 */ +#define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00040000) /*!< ADC DIFSEL bit 18 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */ +#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */ +#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */ +#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */ +#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */ +#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */ +#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */ + +#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */ +#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */ +#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */ +#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */ +#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */ +#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */ +#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ + +#define ADC_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL ((uint32_t)0x0000001F) /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 ((uint32_t)0x00000001) /*!< Dual bit 0 */ +#define ADC_CCR_DUAL_1 ((uint32_t)0x00000002) /*!< Dual bit 1 */ +#define ADC_CCR_DUAL_2 ((uint32_t)0x00000004) /*!< Dual bit 2 */ +#define ADC_CCR_DUAL_3 ((uint32_t)0x00000008) /*!< Dual bit 3 */ +#define ADC_CCR_DUAL_4 ((uint32_t)0x00000010) /*!< Dual bit 4 */ + +#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */ +#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */ +#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */ +#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */ + +#define ADC_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */ + +#define ADC_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */ +#define ADC_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */ +#define ADC_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */ + +#define ADC_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */ +#define ADC_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */ + +#define ADC_CCR_PRESC ((uint32_t)0x003C0000) /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /*!< ADC prescaler bit 0 */ +#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /*!< ADC prescaler bit 1 */ +#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /*!< ADC prescaler bit 2 */ +#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /*!< ADC prescaler bit 3 */ + +#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */ +#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register ********************/ +#define ADC_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */ +#define ADC_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */ +#define ADC_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */ +#define ADC_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */ +#define ADC_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */ +#define ADC_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */ +#define ADC_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */ +#define ADC_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */ +#define ADC_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */ +#define ADC_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */ +#define ADC_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */ +#define ADC_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */ +#define ADC_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */ +#define ADC_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */ +#define ADC_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */ +#define ADC_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */ +#define ADC_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */ + +#define ADC_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */ +#define ADC_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */ +#define ADC_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */ +#define ADC_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */ +#define ADC_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */ +#define ADC_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */ +#define ADC_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */ +#define ADC_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */ +#define ADC_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */ +#define ADC_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */ +#define ADC_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */ +#define ADC_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */ +#define ADC_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */ +#define ADC_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */ +#define ADC_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */ +#define ADC_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */ +#define ADC_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ +/*!*/ +#define DAC_CR_CEN1 ((uint32_t)0x00004000) /*!*/ + +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!*/ +#define DAC_CR_CEN2 ((uint32_t)0x40000000) /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!
      © COPYRIGHT(c) 2015 STMicroelectronics
      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx + * @{ + */ + +#ifndef __STM32L4xx_H +#define __STM32L4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32L4) +#define STM32L4 +#endif /* STM32L4 */ + +/* Uncomment the line below according to the target STM32L4 device used in your + application + */ + +#if !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) + /* #define STM32L471xx */ /*!< STM32L471xx Devices */ + /* #define STM32L475xx */ /*!< STM32L475xx Devices */ +#define STM32L476xx /*!< STM32L476xx Devices */ + /* #define STM32L485xx */ /*!< STM32L485xx Devices */ + /* #define STM32L486xx */ /*!< STM32L486xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.0.0 + */ +#define __STM32L4xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L4xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32L4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L4xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ + |(__CMSIS_DEVICE_VERSION_SUB1 << 16)\ + |(__CMSIS_DEVICE_VERSION_SUB2 << 8 )\ + |(__CMSIS_DEVICE_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32L471xx) + #include "stm32l471xx.h" +#elif defined(STM32L475xx) + #include "stm32l475xx.h" +#elif defined(STM32L476xx) + #include "stm32l476xx.h" +#elif defined(STM32L485xx) + #include "stm32l485xx.h" +#elif defined(STM32L486xx) + #include "stm32l486xx.h" +#else + #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32l4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32L4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.c new file mode 100644 index 0000000000..ec977662f3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.c @@ -0,0 +1,591 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 26-June-2015 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | or PLL_MSI + * | (external 8 MHz xtal) | (internal 4 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 48 | 80 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 48 | 80 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 48 | 80 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 48 | 80 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | YES | NO + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** @addtogroup STM32L4xx_System_Private_Includes + * @{ + */ + +#include "stm32l4xx.h" +#include "hal_tick.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Macros + * @{ + */ + +// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON) +#define USE_PLL_HSE_EXTC (1) // Use external clock +#define USE_PLL_HSE_XTAL (0) // Use external xtal +#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI) +#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 4000000; + + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \ + 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +#if (USE_PLL_HSI != 0) +uint8_t SetSysClock_PLL_HSI(void); +#endif + +uint8_t SetSysClock_PLL_MSI(void); + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00000800; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = MSI_VALUE; // At this stage the MSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2; + + /* Get MSI Range frequency--------------------------------------------------*/ + if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) + { /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8; + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ; + + switch (pllsource) + { + case 0x02: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = (msirange / pllm); + break; + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2; + SystemCoreClock = pllvco/pllr; + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ +#if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { + /* 3- If fail start with HSI or MSI clock */ +#if (USE_PLL_HSI != 0) + if (SetSysClock_PLL_HSI() == 0) +#else + if (SetSysClock_PLL_MSI() == 0) +#endif + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 1 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +#endif +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + + // Used to gain time after DeepSleep in case HSI is used + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + return 0; + } + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + + // Non-USB configuration : sysclock = 80MHz + //RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) + //RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + //RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + //RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB + //RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + + // USB configuration : sysclock = 48 MHz + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) + RCC_OscInitStruct.PLL.PLLN = 24; // VCO output clock = 192 MHz (8 MHz * 24) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB + RCC_OscInitStruct.PLL.PLLR = 4; // PLL clock = 48 MHz (192 MHz / 4) + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 2 + if (bypass == 0) + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + else + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz +#endif + + return 1; // OK +} +#endif + +#if (USE_PLL_HSI != 0) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 3 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz +#endif + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by MSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_MSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + + // Enable LSE Oscillator to automatically calibrate the MSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { + RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode + } + + // Enable MSI oscillator and activate PLL with MSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; // 4 MHz + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 4 MHz (4 MHz / 1) + RCC_OscInitStruct.PLL.PLLN = 40; // VCO output clock = 160 MHz (4 MHz * 40) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 4 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz +#endif + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.h new file mode 100644 index 0000000000..8c067a2b72 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.h @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.h + * @author MCD Application Team + * @version V1.0.0 + * @date 26-June-2015 + * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2015 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L4XX_H +#define __SYSTEM_STM32L4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32L4xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/W7500.sct new file mode 100644 index 0000000000..f9ead04667 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/W7500.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/startup_W7500x.S b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/startup_W7500x.S new file mode 100644 index 0000000000..124a5e65c8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/startup_W7500x.S @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/W7500.sct new file mode 100644 index 0000000000..f9ead04667 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/W7500.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/startup_W7500x.S b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/startup_W7500x.S new file mode 100644 index 0000000000..5b161ed02e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/startup_W7500x.S @@ -0,0 +1,186 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/W7500.ld b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/W7500.ld new file mode 100644 index 0000000000..0d53146fc5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/W7500.ld @@ -0,0 +1,152 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.S b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.S new file mode 100644 index 0000000000..2808b2ad57 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.S @@ -0,0 +1,259 @@ +/* File: startup_W7500.s + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 20 Dezember 2012 + * + */ +/* Copyright (c) 2011 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x200 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + +/* Vector Table */ + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long SSP0_Handler /* 16+ 0: SSP 0 Handler */ + .long SSP1_Handler /* 16+ 1: SSP 1 Handler */ + .long UART0_Handler /* 16+ 2: UART 0 Handler */ + .long UART1_Handler /* 16+ 3: UART 1 Handler */ + .long UART2_Handler /* 16+ 4: UART 2 Handler */ + .long I2C0_Handler /* 16+ 5: I2C 0 Handler */ + .long I2C1_Handler /* 16+ 6: I2C 1 Handler */ + .long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */ + .long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */ + .long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */ + .long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */ + .long DMA_Handler /* 16+11: DMA Combined Handler */ + .long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */ + .long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */ + .long PWM0_Handler /* 16+ 14: PWM0 Handler */ + .long PWM1_Handler /* 16+ 15: PWM1 Handler */ + .long PWM2_Handler /* 16+ 16: PWM2 Handler */ + .long PWM3_Handler /* 16+ 17: PWM3 Handler */ + .long PWM4_Handler /* 16+ 18: PWM4 Handler */ + .long PWM5_Handler /* 16+ 19: PWM5 Handler */ + .long PWM6_Handler /* 16+ 20: PWM6 Handler */ + .long PWM7_Handler /* 16+ 21: PWM7 Handler */ + .long RTC_Handler /* 16+ 22: RTC Handler */ + .long ADC_Handler /* 16+ 23: ADC Handler */ + .long WZTOE_Handler /* 16+ 24: WZTOE Handler */ + .long EXTI_Handler /* 16+ 25: EXTI Handler */ + + .size __isr_vector, . - __isr_vector +/* Reset Handler */ + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif /* __STARTUP_CLEAR_BSS */ + + /*bl _start*/ + bl main + + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + +/* System Exception Handlers */ + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + +/* IRQ Handlers */ + + def_default_handler SSP0_Handler + def_default_handler SSP1_Handler + def_default_handler UART0_Handler + def_default_handler UART1_Handler + def_default_handler UART2_Handler + def_default_handler I2C0_Handler + def_default_handler I2C1_Handler + def_default_handler PORT0_Handler + def_default_handler PORT1_Handler + def_default_handler PORT2_Handler + def_default_handler PORT3_Handler + + def_default_handler DMA_Handler + def_default_handler DUALTIMER0_Handler + def_default_handler DUALTIMER1_Handler + def_default_handler PWM0_Handler + def_default_handler PWM1_Handler + def_default_handler PWM2_Handler + def_default_handler PWM3_Handler + def_default_handler PWM4_Handler + def_default_handler PWM5_Handler + def_default_handler PWM6_Handler + def_default_handler PWM7_Handler + def_default_handler RTC_Handler + def_default_handler ADC_Handler + def_default_handler WZTOE_Handler + def_default_handler EXTI_Handler + + /* + def_default_handler Default_Handler + .weak DEF_IRQHandler + .set DEF_IRQHandler, Default_Handler + */ + + .end + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.o b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.o new file mode 100644 index 0000000000..6154940481 Binary files /dev/null and b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/TOOLCHAIN_GCC_ARM/startup_W7500.o differ diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/W7500.sct new file mode 100644 index 0000000000..f9ead04667 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/W7500.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/startup_W7500x.S b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/startup_W7500x.S new file mode 100644 index 0000000000..124a5e65c8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/startup_W7500x.S @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/W7500.sct b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/W7500.sct new file mode 100644 index 0000000000..f9ead04667 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/W7500.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00020000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/startup_W7500x.S b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/startup_W7500x.S new file mode 100644 index 0000000000..5b161ed02e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/startup_W7500x.S @@ -0,0 +1,186 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_GCC_ARM/W7500.ld b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_GCC_ARM/W7500.ld new file mode 100644 index 0000000000..0d53146fc5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_GCC_ARM/W7500.ld @@ -0,0 +1,152 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_GCC_ARM/startup_W7500.S b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_GCC_ARM/startup_W7500.S new file mode 100644 index 0000000000..2808b2ad57 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_GCC_ARM/startup_W7500.S @@ -0,0 +1,259 @@ +/* File: startup_W7500.s + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 20 Dezember 2012 + * + */ +/* Copyright (c) 2011 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x200 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + +/* Vector Table */ + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long SSP0_Handler /* 16+ 0: SSP 0 Handler */ + .long SSP1_Handler /* 16+ 1: SSP 1 Handler */ + .long UART0_Handler /* 16+ 2: UART 0 Handler */ + .long UART1_Handler /* 16+ 3: UART 1 Handler */ + .long UART2_Handler /* 16+ 4: UART 2 Handler */ + .long I2C0_Handler /* 16+ 5: I2C 0 Handler */ + .long I2C1_Handler /* 16+ 6: I2C 1 Handler */ + .long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */ + .long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */ + .long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */ + .long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */ + .long DMA_Handler /* 16+11: DMA Combined Handler */ + .long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */ + .long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */ + .long PWM0_Handler /* 16+ 14: PWM0 Handler */ + .long PWM1_Handler /* 16+ 15: PWM1 Handler */ + .long PWM2_Handler /* 16+ 16: PWM2 Handler */ + .long PWM3_Handler /* 16+ 17: PWM3 Handler */ + .long PWM4_Handler /* 16+ 18: PWM4 Handler */ + .long PWM5_Handler /* 16+ 19: PWM5 Handler */ + .long PWM6_Handler /* 16+ 20: PWM6 Handler */ + .long PWM7_Handler /* 16+ 21: PWM7 Handler */ + .long RTC_Handler /* 16+ 22: RTC Handler */ + .long ADC_Handler /* 16+ 23: ADC Handler */ + .long WZTOE_Handler /* 16+ 24: WZTOE Handler */ + .long EXTI_Handler /* 16+ 25: EXTI Handler */ + + .size __isr_vector, . - __isr_vector +/* Reset Handler */ + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif /* __STARTUP_CLEAR_BSS */ + + /*bl _start*/ + bl main + + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + +/* System Exception Handlers */ + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + +/* IRQ Handlers */ + + def_default_handler SSP0_Handler + def_default_handler SSP1_Handler + def_default_handler UART0_Handler + def_default_handler UART1_Handler + def_default_handler UART2_Handler + def_default_handler I2C0_Handler + def_default_handler I2C1_Handler + def_default_handler PORT0_Handler + def_default_handler PORT1_Handler + def_default_handler PORT2_Handler + def_default_handler PORT3_Handler + + def_default_handler DMA_Handler + def_default_handler DUALTIMER0_Handler + def_default_handler DUALTIMER1_Handler + def_default_handler PWM0_Handler + def_default_handler PWM1_Handler + def_default_handler PWM2_Handler + def_default_handler PWM3_Handler + def_default_handler PWM4_Handler + def_default_handler PWM5_Handler + def_default_handler PWM6_Handler + def_default_handler PWM7_Handler + def_default_handler RTC_Handler + def_default_handler ADC_Handler + def_default_handler WZTOE_Handler + def_default_handler EXTI_Handler + + /* + def_default_handler Default_Handler + .weak DEF_IRQHandler + .set DEF_IRQHandler, Default_Handler + */ + + .end + diff --git a/libraries/mbed/targets/cmsis/core_caFunc.h b/libraries/mbed/targets/cmsis/core_caFunc.h index 3f40094440..76cf80bace 100644 --- a/libraries/mbed/targets/cmsis/core_caFunc.h +++ b/libraries/mbed/targets/cmsis/core_caFunc.h @@ -2,12 +2,12 @@ * @file core_caFunc.h * @brief CMSIS Cortex-A Core Function Access Header File * @version V3.10 - * @date 9 May 2013 + * @date 30 Oct 2013 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2012 ARM LIMITED +/* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -147,8 +147,6 @@ __STATIC_ASM void __set_PSP(uint32_t topOfProcStack) /** \brief Set User Mode This function changes the processor state to User Mode - - \param [in] topOfProcStack USR/SYS Stack Pointer value to set */ __STATIC_ASM void __set_CPS_USR(void) { @@ -253,7 +251,7 @@ __STATIC_INLINE uint32_t __get_CPACR(void) This function assigns the given value to the Coprocessor Access Control register. - \param [in] cpacr Coporcessor Acccess Control value to set + \param [in] cpacr Coprocessor Acccess Control value to set */ __STATIC_INLINE void __set_CPACR(uint32_t cpacr) { @@ -275,7 +273,7 @@ __STATIC_INLINE uint32_t __get_CBAR() { /** \brief Get TTBR0 - This function returns the value of the Configuration Base Address register. + This function returns the value of the Translation Table Base Register 0. \return Translation Table Base Register 0 value */ @@ -286,7 +284,7 @@ __STATIC_INLINE uint32_t __get_TTBR0() { /** \brief Set TTBR0 - This function assigns the given value to the Coprocessor Access Control register. + This function assigns the given value to the Translation Table Base Register 0. \param [in] ttbr0 Translation Table Base Register 0 value to set */ @@ -309,7 +307,7 @@ __STATIC_INLINE uint32_t __get_DACR() { /** \brief Set DACR - This function assigns the given value to the Coprocessor Access Control register. + This function assigns the given value to the Domain Access Control Register. \param [in] dacr Domain Access Control Register value to set */ @@ -325,7 +323,7 @@ __STATIC_INLINE void __set_DACR(uint32_t dacr) { This function assigns the given value to the System Control Register. - \param [in] sctlr System Control Register, value to set + \param [in] sctlr System Control Register value to set */ __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) { @@ -397,9 +395,9 @@ __STATIC_INLINE void __enable_mmu(void) { __ISB(); } -/** \brief Enable MMU +/** \brief Disable MMU - Enable MMU + Disable MMU */ __STATIC_INLINE void __disable_mmu(void) { // Clear M bit 0 to disable the MMU @@ -477,8 +475,9 @@ __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { __DMB(); //ensure the ordering of data cache maintenance operations and their effects } -/** \brief - * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. +/** \brief Clean and Invalidate the entire data or unified cache + + Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. */ #pragma push #pragma arm @@ -522,12 +521,12 @@ Dccsw CMP R0, #1 BNE Dccisw MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way B cont -Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way +Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way cont SUBS R9, R9, #1 // Decrement the Way number BGE Loop3 SUBS R7, R7, #1 // Decrement the Set number BGE Loop2 -Skip ADD R10, R10, #2 // increment the cache number +Skip ADD R10, R10, #2 // Increment the cache number CMP R3, R10 BGT Loop1 @@ -539,9 +538,6 @@ Finished } #pragma pop -/** \brief __v7_all_cache - helper function - - */ /** \brief Invalidate the whole D$ @@ -577,7 +573,6 @@ __STATIC_INLINE void __v7_clean_inv_dcache_all(void) { #error IAR Compiler support not implemented for Cortex-A #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ - /* GNU gcc specific functions */ #define MODE_USR 0x10 @@ -620,14 +615,12 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) { #if 1 - uint32_t result; - - __ASM volatile ("mrs %0, apsr" : "=r" (result) ); - return (result); + register uint32_t __regAPSR; + __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) ); #else register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); #endif + return(__regAPSR); } @@ -694,22 +687,49 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr) \param [in] topOfProcStack USR/SYS Stack Pointer value to set */ -extern void __set_PSP(uint32_t topOfProcStack); +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __asm__ volatile ( + ".ARM;" + ".eabi_attribute Tag_ABI_align8_preserved,1;" + + "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */ + "MRS R1, CPSR;" + "CPS %0;" /* ;no effect in USR mode */ + "MOV SP, R0;" + "MSR CPSR_c, R1;" /* ;no effect in USR mode */ + "ISB;" + //"BX LR;" + : + : "i"(MODE_SYS) + : "r0", "r1"); + return; +} /** \brief Set User Mode This function changes the processor state to User Mode - - \param [in] topOfProcStack USR/SYS Stack Pointer value to set */ -extern void __set_CPS_USR(void); +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void) +{ + __asm__ volatile ( + ".ARM;" + + "CPS %0;" + //"BX LR;" + : + : "i"(MODE_USR) + : ); + return; +} + /** \brief Enable FIQ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ -#define __enable_fault_irq __enable_fiq +#define __enable_fault_irq() __asm__ volatile ("cpsie f") /** \brief Disable FIQ @@ -717,7 +737,7 @@ extern void __set_CPS_USR(void); This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ -#define __disable_fault_irq __disable_fiq +#define __disable_fault_irq() __asm__ volatile ("cpsid f") /** \brief Get FPSCR @@ -825,7 +845,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void) This function assigns the given value to the Coprocessor Access Control register. - \param [in] cpacr Coporcessor Acccess Control value to set + \param [in] cpacr Coprocessor Acccess Control value to set */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr) { @@ -856,7 +876,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() { /** \brief Get TTBR0 - This function returns the value of the Configuration Base Address register. + This function returns the value of the Translation Table Base Register 0. \return Translation Table Base Register 0 value */ @@ -872,7 +892,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() { /** \brief Set TTBR0 - This function assigns the given value to the Coprocessor Access Control register. + This function assigns the given value to the Translation Table Base Register 0. \param [in] ttbr0 Translation Table Base Register 0 value to set */ @@ -904,7 +924,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() { /** \brief Set DACR - This function assigns the given value to the Coprocessor Access Control register. + This function assigns the given value to the Domain Access Control Register. \param [in] dacr Domain Access Control Register value to set */ @@ -924,7 +944,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr This function assigns the given value to the System Control Register. - \param [in] sctlr System Control Register, value to set + \param [in] sctlr System Control Register value to set */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) { @@ -1005,9 +1025,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) { __ISB(); } -/** \brief Enable MMU +/** \brief Disable MMU - Enable MMU + Disable MMU */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) { // Clear M bit 0 to disable the MMU @@ -1109,14 +1129,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mv __DMB(); //ensure the ordering of data cache maintenance operations and their effects } -/** \brief - * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. +/** \brief Clean and Invalidate the entire data or unified cache + + Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. */ - -/** \brief __v7_all_cache - helper function - - */ - extern void __v7_all_cache(uint32_t op); diff --git a/libraries/mbed/targets/cmsis/core_ca_mmu.h b/libraries/mbed/targets/cmsis/core_ca_mmu.h index 1fb99c5e7e..189b073dbc 100644 --- a/libraries/mbed/targets/cmsis/core_ca_mmu.h +++ b/libraries/mbed/targets/cmsis/core_ca_mmu.h @@ -1,14 +1,13 @@ ;/**************************************************************************//** ; * @file core_ca_mmu.h -; * @brief MMU Startup File for -; * VE_A9_MP Device Series +; * @brief MMU Startup File for A9_MP Device Series ; * @version V1.01 -; * @date 25 March 2013 +; * @date 10 Sept 2014 ; * ; * @note ; * ; ******************************************************************************/ -;/* Copyright (c) 2012 ARM LIMITED +;/* Copyright (c) 2012-2014 ARM LIMITED ; ; All rights reserved. ; Redistribution and use in source and binary forms, with or without @@ -298,7 +297,7 @@ __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, else if ((priv == RW) && (user == READ)) { ap = 0x2; } else if ((priv == RW) && (user == RW)) { ap = 0x3; } else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } - else if ((priv == READ) && (user == READ)) { ap = 0x6; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } } else { //Simplified access @@ -647,7 +646,7 @@ __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, The function creates a section descriptor. Assumptions: - - 16MB super sections not suported + - 16MB super sections not supported - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor - Functions always return 0 diff --git a/libraries/mbed/targets/cmsis/core_cm0.h b/libraries/mbed/targets/cmsis/core_cm0.h index ab31de0ee8..cf2b5d66ba 100644 --- a/libraries/mbed/targets/cmsis/core_cm0.h +++ b/libraries/mbed/targets/cmsis/core_cm0.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -39,13 +39,13 @@ #pragma system_include /* treat file as system include file for MISRA check */ #endif +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + #ifdef __cplusplus extern "C" { #endif -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: @@ -68,8 +68,8 @@ */ /* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ @@ -81,14 +81,18 @@ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) @@ -96,9 +100,16 @@ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + #endif -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all */ #define __FPU_USED 0 @@ -107,26 +118,40 @@ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif #endif #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ +#ifdef __cplusplus +} +#endif + #endif /* __CORE_CM0_H_GENERIC */ #ifndef __CMSIS_GENERIC @@ -134,6 +159,10 @@ #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT +#ifdef __cplusplus + extern "C" { +#endif + /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV @@ -196,14 +225,7 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -212,6 +234,19 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -225,6 +260,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -233,16 +272,9 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -251,6 +283,25 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -258,14 +309,17 @@ typedef union { struct { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + /*@} end of group CMSIS_CORE */ @@ -329,7 +383,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -357,7 +411,7 @@ typedef struct #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ @@ -426,15 +480,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -444,7 +498,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -501,9 +555,9 @@ typedef struct /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable External Interrupt @@ -514,7 +568,7 @@ typedef struct */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -526,7 +580,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -542,7 +596,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); + return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -554,7 +608,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -566,7 +620,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -581,12 +635,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + if((int32_t)(IRQn) < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } } @@ -604,10 +660,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + if((int32_t)(IRQn) < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } } @@ -619,10 +677,10 @@ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -655,15 +713,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -673,10 +731,10 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - #ifdef __cplusplus } #endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/libraries/mbed/targets/cmsis/core_cm0plus.h b/libraries/mbed/targets/cmsis/core_cm0plus.h index 5cea74e9af..123cb400a2 100644 --- a/libraries/mbed/targets/cmsis/core_cm0plus.h +++ b/libraries/mbed/targets/cmsis/core_cm0plus.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -39,13 +39,13 @@ #pragma system_include /* treat file as system include file for MISRA check */ #endif +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + #ifdef __cplusplus extern "C" { #endif -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: @@ -68,8 +68,8 @@ */ /* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ @@ -81,14 +81,18 @@ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) @@ -96,9 +100,16 @@ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + #endif -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all */ #define __FPU_USED 0 @@ -107,26 +118,40 @@ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif #endif #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ +#ifdef __cplusplus +} +#endif + #endif /* __CORE_CM0PLUS_H_GENERIC */ #ifndef __CMSIS_GENERIC @@ -134,6 +159,10 @@ #ifndef __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT +#ifdef __cplusplus + extern "C" { +#endif + /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0PLUS_REV @@ -207,14 +236,7 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -223,6 +245,19 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -236,6 +271,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -244,16 +283,9 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -262,6 +294,25 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -271,12 +322,18 @@ typedef union { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + /*@} end of group CMSIS_CORE */ @@ -344,7 +401,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -372,7 +429,7 @@ typedef struct #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if (__VTOR_PRESENT == 1) /* SCB Interrupt Control State Register Definitions */ @@ -447,15 +504,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -465,7 +522,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -495,7 +552,7 @@ typedef struct #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ @@ -505,11 +562,11 @@ typedef struct #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ @@ -519,7 +576,7 @@ typedef struct #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ @@ -550,7 +607,7 @@ typedef struct #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif @@ -612,9 +669,9 @@ typedef struct /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable External Interrupt @@ -625,7 +682,7 @@ typedef struct */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -637,7 +694,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -653,7 +710,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); + return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -665,7 +722,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -677,7 +734,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -692,12 +749,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + if((int32_t)(IRQn) < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } } @@ -715,10 +774,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + if((int32_t)(IRQn) < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } } @@ -730,10 +791,10 @@ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -766,15 +827,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -784,10 +845,10 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - #ifdef __cplusplus } #endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/libraries/mbed/targets/cmsis/core_cm3.h b/libraries/mbed/targets/cmsis/core_cm3.h index 122c9aa4a8..092ee23da9 100644 --- a/libraries/mbed/targets/cmsis/core_cm3.h +++ b/libraries/mbed/targets/cmsis/core_cm3.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -39,13 +39,13 @@ #pragma system_include /* treat file as system include file for MISRA check */ #endif +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + #ifdef __cplusplus extern "C" { #endif -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: @@ -68,8 +68,8 @@ */ /* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ @@ -81,6 +81,11 @@ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ @@ -90,19 +95,21 @@ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + #endif -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all */ #define __FPU_USED 0 @@ -111,6 +118,11 @@ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -121,21 +133,25 @@ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif #endif #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ +#ifdef __cplusplus +} +#endif + #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC @@ -143,6 +159,10 @@ #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT +#ifdef __cplusplus + extern "C" { +#endif + /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV @@ -212,13 +232,7 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -228,6 +242,22 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -241,6 +271,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -249,13 +283,7 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ @@ -267,6 +295,31 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -276,12 +329,18 @@ typedef union { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + /*@} end of group CMSIS_CORE */ @@ -312,7 +371,7 @@ typedef struct /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ @@ -364,7 +423,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -395,7 +454,7 @@ typedef struct #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if (__CM3_REV < 0x0201) /* core r2p1 */ @@ -429,7 +488,7 @@ typedef struct #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ @@ -458,7 +517,7 @@ typedef struct #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ @@ -501,7 +560,7 @@ typedef struct #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ @@ -511,7 +570,7 @@ typedef struct #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ @@ -537,7 +596,7 @@ typedef struct #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ @@ -563,7 +622,7 @@ typedef struct /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ @@ -574,7 +633,7 @@ typedef struct #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ @@ -606,15 +665,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -624,7 +683,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -675,7 +734,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ @@ -703,19 +762,19 @@ typedef struct #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ @@ -725,7 +784,7 @@ typedef struct #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ @@ -818,31 +877,31 @@ typedef struct #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ @@ -870,7 +929,7 @@ typedef struct #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ @@ -913,11 +972,11 @@ typedef struct /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ @@ -930,7 +989,7 @@ typedef struct #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ @@ -941,7 +1000,7 @@ typedef struct /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ @@ -963,11 +1022,11 @@ typedef struct #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -989,15 +1048,15 @@ typedef struct #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ @@ -1016,15 +1075,15 @@ typedef struct #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1060,7 +1119,7 @@ typedef struct #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ @@ -1070,11 +1129,11 @@ typedef struct #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ @@ -1084,7 +1143,7 @@ typedef struct #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ @@ -1115,7 +1174,7 @@ typedef struct #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif @@ -1172,14 +1231,14 @@ typedef struct #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ @@ -1219,7 +1278,7 @@ typedef struct #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ @@ -1291,13 +1350,13 @@ typedef struct __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } @@ -1310,7 +1369,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } @@ -1322,7 +1381,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1334,7 +1393,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1350,7 +1409,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1362,7 +1421,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1374,7 +1433,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1389,7 +1448,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1404,10 +1463,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + if((int32_t)IRQn < 0) { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } } @@ -1425,10 +1486,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } } @@ -1437,7 +1500,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). @@ -1446,16 +1509,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } @@ -1465,7 +1528,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. @@ -1474,15 +1537,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } @@ -1492,13 +1555,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void NVIC_SystemReset(void) { - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -1531,15 +1594,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -1571,11 +1634,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; } return (ch); } @@ -1618,10 +1681,13 @@ __STATIC_INLINE int32_t ITM_CheckChar (void) { /*@} end of CMSIS_core_DebugFunctions */ -#endif /* __CORE_CM3_H_DEPENDANT */ -#endif /* __CMSIS_GENERIC */ + #ifdef __cplusplus } #endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/libraries/mbed/targets/cmsis/core_cm4.h b/libraries/mbed/targets/cmsis/core_cm4.h index d65016c714..9749c27d24 100644 --- a/libraries/mbed/targets/cmsis/core_cm4.h +++ b/libraries/mbed/targets/cmsis/core_cm4.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -39,13 +39,13 @@ #pragma system_include /* treat file as system include file for MISRA check */ #endif +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + #ifdef __cplusplus extern "C" { #endif -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: @@ -68,8 +68,8 @@ */ /* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ @@ -81,6 +81,11 @@ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ @@ -90,19 +95,21 @@ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + #endif -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP @@ -116,6 +123,18 @@ #define __FPU_USED 0 #endif +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if (__FPU_PRESENT == 1) @@ -140,20 +159,20 @@ #define __FPU_USED 0 #endif -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0 #endif #else #define __FPU_USED 0 #endif -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else @@ -168,7 +187,11 @@ #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif #endif /* __CORE_CM4_H_GENERIC */ @@ -177,6 +200,10 @@ #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT +#ifdef __cplusplus + extern "C" { +#endif + /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV @@ -252,13 +279,9 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -268,6 +291,25 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16 /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -281,6 +323,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -289,13 +335,9 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ @@ -307,6 +349,34 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -322,6 +392,16 @@ typedef union uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + /*@} end of group CMSIS_CORE */ @@ -352,7 +432,7 @@ typedef struct /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ @@ -404,7 +484,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -435,7 +515,7 @@ typedef struct #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ @@ -461,7 +541,7 @@ typedef struct #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ @@ -490,7 +570,7 @@ typedef struct #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ @@ -533,7 +613,7 @@ typedef struct #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ @@ -543,7 +623,7 @@ typedef struct #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ @@ -569,7 +649,7 @@ typedef struct #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ @@ -591,7 +671,7 @@ typedef struct /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ @@ -607,7 +687,7 @@ typedef struct #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ @@ -639,15 +719,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -657,7 +737,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -708,7 +788,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ @@ -736,19 +816,19 @@ typedef struct #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ @@ -758,7 +838,7 @@ typedef struct #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ @@ -851,31 +931,31 @@ typedef struct #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ @@ -903,7 +983,7 @@ typedef struct #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ @@ -946,11 +1026,11 @@ typedef struct /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ @@ -963,7 +1043,7 @@ typedef struct #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ @@ -974,7 +1054,7 @@ typedef struct /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ @@ -996,11 +1076,11 @@ typedef struct #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -1022,15 +1102,15 @@ typedef struct #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ @@ -1049,15 +1129,15 @@ typedef struct #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1093,7 +1173,7 @@ typedef struct #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ @@ -1103,11 +1183,11 @@ typedef struct #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ @@ -1117,7 +1197,7 @@ typedef struct #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ @@ -1148,7 +1228,7 @@ typedef struct #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif @@ -1199,7 +1279,7 @@ typedef struct #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register */ #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ @@ -1241,7 +1321,7 @@ typedef struct #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 */ #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ @@ -1254,7 +1334,7 @@ typedef struct #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ #endif @@ -1311,14 +1391,14 @@ typedef struct #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ @@ -1358,7 +1438,7 @@ typedef struct #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ @@ -1435,13 +1515,13 @@ typedef struct __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } @@ -1454,7 +1534,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } @@ -1466,8 +1546,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1479,7 +1558,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1495,7 +1574,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1507,7 +1586,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1519,7 +1598,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1534,7 +1613,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1549,10 +1628,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + if((int32_t)IRQn < 0) { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } } @@ -1570,10 +1651,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } } @@ -1582,7 +1665,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). @@ -1591,16 +1674,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } @@ -1610,7 +1693,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. @@ -1619,15 +1702,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } @@ -1637,13 +1720,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void NVIC_SystemReset(void) { - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -1676,15 +1759,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -1716,11 +1799,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; } return (ch); } @@ -1763,10 +1846,13 @@ __STATIC_INLINE int32_t ITM_CheckChar (void) { /*@} end of CMSIS_core_DebugFunctions */ -#endif /* __CORE_CM4_H_DEPENDANT */ -#endif /* __CMSIS_GENERIC */ + #ifdef __cplusplus } #endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/libraries/mbed/targets/cmsis/core_cmFunc.h b/libraries/mbed/targets/cmsis/core_cmFunc.h index 0a18fafc30..b6ad0a4c5f 100644 --- a/libraries/mbed/targets/cmsis/core_cmFunc.h +++ b/libraries/mbed/targets/cmsis/core_cmFunc.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -198,7 +198,7 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) } -#if (__CORTEX_M >= 0x03) +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief Enable FIQ @@ -242,6 +242,20 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) } +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xff); +} + + /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. @@ -267,10 +281,10 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) __regFaultMask = (faultMask & (uint32_t)1); } -#endif /* (__CORTEX_M >= 0x03) */ +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ -#if (__CORTEX_M == 0x04) +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) /** \brief Get FPSCR @@ -303,19 +317,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) #endif } -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ @@ -530,7 +532,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } @@ -547,6 +549,19 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v } +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. @@ -576,7 +591,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t #endif /* (__CORTEX_M >= 0x03) */ -#if (__CORTEX_M == 0x04) +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) /** \brief Get FPSCR @@ -616,21 +631,34 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps #endif } -#endif /* (__CORTEX_M == 0x04) */ +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ - /* * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, + * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + #endif /*@} end of CMSIS_Core_RegAccFunctions */ - #endif /* __CORE_CMFUNC_H */ diff --git a/libraries/mbed/targets/cmsis/core_cmInstr.h b/libraries/mbed/targets/cmsis/core_cmInstr.h index d213f0eed7..fca425c51d 100644 --- a/libraries/mbed/targets/cmsis/core_cmInstr.h +++ b/libraries/mbed/targets/cmsis/core_cmInstr.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2014 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -89,24 +89,33 @@ so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __isb(0xF) - +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0) /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __dsb(0xF) - +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0) /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __dmb(0xF) - +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0) /** \brief Reverse byte order (32 bit) @@ -171,8 +180,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in #define __BKPT(value) __breakpoint(value) -#if (__CORTEX_M >= 0x03) - /** \brief Reverse bit order of value This function reverses the bit order of the given value. @@ -180,12 +187,42 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value Value to reverse \return Reversed value */ -#define __RBIT __rbit +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero + return(result); +} +#endif + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief LDR Exclusive (8 bit) - This function performs a exclusive LDR command for 8 bit value. + This function executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) @@ -195,7 +232,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in /** \brief LDR Exclusive (16 bit) - This function performs a exclusive LDR command for 16 bit values. + This function executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) @@ -205,7 +242,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in /** \brief LDR Exclusive (32 bit) - This function performs a exclusive LDR command for 32 bit values. + This function executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) @@ -215,7 +252,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in /** \brief STR Exclusive (8 bit) - This function performs a exclusive STR command for 8 bit values. + This function executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location @@ -227,7 +264,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in /** \brief STR Exclusive (16 bit) - This function performs a exclusive STR command for 16 bit values. + This function executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location @@ -239,7 +276,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in /** \brief STR Exclusive (32 bit) - This function performs a exclusive STR command for 32 bit values. + This function executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location @@ -279,29 +316,83 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in #define __USAT __usat -/** \brief Count leading zeros +/** \brief Rotate Right with Extend (32 bit) - This function counts the number of leading zeros of a data value. + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value + \param [in] value Value to rotate + \return Rotated value */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif +/** \brief LDRT Unprivileged (8 bit) -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ + This function executes a Unprivileged LDRT instruction for 8 bit value. -#include + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ +/** \brief LDRT Unprivileged (16 bit) -#include + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ @@ -322,7 +413,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in No Operation does nothing. This instruction can be used for code alignment purposes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) { __ASM volatile ("nop"); } @@ -333,7 +424,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) { __ASM volatile ("wfi"); } @@ -344,7 +435,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) { __ASM volatile ("wfe"); } @@ -354,7 +445,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) { __ASM volatile ("sev"); } @@ -366,9 +457,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) { - __ASM volatile ("isb"); + __ASM volatile ("isb 0xF":::"memory"); } @@ -377,9 +468,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) { - __ASM volatile ("dsb"); + __ASM volatile ("dsb 0xF":::"memory"); } @@ -388,9 +479,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) { - __ASM volatile ("dmb"); + __ASM volatile ("dmb 0xF":::"memory"); } @@ -401,7 +492,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); @@ -421,7 +512,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; @@ -437,7 +528,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (short)__builtin_bswap16(value); @@ -458,9 +549,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value \param [in] value Number of Bits to rotate \return Rotated value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - return (op1 >> op2) | (op1 << (32 - op2)); + return (op1 >> op2) | (op1 << (32 - op2)); } @@ -475,8 +566,6 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, #define __BKPT(value) __ASM volatile ("bkpt "#value) -#if (__CORTEX_M >= 0x03) - /** \brief Reverse bit order of value This function reverses the bit order of the given value. @@ -484,23 +573,48 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero +#endif + return(result); } +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + /** \brief LDR Exclusive (8 bit) - This function performs a exclusive LDR command for 8 bit value. + This function executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; @@ -512,18 +626,18 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif - return(result); + return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) - This function performs a exclusive LDR command for 16 bit values. + This function executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; @@ -535,18 +649,18 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif - return(result); + return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) - This function performs a exclusive LDR command for 32 bit values. + This function executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; @@ -557,50 +671,50 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui /** \brief STR Exclusive (8 bit) - This function performs a exclusive STR command for 8 bit values. + This function executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (16 bit) - This function performs a exclusive STR command for 16 bit values. + This function executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (32 bit) - This function performs a exclusive STR command for 32 bit values. + This function executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; @@ -614,7 +728,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va This function removes the exclusive lock which is created by LDREX. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } @@ -652,35 +766,149 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) }) -/** \brief Count leading zeros +/** \brief Rotate Right with Extend (32 bit) - This function counts the number of leading zeros of a data value. + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value + \param [in] value Value to rotate + \return Rotated value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } -#endif /* (__CORTEX_M >= 0x03) */ + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ - /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + #endif /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/PortNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/PortNames.h similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/PortNames.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/PortNames.h index 39e761cf76..cc9e85e33b 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/PortNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralNames.h new file mode 100644 index 0000000000..d83d7081f6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralNames.h @@ -0,0 +1,150 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define _SERCOM_SPI_NAME(n, unused) \ + SPI##n, + +#define _SERCOM_PAD_NAME(n, pad) \ + SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)), + +#define _SERCOM_I2C_NAME(n, unused) \ + I2C##n, + + + +typedef enum { + UART_0 = (int)0x42000800UL, // Base address of SERCOM0 + UART_1 = (int)0x42000C00UL, // Base address of SERCOM1 + UART_2 = (int)0x42001000UL, // Base address of SERCOM2 + UART_3 = (int)0x42001400UL, // Base address of SERCOM3 + UART_4 = (int)0x42001800UL, // Base address of SERCOM4 + UART_5 = (int)0x42001C00UL // Base address of SERCOM5 +} UARTName; + +typedef enum { + ADC_0 = 0x0ul, + ADC_1 = 0x1ul, + ADC_2 = 0x2ul, + ADC_3 = 0x3ul, + ADC_4 = 0x4ul, + ADC_5 = 0x5ul, + ADC_6 = 0x6ul, + ADC_7 = 0x7ul, + ADC_10 = 0xAul, + ADC_11 = 0xBul, + ADC_16 = 0x10ul, + ADC_17 = 0x11ul, + ADC_18 = 0x12ul, + ADC_19 = 0x13ul +} ADCName; + +typedef enum { + DAC_0 = 0x42004800UL +} DACName; + +typedef enum { // for each channel + EXTINT_0 = 0, + EXTINT_1, + EXTINT_2, + EXTINT_3, + EXTINT_4, + EXTINT_5, + EXTINT_6, + EXTINT_7, + EXTINT_8, + EXTINT_9, + EXTINT_10, + EXTINT_11, + EXTINT_12, + EXTINT_13, + EXTINT_14, + EXTINT_15 +} EXTINTName; + +typedef enum { + MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~) +} SPIName; + +typedef enum { + MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~) +} I2CName; + +typedef enum { + /* Pad 0 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0) + + /* Pad 1 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1) + + /* Pad 2 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2) + + /* Pad 3 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3) +} SercomPadName; + +typedef enum { + PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */ + PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */ + PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */ +} PWMName; + +struct pwm_pin_channel { + PinName pin; + PWMName pwm; + uint8_t channel_index; +}; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_3 + +// Default peripherals +#define MBED_SPI0 PA18, PA16, PA19, PA17 + +#define MBED_UART0 PA04, PA05 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C0 PA08, PA09 + +#define MBED_ANALOGOUT0 PA02 + +#define MBED_ANALOGIN0 PA03 +#define MBED_ANALOGIN1 PA08 +#define MBED_ANALOGIN2 PB09 +#define MBED_ANALOGIN3 PA04 +#define MBED_ANALOGIN4 PA05 +#define MBED_ANALOGIN5 PA06 +#define MBED_ANALOGIN7 PA07 + +#define MBED_PWMOUT0 PA18 +#define MBED_PWMOUT1 PA19 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.c new file mode 100644 index 0000000000..117e7a5369 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.c @@ -0,0 +1,244 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PA02, ADC_0, 1}, + {PA03, ADC_1, 1}, + {PB08, ADC_2, 1}, + {PB09, ADC_3, 1}, + {PA04, ADC_4, 1}, + {PA05, ADC_5, 1}, + {PA06, ADC_6, 1}, + {PA07, ADC_7, 1}, + {PB02, ADC_10, 1}, + {PB03, ADC_11, 1}, + {PA08, ADC_16, 1}, + {PA09, ADC_17, 1}, + {PA10, ADC_18, 1}, + {PA11, ADC_19, 1}, + + /* Not connected */ + {NC , NC , NC} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {PA02, DAC_0, 1}, + + /* Not connected */ + {NC , NC , NC} +}; + +/************SERCOM Pins***********/ +const PinMap PinMap_SERCOM_PAD[] = { + {PA00, SERCOM1_PAD0, 3}, + {PA01, SERCOM1_PAD1, 3}, + {PA04, SERCOM0_PAD0, 3}, + {PA05, SERCOM0_PAD1, 3}, + {PA06, SERCOM0_PAD2, 3}, + {PA07, SERCOM0_PAD3, 3}, + {PA08, SERCOM0_PAD0, 2}, + {PA09, SERCOM0_PAD1, 2}, + {PA10, SERCOM0_PAD2, 2}, + {PA11, SERCOM0_PAD3, 2}, + {PA12, SERCOM2_PAD0, 2}, + {PA13, SERCOM2_PAD1, 2}, + {PA14, SERCOM2_PAD2, 2}, + {PA15, SERCOM2_PAD3, 2}, + {PA16, SERCOM1_PAD0, 2}, + {PA17, SERCOM1_PAD1, 2}, + {PA18, SERCOM1_PAD2, 2}, + {PA19, SERCOM1_PAD3, 2}, + {PA20, SERCOM3_PAD2, 3}, + {PA21, SERCOM3_PAD3, 3}, + {PA22, SERCOM3_PAD0, 2}, + {PA23, SERCOM3_PAD1, 2}, + {PA24, SERCOM3_PAD2, 2}, + {PA25, SERCOM3_PAD3, 2}, + {PA30, SERCOM1_PAD2, 3}, + {PA31, SERCOM1_PAD3, 3}, + {PB02, SERCOM5_PAD0, 3}, + {PB03, SERCOM5_PAD1, 3}, + {PB08, SERCOM4_PAD0, 3}, + {PB09, SERCOM4_PAD1, 3}, + {PB10, SERCOM4_PAD2, 3}, + {PB11, SERCOM4_PAD3, 3}, + {PB22, SERCOM5_PAD2, 3}, + {PB23, SERCOM5_PAD3, 3}, + + /* Not connected */ + {NC , NC , NC} +}; + +/*******SERCOM Pins extended*******/ +const PinMap PinMap_SERCOM_PADEx[] = { + {PA08, SERCOM2_PAD0, 3}, + {PA09, SERCOM2_PAD1, 3}, + {PA10, SERCOM2_PAD2, 3}, + {PA11, SERCOM2_PAD3, 3}, + {PA12, SERCOM4_PAD0, 3}, + {PA13, SERCOM4_PAD1, 3}, + {PA14, SERCOM4_PAD2, 3}, + {PA15, SERCOM4_PAD3, 3}, + {PA16, SERCOM3_PAD0, 3}, + {PA17, SERCOM3_PAD1, 3}, + {PA18, SERCOM3_PAD2, 3}, + {PA19, SERCOM3_PAD3, 3}, + {PA20, SERCOM5_PAD2, 2}, + {PA21, SERCOM5_PAD3, 2}, + {PA22, SERCOM5_PAD0, 3}, + {PA23, SERCOM5_PAD1, 3}, + {PA24, SERCOM5_PAD2, 3}, + {PA25, SERCOM5_PAD3, 3}, + + /* Not connected */ + {NC , NC , NC} +}; + + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PA00, PWM_2, 4}, + {PA01, PWM_2, 4}, + {PA04, PWM_0, 4}, + {PA05, PWM_0, 4}, + {PA06, PWM_1, 4}, + {PA07, PWM_1, 4}, + {PA08, PWM_1, 5}, + {PA09, PWM_1, 5}, + {PA10, PWM_1, 4}, + {PA11, PWM_1, 4}, + {PA12, PWM_2, 4}, + {PA13, PWM_2, 4}, + {PA14, PWM_0, 5}, + {PA15, PWM_0, 5}, + {PA16, PWM_2, 4}, + {PA17, PWM_2, 4}, + {PA18, PWM_0, 5}, + {PA19, PWM_0, 5}, + {PA20, PWM_0, 5}, + {PA21, PWM_0, 5}, + {PA22, PWM_0, 5}, + {PA23, PWM_0, 5}, + {PA24, PWM_1, 5}, + {PA25, PWM_1, 5}, + {PA30, PWM_1, 4}, + {PA31, PWM_1, 4}, + {PB10, PWM_0, 5}, + {PB11, PWM_0, 5}, + + /* Not connected */ + {NC , NC , NC} +}; + +/**********EXTINT*************/ +const PinMap PinMap_EXTINT[] = { + {PA16, EXTINT_0, 0}, + {PA00, EXTINT_0, 0}, + + {PA17, EXTINT_1, 0}, + {PA01, EXTINT_1, 0}, + + {PA18, EXTINT_2, 0}, + {PA02, EXTINT_2, 0}, + {PB02, EXTINT_2, 0}, + + {PA03, EXTINT_3, 0}, + {PA19, EXTINT_3, 0}, + {PB03, EXTINT_3, 0}, + + {PA04, EXTINT_4, 0}, + {PA20, EXTINT_4, 0}, + + {PA05, EXTINT_5, 0}, + {PA21, EXTINT_5, 0}, + + {PA06, EXTINT_6, 0}, + {PA22, EXTINT_6, 0}, + {PB22, EXTINT_6, 0}, + + {PA07, EXTINT_7, 0}, + {PA23, EXTINT_7, 0}, + {PB23, EXTINT_7, 0}, + + {PA28, EXTINT_8, 0}, + {PB08, EXTINT_8, 0}, + + {PA09, EXTINT_9, 0}, + {PB09, EXTINT_9, 0}, + + {PA10, EXTINT_10, 0}, + {PA30, EXTINT_10, 0}, + {PB10, EXTINT_10, 0}, + + {PA11, EXTINT_11, 0}, + {PA31, EXTINT_11, 0}, + {PB11, EXTINT_11, 0}, + + {PA12, EXTINT_12, 0}, + {PA24, EXTINT_12, 0}, + + {PA13, EXTINT_13, 0}, + {PA25, EXTINT_13, 0}, + + {PA14, EXTINT_14, 0}, + + {PA15, EXTINT_15, 0}, + {PA27, EXTINT_15, 0}, + + /* Not connected */ + {NC , NC , NC} +}; + +const struct pwm_pin_channel pwn_pins[] = { + {PA00, PWM_2, 0}, + {PA01, PWM_2, 1}, + {PA04, PWM_0, 0}, + {PA05, PWM_0, 1}, + {PA06, PWM_1, 0}, + {PA07, PWM_1, 1}, + {PA08, PWM_1, 2}, + {PA09, PWM_1, 3}, + {PA10, PWM_1, 0}, + {PA11, PWM_1, 1}, + {PA12, PWM_2, 0}, + {PA13, PWM_2, 1}, + {PA14, PWM_0, 4}, + {PA15, PWM_0, 5}, + {PA16, PWM_2, 0}, + {PA17, PWM_2, 1}, + {PA18, PWM_0, 2}, + {PA19, PWM_0, 3}, + {PA20, PWM_0, 6}, + {PA21, PWM_0, 7}, + {PA22, PWM_0, 4}, + {PA23, PWM_0, 5}, + {PA24, PWM_1, 2}, + {PA25, PWM_1, 3}, + {PA30, PWM_1, 0}, + {PA31, PWM_1, 1}, + {PB10, PWM_0, 4}, + {PB11, PWM_0, 5}, + + /* Not connected */ + {NC , NC , NC} +}; + + + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.h new file mode 100644 index 0000000000..1982babc49 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/*********SERCOM*************/ +extern const PinMap PinMap_SERCOM_PAD[]; +extern const PinMap PinMap_SERCOM_PADEx[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/**********EXTINT*************/ +extern const PinMap PinMap_EXTINT[]; + + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PinNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PinNames.h new file mode 100644 index 0000000000..afcfd2cd76 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PinNames.h @@ -0,0 +1,95 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INPUT_OUTPUT //pin state can be set and read back +} PinDirection; + +typedef enum { + PA00 = 0, + PA01 = 1, + PA02 = 2, + PA03 = 3, + PA04 = 4, + PA05 = 5, + PA06 = 6, + PA07 = 7, + PA08 = 8, + PA09 = 9, + PA10 = 10, + PA11 = 11, + PA12 = 12, + PA13 = 13, + PA14 = 14, + PA15 = 15, + PA16 = 16, + PA17 = 17, + PA18 = 18, + PA19 = 19, + PA20 = 20, + PA21 = 21, + PA22 = 22, + PA23 = 23, + PA24 = 24, + PA25 = 25, + PA27 = 27, + PA28 = 28, + PA30 = 30, + PA31 = 31, + + PB02 = 34, + PB03 = 35, + PB08 = 40, + PB09 = 41, + PB10 = 42, + PB11 = 43, + PB22 = 54, + PB23 = 55, + + USBTX = PB10, + USBRX = PB11, + + LED1 = PA23, + LED2 = PA23, + LED3 = PA23, + LED4 = PA23, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/mbed_overrides.c similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/mbed_overrides.c index 73e8d6009b..f6b9e40105 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/mbed_overrides.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/samw25_xplained_pro.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/samw25_xplained_pro.h new file mode 100644 index 0000000000..bb677c618a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/samw25_xplained_pro.h @@ -0,0 +1,530 @@ +/** + * \file + * + * \brief SAM W25 Xplained Pro board definition + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef SAMW25_XPLAINED_PRO_H_INCLUDED +#define SAMW25_XPLAINED_PRO_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup group_common_boards + * \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board + * + * @{ + */ + +void system_board_init(void); + +/** + * \defgroup samd21_xplained_pro_features_group Features + * + * Symbols that describe features and capabilities of the board. + * + * @{ + */ + +/** Name string macro */ +#define BOARD_NAME "SAMW25_XPLAINED_PRO" + +/** \name Resonator definitions + * @{ */ +#define BOARD_FREQ_SLCK_XTAL (32768U) +#define BOARD_FREQ_SLCK_BYPASS (32768U) +#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */ +#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */ +#define BOARD_MCK CHIP_FREQ_CPU_MAX +#define BOARD_OSC_STARTUP_US 15625 +/** @} */ + +/** \name LED0 definitions + * @{ */ +#define LED0_PIN PIN_PA23 +#define LED0_ACTIVE false +#define LED0_INACTIVE !LED0_ACTIVE +/** @} */ + +/** \name SW0 definitions + * @{ */ +#define SW0_PIN PIN_PB23 +#define SW0_ACTIVE false +#define SW0_INACTIVE !SW0_ACTIVE +#define SW0_EIC_PIN PIN_PB23A_EIC_EXTINT7 +#define SW0_EIC_MUX MUX_PA23A_EIC_EXTINT7 +#define SW0_EIC_PINMUX PINMUX_PA23A_EIC_EXTINT7 +#define SW0_EIC_LINE 7 +/** @} */ + +/** + * \name LED #0 definitions + * + * Wrapper macros for LED0, to ensure common naming across all Xplained Pro + * boards. + * + * @{ */ +#define LED_0_NAME "LED0 (yellow)" +#define LED_0_PIN LED0_PIN +#define LED_0_ACTIVE LED0_ACTIVE +#define LED_0_INACTIVE LED0_INACTIVE +#define LED0_GPIO LED0_PIN +#define LED0 LED0_PIN + +#define LED_0_PWM_MODULE TCC0 +#define LED_0_PWM_CHANNEL 0 +#define LED_0_PWM_OUTPUT 0 +#define LED_0_PWM_PIN PIN_PA23F_TCC0_WO5 +#define LED_0_PWM_MUX MUX_PA23F_TCC0_WO5 +#define LED_0_PWM_PINMUX PINMUX_PA23F_TCC0_WO5 +/** @} */ + +/** Number of on-board LEDs */ +#define LED_COUNT 1 + + +/** + * \name Button #0 definitions + * + * Wrapper macros for SW0, to ensure common naming across all Xplained Pro + * boards. + * + * @{ */ +#define BUTTON_0_NAME "SW0" +#define BUTTON_0_PIN SW0_PIN +#define BUTTON_0_ACTIVE SW0_ACTIVE +#define BUTTON_0_INACTIVE SW0_INACTIVE +#define BUTTON_0_EIC_PIN SW0_EIC_PIN +#define BUTTON_0_EIC_MUX SW0_EIC_MUX +#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX +#define BUTTON_0_EIC_LINE SW0_EIC_LINE +/** @} */ + +/** Number of on-board buttons */ +#define BUTTON_COUNT 1 + +/** \name Extension header #1 pin definitions + * @{ + */ +#define EXT1_PIN_3 PIN_PA02 +#define EXT1_PIN_4 PIN_PA03 +#define EXT1_PIN_5 PIN_PB02 +#define EXT1_PIN_6 PIN_PB03 +#define EXT1_PIN_7 PIN_PA10 +#define EXT1_PIN_8 PIN_PA11 +#define EXT1_PIN_9 PIN_PA20 +#define EXT1_PIN_10 PIN_PA21 +#define EXT1_PIN_11 PIN_PA08 +#define EXT1_PIN_12 PIN_PA09 +#define EXT1_PIN_13 PIN_PB11 +#define EXT1_PIN_14 PIN_PB10 +#define EXT1_PIN_15 PIN_PA17 +#define EXT1_PIN_16 PIN_PA18 +#define EXT1_PIN_17 PIN_PA16 +#define EXT1_PIN_18 PIN_PA19 +/** @} */ + +/** \name Extension header #1 pin definitions by function + * @{ + */ +#define EXT1_PIN_ADC_0 EXT1_PIN_3 +#define EXT1_PIN_ADC_1 EXT1_PIN_4 +#define EXT1_PIN_GPIO_0 EXT1_PIN_5 +#define EXT1_PIN_GPIO_1 EXT1_PIN_6 +#define EXT1_PIN_PWM_0 EXT1_PIN_7 +#define EXT1_PIN_PWM_1 EXT1_PIN_8 +#define EXT1_PIN_IRQ EXT1_PIN_9 +#define EXT1_PIN_I2C_SDA EXT1_PIN_11 +#define EXT1_PIN_I2C_SCL EXT1_PIN_12 +#define EXT1_PIN_UART_RX EXT1_PIN_13 +#define EXT1_PIN_UART_TX EXT1_PIN_14 +#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10 +#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15 +#define EXT1_PIN_SPI_MOSI EXT1_PIN_16 +#define EXT1_PIN_SPI_MISO EXT1_PIN_17 +#define EXT1_PIN_SPI_SCK EXT1_PIN_18 +/** @} */ + +/** \name Extension header #1 ADC definitions + * @{ + */ +#define EXT1_ADC_MODULE ADC +#define EXT1_ADC_0_CHANNEL 0 +#define EXT1_ADC_0_PIN PIN_PA02B_ADC_AIN0 +#define EXT1_ADC_0_MUX MUX_PA02B_ADC_AIN0 +#define EXT1_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0 +#define EXT1_ADC_1_CHANNEL 1 +#define EXT1_ADC_1_PIN PIN_PA03B_ADC_AIN1 +#define EXT1_ADC_1_MUX MUX_PA03B_ADC_AIN1 +#define EXT1_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1 +/** @} */ + +/** \name Extension header #1 PWM definitions + * @{ + */ +#define EXT1_PWM_MODULE TCC0 +#define EXT1_PWM_0_CHANNEL 2 +#define EXT1_PWM_0_PIN PIN_PA10F_TCC0_WO2 +#define EXT1_PWM_0_MUX MUX_PA10F_TCC0_WO2 +#define EXT1_PWM_0_PINMUX PINMUX_PA10F_TCC0_WO2 +#define EXT1_PWM_1_CHANNEL 3 +#define EXT1_PWM_1_PIN PIN_PA11F_TCC0_WO3 +#define EXT1_PWM_1_MUX MUX_PA11F_TCC0_WO3 +#define EXT1_PWM_1_PINMUX PINMUX_PA11F_TCC0_WO3 +/** @} */ + +/** \name Extension header #1 IRQ/External interrupt definitions + * @{ + */ +#define EXT1_IRQ_MODULE EIC +#define EXT1_IRQ_INPUT 4 +#define EXT1_IRQ_PIN PIN_PA20A_EIC_EXTINT4 +#define EXT1_IRQ_MUX MUX_PA20A_EIC_EXTINT4 +#define EXT1_IRQ_PINMUX PINMUX_PA20A_EIC_EXTINT4 +/** @} */ + +/** \name Extension header #1 I2C definitions + * @{ + */ +#define EXT1_I2C_MODULE SERCOM0 +#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0 +#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1 +/** @} */ + +/** \name Extension header #1 UART definitions + * @{ + */ +#define EXT1_UART_MODULE SERCOM4 +#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3 +#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED +#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED +#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2 +#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3 +/** @} */ + +/** \name Extension header #1 SPI definitions + * @{ + */ +#define EXT1_SPI_MODULE SERCOM1 +#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E +#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 +#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1 +#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 +#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 + +/** \name Extension header #3 pin definitions + * @{ + */ +#define EXT3_PIN_3 PIN_PA04 +#define EXT3_PIN_4 PIN_PA05 +#define EXT3_PIN_5 PIN_PB22 +#define EXT3_PIN_6 PIN_PB23 +#define EXT3_PIN_7 PIN_PA22 +#define EXT3_PIN_8 PIN_PA23 +#define EXT3_PIN_9 PIN_PA06 +#define EXT3_PIN_10 0 +#define EXT3_PIN_11 PIN_PA08 +#define EXT3_PIN_12 PIN_PA09 +#define EXT3_PIN_13 PIN_PA01 +#define EXT3_PIN_14 PIN_PA00 +#define EXT3_PIN_15 PIN_PA07 +#define EXT3_PIN_16 PIN_PA18 +#define EXT3_PIN_17 PIN_PA16 +#define EXT3_PIN_18 PIN_PA19 +/** @} */ + +/** \name Extension header #3 pin definitions by function + * @{ + */ +#define EXT3_PIN_ADC_0 EXT3_PIN_3 +#define EXT3_PIN_ADC_1 EXT3_PIN_4 +#define EXT3_PIN_GPIO_0 EXT3_PIN_5 +#define EXT3_PIN_GPIO_1 EXT3_PIN_6 +#define EXT3_PIN_PWM_0 EXT3_PIN_7 +#define EXT3_PIN_PWM_1 EXT3_PIN_8 +#define EXT3_PIN_IRQ EXT3_PIN_9 +#define EXT3_PIN_I2C_SDA EXT3_PIN_11 +#define EXT3_PIN_I2C_SCL EXT3_PIN_12 +#define EXT3_PIN_UART_RX EXT3_PIN_13 +#define EXT3_PIN_UART_TX EXT3_PIN_14 +#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15 +#define EXT3_PIN_SPI_MOSI EXT3_PIN_16 +#define EXT3_PIN_SPI_MISO EXT3_PIN_17 +#define EXT3_PIN_SPI_SCK EXT3_PIN_18 +/** @} */ + +/** \name Extension header #3 ADC definitions + * @{ + */ +#define EXT3_ADC_MODULE ADC +#define EXT3_ADC_0_CHANNEL 4 +#define EXT3_ADC_0_PIN PIN_PA04B_ADC_AIN4 +#define EXT3_ADC_0_MUX MUX_PA04B_ADC_AIN4 +#define EXT3_ADC_0_PINMUX PINMUX_PA04B_ADC_AIN4 +#define EXT3_ADC_1_CHANNEL 5 +#define EXT3_ADC_1_PIN PIN_PA05B_ADC_AIN5 +#define EXT3_ADC_1_MUX MUX_PA05B_ADC_AIN5 +#define EXT3_ADC_1_PINMUX PINMUX_PA05B_ADC_AIN5 +/** @} */ + +/** \name Extension header #3 PWM definitions + * @{ + */ +#define EXT3_PWM_MODULE TC4 +#define EXT3_PWM_0_CHANNEL 0 +#define EXT3_PWM_0_PIN PIN_PA22E_TC4_WO0 +#define EXT3_PWM_0_MUX MUX_PA22E_TC4_WO0 +#define EXT3_PWM_0_PINMUX PINMUX_PA22E_TC4_WO0 +#define EXT3_PWM_1_CHANNEL 1 +#define EXT3_PWM_1_PIN PIN_PA23E_TC4_WO1 +#define EXT3_PWM_1_MUX MUX_PA23E_TC4_WO1 +#define EXT3_PWM_1_PINMUX PINMUX_PA23E_TC4_WO1 +/** @} */ + +/** \name Extension header #3 IRQ/External interrupt definitions + * @{ + */ +#define EXT3_IRQ_MODULE EIC +#define EXT3_IRQ_INPUT 6 +#define EXT3_IRQ_PIN PIN_PA06A_EIC_EXTINT6 +#define EXT3_IRQ_MUX MUX_PA06A_EIC_EXTINT6 +#define EXT3_IRQ_PINMUX PINMUX_PA06A_EIC_EXTINT6 +/** @} */ + +/** \name Extension header #3 I2C definitions + * @{ + */ +#define EXT3_I2C_MODULE SERCOM0 +#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0 +#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1 +/** @} */ + +/** \name Extension header #3 UART definitions + * @{ + */ +#define EXT3_UART_MODULE SERCOM1 +#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 +#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_PA00D_SERCOM1_PAD0 +#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_PA01D_SERCOM1_PAD1 +#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED +#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED +/** @} */ + +/** \name Extension header #3 SPI definitions + * @{ + */ +#define EXT3_SPI_MODULE SERCOM1 +#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E +#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 +#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED /* PA07 */ +#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 +#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 +/** @} */ + +/** \name Extension header #3 Dataflash + * @{ + */ +#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE +#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING +#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0 +#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1 +#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2 +#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3 +/** @} */ + +/** \name USB definitions + * @{ + */ +#define USB_ID +#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP +#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP +#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP +#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM +#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM +#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM +#define USB_VBUS_PIN PIN_PA05 +#define USB_VBUS_EIC_LINE 5 +#define USB_VBUS_EIC_MUX MUX_PA05A_EIC_EXTINT5 +#define USB_VBUS_EIC_PINMUX PINMUX_PA05A_EIC_EXTINT5 +#define USB_ID_PIN PIN_PA04 +#define USB_ID_EIC_LINE 4 +#define USB_ID_EIC_MUX MUX_PA04A_EIC_EXTINT4 +#define USB_ID_EIC_PINMUX PINMUX_PA04A_EIC_EXTINT4 +/** @} */ + +/** \name Embedded debugger GPIO interface definitions + * @{ + */ +#define EDBG_GPIO0_PIN PIN_PB22 +#define EDBG_GPIO1_PIN PIN_PB23 +#define EDBG_GPIO2_PIN PIN_PA22 +#define EDBG_GPIO3_PIN PIN_PA24 +/** @} */ + +/** \name Embedded debugger USART interface definitions + * @{ + */ +#define EDBG_UART_MODULE -1 /* Not available on this board */ +#define EDBG_UART_RX_PIN -1 /* Not available on this board */ +#define EDBG_UART_RX_MUX -1 /* Not available on this board */ +#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */ +#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */ +#define EDBG_UART_TX_PIN -1 /* Not available on this board */ +#define EDBG_UART_TX_MUX -1 /* Not available on this board */ +#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */ +#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */ +/** @} */ + +/** \name Embedded debugger I2C interface definitions + * @{ + */ +#define EDBG_I2C_MODULE SERCOM0 +#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0 +#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1 +/** @} */ + +/** \name Embedded debugger SPI interface definitions + * @{ + */ +#define EDBG_SPI_MODULE SERCOM1 +#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E +#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 +#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED /* PA_06 */ +#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 +#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 +/** @} */ + +/** \name Embedded debugger CDC Gateway USART interface definitions + * @{ + */ +#define EDBG_CDC_MODULE SERCOM4 +#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3 +#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_UNUSED +#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_UNUSED +#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2 +#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3 +/** @} */ + +/** @} */ + +/** \name 802.15.4 TRX Interface definitions + * @{ + */ + +#define AT86RFX_SPI EXT1_SPI_MODULE +#define AT86RFX_RST_PIN EXT1_PIN_7 +#define AT86RFX_MISC_PIN EXT1_PIN_12 +#define AT86RFX_IRQ_PIN EXT1_PIN_9 +#define AT86RFX_SLP_PIN EXT1_PIN_10 +#define AT86RFX_SPI_CS EXT1_PIN_15 +#define AT86RFX_SPI_MOSI EXT1_PIN_16 +#define AT86RFX_SPI_MISO EXT1_PIN_17 +#define AT86RFX_SPI_SCK EXT1_PIN_18 +#define AT86RFX_CSD EXT1_PIN_5 +#define AT86RFX_CPS EXT1_PIN_8 + +#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING +#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0 +#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED +#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2 +#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3 + +#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT +#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX + + +/** Enables the transceiver main interrupt. */ +#define ENABLE_TRX_IRQ() + +/** Disables the transceiver main interrupt. */ +#define DISABLE_TRX_IRQ() + +/** Clears the transceiver main interrupt. */ +#define CLEAR_TRX_IRQ() + +/* + * This macro saves the trx interrupt status and disables the trx interrupt. + */ +#define ENTER_TRX_REGION() + +/* + * This macro restores the transceiver interrupt status + */ +#define LEAVE_TRX_REGION() + +/** @} */ + +/** + * \brief Turns off the specified LEDs. + * + * \param led_gpio LED to turn off (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true) + +/** + * \brief Turns on the specified LEDs. + * + * \param led_gpio LED to turn on (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false) + +/** + * \brief Toggles the specified LEDs. + * + * \param led_gpio LED to toggle (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio) + +#ifdef __cplusplus +} +#endif + +#endif /* SAMW25_XPLAINED_PRO_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/analogout_api.c similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/analogout_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/analogout_api.c index a63233dbeb..4fc477638a 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/analogout_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device.h new file mode 100644 index 0000000000..916e982bdc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device.h @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 +#define DEVICE_SERIAL_ASYNCH 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 +#define DEVICE_I2C_ASYNCH 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 +#define DEVICE_SPI_ASYNCH 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 0 +#define DEVICE_MAC_OFFSET 0 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralNames.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralNames.h index 8f950cf796..50c46e0b61 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.c similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.c index 3b65c61cec..5ab715d6f3 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.h new file mode 100644 index 0000000000..1982babc49 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/*********SERCOM*************/ +extern const PinMap PinMap_SERCOM_PAD[]; +extern const PinMap PinMap_SERCOM_PADEx[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/**********EXTINT*************/ +extern const PinMap PinMap_EXTINT[]; + + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PinNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PinNames.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PinNames.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PinNames.h index 07466e407d..9a81eb4239 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PinNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c new file mode 100644 index 0000000000..f6b9e40105 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "compiler.h" +#include "system.h" + +uint8_t g_sys_init = 0; + +//called before main - implement here if board needs it ortherwise, let +// the application override this if necessary +//TODO: To be implemented by adding system init and board init +void mbed_sdk_init() +{ + if(g_sys_init == 0) { + g_sys_init = 1; + system_init(); + } +} +/***************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/analogout_api.c new file mode 100644 index 0000000000..4fc477638a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/analogout_api.c @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogout_api.h" + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "dac.h" + +struct dac_module dac_instance; +extern uint8_t g_sys_init; + +#define MAX_VAL_10BIT 0x03FF + +void analogout_init(dac_t *obj, PinName pin) +{ + MBED_ASSERT(obj); + if (g_sys_init == 0) { + system_init(); + g_sys_init = 1; + } + + struct dac_config config_dac; + struct dac_chan_config config_dac_chan; + uint32_t pos_input; + pos_input = pinmap_find_peripheral(pin, PinMap_DAC); + MBED_ASSERT(pos_input != NC); + + obj->dac = DAC_0; + + dac_get_config_defaults(&config_dac); + dac_init(&dac_instance, (Dac *)DAC_0, &config_dac); + + dac_chan_get_config_defaults(&config_dac_chan); + dac_chan_set_config(&dac_instance, DAC_CHANNEL_0, &config_dac_chan); + dac_chan_enable(&dac_instance, DAC_CHANNEL_0); + + dac_enable(&dac_instance); +} + +void analogout_free(dac_t *obj) +{ + MBED_ASSERT(obj); + struct system_pinmux_config pin_conf; + + dac_disable(&dac_instance); + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; + pin_conf.powersave = false; + pin_conf.mux_position = SYSTEM_PINMUX_GPIO; + system_pinmux_pin_set_config(PA02, &pin_conf); /*PA02 is the only DAC pin available*/ +} + +void analogout_write(dac_t *obj, float value) +{ + MBED_ASSERT(obj); + uint16_t count_val = 0; + if (value < 0.0f) { + count_val = 0; + } else if (value > 1.0f) { + count_val = MAX_VAL_10BIT; + } else { + count_val = (uint16_t)(value * (float)MAX_VAL_10BIT); + } + dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val); + +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + MBED_ASSERT(obj); + uint16_t count_val; + count_val = (uint16_t)((value * (float)MAX_VAL_10BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/ + dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val); + +} + +static uint32_t data_reg_read(dac_t *obj) +{ + Dac *const dac_module = (Dac *)obj->dac; + return (uint32_t)dac_module->DATA.reg; +} + +float analogout_read(dac_t *obj) +{ + MBED_ASSERT(obj); + uint32_t data_val = data_reg_read(obj); + return data_val/(float)MAX_VAL_10BIT; +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + MBED_ASSERT(obj); + uint32_t data_val = data_reg_read(obj); + return (uint16_t)((data_val / (float)MAX_VAL_10BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/ +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device.h new file mode 100644 index 0000000000..916e982bdc --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device.h @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 +#define DEVICE_SERIAL_ASYNCH 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 +#define DEVICE_I2C_ASYNCH 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 +#define DEVICE_SPI_ASYNCH 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 0 +#define DEVICE_MAC_OFFSET 0 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralNames.h new file mode 100644 index 0000000000..66ac2f0add --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralNames.h @@ -0,0 +1,161 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define _SERCOM_SPI_NAME(n, unused) \ + SPI##n, + +#define _SERCOM_PAD_NAME(n, pad) \ + SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)), + +#define _SERCOM_I2C_NAME(n, unused) \ + I2C##n, + + + +typedef enum { + UART_0 = (int)0x42000000UL, // Base address of SERCOM0 + UART_1 = (int)0x42000400UL, // Base address of SERCOM1 + UART_2 = (int)0x42000800UL, // Base address of SERCOM2 + UART_3 = (int)0x42000C00UL, // Base address of SERCOM3 + UART_4 = (int)0x42001000UL, // Base address of SERCOM4 + UART_5 = (int)0x43000400UL // Base address of SERCOM5 +} UARTName; + +typedef enum { + ADC_0 = 0x0ul, + ADC_1 = 0x1ul, + ADC_2 = 0x2ul, + ADC_3 = 0x3ul, + ADC_4 = 0x4ul, + ADC_5 = 0x5ul, + ADC_6 = 0x6ul, + ADC_7 = 0x7ul, + ADC_8 = 0x8ul, + ADC_9 = 0x9ul, + ADC_10 = 0xAul, + ADC_11 = 0xBul, + ADC_12 = 0xCul, + ADC_13 = 0xDul, + ADC_14 = 0xEul, + ADC_15 = 0xFul, + ADC_16 = 0x10ul, + ADC_17 = 0x11ul, + ADC_18 = 0x12ul, + ADC_19 = 0x13ul +} ADCName; + +typedef enum { + DAC_0 = 0x42003000UL +} DACName; + +typedef enum { // for each channel + EXTINT_0 = 0, + EXTINT_1, + EXTINT_2, + EXTINT_3, + EXTINT_4, + EXTINT_5, + EXTINT_6, + EXTINT_7, + EXTINT_8, + EXTINT_9, + EXTINT_10, + EXTINT_11, + EXTINT_12, + EXTINT_13, + EXTINT_14, + EXTINT_15 +} EXTINTName; + +typedef enum { + MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~) +} SPIName; + +typedef enum { + MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~) +} I2CName; + +typedef enum { + /* Pad 0 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0) + + /* Pad 1 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1) + + /* Pad 2 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2) + + /* Pad 3 definitions */ + MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3) +} SercomPadName; + +typedef enum { + PWM_0 = (0x42001400UL), /**< \brief (TCC0) APB Base Address */ + PWM_1 = (0x42001800UL), /**< \brief (TCC1) APB Base Address */ + PWM_2 = (0x42001C00UL), /**< \brief (TCC2) APB Base Address */ +} PWMName; + +struct pwm_pin_channel { + PinName pin; + PWMName pwm; + uint8_t channel_index; +}; + +struct dac_pin_channel { + PinName pin; + DACName dac; + uint8_t channel_index; +}; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_3 + +// Default peripherals +#define MBED_SPI0 PA06, PA04, PA07, PA05 + +#define MBED_UART0 PB08, PB09 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C0 PA08, PA09 + +#define MBED_ANALOGIN0 PB05 +#define MBED_ANALOGIN1 PA03 +#define MBED_ANALOGIN2 PA06 +#define MBED_ANALOGIN3 PA07 +#define MBED_ANALOGIN4 PB02 +#define MBED_ANALOGIN5 PB03 +#define MBED_ANALOGIN7 PA08 +#define MBED_ANALOGIN8 PA09 + +#define MBED_PWMOUT0 PB12 +#define MBED_PWMOUT1 PB13 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.c new file mode 100644 index 0000000000..ebb38b66ae --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.c @@ -0,0 +1,313 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PA02, ADC_0, 1}, + {PA03, ADC_1, 1}, + {PB08, ADC_2, 1}, + {PB09, ADC_3, 1}, + {PA04, ADC_4, 1}, + {PA05, ADC_5, 1}, + {PA06, ADC_6, 1}, + {PA07, ADC_7, 1}, + {PB00, ADC_8, 1}, + {PB01, ADC_9, 1}, + {PB02, ADC_10, 1}, + {PB03, ADC_11, 1}, + {PB04, ADC_12, 1}, + {PB05, ADC_13, 1}, + {PB06, ADC_14, 1}, + {PB07, ADC_15, 1}, + {PA08, ADC_16, 1}, + {PA09, ADC_17, 1}, + {PA10, ADC_18, 1}, + {PA11, ADC_19, 1}, + + /* Not connected */ + {NC , NC , NC} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {PA02, DAC_0, 1}, + {PA05, DAC_0, 1}, + + /* Not connected */ + {NC , NC , NC} +}; + +/************SERCOM Pins***********/ +const PinMap PinMap_SERCOM_PAD[] = { + {PA04, SERCOM0_PAD0, 3}, + {PA08, SERCOM0_PAD0, 2}, + {PA05, SERCOM0_PAD1, 3}, + {PA09, SERCOM0_PAD1, 2}, + {PA06, SERCOM0_PAD2, 3}, + {PA10, SERCOM0_PAD2, 2}, + {PA07, SERCOM0_PAD3, 3}, + {PA11, SERCOM0_PAD3, 2}, + {PA16, SERCOM1_PAD0, 2}, + {PA00, SERCOM1_PAD0, 3}, + {PA17, SERCOM1_PAD1, 2}, + {PA01, SERCOM1_PAD1, 3}, + {PA30, SERCOM1_PAD2, 3}, + {PA18, SERCOM1_PAD2, 2}, + {PA31, SERCOM1_PAD3, 3}, + {PA19, SERCOM1_PAD3, 2}, + {PA12, SERCOM2_PAD0, 2}, + {PA13, SERCOM2_PAD1, 2}, + {PA14, SERCOM2_PAD2, 2}, + {PA15, SERCOM2_PAD3, 2}, + {PA22, SERCOM3_PAD0, 2}, + {PA27, SERCOM3_PAD0, 5}, + {PA23, SERCOM3_PAD1, 2}, + {PA20, SERCOM3_PAD2, 3}, + {PA24, SERCOM3_PAD2, 2}, + {PA21, SERCOM3_PAD3, 3}, + {PA25, SERCOM3_PAD3, 2}, + {PB08, SERCOM4_PAD0, 3}, + {PB12, SERCOM4_PAD0, 2}, + {PB09, SERCOM4_PAD1, 3}, + {PB13, SERCOM4_PAD1, 2}, + {PB31, SERCOM4_PAD1, 5}, + {PB10, SERCOM4_PAD2, 3}, + {PB14, SERCOM4_PAD2, 2}, + {PB30, SERCOM4_PAD2, 5}, + {PB11, SERCOM4_PAD3, 3}, + {PB15, SERCOM4_PAD3, 2}, + {PB02, SERCOM5_PAD0, 3}, + {PB16, SERCOM5_PAD0, 2}, + {PB03, SERCOM5_PAD1, 3}, + {PB17, SERCOM5_PAD1, 2}, + {PB00, SERCOM5_PAD2, 3}, + {PB22, SERCOM5_PAD2, 3}, + {PB01, SERCOM5_PAD3, 3}, + {PB23, SERCOM5_PAD3, 3}, + + /* Not connected */ + {NC , NC , NC} +}; + +/*******SERCOM Pins extended*******/ +const PinMap PinMap_SERCOM_PADEx[] = { + {PA08, SERCOM2_PAD0, 3}, + {PA09, SERCOM2_PAD1, 3}, + {PA10, SERCOM2_PAD2, 3}, + {PA11, SERCOM2_PAD3, 3}, + {PA16, SERCOM3_PAD0, 3}, + {PA17, SERCOM3_PAD1, 3}, + {PA18, SERCOM3_PAD2, 3}, + {PA19, SERCOM3_PAD3, 3}, + {PA12, SERCOM4_PAD0, 3}, + {PA13, SERCOM4_PAD1, 3}, + {PA14, SERCOM4_PAD2, 3}, + {PA15, SERCOM4_PAD3, 3}, + {PA22, SERCOM5_PAD0, 3}, + {PA23, SERCOM5_PAD1, 3}, + {PA20, SERCOM5_PAD2, 2}, + {PA24, SERCOM5_PAD2, 3}, + {PA21, SERCOM5_PAD3, 2}, + {PA25, SERCOM5_PAD3, 3}, + {PB31, SERCOM5_PAD1, 3}, + {PB30, SERCOM5_PAD0, 3}, + + /* Not connected */ + {NC , NC , NC} +}; + + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PA04, PWM_0, 4}, + {PA08, PWM_0, 4}, + {PB30, PWM_0, 4}, + {PA16, PWM_0, 5}, + {PA05, PWM_0, 4}, + {PA09, PWM_0, 4}, + {PB31, PWM_0, 4}, + {PA17, PWM_2, 4}, + {PA10, PWM_0, 5}, + {PA18, PWM_0, 5}, + {PA11, PWM_0, 5}, + {PA19, PWM_0, 5}, + {PA22, PWM_0, 5}, + {PB10, PWM_0, 5}, + {PB16, PWM_0, 5}, + {PA14, PWM_0, 5}, + {PA15, PWM_0, 5}, + {PA23, PWM_0, 5}, + {PB11, PWM_0, 5}, + {PB17, PWM_0, 5}, + {PA12, PWM_0, 5}, + {PA16, PWM_0, 5}, + {PA20, PWM_0, 5}, + {PB12, PWM_0, 5}, + {PA13, PWM_0, 5}, + {PA17, PWM_0, 5}, + {PA21, PWM_0, 5}, + {PB13, PWM_0, 5}, + {PA06, PWM_1, 4}, + {PA10, PWM_1, 4}, + {PA30, PWM_1, 4}, + {PA07, PWM_1, 4}, + {PA11, PWM_1, 4}, + {PA31, PWM_1, 4}, + {PA08, PWM_1, 5}, + {PA24, PWM_1, 5}, + {PB30, PWM_1, 5}, + {PA09, PWM_1, 5}, + {PA25, PWM_1, 5}, + {PB31, PWM_1, 5}, + {PA12, PWM_2, 4}, + {PA16, PWM_2, 4}, + {PA00, PWM_2, 4}, + {PA13, PWM_2, 4}, + {PA17, PWM_2, 4}, + {PA01, PWM_2, 4}, + + /* Not connected */ + {NC , NC , NC} +}; + +/**********EXTINT*************/ +const PinMap PinMap_EXTINT[] = { + {PA16, EXTINT_0, 0}, + {PB00, EXTINT_0, 0}, + {PB16, EXTINT_0, 0}, + {PA00, EXTINT_0, 0}, + + {PA17, EXTINT_1, 0}, + {PB01, EXTINT_1, 0}, + {PB17, EXTINT_1, 0}, + {PA01, EXTINT_1, 0}, + + {PA02, EXTINT_2, 0}, + {PA18, EXTINT_2, 0}, + {PB02, EXTINT_2, 0}, + + {PA03, EXTINT_3, 0}, + {PA19, EXTINT_3, 0}, + {PB03, EXTINT_3, 0}, + + {PA04, EXTINT_4, 0}, + {PA20, EXTINT_4, 0}, + {PB04, EXTINT_4, 0}, + + {PA05, EXTINT_5, 0}, + {PA21, EXTINT_5, 0}, + {PB05, EXTINT_5, 0}, + + {PA06, EXTINT_6, 0}, + {PA22, EXTINT_6, 0}, + {PB06, EXTINT_6, 0}, + {PB22, EXTINT_6, 0}, + + {PA07, EXTINT_7, 0}, + {PA23, EXTINT_7, 0}, + {PB07, EXTINT_7, 0}, + {PB23, EXTINT_7, 0}, + + {PB08, EXTINT_8, 0}, + + {PA09, EXTINT_9, 0}, + {PB09, EXTINT_9, 0}, + + {PA10, EXTINT_10, 0}, + {PA30, EXTINT_10, 0}, + {PB10, EXTINT_10, 0}, + + {PA11, EXTINT_11, 0}, + {PA31, EXTINT_11, 0}, + {PB11, EXTINT_11, 0}, + + {PA12, EXTINT_12, 0}, + {PA24, EXTINT_12, 0}, + {PB12, EXTINT_12, 0}, + + {PA13, EXTINT_13, 0}, + {PA25, EXTINT_13, 0}, + {PB13, EXTINT_13, 0}, + + {PB14, EXTINT_14, 0}, + {PB30, EXTINT_14, 0}, + {PA14, EXTINT_14, 0}, + + {PA27, EXTINT_15, 0}, + {PB15, EXTINT_15, 0}, + {PB31, EXTINT_15, 0}, + {PA15, EXTINT_15, 0}, + + /* Not connected */ + {NC , NC , NC} +}; + +const struct pwm_pin_channel pwn_pins[] = { + {PA04, PWM_0, 0}, + {PA08, PWM_0, 0}, + {PB30, PWM_0, 0}, + {PA16, PWM_0, 6}, + {PA05, PWM_0, 1}, + {PA09, PWM_0, 1}, + {PB31, PWM_0, 1}, + {PA17, PWM_0, 1}, + {PA10, PWM_0, 2}, + {PA18, PWM_0, 2}, + {PA11, PWM_0, 3}, + {PA19, PWM_0, 3}, + {PA22, PWM_0, 4}, + {PB10, PWM_0, 4}, + {PB16, PWM_0, 4}, + {PA14, PWM_0, 4}, + {PA15, PWM_0, 5}, + {PA23, PWM_0, 5}, + {PB11, PWM_0, 5}, + {PB17, PWM_0, 5}, + {PA12, PWM_0, 6}, + {PA16, PWM_0, 6}, + {PA20, PWM_0, 6}, + {PB12, PWM_0, 6}, + {PA13, PWM_0, 7}, + {PA17, PWM_2, 1}, + {PA21, PWM_0, 7}, + {PB13, PWM_0, 7}, + {PA06, PWM_1, 0}, + {PA10, PWM_1, 0}, + {PA30, PWM_1, 0}, + {PA07, PWM_1, 1}, + {PA11, PWM_1, 1}, + {PA31, PWM_1, 1}, + {PA08, PWM_1, 2}, + {PA24, PWM_1, 2}, + {PB30, PWM_1, 2}, + {PA09, PWM_1, 3}, + {PA25, PWM_1, 3}, + {PB31, PWM_1, 3}, + {PA12, PWM_2, 0}, + {PA16, PWM_2, 0}, + {PA00, PWM_2, 0}, + {PA13, PWM_2, 1}, + {PA17, PWM_2, 1}, + {PA01, PWM_2, 1}, + + /* Not connected */ + {NC , NC , NC} +}; + + + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/PeripheralPins.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PinNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PinNames.h new file mode 100644 index 0000000000..27e0c66f3e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PinNames.h @@ -0,0 +1,107 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013 Nordic Semiconductor + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INPUT_OUTPUT //pin state can be set and read back +} PinDirection; + +typedef enum { + PA00 = 0, + PA01 = 1, + PA02 = 2, + PA03 = 3, + PA04 = 4, + PA05 = 5, + PA06 = 6, + PA07 = 7, + PA08 = 8, + PA09 = 9, + PA10 = 10, + PA11 = 11, + PA12 = 12, + PA13 = 13, + PA14 = 14, + PA15 = 15, + PA16 = 16, + PA17 = 17, + PA18 = 18, + PA19 = 19, + PA20 = 20, + PA21 = 21, + PA22 = 22, + PA23 = 23, + PA24 = 24, + PA25 = 25, + PA27 = 27, + PA30 = 30, + PA31 = 31, + PB00 = 32, + PB01 = 33, + PB02 = 34, + PB03 = 35, + PB04 = 36, + PB05 = 37, + PB06 = 38, + PB07 = 39, + PB08 = 40, + PB09 = 41, + PB10 = 42, + PB11 = 43, + PB12 = 44, + PB13 = 45, + PB14 = 46, + PB15 = 47, + PB16 = 48, + PB17 = 49, + PB22 = 54, + PB23 = 55, + PB30 = 62, + PB31 = 63, + + USBTX = PA22, + USBRX = PA23, + + LED1 = PB10, + LED2 = PB10, + LED3 = PB10, + LED4 = PB10, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/mbed_overrides.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/mbed_overrides.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/saml21_xplained_pro.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/saml21_xplained_pro.h new file mode 100644 index 0000000000..27e9f03764 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/saml21_xplained_pro.h @@ -0,0 +1,599 @@ +/** + * \file + * + * \brief SAM L21 Xplained Pro board definition + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef SAML21_XPLAINED_PRO_H_INCLUDED +#define SAML21_XPLAINED_PRO_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup group_common_boards + * \defgroup saml21_xplained_pro_group SAM L21 Xplained Pro board + * + * @{ + */ + +void system_board_init(void); + +/** + * \defgroup saml21_xplained_pro_features_group Features + * + * Symbols that describe features and capabilities of the board. + * + * @{ + */ + +/** Name string macro */ +#define BOARD_NAME "SAML21_XPLAINED_PRO" + +/** \name Resonator definitions + * @{ */ +#define BOARD_FREQ_SLCK_XTAL (32768U) +#define BOARD_FREQ_SLCK_BYPASS (32768U) +#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */ +#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */ +#define BOARD_MCK CHIP_FREQ_CPU_MAX +#define BOARD_OSC_STARTUP_US 15625 +/** @} */ + +/** \name LED0 definitions + * @{ */ +#define LED0_PIN PIN_PB10 +#define LED0_ACTIVE false +#define LED0_INACTIVE !LED0_ACTIVE +/** @} */ + +/** \name SW0 definitions + * @{ */ +#define SW0_PIN PIN_PA02 +#define SW0_ACTIVE false +#define SW0_INACTIVE !SW0_ACTIVE +#define SW0_EIC_PIN PIN_PA02A_EIC_EXTINT2 +#define SW0_EIC_MUX MUX_PA02A_EIC_EXTINT2 +#define SW0_EIC_PINMUX PINMUX_PA02A_EIC_EXTINT2 +#define SW0_EIC_LINE 2 +/** @} */ + +/** + * \name LED #0 definitions + * + * Wrapper macros for LED0, to ensure common naming across all Xplained Pro + * boards. + * + * @{ */ +#define LED_0_NAME "LED0 (yellow)" +#define LED_0_PIN LED0_PIN +#define LED_0_ACTIVE LED0_ACTIVE +#define LED_0_INACTIVE LED0_INACTIVE +#define LED0_GPIO LED0_PIN +#define LED0 LED0_PIN + +#define LED_0_PWM4CTRL_MODULE TCC0 +#define LED_0_PWM4CTRL_CHANNEL 0 +#define LED_0_PWM4CTRL_OUTPUT 0 +#define LED_0_PWM4CTRL_PIN PIN_PB10F_TCC0_WO4 +#define LED_0_PWM4CTRL_MUX MUX_PB10F_TCC0_WO4 +#define LED_0_PWM4CTRL_PINMUX PINMUX_PB10F_TCC0_WO4 +/** @} */ + +/** Number of on-board LEDs */ +#define LED_COUNT 1 + + +/** + * \name Button #0 definitions + * + * Wrapper macros for SW0, to ensure common naming across all Xplained Pro + * boards. + * + * @{ */ +#define BUTTON_0_NAME "SW0" +#define BUTTON_0_PIN SW0_PIN +#define BUTTON_0_ACTIVE SW0_ACTIVE +#define BUTTON_0_INACTIVE SW0_INACTIVE +#define BUTTON_0_EIC_PIN SW0_EIC_PIN +#define BUTTON_0_EIC_MUX SW0_EIC_MUX +#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX +#define BUTTON_0_EIC_LINE SW0_EIC_LINE +/** @} */ + +/** Number of on-board buttons */ +#define BUTTON_COUNT 1 + +/** \name Extension header #1 pin definitions + * @{ + */ +#define EXT1_PIN_3 PIN_PB05 +#define EXT1_PIN_4 PIN_PA03 +#define EXT1_PIN_5 PIN_PB06 +#define EXT1_PIN_6 PIN_PB07 +#define EXT1_PIN_7 PIN_PA12 +#define EXT1_PIN_8 PIN_PA13 +#define EXT1_PIN_9 PIN_PB04 +#define EXT1_PIN_10 PIN_PA02 +#define EXT1_PIN_11 PIN_PA08 +#define EXT1_PIN_12 PIN_PA09 +#define EXT1_PIN_13 PIN_PB09 +#define EXT1_PIN_14 PIN_PB08 +#define EXT1_PIN_15 PIN_PA05 +#define EXT1_PIN_16 PIN_PA06 +#define EXT1_PIN_17 PIN_PA04 +#define EXT1_PIN_18 PIN_PA07 +/** @} */ + +/** \name Extension header #1 pin definitions by function + * @{ + */ +#define EXT1_PIN_ADC_0 EXT1_PIN_3 +#define EXT1_PIN_ADC_1 EXT1_PIN_4 +#define EXT1_PIN_GPIO_0 EXT1_PIN_5 +#define EXT1_PIN_GPIO_1 EXT1_PIN_6 +#define EXT1_PIN_PWM_0 EXT1_PIN_7 +#define EXT1_PIN_PWM_1 EXT1_PIN_8 +#define EXT1_PIN_IRQ EXT1_PIN_9 +#define EXT1_PIN_I2C_SDA EXT1_PIN_11 +#define EXT1_PIN_I2C_SCL EXT1_PIN_12 +#define EXT1_PIN_UART_RX EXT1_PIN_13 +#define EXT1_PIN_UART_TX EXT1_PIN_14 +#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10 +#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15 +#define EXT1_PIN_SPI_MOSI EXT1_PIN_16 +#define EXT1_PIN_SPI_MISO EXT1_PIN_17 +#define EXT1_PIN_SPI_SCK EXT1_PIN_18 +/** @} */ + +/** \name Extension header #1 ADC definitions + * @{ + */ +#define EXT1_ADC_MODULE ADC +#define EXT1_ADC_13_CHANNEL 13 +#define EXT1_ADC_13_PIN PIN_PB05B_ADC_AIN13 +#define EXT1_ADC_13_MUX MUX_PB05B_ADC_AIN13 +#define EXT1_ADC_13_PINMUX PINMUX_PB05B_ADC_AIN13 +#define EXT1_ADC_1_CHANNEL 1 +#define EXT1_ADC_1_PIN PIN_PA03B_ADC_AIN1 +#define EXT1_ADC_1_MUX MUX_PA03B_ADC_AIN1 +#define EXT1_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1 +/** @} */ + +/** \name Extension header #1 PWM definitions + * @{ + */ +#define EXT1_PWM_MODULE TC2 +#define EXT1_PWM_0_CHANNEL 0 +#define EXT1_PWM_0_PIN PIN_PB02E_TC2_WO0 +#define EXT1_PWM_0_MUX MUX_PB02E_TC2_WO0 +#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC2_WO0 +#define EXT1_PWM_1_CHANNEL 1 +#define EXT1_PWM_1_PIN PIN_PB03E_TC2_WO1 +#define EXT1_PWM_1_MUX MUX_PB03E_TC2_WO1 +#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC2_WO1 +/** @} */ + +/** \name Extension header #1 IRQ/External interrupt definitions + * @{ + */ +#define EXT1_IRQ_MODULE EIC +#define EXT1_IRQ_INPUT 4 +#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4 +#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4 +#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4 +/** @} */ + +/** \name Extension header #1 I2C definitions + * @{ + */ +#define EXT1_I2C_MODULE SERCOM2 +#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 +#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 +#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX +#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX +/** @} */ + +/** \name Extension header #1 UART definitions + * @{ + */ +#define EXT1_UART_MODULE SERCOM4 +#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 +#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0 +#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1 +#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED +#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED +#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX +#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX +/** @} */ + +/** \name Extension header #1 SPI definitions + * @{ + */ +#define EXT1_SPI_MODULE SERCOM0 +#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E +#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0 +#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1 +#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2 +#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3 +#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX +#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX +/** @} */ + +/** \name Extension header #2 pin definitions + * @{ + */ +#define EXT2_PIN_3 PIN_PA10 +#define EXT2_PIN_4 PIN_PA11 +#define EXT2_PIN_5 PIN_PA20 +#define EXT2_PIN_6 PIN_PA21 +#define EXT2_PIN_7 PIN_PB12 +#define EXT2_PIN_8 PIN_PB13 +#define EXT2_PIN_9 PIN_PB14 +#define EXT2_PIN_10 PIN_PB15 +#define EXT2_PIN_11 PIN_PA08 +#define EXT2_PIN_12 PIN_PA09 +#define EXT2_PIN_13 PIN_PA19 +#define EXT2_PIN_14 PIN_PA18 +#define EXT2_PIN_15 PIN_PA17 +#define EXT2_PIN_16 PIN_PB22 +#define EXT2_PIN_17 PIN_PB16 +#define EXT2_PIN_18 PIN_PB23 +/** @} */ + +/** \name Extension header #2 pin definitions by function + * @{ + */ +#define EXT2_PIN_ADC_0 EXT2_PIN_3 +#define EXT2_PIN_ADC_1 EXT2_PIN_4 +#define EXT2_PIN_GPIO_0 EXT2_PIN_5 +#define EXT2_PIN_GPIO_1 EXT2_PIN_6 +#define EXT2_PIN_PWM_0 EXT2_PIN_7 +#define EXT2_PIN_PWM_1 EXT2_PIN_8 +#define EXT2_PIN_IRQ EXT2_PIN_9 +#define EXT2_PIN_I2C_SDA EXT2_PIN_11 +#define EXT2_PIN_I2C_SCL EXT2_PIN_12 +#define EXT2_PIN_UART_RX EXT2_PIN_13 +#define EXT2_PIN_UART_TX EXT2_PIN_14 +#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10 +#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15 +#define EXT2_PIN_SPI_MOSI EXT2_PIN_16 +#define EXT2_PIN_SPI_MISO EXT2_PIN_17 +#define EXT2_PIN_SPI_SCK EXT2_PIN_18 +/** @} */ + +/** \name Extension header #2 ADC definitions + * @{ + */ +#define EXT2_ADC_MODULE ADC +#define EXT2_ADC_0_CHANNEL 18 +#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18 +#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18 +#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18 +#define EXT2_ADC_1_CHANNEL 19 +#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19 +#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19 +#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19 +/** @} */ + +/** \name Extension header #2 PWM definitions + * @{ + */ +#define EXT2_PWM_MODULE TC0 +#define EXT2_PWM_0_CHANNEL 0 +#define EXT2_PWM_0_PIN PIN_PB12E_TC0_WO0 +#define EXT2_PWM_0_MUX MUX_PB12E_TC0_WO0 +#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC0_WO0 +#define EXT2_PWM_1_CHANNEL 1 +#define EXT2_PWM_1_PIN PIN_PB13E_TC0_WO1 +#define EXT2_PWM_1_MUX MUX_PB13E_TC0_WO1 +#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC0_WO1 +/** @} */ + +/** \name Extension header #2 IRQ/External interrupt definitions + * @{ + */ +#define EXT2_IRQ_MODULE EIC +#define EXT2_IRQ_INPUT 14 +#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14 +#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14 +#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14 +/** @} */ + +/** \name Extension header #2 I2C definitions +* @{ +*/ +#define EXT2_I2C_MODULE SERCOM2 +#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 +#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 +#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX +#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX +/** @} */ + +/** \name Extension header #2 UART definitions + * @{ + */ +#define EXT2_UART_MODULE SERCOM1 +#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3 +#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED +#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED +#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 +#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 +#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX +#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX +/** @} */ + +/** \name Extension header #2 SPI definitions + * @{ + */ +#define EXT2_SPI_MODULE SERCOM5 +#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E +#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 +#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED +#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 +#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 +#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX +#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX +/** @} */ + +/** \name Extension header #3 pin definitions + * @{ + */ +#define EXT3_PIN_3 PIN_PB00 +#define EXT3_PIN_4 PIN_PB01 +#define EXT3_PIN_5 PIN_PB30 +#define EXT3_PIN_6 PIN_PA15 +#define EXT3_PIN_7 PIN_PB10 +#define EXT3_PIN_8 PIN_PB11 +#define EXT3_PIN_9 PIN_PA16 +#define EXT3_PIN_10 PIN_PA27 +#define EXT3_PIN_11 PIN_PA08 +#define EXT3_PIN_12 PIN_PA09 +#define EXT3_PIN_13 PIN_PA19 +#define EXT3_PIN_14 PIN_PA18 +#define EXT3_PIN_15 PIN_PB17 +#define EXT3_PIN_16 PIN_PB22 +#define EXT3_PIN_17 PIN_PB16 +#define EXT3_PIN_18 PIN_PB23 +/** @} */ + +/** \name Extension header #3 pin definitions by function + * @{ + */ +#define EXT3_PIN_ADC_0 EXT3_PIN_3 +#define EXT3_PIN_ADC_1 EXT3_PIN_4 +#define EXT3_PIN_GPIO_0 EXT3_PIN_5 +#define EXT3_PIN_GPIO_1 EXT3_PIN_6 +#define EXT3_PIN_PWM_0 EXT3_PIN_7 +#define EXT3_PIN_PWM_1 EXT3_PIN_8 +#define EXT3_PIN_IRQ EXT3_PIN_9 +#define EXT3_PIN_I2C_SDA EXT3_PIN_11 +#define EXT3_PIN_I2C_SCL EXT3_PIN_12 +#define EXT3_PIN_UART_RX EXT3_PIN_13 +#define EXT3_PIN_UART_TX EXT3_PIN_14 +#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10 +#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15 +#define EXT3_PIN_SPI_MOSI EXT3_PIN_16 +#define EXT3_PIN_SPI_MISO EXT3_PIN_17 +#define EXT3_PIN_SPI_SCK EXT3_PIN_18 +/** @} */ + +/** \name Extension header #3 ADC definitions + * @{ + */ +#define EXT3_ADC_MODULE ADC +#define EXT3_ADC_0_CHANNEL 8 +#define EXT3_ADC_0_PIN PIN_PB00B_ADC_AIN8 +#define EXT3_ADC_0_MUX MUX_PB00B_ADC_AIN8 +#define EXT3_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8 +#define EXT3_ADC_1_CHANNEL 9 +#define EXT3_ADC_1_PIN PIN_PB01B_ADC_AIN9 +#define EXT3_ADC_1_MUX MUX_PB01B_ADC_AIN9 +#define EXT3_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9 +/** @} */ + +/** \name Extension header #3 IRQ/External interrupt definitions + * @{ + */ +#define EXT3_IRQ_MODULE EIC +#define EXT3_IRQ_INPUT 0 +#define EXT3_IRQ_PIN PIN_PA16A_EIC_EXTINT0 +#define EXT3_IRQ_MUX MUX_PA16A_EIC_EXTINT0 +#define EXT3_IRQ_PINMUX PINMUX_PA16A_EIC_EXTINT0 +/** @} */ + +/** \name Extension header #3 I2C definitions + * @{ + */ +#define EXT3_I2C_MODULE SERCOM2 +#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 +#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 +#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX +#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX +/** @} */ + +/** \name Extension header #3 UART definitions + * @{ + */ +#define EXT3_UART_MODULE SERCOM1 +#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3 +#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED +#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED +#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 +#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 +#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX +#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX + +/** @} */ + +/** \name Extension header #3 SPI definitions + * @{ + */ +#define EXT3_SPI_MODULE SERCOM5 +#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E +#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 +#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1 +#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 +#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 +#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX +#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX +/** @} */ + +/** \name Embedded debugger I2C interface definitions + * @{ + */ +#define EDBG_I2C_MODULE SERCOM2 +#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0 +#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1 +#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX +#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX +/** @} */ + +/** \name Embedded debugger SPI interface definitions + * @{ + */ +#define EDBG_SPI_MODULE SERCOM5 +#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E +#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 +#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1 +#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 +#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 +#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX +#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX +/** @} */ + +/** \name Embedded debugger CDC Gateway USART interface definitions + * @{ + */ +#define EDBG_CDC_MODULE SERCOM3 +#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1 +#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0 +#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1 +#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED +#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED +#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX +#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX +/** @} */ + +/** \name USB definitions + * @{ + */ +#define USB_ID +#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP +#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP +#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP +#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM +#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM +#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM +#define USB_VBUS_PIN PIN_PA14 +#define USB_VBUS_EIC_LINE 14 +#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14 +#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14 +#define USB_ID_PIN PIN_PB02 +#define USB_ID_EIC_LINE 2 +#define USB_ID_EIC_MUX MUX_PB02A_EIC_EXTINT2 +#define USB_ID_EIC_PINMUX PINMUX_PB02A_EIC_EXTINT2 +/** @} */ + +/** \name CCL interface definitions + * @{ + */ +#define CCL_LUT0_IN0_MUX MUX_PA04I_CCL_IN0 +#define CCL_LUT0_IN1_MUX MUX_PA05I_CCL_IN1 +#define CCL_LUT0_IN2_MUX MUX_PA06I_CCL_IN2 +#define CCL_LUT0_OUT_MUX MUX_PA07I_CCL_OUT0 + +#define CCL_LUT0_IN0_PIN PIN_PA04I_CCL_IN0 +#define CCL_LUT0_IN1_PIN PIN_PA05I_CCL_IN1 +#define CCL_LUT0_IN2_PIN PIN_PA06I_CCL_IN2 +#define CCL_LUT0_OUT_PIN PIN_PA07I_CCL_OUT0 + +#define CCL_LUT1_IN0_MUX MUX_PA08I_CCL_IN3 +#define CCL_LUT1_IN1_MUX MUX_PA09I_CCL_IN4 +#define CCL_LUT1_IN2_MUX MUX_PA10I_CCL_IN5 +#define CCL_LUT1_OUT_MUX MUX_PA11I_CCL_OUT1 + +#define CCL_LUT1_IN0_PIN PIN_PA08I_CCL_IN3 +#define CCL_LUT1_IN1_PIN PIN_PA09I_CCL_IN4 +#define CCL_LUT1_IN2_PIN PIN_PA10I_CCL_IN5 +#define CCL_LUT1_OUT_PIN PIN_PA11I_CCL_OUT1 +/** @} */ + +/** + * \brief Turns off the specified LEDs. + * + * \param led_gpio LED to turn off (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true) + +/** + * \brief Turns on the specified LEDs. + * + * \param led_gpio LED to turn on (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false) + +/** + * \brief Toggles the specified LEDs. + * + * \param led_gpio LED to toggle (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* SAML21_XPLAINED_PRO_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/analogout_api.c new file mode 100644 index 0000000000..b2e73bc208 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/analogout_api.c @@ -0,0 +1,116 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogout_api.h" + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "dac.h" + +extern uint8_t g_sys_init; + +#define MAX_VAL_12BIT 0x0FFF /*12 Bit DAC for SAML21*/ + +void analogout_init(dac_t *obj, PinName pin) +{ + MBED_ASSERT(obj); + if (g_sys_init == 0) { + system_init(); + g_sys_init = 1; + } + struct dac_config config_dac; + struct dac_chan_config config_dac_chan; + uint32_t dacperipheral; + uint32_t ch_index; + + dacperipheral = pinmap_find_peripheral(pin, PinMap_DAC); + MBED_ASSERT(dacperipheral != NC); + obj->pin = pin; + obj->dac = dacperipheral; + if (pin == PA02) { + ch_index = 0; + } else if (pin == PA05) { + ch_index = 1; + } else { /*Only 2 pins for DAC*/ + return 0; + } + obj->channel = ch_index; + + dac_get_config_defaults(&config_dac); + dac_init(&(obj->dac_instance), (Dac *)dacperipheral, &config_dac); + dac_chan_get_config_defaults(&config_dac_chan); + dac_chan_set_config(&(obj->dac_instance), ch_index, &config_dac_chan); + dac_chan_enable(&(obj->dac_instance), ch_index); + dac_enable(&(obj->dac_instance)); +} + +void analogout_free(dac_t *obj) +{ + MBED_ASSERT(obj); + struct system_pinmux_config pin_conf; + + dac_disable(&(obj->dac_instance)); + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; + pin_conf.powersave = false; + pin_conf.mux_position = SYSTEM_PINMUX_GPIO; + system_pinmux_pin_set_config(obj->pin, &pin_conf); +} + +void analogout_write(dac_t *obj, float value) +{ + MBED_ASSERT(obj); + uint16_t count_val = 0; + if (value < 0.0f) { + count_val = 0; + } else if (value > 1.0f) { + count_val = MAX_VAL_12BIT; + } else { + count_val = (uint16_t)(value * (float)MAX_VAL_12BIT); + } + dac_chan_write(&(obj->dac_instance), obj->channel, count_val); + +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + MBED_ASSERT(obj); + uint16_t count_val; + count_val = (uint16_t)((value * (float)MAX_VAL_12BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/ + dac_chan_write(&(obj->dac_instance), obj->channel, count_val); + +} + +static uint32_t data_reg_read(dac_t *obj) +{ + Dac *const dac_module = (Dac *)obj->dac; + return (uint32_t)dac_module->DATA[obj->channel].reg; +} + +float analogout_read(dac_t *obj) +{ + MBED_ASSERT(obj); + uint32_t data_val = data_reg_read(obj); + return data_val/(float)MAX_VAL_12BIT; +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + MBED_ASSERT(obj); + uint32_t data_val = data_reg_read(obj); + return (uint16_t)((data_val / (float)MAX_VAL_12BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/ +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/device.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21J18A/device.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralNames.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralNames.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralNames.h index b549d22d70..46dd46a34c 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.c similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.c index ae018a9962..67a253a53f 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.h similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.h index 0571b092e6..edc62995d7 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PinNames.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PinNames.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PinNames.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PinNames.h index 4d27e4428f..d4aa73f78e 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PinNames.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c new file mode 100644 index 0000000000..f6b9e40105 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c @@ -0,0 +1,32 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "compiler.h" +#include "system.h" + +uint8_t g_sys_init = 0; + +//called before main - implement here if board needs it ortherwise, let +// the application override this if necessary +//TODO: To be implemented by adding system init and board init +void mbed_sdk_init() +{ + if(g_sys_init == 0) { + g_sys_init = 1; + system_init(); + } +} +/***************************************************************/ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/device.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/device.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device.h index 3fb36eb1eb..c18588a337 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21G18A/device.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/analogin_api.c similarity index 79% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/analogin_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/analogin_api.c index 06fa1d77fc..a780997a5d 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/analogin_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -119,6 +119,45 @@ void adc_configure_ain_pin(uint32_t pin) PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +#elif (SAML21E) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +#elif (SAML21G) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +#elif (SAML21J) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, + PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, #else # error ADC pin mappings are not defined for this device. #endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_board.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_board.h new file mode 100644 index 0000000000..be06f54b71 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_board.h @@ -0,0 +1,50 @@ +/** + * \file + * + * \brief SAM D21 Xplained Pro board configuration. + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CONF_BOARD_H_INCLUDED +#define CONF_BOARD_H_INCLUDED + +#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_clocks.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_clocks.h new file mode 100644 index 0000000000..c847dbe97c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_clocks.h @@ -0,0 +1,198 @@ +/** + * \file + * + * \brief SAM D21 Clock configuration + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include + +#ifndef CONF_CLOCKS_H_INCLUDED +# define CONF_CLOCKS_H_INCLUDED + +/* System clock bus configuration */ +# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false +# define CONF_CLOCK_FLASH_WAIT_STATES 0 +# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 +# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 +# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 +# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 + +/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */ +# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1 +# define CONF_CLOCK_OSC8M_ON_DEMAND true +# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY true + +/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */ +# define CONF_CLOCK_XOSC_ENABLE false +# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL +# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL +# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768 +# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true +# define CONF_CLOCK_XOSC_ON_DEMAND true +# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false + +/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */ +# define CONF_CLOCK_XOSC32K_ENABLE false +# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL +# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536 +# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false +# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false +# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true +# define CONF_CLOCK_XOSC32K_ON_DEMAND false +# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY true + +/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */ +# define CONF_CLOCK_OSC32K_ENABLE false +# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130 +# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT false +# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true +# define CONF_CLOCK_OSC32K_ON_DEMAND true +# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false + +/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */ +# define CONF_CLOCK_DFLL_ENABLE false +# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN +# define CONF_CLOCK_DFLL_ON_DEMAND false + +/* DFLL open loop mode configuration */ +# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4) + +/* DFLL closed loop mode configuration */ +# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1 +# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768) +# define CONF_CLOCK_DFLL_QUICK_LOCK true +# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true +# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true +# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true +# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 8) +# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 8) + +/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */ +# define CONF_CLOCK_DPLL_ENABLE false +# define CONF_CLOCK_DPLL_ON_DEMAND false +# define CONF_CLOCK_DPLL_RUN_IN_STANDBY true +# define CONF_CLOCK_DPLL_LOCK_BYPASS false +# define CONF_CLOCK_DPLL_WAKE_UP_FAST false +# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE true + +# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT +# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K +# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT + +# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768 +# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1 +# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000 + +/* DPLL GCLK reference configuration */ +# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1 +/* DPLL GCLK lock timer configuration */ +# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1 + +/* Set this to true to configure the GCLK when running clocks_init. If set to + * false, none of the GCLK generators will be configured in clocks_init(). */ +# define CONF_CLOCK_CONFIGURE_GCLK true + +/* Configure GCLK generator 0 (Main Clock) */ +# define CONF_CLOCK_GCLK_0_ENABLE true +# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_0_PRESCALER 1 +# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false + +/* Configure GCLK generator 1 */ +# define CONF_CLOCK_GCLK_1_ENABLE true +# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY true +# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_1_PRESCALER 1 +# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false + +/* Configure GCLK generator 2 (RTC) */ +# define CONF_CLOCK_GCLK_2_ENABLE true +# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY true +# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_ULP32K +# define CONF_CLOCK_GCLK_2_PRESCALER 32 +# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false + +/* Configure GCLK generator 3 */ +# define CONF_CLOCK_GCLK_3_ENABLE false +# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_3_PRESCALER 1 +# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false + +/* Configure GCLK generator 4 */ +# define CONF_CLOCK_GCLK_4_ENABLE false +# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_4_PRESCALER 1 +# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false + +/* Configure GCLK generator 5 */ +# define CONF_CLOCK_GCLK_5_ENABLE false +# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_5_PRESCALER 1 +# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false + +/* Configure GCLK generator 6 */ +# define CONF_CLOCK_GCLK_6_ENABLE false +# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_6_PRESCALER 1 +# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false + +/* Configure GCLK generator 7 */ +# define CONF_CLOCK_GCLK_7_ENABLE false +# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_7_PRESCALER 1 +# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false + +/* Configure GCLK generator 8 */ +# define CONF_CLOCK_GCLK_8_ENABLE false +# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M +# define CONF_CLOCK_GCLK_8_PRESCALER 1 +# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false + +#endif /* CONF_CLOCKS_H_INCLUDED */ + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_dma.h new file mode 100644 index 0000000000..ffb71f634f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_dma.h @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief SAM D21 Direct Memory Access Driver Configuration Header + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef CONF_DMA_H_INCLUDED +#define CONF_DMA_H_INCLUDED + +# define CONF_MAX_USED_CHANNEL_NUM 1 + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_extint.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_extint.h new file mode 100644 index 0000000000..fac3865bd0 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_extint.h @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief SAM D21 External Interrupt Driver Configuration Header + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef CONF_EXTINT_H_INCLUDED +#define CONF_EXTINT_H_INCLUDED + +# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_spi.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_spi.h new file mode 100644 index 0000000000..c01eb2bd0d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_spi.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief SAM D21 SPI configuration + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + + +#ifndef CONF_SPI_H_INCLUDED +# define CONF_SPI_H_INCLUDED + +# define CONF_SPI_MASTER_ENABLE true +# define CONF_SPI_SLAVE_ENABLE false +# define CONF_SPI_TIMEOUT 10000 + +#endif /* CONF_SPI_H_INCLUDED */ + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_test.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_test.h new file mode 100644 index 0000000000..35943dad1c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_test.h @@ -0,0 +1,57 @@ +/** + * \file + * + * \brief SAM D21 Xplained Pro test configuration. + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef CONF_TEST_H_INCLUDED +#define CONF_TEST_H_INCLUDED + +#define CONF_STDIO_USART EDBG_CDC_MODULE +#define CONF_STDIO_MUX_SETTING EDBG_CDC_SERCOM_MUX_SETTING +#define CONF_STDIO_PINMUX_PAD0 EDBG_CDC_SERCOM_PINMUX_PAD0 +#define CONF_STDIO_PINMUX_PAD1 EDBG_CDC_SERCOM_PINMUX_PAD1 +#define CONF_STDIO_PINMUX_PAD2 EDBG_CDC_SERCOM_PINMUX_PAD2 +#define CONF_STDIO_PINMUX_PAD3 EDBG_CDC_SERCOM_PINMUX_PAD3 +#define CONF_STDIO_BAUDRATE 38400 + +#endif /* CONF_TEST_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_board.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_board.h new file mode 100644 index 0000000000..5bc0a39e26 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_board.h @@ -0,0 +1,50 @@ +/** + * \file + * + * \brief SAM L21 Xplained Pro board configuration. + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CONF_BOARD_H_INCLUDED +#define CONF_BOARD_H_INCLUDED + +#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_clocks.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_clocks.h new file mode 100644 index 0000000000..efc5de493a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_clocks.h @@ -0,0 +1,200 @@ +/** + * \file + * + * \brief SAM L21 Clock configuration + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include + +#ifndef CONF_CLOCKS_H_INCLUDED +# define CONF_CLOCKS_H_INCLUDED + +/* System clock bus configuration */ +# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false +# define CONF_CLOCK_FLASH_WAIT_STATES 0 +# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 +# define CONF_CLOCK_LOW_POWER_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 +# define CONF_CLOCK_BACKUP_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 + +/* SYSTEM_CLOCK_SOURCE_OSC16M configuration - Internal 16MHz oscillator */ +# define CONF_CLOCK_OSC16M_FREQ_SEL SYSTEM_OSC16M_4M +# define CONF_CLOCK_OSC16M_ON_DEMAND true +# define CONF_CLOCK_OSC16M_RUN_IN_STANDBY false + +/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */ +# define CONF_CLOCK_XOSC_ENABLE false +# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL +# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL +# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768 +# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true +# define CONF_CLOCK_XOSC_ON_DEMAND true +# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false + +/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */ +# define CONF_CLOCK_XOSC32K_ENABLE false +# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL +# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536 +# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false +# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true +# define CONF_CLOCK_XOSC32K_ON_DEMAND true +# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false + +/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */ +# define CONF_CLOCK_OSC32K_ENABLE false +# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130 +# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true +# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true +# define CONF_CLOCK_OSC32K_ON_DEMAND true +# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false + + +/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */ +# define CONF_CLOCK_DFLL_ENABLE false +# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN +# define CONF_CLOCK_DFLL_ON_DEMAND false +# define CONF_CLOCK_DFLL_RUN_IN_STANDBY false + +/* DFLL open loop mode configuration */ +# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4) + +/* DFLL closed loop mode configuration */ +# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1 +# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768) +# define CONF_CLOCK_DFLL_QUICK_LOCK true +# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true +# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true +# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true +# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4) +# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4) + +/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */ +# define CONF_CLOCK_DPLL_ENABLE false +# define CONF_CLOCK_DPLL_ON_DEMAND true +# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false +# define CONF_CLOCK_DPLL_LOCK_BYPASS false +# define CONF_CLOCK_DPLL_WAKE_UP_FAST false +# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false + +# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT +# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K +# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT +# define CONF_CLOCK_DPLL_PRESCALER SYSTEM_CLOCK_SOURCE_DPLL_DIV_1 + + +# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768 +# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1 +# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000 + +/* DPLL GCLK reference configuration */ +# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1 +/* DPLL GCLK lock timer configuration */ +# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1 + + +/* Set this to true to configure the GCLK when running clocks_init. If set to + * false, none of the GCLK generators will be configured in clocks_init(). */ +# define CONF_CLOCK_CONFIGURE_GCLK true + +/* Configure GCLK generator 0 (Main Clock) */ +# define CONF_CLOCK_GCLK_0_ENABLE true +# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M +# define CONF_CLOCK_GCLK_0_PRESCALER 1 +# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false + +/* Configure GCLK generator 1 */ +# define CONF_CLOCK_GCLK_1_ENABLE false +# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K +# define CONF_CLOCK_GCLK_1_PRESCALER 1 +# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false + +/* Configure GCLK generator 2 */ +# define CONF_CLOCK_GCLK_2_ENABLE false +# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M +# define CONF_CLOCK_GCLK_2_PRESCALER 1 +# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false + +/* Configure GCLK generator 3 */ +# define CONF_CLOCK_GCLK_3_ENABLE false +# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M +# define CONF_CLOCK_GCLK_3_PRESCALER 1 +# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false + +/* Configure GCLK generator 4 */ +# define CONF_CLOCK_GCLK_4_ENABLE false +# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M +# define CONF_CLOCK_GCLK_4_PRESCALER 1 +# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false + +/* Configure GCLK generator 5 */ +# define CONF_CLOCK_GCLK_5_ENABLE false +# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M +# define CONF_CLOCK_GCLK_5_PRESCALER 1 +# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false + +/* Configure GCLK generator 6 */ +# define CONF_CLOCK_GCLK_6_ENABLE false +# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M +# define CONF_CLOCK_GCLK_6_PRESCALER 1 +# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false + +/* Configure GCLK generator 7 */ +# define CONF_CLOCK_GCLK_7_ENABLE false +# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M +# define CONF_CLOCK_GCLK_7_PRESCALER 1 +# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false + +/* Configure GCLK generator 8 */ +# define CONF_CLOCK_GCLK_8_ENABLE false +# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false +# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M +# define CONF_CLOCK_GCLK_8_PRESCALER 1 +# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false +#endif /* CONF_CLOCKS_H_INCLUDED */ + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_dma.h new file mode 100644 index 0000000000..d69e2c875b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_dma.h @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief SAM L21 Direct Memory Access Driver Configuration Header + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef CONF_DMA_H_INCLUDED +#define CONF_DMA_H_INCLUDED + +# define CONF_MAX_USED_CHANNEL_NUM 1 + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_extint.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_extint.h new file mode 100644 index 0000000000..55ffb24fae --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_extint.h @@ -0,0 +1,52 @@ +/** + * \file + * + * \brief SAM L21 External Interrupt Driver Configuration Header + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef CONF_EXTINT_H_INCLUDED +#define CONF_EXTINT_H_INCLUDED + +# define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK +# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_spi.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_spi.h new file mode 100644 index 0000000000..499cd2692e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_spi.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief SAM L21 SPI configuration + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + + +#ifndef CONF_SPI_H_INCLUDED +# define CONF_SPI_H_INCLUDED + +# define CONF_SPI_MASTER_ENABLE true +# define CONF_SPI_SLAVE_ENABLE false +# define CONF_SPI_TIMEOUT 10000 + +#endif /* CONF_SPI_H_INCLUDED */ + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_test.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_test.h new file mode 100644 index 0000000000..4d98422ea7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_test.h @@ -0,0 +1,58 @@ +/** + * \file + * + * \brief SAM L21 Xplained Pro test configuration. + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CONF_TEST_H_INCLUDED +#define CONF_TEST_H_INCLUDED + +#define CONF_STDIO_USART EDBG_CDC_MODULE +#define CONF_STDIO_MUX_SETTING EDBG_CDC_SERCOM_MUX_SETTING +#define CONF_STDIO_PINMUX_PAD0 EDBG_CDC_SERCOM_PINMUX_PAD0 +#define CONF_STDIO_PINMUX_PAD1 EDBG_CDC_SERCOM_PINMUX_PAD1 +#define CONF_STDIO_PINMUX_PAD2 EDBG_CDC_SERCOM_PINMUX_PAD2 +#define CONF_STDIO_PINMUX_PAD3 EDBG_CDC_SERCOM_PINMUX_PAD3 +#define CONF_STDIO_BAUDRATE 38400 + +#endif /* CONF_TEST_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_board.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_board.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_board.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_board.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_clocks.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_clocks.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_clocks.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_clocks.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_dma.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_dma.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_extint.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_extint.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_extint.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_extint.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_spi.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_spi.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_spi.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_spi.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_test.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_test.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/config/conf_test.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_test.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api.c similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api.c index dfa051b67d..b72a6d90cd 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api_HAL.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api_HAL.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api_HAL.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api_HAL.h index 121df4c22c..c5c0ef52ac 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/dma_api_HAL.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api_HAL.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/adc/adc_sam_d_r/adc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/adc/adc_sam_d_r/adc.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/adc/adc_sam_d_r/adc_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc_feature.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/adc/adc_sam_d_r/adc_feature.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc_feature.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc.c new file mode 100644 index 0000000000..3ae68f5fb7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc.c @@ -0,0 +1,769 @@ +/** + * \file + * + * \brief SAM Peripheral Analog-to-Digital Converter Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "adc.h" +#if (ADC_INST_NUM > 1) || (SAMC20) + +# define _ADC_GCLK_ID(n,unused) TPASTE3(ADC,n,_GCLK_ID), +# define _ADC_APBCMASK(n,unused) TPASTE2(MCLK_APBCMASK_ADC,n), + +# define _ADC_FUSES_BIASCOMP_ADDR(n,unused) TPASTE3(ADC,n,_FUSES_BIASCOMP_ADDR), +# define _ADC_FUSES_BIASCOMP_Pos(n,unused) TPASTE3(ADC,n,_FUSES_BIASCOMP_Pos), +# define _ADC_FUSES_BIASREFBUF_ADDR(n,unused) TPASTE3(ADC,n,_FUSES_BIASREFBUF_ADDR), +# define _ADC_FUSES_BIASREFBUF_Pos(n,unused) TPASTE3(ADC,n,_FUSES_BIASREFBUF_Pos), +# define _ADC_EXTCHANNEL_MSB(n,unused) TPASTE3(ADC,n,_EXTCHANNEL_MSB), + +# define ADC_GCLK_ID MREPEAT(ADC_INST_NUM, _ADC_GCLK_ID, 0) +# define ADC_APBCMASKS MREPEAT(ADC_INST_NUM, _ADC_APBCMASK, 0) + +# define ADC_FUSES_BIASCOMP_ADDR MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_ADDR, 0) +# define ADC_FUSES_BIASCOMP_Pos MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_Pos, 0) +# define ADC_FUSES_BIASREFBUF_ADDR MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_ADDR, 0) +# define ADC_FUSES_BIASREFBUF_Pos MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_Pos, 0) +# define ADC_EXTCHANNEL_MSB MREPEAT(ADC_INST_NUM, _ADC_EXTCHANNEL_MSB, 0) + +#endif + +/* List of ADC GCLK IDs */ +const uint8_t _adc_gclk_ids[ADC_INST_NUM] = { ADC_GCLK_ID }; + +/* List of ADC APB Masks */ +#if (SAML21) +const uint32_t _adc_apbcmasks[ADC_INST_NUM] = { MCLK_APBDMASK_ADC }; +#else +const uint32_t _adc_apbcmasks[ADC_INST_NUM] = { ADC_APBCMASKS }; +#endif + +/* List of Number of external channels of ADC modules. */ +const uint32_t _adc_extchannel_msb[ADC_INST_NUM] = { ADC_EXTCHANNEL_MSB }; + +/* List of address of comparator scaling of ADC modules. */ +const uint32_t _adc_biascomp_addr[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_ADDR }; + +/* List of address of bias reference buffer scaling of ADC modules. */ +const uint32_t _adc_biasrefbuf_addr[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_ADDR }; + +/* List of offset of comparator scaling of ADC modules. */ +const uint8_t _adc_biascomp_pos[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_Pos }; + +/* List of offset of bias reference buffer scaling of ADC modules. */ +const uint8_t _adc_biasrefbuf_pos[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_Pos }; + + +/** + * \internal Find the index of given ADC module instance. + * + * \param[in] ADC module instance pointer. + * + * \return Index of the given ADC module instance. + */ +uint8_t _adc_get_inst_index( + Adc *const hw) +{ + /* List of available ADC modules. */ + Adc *const adc_modules[ADC_INST_NUM] = ADC_INSTS; + + /* Find index for ADC instance. */ + for (uint32_t i = 0; i < ADC_INST_NUM; i++) { + if (hw == adc_modules[i]) { + return i; + } + } + + /* Invalid data given. */ + Assert(false); + return 0; +} + +/** + * \brief Initializes an ADC configuration structure to defaults. + * + * Initializes a given ADC configuration struct to a set of known default + * values. This function should be called on any new instance of the + * configuration struct before being modified by the user application. + * + * The default configuration is as follows: + * \li GCLK generator 0 (GCLK main) clock source + * \li Internal bandgap reference + * \li Div 2 clock prescaler + * \li 12-bit resolution + * \li Window monitor disabled + * \li Positive input on ADC PIN 1 + * \li Negative input on Internal ground + * \li Averaging disabled + * \li Oversampling disabled + * \li Right adjust data + * \li Single-ended mode + * \li Free running disabled + * \li All events (input and generation) disabled + * \li ADC run in standby disabled + * \li ADC On demand disabled + * \li No sampling time compensation + * \li Disable the positive input sequense + * \li No reference compensation + * \li No gain/offset correction + * \li No added sampling time + * + * \param[out] config Pointer to configuration struct to initialize to + * default values + */ +void adc_get_config_defaults(struct adc_config *const config) +{ + Assert(config); + config->clock_source = GCLK_GENERATOR_0; + config->reference = ADC_REFERENCE_INTREF; + config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV2; + config->resolution = ADC_RESOLUTION_12BIT; + config->window.window_mode = ADC_WINDOW_MODE_DISABLE; + config->window.window_upper_value = 0; + config->window.window_lower_value = 0; + config->positive_input = ADC_POSITIVE_INPUT_PIN1; + config->negative_input = ADC_NEGATIVE_INPUT_GND; + config->accumulate_samples = ADC_ACCUMULATE_DISABLE; + config->divide_result = ADC_DIVIDE_RESULT_DISABLE; + config->left_adjust = false; + config->differential_mode = false; + config->freerunning = false; + config->event_action = ADC_EVENT_ACTION_DISABLED; + config->run_in_standby = false; + config->on_demand = false; + config->sampling_time_compensation_enable = false; + config->positive_input_sequence_mask_enable = 0; + config->reference_compensation_enable = false; + config->correction.correction_enable = false; + config->correction.gain_correction = ADC_GAINCORR_RESETVALUE; + config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE; + config->sample_length = 0; +} + +/** + * \brief Sets the ADC window mode. + * + * Sets the ADC window mode to a given mode and value range. + * + * \param[in] module_inst Pointer to the ADC software instance struct + * \param[in] window_mode Window monitor mode to set + * \param[in] window_lower_value Lower window monitor threshold value + * \param[in] window_upper_value Upper window monitor threshold value + */ +void adc_set_window_mode( + struct adc_module *const module_inst, + const enum adc_window_mode window_mode, + const int16_t window_lower_value, + const int16_t window_upper_value) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Adc *const adc_module = module_inst->hw; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Set window mode */ + adc_module->CTRLC.reg = window_mode; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Set lower window monitor threshold value */ + adc_module->WINLT.reg = window_lower_value; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Set upper window monitor threshold value */ + adc_module->WINUT.reg = window_upper_value; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } +} + +/** +* \internal Configure MUX settings for the analog pins. +* +* This function will set the given ADC input pins +* to the analog function in the pin mux, giving +* the ADC access to the analog signal. +* +* \param [in] index Index of the ADC module instance. +* \param [in] pin AINxx pin to configure +*/ +static inline void _adc_configure_ain_pin(uint8_t index, uint32_t pin) +{ +#define PIN_INVALID_ADC_AIN 0xFFFFUL + + /* Pinmapping table for AINxx -> GPIO pin number */ +#if (SAML21) + const uint32_t pinmapping[] = { +# if (SAML21E) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +# elif (SAML21G) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +# elif (SAML21J) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, + PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +# else +# error ADC pin mappings are not defined for this device. +# endif + }; +#elif (SAMC20) + const uint32_t pinmapping[] = { +# if (SAMC20E) + PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, + PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, + PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, + PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, +# elif (SAMC20G) + PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, + PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3, + PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, + PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, + PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, + PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, +# elif (SAMC20J) + PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, + PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3, + PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, + PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, + PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, + PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, +# else +# error ADC pin mappings are not defined for this device. +# endif + }; +#elif (SAMC21) + const uint32_t *pinmapping = NULL;; + const uint32_t pinmapping0[] = { +# if (SAMC21E) + PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, + PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, + PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, + PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, +# elif (SAMC21G) + PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, + PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3, + PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, + PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, + PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, + PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, +# elif (SAMC21J) + PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1, + PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3, + PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5, + PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7, + PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9, + PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11, +# else +# error ADC pin mappings are not defined for this device. +# endif + }; + const uint32_t pinmapping1[] = { +# if (SAMC21E) + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11, +# elif (SAMC21G) + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PB02B_ADC1_AIN2, PIN_PB03B_ADC1_AIN3, + PIN_PB08B_ADC1_AIN4, PIN_PB09B_ADC1_AIN5, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11, +# elif (SAMC21J) + PIN_PB00B_ADC1_AIN0, PIN_PB01B_ADC1_AIN1, + PIN_PB02B_ADC1_AIN2, PIN_PB03B_ADC1_AIN3, + PIN_PB08B_ADC1_AIN4, PIN_PB09B_ADC1_AIN5, + PIN_PB04B_ADC1_AIN6, PIN_PB05B_ADC1_AIN7, + PIN_PB06B_ADC1_AIN8, PIN_PB07B_ADC1_AIN9, + PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11, +# else +# error ADC pin mappings are not defined for this device. +# endif + }; + + switch(index) { + case 0: + pinmapping = pinmapping0; + break; + case 1: + pinmapping = pinmapping1; + break; + default: + break; + } + Assert(pinmapping); +#endif + + uint32_t pin_map_result = PIN_INVALID_ADC_AIN; + + if (pin <= _adc_extchannel_msb[index]) { + pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos]; + + Assert(pin_map_result != PIN_INVALID_ADC_AIN); + + struct system_pinmux_config config; + system_pinmux_get_config_defaults(&config); + + /* Analog functions are all on MUX setting B */ + config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; + config.mux_position = 1; + + system_pinmux_pin_set_config(pin_map_result, &config); + } +} + +/** + * \internal Writes an ADC configuration to the hardware module. + * + * Writes out a given ADC module configuration to the hardware module. + * + * \param[in] index Index of the ADC module instance + * \param[out] module_inst Pointer to the ADC software instance struct + * \param[in] config Pointer to configuration struct + * + * \return Status of the configuration procedure. + * \retval STATUS_OK The configuration was successful + * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided + */ +static enum status_code _adc_set_config( + uint8_t index, + struct adc_module *const module_inst, + struct adc_config *const config) +{ + uint8_t adjres = 0; + uint32_t resolution = ADC_RESOLUTION_16BIT; + enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE; + + /* Get the hardware module pointer */ + Adc *const adc_module = module_inst->hw; + + /* Configure GCLK channel and enable clock */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = config->clock_source; + system_gclk_chan_set_config(_adc_gclk_ids[index], &gclk_chan_conf); + system_gclk_chan_enable(_adc_gclk_ids[index]); + + /* Setup pinmuxing for analog inputs */ + _adc_configure_ain_pin(index, config->positive_input); + _adc_configure_ain_pin(index, config->negative_input); + + /* Set pinmux for positive input sequence*/ + for(uint8_t i=0; i <= _adc_extchannel_msb[index]; i++) { + if(config->positive_input_sequence_mask_enable & (1 << i)) { + _adc_configure_ain_pin(index, i); + } + } + + /* Configure run in standby and on demand */ + adc_module->CTRLA.reg = ((config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos) + | (config->on_demand << ADC_CTRLA_ONDEMAND_Pos)) ; + + /* Configure reference */ + adc_module->REFCTRL.reg = + (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) + | (config->reference); + + /* Set adjusting result and number of samples */ + switch (config->resolution) { + + case ADC_RESOLUTION_CUSTOM: + adjres = config->divide_result; + accumulate = config->accumulate_samples; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; + + case ADC_RESOLUTION_13BIT: + /* Increase resolution by 1 bit */ + adjres = ADC_DIVIDE_RESULT_2; + accumulate = ADC_ACCUMULATE_SAMPLES_4; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; + + case ADC_RESOLUTION_14BIT: + /* Increase resolution by 2 bit */ + adjres = ADC_DIVIDE_RESULT_4; + accumulate = ADC_ACCUMULATE_SAMPLES_16; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; + case ADC_RESOLUTION_15BIT: + /* Increase resolution by 3 bit */ + adjres = ADC_DIVIDE_RESULT_2; + accumulate = ADC_ACCUMULATE_SAMPLES_64; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; + + case ADC_RESOLUTION_16BIT: + /* Increase resolution by 4 bit */ + adjres = ADC_DIVIDE_RESULT_DISABLE; + accumulate = ADC_ACCUMULATE_SAMPLES_256; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; + case ADC_RESOLUTION_8BIT: + /* 8-bit result register */ + resolution = ADC_RESOLUTION_8BIT; + break; + case ADC_RESOLUTION_10BIT: + /* 10-bit result register */ + resolution = ADC_RESOLUTION_10BIT; + break; + case ADC_RESOLUTION_12BIT: + /* 12-bit result register */ + resolution = ADC_RESOLUTION_12BIT; + break; + + default: + /* Unknown. Abort. */ + return STATUS_ERR_INVALID_ARG; + } + + adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Check validity of sample length value */ + if (config->sample_length > 63) { + return STATUS_ERR_INVALID_ARG; + } else { + /* Configure sample length */ + adc_module->SAMPCTRL.reg = + (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos) + | (config->sampling_time_compensation_enable << ADC_SAMPCTRL_OFFCOMP_Pos); + } + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure CTRLB */ + adc_module->CTRLB.reg = + config->clock_prescaler; + adc_module->CTRLC.reg = + resolution | + (config->correction.correction_enable << ADC_CTRLC_CORREN_Pos) | + (config->freerunning << ADC_CTRLC_FREERUN_Pos) | + (config->left_adjust << ADC_CTRLC_LEFTADJ_Pos) | + (config->differential_mode << ADC_CTRLC_DIFFMODE_Pos); + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Check validity of window thresholds */ + if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) { + switch (resolution) { + case ADC_RESOLUTION_8BIT: + if (config->differential_mode && + (config->window.window_lower_value > 127 || + config->window.window_lower_value < -128 || + config->window.window_upper_value > 127 || + config->window.window_upper_value < -128)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 255 || + config->window.window_upper_value > 255) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + case ADC_RESOLUTION_10BIT: + if (config->differential_mode && + (config->window.window_lower_value > 511 || + config->window.window_lower_value < -512 || + config->window.window_upper_value > 511 || + config->window.window_upper_value < -512)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 1023 || + config->window.window_upper_value > 1023) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + case ADC_RESOLUTION_12BIT: + if (config->differential_mode && + (config->window.window_lower_value > 2047 || + config->window.window_lower_value < -2048 || + config->window.window_upper_value > 2047 || + config->window.window_upper_value < -2048)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 4095 || + config->window.window_upper_value > 4095) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + case ADC_RESOLUTION_16BIT: + if (config->differential_mode && + (config->window.window_lower_value > 32767 || + config->window.window_lower_value < -32768 || + config->window.window_upper_value > 32767 || + config->window.window_upper_value < -32768)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 65535 || + config->window.window_upper_value > 65535) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + } + } + + /* Configure window mode */ + adc_module->CTRLC.reg |= config->window.window_mode; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure lower threshold */ + adc_module->WINLT.reg = + config->window.window_lower_value << ADC_WINLT_WINLT_Pos; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure lower threshold */ + adc_module->WINUT.reg = config->window.window_upper_value << + ADC_WINUT_WINUT_Pos; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure pin scan mode and positive and negative input pins */ + adc_module->INPUTCTRL.reg = + config->negative_input | + config->positive_input; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure events */ + adc_module->EVCTRL.reg = config->event_action; + + /* Disable all interrupts */ + adc_module->INTENCLR.reg = + (1 << ADC_INTENCLR_WINMON_Pos) |(1 << ADC_INTENCLR_OVERRUN_Pos) + | (1 << ADC_INTENCLR_RESRDY_Pos); + + if (config->correction.correction_enable) { + /* Make sure gain_correction value is valid */ + if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) { + return STATUS_ERR_INVALID_ARG; + } else { + /* Set gain correction value */ + adc_module->GAINCORR.reg = config->correction.gain_correction << + ADC_GAINCORR_GAINCORR_Pos; + } + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Make sure offset correction value is valid */ + if (config->correction.offset_correction > 2047 || + config->correction.offset_correction < -2048) { + return STATUS_ERR_INVALID_ARG; + } else { + /* Set offset correction value */ + adc_module->OFFSETCORR.reg = config->correction.offset_correction << + ADC_OFFSETCORR_OFFSETCORR_Pos; + } + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + } + + /* Load in the fixed device ADC calibration constants */ + adc_module->CALIB.reg = + ADC_CALIB_BIASREFBUF( + (*(uint32_t *)_adc_biasrefbuf_addr[index] >> _adc_biasrefbuf_pos[index]) + ) | + ADC_CALIB_BIASCOMP( + (*(uint32_t *)_adc_biascomp_addr[index] >> _adc_biascomp_pos[index]) + ); + + return STATUS_OK; +} + +/** + * \brief Initializes the ADC. + * + * Initializes the ADC device struct and the hardware module based on the + * given configuration struct values. + * + * \param[out] module_inst Pointer to the ADC software instance struct + * \param[in] hw Pointer to the ADC module instance + * \param[in] config Pointer to the configuration struct + * + * \return Status of the initialization procedure. + * \retval STATUS_OK The initialization was successful + * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided + * \retval STATUS_BUSY The module is busy with a reset operation + * \retval STATUS_ERR_DENIED The module is enabled + */ +enum status_code adc_init( + struct adc_module *const module_inst, + Adc *hw, + struct adc_config *config) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(hw); + Assert(config); + + /* Temporary variable to hold ADC instance number */ + uint8_t instance = _adc_get_inst_index(hw); + + /* Associate the software module instance with the hardware module */ + module_inst->hw = hw; + + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, _adc_apbcmasks[instance]); + + if (hw->CTRLA.reg & ADC_CTRLA_SWRST) { + /* We are in the middle of a reset. Abort. */ + return STATUS_BUSY; + } + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) { + /* Module must be disabled before initialization. Abort. */ + return STATUS_ERR_DENIED; + } + + /* Store the selected reference for later use */ + module_inst->reference = config->reference; + + /* Make sure the voltage reference is enabled if requested by the config */ + if (module_inst->reference == ADC_REFERENCE_INTREF) { + system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT); + } + +#if ADC_CALLBACK_MODE == true + for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) { + module_inst->callback[i] = NULL; + }; + + module_inst->registered_callback_mask = 0; + module_inst->enabled_callback_mask = 0; + module_inst->remaining_conversions = 0; + module_inst->job_status = STATUS_OK; + + _adc_instances[instance] = module_inst; + + if (config->event_action == ADC_EVENT_ACTION_DISABLED && + !config->freerunning) { + module_inst->software_trigger = true; + } else { + module_inst->software_trigger = false; + } +#endif + + /* Write configuration to module */ + return _adc_set_config(instance, module_inst, config); +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc_feature.h new file mode 100644 index 0000000000..2c146181cb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc_feature.h @@ -0,0 +1,726 @@ +/** + * \file + * + * \brief SAM ADC functionality + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef ADC_FEATURE_H_INCLUDED +#define ADC_FEATURE_H_INCLUDED + +/** + * \addtogroup asfdoc_sam0_adc_group + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*@{*/ +#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__) +/** Output Driver Strength Selection feature support. */ +# define FEATURE_ADC_SUPPORT_MASTER_SLAVE +#endif +/*@}*/ + +#if ADC_CALLBACK_MODE == true +# include + +#if !defined(__DOXYGEN__) +extern struct adc_module *_adc_instances[ADC_INST_NUM]; +#endif + +/** Forward definition of the device instance. */ +struct adc_module; + +/** Type of the callback functions. */ +typedef void (*adc_callback_t)(struct adc_module *const module); + +/** + * \brief ADC callback enum. + * + * Callback types for ADC callback driver. + * + */ +enum adc_callback { + /** Callback for buffer received */ + ADC_CALLBACK_READ_BUFFER, + /** Callback when window is hit */ + ADC_CALLBACK_WINDOW, + /** Callback for error */ + ADC_CALLBACK_ERROR, +# if !defined(__DOXYGEN__) + /** Number of available callbacks */ + ADC_CALLBACK_N, +# endif +}; + +#endif + +/** + * \brief ADC reference voltage enum. + * + * Enum for the possible reference voltages for the ADC. + * + */ +enum adc_reference { + /** Internal Bandgap Reference */ + ADC_REFERENCE_INTREF = ADC_REFCTRL_REFSEL_INTREF, + /** 1/1.48VCC reference */ + ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0, + /** 1/2VCC (only for internal VCC > 2.1V) */ + ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1, + /** External reference A */ + ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA, +#if (SAML21) + /** External reference B. */ + ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB, +#endif +#if (SAMC20) || (SAMC21) + /** DAC. */ + ADC_REFERENCE_DAC = ADC_REFCTRL_REFSEL_DAC, +#endif + /** VDDANA. */ + ADC_REFERENCE_INTVCC2 = ADC_REFCTRL_REFSEL_INTVCC2, +}; + +/** + * \brief ADC clock prescaler enum. + * + * Enum for the possible clock prescaler values for the ADC. + * + */ +enum adc_clock_prescaler { + /** ADC clock division factor 2 */ + ADC_CLOCK_PRESCALER_DIV2 = ADC_CTRLB_PRESCALER_DIV2, + /** ADC clock division factor 4 */ + ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4, + /** ADC clock division factor 8 */ + ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8, + /** ADC clock division factor 16 */ + ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16, + /** ADC clock division factor 32 */ + ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32, + /** ADC clock division factor 64 */ + ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64, + /** ADC clock division factor 128 */ + ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128, + /** ADC clock division factor 256 */ + ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256, +}; + +/** + * \brief ADC resolution enum. + * + * Enum for the possible resolution values for the ADC. + * + */ +enum adc_resolution { + /** ADC 12-bit resolution */ + ADC_RESOLUTION_12BIT = ADC_CTRLC_RESSEL_12BIT, + /** ADC 16-bit resolution using oversampling and decimation */ + ADC_RESOLUTION_16BIT = ADC_CTRLC_RESSEL_16BIT, + /** ADC 10-bit resolution */ + ADC_RESOLUTION_10BIT = ADC_CTRLC_RESSEL_10BIT, + /** ADC 8-bit resolution */ + ADC_RESOLUTION_8BIT = ADC_CTRLC_RESSEL_8BIT, + /** ADC 13-bit resolution using oversampling and decimation */ + ADC_RESOLUTION_13BIT, + /** ADC 14-bit resolution using oversampling and decimation */ + ADC_RESOLUTION_14BIT, + /** ADC 15-bit resolution using oversampling and decimation */ + ADC_RESOLUTION_15BIT, + /** ADC 16-bit result register for use with averaging. When using this mode + * the ADC result register will be set to 16-bit wide, and the number of + * samples to accumulate and the division factor is configured by the + * \ref adc_config.accumulate_samples and \ref adc_config.divide_result + * members in the configuration struct. + */ + ADC_RESOLUTION_CUSTOM, +}; + +/** + * \brief ADC window monitor mode enum. + * + * Enum for the possible window monitor modes for the ADC. + * + */ +enum adc_window_mode { + /** No window mode */ + ADC_WINDOW_MODE_DISABLE = ADC_CTRLC_WINMODE_DISABLE, + /** RESULT > WINLT */ + ADC_WINDOW_MODE_ABOVE_LOWER = ADC_CTRLC_WINMODE_MODE1, + /** RESULT < WINUT */ + ADC_WINDOW_MODE_BELOW_UPPER = ADC_CTRLC_WINMODE_MODE2, + /** WINLT < RESULT < WINUT */ + ADC_WINDOW_MODE_BETWEEN = ADC_CTRLC_WINMODE_MODE3, + /** !(WINLT < RESULT < WINUT) */ + ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_CTRLC_WINMODE_MODE4, +}; + +/** + * \brief ADC event action enum. + * + * Enum for the possible actions to take on an incoming event. + * + */ +enum adc_event_action { + /** Event action disabled */ + ADC_EVENT_ACTION_DISABLED = 0, + /** Flush ADC and start conversion */ + ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_FLUSHEI, + /** Start conversion */ + ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI, +}; + +/** + * \brief ADC positive MUX input selection enum. + * + * Enum for the possible positive MUX input selections for the ADC. + * + */ +enum adc_positive_input { + /** ADC0 pin */ + ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_AIN0, + /** ADC1 pin */ + ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_AIN1, + /** ADC2 pin */ + ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_AIN2, + /** ADC3 pin */ + ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_AIN3, + /** ADC4 pin */ + ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_AIN4, + /** ADC5 pin */ + ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_AIN5, + /** ADC6 pin */ + ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_AIN6, + /** ADC7 pin */ + ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_AIN7, + /** ADC8 pin */ + ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_AIN8, + /** ADC9 pin */ + ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_AIN9, + /** ADC10 pin */ + ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_AIN10, + /** ADC11 pin */ + ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_AIN11, +#if !(SAMC20) && !(SAMC21) + /** ADC12 pin. */ + ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_AIN12, + /** ADC13 pin */ + ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_AIN13, + /** ADC14 pin */ + ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_AIN14, + /** ADC15 pin */ + ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_AIN15, + /** ADC16 pin */ + ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_AIN16, + /** ADC17 pin */ + ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_AIN17, + /** ADC18 pin */ + ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_AIN18, + /** ADC19 pin */ + ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_AIN19, + /** ADC20 pin */ + ADC_POSITIVE_INPUT_PIN20 = ADC_INPUTCTRL_MUXPOS_AIN20, + /** ADC21 pin */ + ADC_POSITIVE_INPUT_PIN21 = ADC_INPUTCTRL_MUXPOS_AIN21, + /** ADC22 pin */ + ADC_POSITIVE_INPUT_PIN22 = ADC_INPUTCTRL_MUXPOS_AIN22, + /** ADC23 pin */ + ADC_POSITIVE_INPUT_PIN23 = ADC_INPUTCTRL_MUXPOS_AIN23, + /** Temperature reference */ + ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP, +#endif + /** Bandgap voltage. */ + ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, + /** 1/4 scaled core supply */ + ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, + /** 1/4 scaled I/O supply */ + ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, + /** DAC input */ + ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, +#if !(SAMC20) && !(SAMC21) + /** SCALEDVBAT. */ + ADC_POSITIVE_INPUT_SCALEDVBAT = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT, + /** OPAMP01 */ + ADC_POSITIVE_INPUT_OPAMP01 = ADC_INPUTCTRL_MUXPOS_OPAMP01, + /** OPAMP02 */ + ADC_POSITIVE_INPUT_OPAMP2 = ADC_INPUTCTRL_MUXPOS_OPAMP2, +#endif +}; + +/** + * \brief ADC negative MUX input selection enum. + * + * Enum for the possible negative MUX input selections for the ADC. + * + */ +enum adc_negative_input { + /** ADC0 pin */ + ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_AIN0, + /** ADC1 pin */ + ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_AIN1, + /** ADC2 pin */ + ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_AIN2, + /** ADC3 pin */ + ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_AIN3, + /** ADC4 pin */ + ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_AIN4, + /** ADC5 pin */ + ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_AIN5, +#if !(SAMC20) && !(SAMC21) + /** ADC6 pin. */ + ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_AIN6, + /** ADC7 pin */ + ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_AIN7, +#endif + /** Internal ground. */ + ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG(0x18u), +}; + +/** + * \brief ADC number of accumulated samples enum. + * + * Enum for the possible numbers of ADC samples to accumulate. + * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM + * resolution setting is used. + * + */ +enum adc_accumulate_samples { + /** No averaging */ + ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1, + /** Average 2 samples */ + ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2, + /** Average 4 samples */ + ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4, + /** Average 8 samples */ + ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8, + /** Average 16 samples */ + ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16, + /** Average 32 samples */ + ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32, + /** Average 64 samples */ + ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64, + /** Average 128 samples */ + ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128, + /** Average 256 samples */ + ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256, + /** Average 512 samples */ + ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512, + /** Average 1024 samples */ + ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024, +}; + +/** + * \brief ADC possible dividers for the result register. + * + * Enum for the possible division factors to use when accumulating + * multiple samples. To keep the same resolution for the averaged + * result and the actual input value, the division factor must + * be equal to the number of samples accumulated. This setting is only + * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used. + */ +enum adc_divide_result { + /** Don't divide result register after accumulation */ + ADC_DIVIDE_RESULT_DISABLE = 0, + /** Divide result register by 2 after accumulation */ + ADC_DIVIDE_RESULT_2 = 1, + /** Divide result register by 4 after accumulation */ + ADC_DIVIDE_RESULT_4 = 2, + /** Divide result register by 8 after accumulation */ + ADC_DIVIDE_RESULT_8 = 3, + /** Divide result register by 16 after accumulation */ + ADC_DIVIDE_RESULT_16 = 4, + /** Divide result register by 32 after accumulation */ + ADC_DIVIDE_RESULT_32 = 5, + /** Divide result register by 64 after accumulation */ + ADC_DIVIDE_RESULT_64 = 6, + /** Divide result register by 128 after accumulation */ + ADC_DIVIDE_RESULT_128 = 7, +}; + +#if ADC_CALLBACK_MODE == true +/** + * Enum for the possible ADC interrupt flags. + */ +enum adc_interrupt_flag { + /** ADC result ready */ + ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY, + /** Window monitor match */ + ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON, + /** ADC result overwritten before read */ + ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN, +}; +#endif + +/** + * \brief ADC oversampling and decimation enum. + * + * Enum for the possible numbers of bits resolution can be increased by when + * using oversampling and decimation. + * + */ +enum adc_oversampling_and_decimation { + /** Don't use oversampling and decimation mode */ + ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0, + /** 1 bit resolution increase */ + ADC_OVERSAMPLING_AND_DECIMATION_1BIT, + /** 2 bits resolution increase */ + ADC_OVERSAMPLING_AND_DECIMATION_2BIT, + /** 3 bits resolution increase */ + ADC_OVERSAMPLING_AND_DECIMATION_3BIT, + /** 4 bits resolution increase */ + ADC_OVERSAMPLING_AND_DECIMATION_4BIT +}; + +#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE +/** + * Enum for the trigger selection in dual mode. + */ +enum adc_dual_mode_trigger_selection { + /** Start event or software trigger will start a conversion on both ADCs. */ + ADC_DUAL_MODE_BOTH = ADC_CTRLC_DUALSEL_BOTH, + /** START event or software trigger will alternatingly start a conversion on ADC0 and ADC1. */ + ADC_DUAL_MODE_INTERLEAVE = ADC_CTRLC_DUALSEL_INTERLEAVE, +}; +#endif + +/** + * \brief Window monitor configuration structure. + * + * Window monitor configuration structure. + */ +struct adc_window_config { + /** Selected window mode */ + enum adc_window_mode window_mode; + /** Lower window value */ + int32_t window_lower_value; + /** Upper window value */ + int32_t window_upper_value; +}; + +/** + * \brief ADC event enable/disable structure. + * + * Event flags for the ADC module. This is used to enable and + * disable events via \ref adc_enable_events() and \ref adc_disable_events(). + */ +struct adc_events { + /** Enable event generation on conversion done */ + bool generate_event_on_conversion_done; + /** Enable event generation on window monitor */ + bool generate_event_on_window_monitor; +}; + +/** + * \brief Gain and offset correction configuration structure. + * + * Gain and offset correction configuration structure. + * Part of the \ref adc_config struct and will be initialized by + * \ref adc_get_config_defaults. + */ +struct adc_correction_config { + /** + * Enables correction for gain and offset based on values of gain_correction and + * offset_correction if set to true + */ + bool correction_enable; + /** + * This value defines how the ADC conversion result is compensated for gain + * error before written to the result register. This is a fractional value, + * 1-bit integer plus an 11-bit fraction, therefore + * 1/2 gain_correction < 2. Valid \c gain_correction values ranges from + * \c 0b010000000000 to \c 0b111111111111. + */ + uint16_t gain_correction; + /** + * This value defines how the ADC conversion result is compensated for + * offset error before written to the result register. This is a 12-bit + * value in two's complement format. + */ + int16_t offset_correction; +}; + +/** + * \brief ADC configuration structure. + * + * Configuration structure for an ADC instance. This structure should be + * initialized by the \ref adc_get_config_defaults() + * function before being modified by the user application. + */ +struct adc_config { + /** GCLK generator used to clock the peripheral */ + enum gclk_generator clock_source; + /** Voltage reference */ + enum adc_reference reference; + /** Clock prescaler */ + enum adc_clock_prescaler clock_prescaler; + /** Result resolution */ + enum adc_resolution resolution; + /** Positive MUX input */ + enum adc_positive_input positive_input; + /** Negative MUX input */ + enum adc_negative_input negative_input; + /** Number of ADC samples to accumulate when using the + * \c ADC_RESOLUTION_CUSTOM mode + */ + enum adc_accumulate_samples accumulate_samples; + /** Division ration when using the ADC_RESOLUTION_CUSTOM mode */ + enum adc_divide_result divide_result; + /** Left adjusted result */ + bool left_adjust; + /** Enables differential mode if true */ + bool differential_mode; + /** Enables free running mode if true */ + bool freerunning; + /** ADC run in standby control */ + bool run_in_standby; + /** ADC On demand control */ + bool on_demand; + /** + * Enables sampling period offset compensation if true + */ + bool sampling_time_compensation_enable; + /** + * Positive input enabled mask for conversion sequence. + * The sequence start from the lowest input, and go to the next enabled input + * automatically when the conversion is done. If no bits are set the + * sequence is disabled. + */ + uint32_t positive_input_sequence_mask_enable; + /** + * Enables reference buffer offset compensation if true. + * This will increase the accuracy of the gain stage, but decreases the input + * impedance; therefore the startup time of the reference must be increased. + */ + bool reference_compensation_enable; + /** + * This value (0-63) control the ADC sampling time in number of half ADC + * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus + * controlling the ADC input impedance. Sampling time is set according to + * the formula: + * Sample time = (sample_length+1) * (ADCclk / 2). + */ + uint8_t sample_length; + /** Window monitor configuration structure */ + struct adc_window_config window; + /** Gain and offset correction configuration structure */ + struct adc_correction_config correction; + /** Event action to take on incoming event */ + enum adc_event_action event_action; +}; + +/** + * \brief ADC software device instance structure. + * + * ADC software instance structure, used to retain software state information + * of an associated hardware module instance. + * + * \note The fields of this structure should not be altered by the user + * application; they are reserved for module-internal use only. + */ +struct adc_module { +#if !defined(__DOXYGEN__) + /** Pointer to ADC hardware module */ + Adc *hw; + /** Keep reference configuration so we know when enable is called */ + enum adc_reference reference; +# if ADC_CALLBACK_MODE == true + /** Array to store callback functions */ + adc_callback_t callback[ADC_CALLBACK_N]; + /** Pointer to buffer used for ADC results */ + volatile uint16_t *job_buffer; + /** Remaining number of conversions in current job */ + volatile uint16_t remaining_conversions; + /** Bit mask for callbacks registered */ + uint8_t registered_callback_mask; + /** Bit mask for callbacks enabled */ + uint8_t enabled_callback_mask; + /** Holds the status of the ongoing or last conversion job */ + volatile enum status_code job_status; + /** If software triggering is needed */ + bool software_trigger; +# endif +#endif +}; + +#if !defined(__DOXYGEN__) + +/** + * \brief Determines if the hardware module(s) are currently synchronizing to the bus. + * + * Checks to see if the underlying hardware peripheral module(s) are currently + * synchronizing across multiple clock domains to the hardware bus. This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * + * \param[in] module_inst Pointer to the ADC software instance struct + * + * \return Synchronization status of the underlying hardware module(s). + * + * \retval true if the module synchronization is ongoing + * \retval false if the module has completed synchronization + */ +static inline bool adc_is_syncing( + struct adc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + + Adc *const adc_module = module_inst->hw; + + if (adc_module->SYNCBUSY.reg) { + return true; + } + + return false; +} +#endif + +/** + * \name Positive Input Sequence + * @{ + */ + +/** + * \brief Enable positive input sequence mask for conversion. + * + * The sequence start from the lowest input, and go to the next enabled input + * automatically when the conversion is done. If no bits are set the + * sequence is disabled. + * + * \param[in] module_inst Pointer to the ADC software instance struct + * \param[in] eanble_seq_mask Sequence mask + */ +static inline void adc_enable_positive_input_sequence( + struct adc_module *const module_inst, + uint32_t positive_input_sequence_mask_enable) +{ + /* Sanity check arguments */ + Assert(module_inst); + + Adc *const adc_module = module_inst->hw; + adc_module->SEQCTRL.reg = positive_input_sequence_mask_enable; +} + +/** + * \brief Disable positive input in the sequence. + * + * Disable positive input in the sequence. + * + * \param[in] module_inst Pointer to the ADC software instance struct + */ +static inline void adc_disable_positive_input_sequence( + struct adc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + + Adc *const adc_module = module_inst->hw; + adc_module->SEQCTRL.reg = 0; +} + +/** + * \brief Get ADC sequence status. + * + * Check if a sequence is done and get last conversion done in the sequence. + * + * \param[in] module_inst Pointer to the ADC software instance struct + * \param[out] is_sequence_busy Sequence busy status + * \param[out] sequence_state This value identifies the last conversion + * done in the sequence + */ +static inline void adc_get_sequence_status( + struct adc_module *const module_inst, + bool * is_sequence_busy, + uint8_t *sequence_state) +{ + /* Sanity check arguments */ + Assert(module_inst); + uint8_t temp = false; + Adc *const adc_module = module_inst->hw; + temp = adc_module->SEQSTATUS.reg; + if(temp & ADC_SEQSTATUS_SEQBUSY) { + *is_sequence_busy = true; + } + *sequence_state = temp & ADC_SEQSTATUS_SEQSTATE_Msk; +} + +/** @} */ + +#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE +/** + * \brief Set ADC master and slave mode. + * + * Enable ADC module Master-Slave Operation and select dual mode trigger. + * + * \param[in] master_inst Pointer to the master ADC software instance struct + * \param[in] slave_inst Pointer to the slave ADC software instance struct + * \param[in] dualsel Dual mode trigger selection + * + */ +static inline void adc_set_master_slave_mode( + struct adc_module *const master_inst, + struct adc_module *const slave_inst, + enum adc_dual_mode_trigger_selection dualsel) +{ + /* Sanity check arguments */ + Assert(master_inst); + Assert(slave_inst); + + slave_inst->hw->CTRLA.reg |= ADC_CTRLA_SLAVEEN; + master_inst->hw->CTRLC.reg |= dualsel; + +}; +#endif +/** @} */ + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* ADC_FEATURE_H_INCLUDED */ + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc.c new file mode 100644 index 0000000000..94330712a3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc.c @@ -0,0 +1,704 @@ +/** + * \file + * + * \brief SAM Peripheral Analog-to-Digital Converter Driver + * + * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "adc.h" + +#if SAMD20 +/* The Die revision D number */ +#define REVISON_D_NUM 3 +#endif + +/** + * \brief Initializes an ADC configuration structure to defaults + * + * Initializes a given ADC configuration struct to a set of known default + * values. This function should be called on any new instance of the + * configuration struct before being modified by the user application. + * + * The default configuration is as follows: + * \li GCLK generator 0 (GCLK main) clock source + * \li 1V from internal bandgap reference + * \li Div 4 clock prescaler + * \li 12-bit resolution + * \li Window monitor disabled + * \li No gain + * \li Positive input on ADC PIN 0 + * \li Negative input on ADC PIN 1 + * \li Averaging disabled + * \li Oversampling disabled + * \li Right adjust data + * \li Single-ended mode + * \li Free running disabled + * \li All events (input and generation) disabled + * \li Sleep operation disabled + * \li No reference compensation + * \li No gain/offset correction + * \li No added sampling time + * \li Pin scan mode disabled + * + * \param[out] config Pointer to configuration struct to initialize to + * default values + */ +void adc_get_config_defaults(struct adc_config *const config) +{ + Assert(config); + config->clock_source = GCLK_GENERATOR_0; + config->reference = ADC_REFERENCE_INT1V; + config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4; + config->resolution = ADC_RESOLUTION_12BIT; + config->window.window_mode = ADC_WINDOW_MODE_DISABLE; + config->window.window_upper_value = 0; + config->window.window_lower_value = 0; + config->gain_factor = ADC_GAIN_FACTOR_1X; +#if SAMR21 + config->positive_input = ADC_POSITIVE_INPUT_PIN6 ; +#else + config->positive_input = ADC_POSITIVE_INPUT_PIN0 ; +#endif + config->negative_input = ADC_NEGATIVE_INPUT_GND ; + config->accumulate_samples = ADC_ACCUMULATE_DISABLE; + config->divide_result = ADC_DIVIDE_RESULT_DISABLE; + config->left_adjust = false; + config->differential_mode = false; + config->freerunning = false; + config->event_action = ADC_EVENT_ACTION_DISABLED; + config->run_in_standby = false; + config->reference_compensation_enable = false; + config->correction.correction_enable = false; + config->correction.gain_correction = ADC_GAINCORR_RESETVALUE; + config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE; + config->sample_length = 0; + config->pin_scan.offset_start_scan = 0; + config->pin_scan.inputs_to_scan = 0; +} + +/** + * \brief Sets the ADC window mode + * + * Sets the ADC window mode to a given mode and value range. + * + * \param[in] module_inst Pointer to the ADC software instance struct + * \param[in] window_mode Window monitor mode to set + * \param[in] window_lower_value Lower window monitor threshold value + * \param[in] window_upper_value Upper window monitor threshold value + */ +void adc_set_window_mode( + struct adc_module *const module_inst, + const enum adc_window_mode window_mode, + const int16_t window_lower_value, + const int16_t window_upper_value) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Adc *const adc_module = module_inst->hw; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Set window mode */ + adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Set lower window monitor threshold value */ + adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Set upper window monitor threshold value */ + adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos; +} + +/** +* \internal Configure MUX settings for the analog pins +* +* This function will set the given ADC input pins +* to the analog function in the pinmux, giving +* the ADC access to the analog signal +* +* \param [in] pin AINxx pin to configure +*/ +static inline void _adc_configure_ain_pin(uint32_t pin) +{ +#define PIN_INVALID_ADC_AIN 0xFFFFUL + + /* Pinmapping table for AINxx -> GPIO pin number */ + const uint32_t pinmapping[] = { +#if (SAMD20E) || (SAMD21E)|| (SAMDA1E) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, +#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, +#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, + PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, +#elif SAMR21E + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +#elif SAMR21G + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, + PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +#elif (SAMD10C) || (SAMD11C) + PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +#elif (SAMD10DS) || (SAMD11DS) + PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, + PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, + PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, + PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +#elif (SAMD10DM) || (SAMD11DM) + PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, + PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, + PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, + PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, + PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, + PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, +#else +# error ADC pin mappings are not defined for this device. +#endif + }; + + uint32_t pin_map_result = PIN_INVALID_ADC_AIN; + + if (pin <= ADC_EXTCHANNEL_MSB) { + pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos]; + + Assert(pin_map_result != PIN_INVALID_ADC_AIN); + + struct system_pinmux_config config; + system_pinmux_get_config_defaults(&config); + + /* Analog functions are all on MUX setting B */ + config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; + config.mux_position = 1; + + system_pinmux_pin_set_config(pin_map_result, &config); + } +} + +/** + * \internal Writes an ADC configuration to the hardware module + * + * Writes out a given ADC module configuration to the hardware module. + * + * \param[out] module_inst Pointer to the ADC software instance struct + * \param[in] config Pointer to configuration struct + * + * \return Status of the configuration procedure + * \retval STATUS_OK The configuration was successful + * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided + */ +static enum status_code _adc_set_config( + struct adc_module *const module_inst, + struct adc_config *const config) +{ + uint8_t adjres = 0; + uint32_t resolution = ADC_RESOLUTION_16BIT; + enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE; +#if SAMD20 + uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos); +#endif + + /* Get the hardware module pointer */ + Adc *const adc_module = module_inst->hw; + + /* Configure GCLK channel and enable clock */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = config->clock_source; + system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf); + system_gclk_chan_enable(ADC_GCLK_ID); + + /* Setup pinmuxing for analog inputs */ + if (config->pin_scan.inputs_to_scan != 0) { + uint8_t offset = config->pin_scan.offset_start_scan; + uint8_t start_pin = + offset +(uint8_t)config->positive_input; + uint8_t end_pin = + start_pin + config->pin_scan.inputs_to_scan; + + while (start_pin < end_pin) { + _adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input); + start_pin++; + offset++; + } + _adc_configure_ain_pin(config->negative_input); + } else { + _adc_configure_ain_pin(config->positive_input); + _adc_configure_ain_pin(config->negative_input); + } + + /* Configure run in standby */ + adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos); + + /* Configure reference */ + adc_module->REFCTRL.reg = + (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) | + (config->reference); + + /* Set adjusting result and number of samples */ + switch (config->resolution) { + + case ADC_RESOLUTION_CUSTOM: + adjres = config->divide_result; + accumulate = config->accumulate_samples; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; + + case ADC_RESOLUTION_13BIT: + /* Increase resolution by 1 bit */ + adjres = ADC_DIVIDE_RESULT_2; + accumulate = ADC_ACCUMULATE_SAMPLES_4; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; + + case ADC_RESOLUTION_14BIT: + /* Increase resolution by 2 bit */ + adjres = ADC_DIVIDE_RESULT_4; + accumulate = ADC_ACCUMULATE_SAMPLES_16; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; +#if SAMD20 + /* See $35.1.8 for ADC errata of SAM D20. + The revisions before D have this issue.*/ + case ADC_RESOLUTION_15BIT: + /* Increase resolution by 3 bit */ + if(revision_num < REVISON_D_NUM) { + adjres = ADC_DIVIDE_RESULT_8; + } else { + adjres = ADC_DIVIDE_RESULT_2; + } + accumulate = ADC_ACCUMULATE_SAMPLES_64; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; + + case ADC_RESOLUTION_16BIT: + if(revision_num < REVISON_D_NUM) { + /* Increase resolution by 4 bit */ + adjres = ADC_DIVIDE_RESULT_16; + } else { + adjres = ADC_DIVIDE_RESULT_DISABLE; + } + accumulate = ADC_ACCUMULATE_SAMPLES_256; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; +#else + case ADC_RESOLUTION_15BIT: + /* Increase resolution by 3 bit */ + adjres = ADC_DIVIDE_RESULT_2; + accumulate = ADC_ACCUMULATE_SAMPLES_64; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; + + case ADC_RESOLUTION_16BIT: + /* Increase resolution by 4 bit */ + adjres = ADC_DIVIDE_RESULT_DISABLE; + accumulate = ADC_ACCUMULATE_SAMPLES_256; + /* 16-bit result register */ + resolution = ADC_RESOLUTION_16BIT; + break; +#endif + case ADC_RESOLUTION_8BIT: + /* 8-bit result register */ + resolution = ADC_RESOLUTION_8BIT; + break; + case ADC_RESOLUTION_10BIT: + /* 10-bit result register */ + resolution = ADC_RESOLUTION_10BIT; + break; + case ADC_RESOLUTION_12BIT: + /* 12-bit result register */ + resolution = ADC_RESOLUTION_12BIT; + break; + + default: + /* Unknown. Abort. */ + return STATUS_ERR_INVALID_ARG; + } + + adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate; + + /* Check validity of sample length value */ + if (config->sample_length > 63) { + return STATUS_ERR_INVALID_ARG; + } else { + /* Configure sample length */ + adc_module->SAMPCTRL.reg = + (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos); + } + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure CTRLB */ + adc_module->CTRLB.reg = + config->clock_prescaler | + resolution | + (config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) | + (config->freerunning << ADC_CTRLB_FREERUN_Pos) | + (config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) | + (config->differential_mode << ADC_CTRLB_DIFFMODE_Pos); + + /* Check validity of window thresholds */ + if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) { + switch (resolution) { + case ADC_RESOLUTION_8BIT: + if (config->differential_mode && + (config->window.window_lower_value > 127 || + config->window.window_lower_value < -128 || + config->window.window_upper_value > 127 || + config->window.window_upper_value < -128)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 255 || + config->window.window_upper_value > 255) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + case ADC_RESOLUTION_10BIT: + if (config->differential_mode && + (config->window.window_lower_value > 511 || + config->window.window_lower_value < -512 || + config->window.window_upper_value > 511 || + config->window.window_upper_value < -512)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 1023 || + config->window.window_upper_value > 1023) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + case ADC_RESOLUTION_12BIT: + if (config->differential_mode && + (config->window.window_lower_value > 2047 || + config->window.window_lower_value < -2048 || + config->window.window_upper_value > 2047 || + config->window.window_upper_value < -2048)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 4095 || + config->window.window_upper_value > 4095) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + case ADC_RESOLUTION_16BIT: + if (config->differential_mode && + (config->window.window_lower_value > 32767 || + config->window.window_lower_value < -32768 || + config->window.window_upper_value > 32767 || + config->window.window_upper_value < -32768)) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } else if (config->window.window_lower_value > 65535 || + config->window.window_upper_value > 65535) { + /* Invalid value */ + return STATUS_ERR_INVALID_ARG; + } + break; + } + } + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure window mode */ + adc_module->WINCTRL.reg = config->window.window_mode; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure lower threshold */ + adc_module->WINLT.reg = + config->window.window_lower_value << ADC_WINLT_WINLT_Pos; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure lower threshold */ + adc_module->WINUT.reg = config->window.window_upper_value << + ADC_WINUT_WINUT_Pos; + + uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan; + if (inputs_to_scan > 0) { + /* + * Number of input sources included is the value written to INPUTSCAN + * plus 1. + */ + inputs_to_scan--; + } + + if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || + config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { + /* Invalid number of input pins or input offset */ + return STATUS_ERR_INVALID_ARG; + } + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Configure pin scan mode and positive and negative input pins */ + adc_module->INPUTCTRL.reg = + config->gain_factor | + (config->pin_scan.offset_start_scan << + ADC_INPUTCTRL_INPUTOFFSET_Pos) | + (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) | + config->negative_input | + config->positive_input; + + /* Configure events */ + adc_module->EVCTRL.reg = config->event_action; + + /* Disable all interrupts */ + adc_module->INTENCLR.reg = + (1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) | + (1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos); + + if (config->correction.correction_enable) { + /* Make sure gain_correction value is valid */ + if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) { + return STATUS_ERR_INVALID_ARG; + } else { + /* Set gain correction value */ + adc_module->GAINCORR.reg = config->correction.gain_correction << + ADC_GAINCORR_GAINCORR_Pos; + } + + /* Make sure offset correction value is valid */ + if (config->correction.offset_correction > 2047 || + config->correction.offset_correction < -2048) { + return STATUS_ERR_INVALID_ARG; + } else { + /* Set offset correction value */ + adc_module->OFFSETCORR.reg = config->correction.offset_correction << + ADC_OFFSETCORR_OFFSETCORR_Pos; + } + } + + /* Load in the fixed device ADC calibration constants */ + adc_module->CALIB.reg = + ADC_CALIB_BIAS_CAL( + (*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos) + ) | + ADC_CALIB_LINEARITY_CAL( + (*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos) + ); + + return STATUS_OK; +} + +/** + * \brief Initializes the ADC channel sequence + * + * Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one + * automatically after a conversion done, causing the next conversion + * to be done with the positive input equal to MUXPOS + INPUTOFFSET, + * it is scanning continuously one by one even ADC channels are not continuous. + * + * Initializes the ADC channel sequence by the sequence of pin_array. + * + * \param[in] pin_array The array of the Mux selection for the positive ADC input + * \param[in] size The size of pin_array + */ +void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size) +{ + for (int i = 0; i < size; i++) { + _adc_configure_ain_pin(pin_array[i]); + } +} + +/** + * \brief Initializes the ADC + * + * Initializes the ADC device struct and the hardware module based on the + * given configuration struct values. + * + * \param[out] module_inst Pointer to the ADC software instance struct + * \param[in] hw Pointer to the ADC module instance + * \param[in] config Pointer to the configuration struct + * + * \return Status of the initialization procedure. + * \retval STATUS_OK The initialization was successful + * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided + * \retval STATUS_BUSY The module is busy with a reset operation + * \retval STATUS_ERR_DENIED The module is enabled + */ +enum status_code adc_init( + struct adc_module *const module_inst, + Adc *hw, + struct adc_config *config) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(hw); + Assert(config); + + /* Associate the software module instance with the hardware module */ + module_inst->hw = hw; + + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC); + + if (hw->CTRLA.reg & ADC_CTRLA_SWRST) { + /* We are in the middle of a reset. Abort. */ + return STATUS_BUSY; + } + + if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) { + /* Module must be disabled before initialization. Abort. */ + return STATUS_ERR_DENIED; + } + + /* Store the selected reference for later use */ + module_inst->reference = config->reference; + + /* Make sure bandgap is enabled if requested by the config */ + if (module_inst->reference == ADC_REFERENCE_INT1V) { + system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP); + } + +#if ADC_CALLBACK_MODE == true + for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) { + module_inst->callback[i] = NULL; + }; + + module_inst->registered_callback_mask = 0; + module_inst->enabled_callback_mask = 0; + module_inst->remaining_conversions = 0; + module_inst->job_status = STATUS_OK; + + _adc_instances[0] = module_inst; + + if (config->event_action == ADC_EVENT_ACTION_DISABLED && + !config->freerunning) { + module_inst->software_trigger = true; + } else { + module_inst->software_trigger = false; + } +#endif + + /* Write configuration to module */ + return _adc_set_config(module_inst, config); +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc_feature.h new file mode 100644 index 0000000000..abd7b12ce8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc_feature.h @@ -0,0 +1,728 @@ +/** + * \file + * + * \brief SAM ADC functionality + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef ADC_FEATURE_H_INCLUDED +#define ADC_FEATURE_H_INCLUDED + +/** + * \addtogroup asfdoc_sam0_adc_group + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if ADC_CALLBACK_MODE == true +# include + +#if !defined(__DOXYGEN__) +extern struct adc_module *_adc_instances[ADC_INST_NUM]; +#endif + +/** Forward definition of the device instance. */ +struct adc_module; + +/** Type of the callback functions. */ +typedef void (*adc_callback_t)(struct adc_module *const module); + +/** + * \brief ADC Callback enum + * + * Callback types for ADC callback driver. + * + */ +enum adc_callback { + /** Callback for buffer received. */ + ADC_CALLBACK_READ_BUFFER, + /** Callback when window is hit. */ + ADC_CALLBACK_WINDOW, + /** Callback for error. */ + ADC_CALLBACK_ERROR, +# if !defined(__DOXYGEN__) + /** Number of available callbacks. */ + ADC_CALLBACK_N, +# endif +}; + +#endif + +/** + * \brief ADC reference voltage enum + * + * Enum for the possible reference voltages for the ADC. + * + */ +enum adc_reference { + /** 1.0V voltage reference. */ + ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V, + /** 1/1.48VCC reference. */ + ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0, + /** 1/2VCC (only for internal VCC > 2.1V). */ + ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1, + /** External reference A. */ + ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA, + /** External reference B. */ + ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB, +}; + +/** + * \brief ADC clock prescaler enum + * + * Enum for the possible clock prescaler values for the ADC. + * + */ +enum adc_clock_prescaler { + /** ADC clock division factor 4. */ + ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4, + /** ADC clock division factor 8. */ + ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8, + /** ADC clock division factor 16. */ + ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16, + /** ADC clock division factor 32. */ + ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32, + /** ADC clock division factor 64. */ + ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64, + /** ADC clock division factor 128. */ + ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128, + /** ADC clock division factor 256. */ + ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256, + /** ADC clock division factor 512. */ + ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512, +}; + +/** + * \brief ADC resolution enum + * + * Enum for the possible resolution values for the ADC. + * + */ +enum adc_resolution { + /** ADC 12-bit resolution. */ + ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT, + /** ADC 16-bit resolution using oversampling and decimation. */ + ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT, + /** ADC 10-bit resolution. */ + ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT, + /** ADC 8-bit resolution. */ + ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT, + /** ADC 13-bit resolution using oversampling and decimation. */ + ADC_RESOLUTION_13BIT, + /** ADC 14-bit resolution using oversampling and decimation. */ + ADC_RESOLUTION_14BIT, + /** ADC 15-bit resolution using oversampling and decimation. */ + ADC_RESOLUTION_15BIT, + /** ADC 16-bit result register for use with averaging. When using this mode + * the ADC result register will be set to 16-bit wide, and the number of + * samples to accumulate and the division factor is configured by the + * \ref adc_config.accumulate_samples and \ref adc_config.divide_result + * members in the configuration struct. + */ + ADC_RESOLUTION_CUSTOM, +}; + +/** + * \brief ADC window monitor mode enum + * + * Enum for the possible window monitor modes for the ADC. + * + */ +enum adc_window_mode { + /** No window mode. */ + ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE, + /** RESULT > WINLT. */ + ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1, + /** RESULT < WINUT. */ + ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2, + /** WINLT < RESULT < WINUT. */ + ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3, + /** !(WINLT < RESULT < WINUT). */ + ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4, +}; + +/** + * \brief ADC gain factor selection enum + * + * Enum for the possible gain factor values for the ADC. + * + */ +enum adc_gain_factor { + /** 1x gain. */ + ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X, + /** 2x gain. */ + ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X, + /** 4x gain. */ + ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X, + /** 8x gain. */ + ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X, + /** 16x gain. */ + ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X, + /** 1/2x gain. */ + ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2, +}; + +/** + * \brief ADC event action enum + * + * Enum for the possible actions to take on an incoming event. + * + */ +enum adc_event_action { + /** Event action disabled. */ + ADC_EVENT_ACTION_DISABLED = 0, + /** Flush ADC and start conversion. */ + ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI, + /** Start conversion. */ + ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI, +}; + +/** + * \brief ADC positive MUX input selection enum + * + * Enum for the possible positive MUX input selections for the ADC. + * + */ +enum adc_positive_input { + /** ADC0 pin. */ + ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0, + /** ADC1 pin. */ + ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1, + /** ADC2 pin. */ + ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2, + /** ADC3 pin. */ + ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3, + /** ADC4 pin. */ + ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4, + /** ADC5 pin. */ + ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5, + /** ADC6 pin. */ + ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6, + /** ADC7 pin. */ + ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7, + /** ADC8 pin. */ + ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8, + /** ADC9 pin. */ + ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9, + /** ADC10 pin. */ + ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10, + /** ADC11 pin. */ + ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11, + /** ADC12 pin. */ + ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12, + /** ADC13 pin. */ + ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13, + /** ADC14 pin. */ + ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14, + /** ADC15 pin. */ + ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15, + /** ADC16 pin. */ + ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16, + /** ADC17 pin. */ + ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17, + /** ADC18 pin. */ + ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18, + /** ADC19 pin. */ + ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19, + /** Temperature reference. */ + ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP, + /** Bandgap voltage. */ + ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, + /** 1/4 scaled core supply. */ + ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, + /** 1/4 scaled I/O supply. */ + ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, + /** DAC input. */ + ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, +}; + +/** + * \brief ADC negative MUX input selection enum + * + * Enum for the possible negative MUX input selections for the ADC. + * + */ +enum adc_negative_input { + /** ADC0 pin. */ + ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0, + /** ADC1 pin. */ + ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1, + /** ADC2 pin. */ + ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2, + /** ADC3 pin. */ + ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3, + /** ADC4 pin. */ + ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4, + /** ADC5 pin. */ + ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5, + /** ADC6 pin. */ + ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6, + /** ADC7 pin. */ + ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7, + /** Internal ground. */ + ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, + /** I/O ground. */ + ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND, +}; + +/** + * \brief ADC number of accumulated samples enum + * + * Enum for the possible numbers of ADC samples to accumulate. + * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM + * resolution setting is used. + * + */ +enum adc_accumulate_samples { + /** No averaging. */ + ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1, + /** Average 2 samples. */ + ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2, + /** Average 4 samples. */ + ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4, + /** Average 8 samples. */ + ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8, + /** Average 16 samples. */ + ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16, + /** Average 32 samples. */ + ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32, + /** Average 64 samples. */ + ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64, + /** Average 128 samples. */ + ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128, + /** Average 256 samples. */ + ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256, + /** Average 512 samples. */ + ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512, + /** Average 1024 samples. */ + ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024, +}; + +/** + * \brief ADC possible dividers for the result register + * + * Enum for the possible division factors to use when accumulating + * multiple samples. To keep the same resolution for the averaged + * result and the actual input value, the division factor must + * be equal to the number of samples accumulated. This setting is only + * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used. + */ +enum adc_divide_result { + /** Don't divide result register after accumulation. */ + ADC_DIVIDE_RESULT_DISABLE = 0, + /** Divide result register by 2 after accumulation. */ + ADC_DIVIDE_RESULT_2 = 1, + /** Divide result register by 4 after accumulation. */ + ADC_DIVIDE_RESULT_4 = 2, + /** Divide result register by 8 after accumulation. */ + ADC_DIVIDE_RESULT_8 = 3, + /** Divide result register by 16 after accumulation. */ + ADC_DIVIDE_RESULT_16 = 4, + /** Divide result register by 32 after accumulation. */ + ADC_DIVIDE_RESULT_32 = 5, + /** Divide result register by 64 after accumulation. */ + ADC_DIVIDE_RESULT_64 = 6, + /** Divide result register by 128 after accumulation. */ + ADC_DIVIDE_RESULT_128 = 7, +}; + +#if ADC_CALLBACK_MODE == true +/** + * Enum for the possible ADC interrupt flags. + */ +enum adc_interrupt_flag { + /** ADC result ready. */ + ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY, + /** Window monitor match. */ + ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON, + /** ADC result overwritten before read. */ + ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN, +}; +#endif + +/** + * \brief ADC oversampling and decimation enum + * + * Enum for the possible numbers of bits resolution can be increased by when + * using oversampling and decimation. + * + */ +enum adc_oversampling_and_decimation { + /** Don't use oversampling and decimation mode. */ + ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0, + /** 1 bit resolution increase. */ + ADC_OVERSAMPLING_AND_DECIMATION_1BIT, + /** 2 bits resolution increase. */ + ADC_OVERSAMPLING_AND_DECIMATION_2BIT, + /** 3 bits resolution increase. */ + ADC_OVERSAMPLING_AND_DECIMATION_3BIT, + /** 4 bits resolution increase. */ + ADC_OVERSAMPLING_AND_DECIMATION_4BIT +}; + +/** + * \brief Window monitor configuration structure + * + * Window monitor configuration structure. + */ +struct adc_window_config { + /** Selected window mode. */ + enum adc_window_mode window_mode; + /** Lower window value. */ + int32_t window_lower_value; + /** Upper window value. */ + int32_t window_upper_value; +}; + +/** + * \brief ADC event enable/disable structure. + * + * Event flags for the ADC module. This is used to enable and + * disable events via \ref adc_enable_events() and \ref adc_disable_events(). + */ +struct adc_events { + /** Enable event generation on conversion done. */ + bool generate_event_on_conversion_done; + /** Enable event generation on window monitor. */ + bool generate_event_on_window_monitor; +}; + +/** + * \brief Gain and offset correction configuration structure + * + * Gain and offset correction configuration structure. + * Part of the \ref adc_config struct and will be initialized by + * \ref adc_get_config_defaults. + */ +struct adc_correction_config { + /** + * Enables correction for gain and offset based on values of gain_correction and + * offset_correction if set to true. + */ + bool correction_enable; + /** + * This value defines how the ADC conversion result is compensated for gain + * error before written to the result register. This is a fractional value, + * 1-bit integer plus an 11-bit fraction, therefore + * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from + * \c 0b010000000000 to \c 0b111111111111. + */ + uint16_t gain_correction; + /** + * This value defines how the ADC conversion result is compensated for + * offset error before written to the result register. This is a 12-bit + * value in two's complement format. + */ + int16_t offset_correction; +}; + +/** + * \brief Pin scan configuration structure + * + * Pin scan configuration structure. Part of the \ref adc_config struct and will + * be initialized by \ref adc_get_config_defaults. + */ +struct adc_pin_scan_config { + /** + * Offset (relative to selected positive input) of the first input pin to be + * used in pin scan mode. + */ + uint8_t offset_start_scan; + /** + * Number of input pins to scan in pin scan mode. A value below two will + * disable pin scan mode. + */ + uint8_t inputs_to_scan; +}; + +/** + * \brief ADC configuration structure + * + * Configuration structure for an ADC instance. This structure should be + * initialized by the \ref adc_get_config_defaults() + * function before being modified by the user application. + */ +struct adc_config { + /** GCLK generator used to clock the peripheral. */ + enum gclk_generator clock_source; + /** Voltage reference. */ + enum adc_reference reference; + /** Clock prescaler. */ + enum adc_clock_prescaler clock_prescaler; + /** Result resolution. */ + enum adc_resolution resolution; + /** Gain factor. */ + enum adc_gain_factor gain_factor; + /** Positive MUX input. */ + enum adc_positive_input positive_input; + /** Negative MUX input. For singled-ended conversion mode, the negative + * input must be connected to ground. This ground could be the internal + * GND, IOGND or an external ground connected to a pin. */ + enum adc_negative_input negative_input; + /** Number of ADC samples to accumulate when using the + * \c ADC_RESOLUTION_CUSTOM mode.Note: if the result width increases, + * result resolution will be changed accordingly. + */ + enum adc_accumulate_samples accumulate_samples; + /** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */ + enum adc_divide_result divide_result; + /** Left adjusted result. */ + bool left_adjust; + /** Enables differential mode if true. + * if false, ADC will run in singled-ended mode. */ + bool differential_mode; + /** Enables free running mode if true. */ + bool freerunning; + /** Enables ADC in standby sleep mode if true. */ + bool run_in_standby; + /** + * Enables reference buffer offset compensation if true. + * This will increase the accuracy of the gain stage, but decreases the input + * impedance; therefore the startup time of the reference must be increased. + */ + bool reference_compensation_enable; + /** + * This value (0-63) control the ADC sampling time in number of half ADC + * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus + * controlling the ADC input impedance. Sampling time is set according to + * the formula: + * Sample time = (sample_length+1) * (ADCclk / 2). + */ + uint8_t sample_length; + /** Window monitor configuration structure. */ + struct adc_window_config window; + /** Gain and offset correction configuration structure. */ + struct adc_correction_config correction; + /** Event action to take on incoming event. */ + enum adc_event_action event_action; + /** Pin scan configuration structure. */ + struct adc_pin_scan_config pin_scan; +}; + +/** + * \brief ADC software device instance structure. + * + * ADC software instance structure, used to retain software state information + * of an associated hardware module instance. + * + * \note The fields of this structure should not be altered by the user + * application; they are reserved for module-internal use only. + */ +struct adc_module { +#if !defined(__DOXYGEN__) + /** Pointer to ADC hardware module. */ + Adc *hw; + /** Keep reference configuration so we know when enable is called. */ + enum adc_reference reference; +# if ADC_CALLBACK_MODE == true + /** Array to store callback functions. */ + adc_callback_t callback[ADC_CALLBACK_N]; + /** Pointer to buffer used for ADC results. */ + volatile uint16_t *job_buffer; + /** Remaining number of conversions in current job. */ + volatile uint16_t remaining_conversions; + /** Bit mask for callbacks registered. */ + uint8_t registered_callback_mask; + /** Bit mask for callbacks enabled. */ + uint8_t enabled_callback_mask; + /** Holds the status of the ongoing or last conversion job. */ + volatile enum status_code job_status; + /** If software triggering is needed. */ + bool software_trigger; +# endif +#endif +}; + +#if !defined(__DOXYGEN__) + +/** + * \brief Determines if the hardware module(s) are currently synchronizing to the bus. + * + * Checks to see if the underlying hardware peripheral module(s) are currently + * synchronizing across multiple clock domains to the hardware bus. This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * + * \param[in] module_inst Pointer to the ADC software instance struct + * + * \return Synchronization status of the underlying hardware module(s). + * + * \retval true if the module synchronization is ongoing + * \retval false if the module has completed synchronization + */ +static inline bool adc_is_syncing( + struct adc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + + Adc *const adc_module = module_inst->hw; + + if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) { + return true; + } + + return false; +} +#endif + +/** + * \name ADC Gain and Pin Scan Mode + * @{ + */ + +/** + * \brief Sets ADC gain factor + * + * Sets the ADC gain factor to a specified gain setting. + * + * \param[in] module_inst Pointer to the ADC software instance struct + * \param[in] gain_factor Gain factor value to set + */ +static inline void adc_set_gain( + struct adc_module *const module_inst, + const enum adc_gain_factor gain_factor) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Adc *const adc_module = module_inst->hw; + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Set new gain factor */ + adc_module->INPUTCTRL.reg = + (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) | + (gain_factor); +} + +/** + * \brief Sets the ADC pin scan mode + * + * Configures the pin scan mode of the ADC module. In pin scan mode, the first + * conversion will start at the configured positive input + start_offset. When + * a conversion is done, a conversion will start on the next input, until + * \c inputs_to_scan number of conversions are made. + * + * \param[in] module_inst Pointer to the ADC software instance struct + * \param[in] inputs_to_scan Number of input pins to perform a conversion on + * (must be two or more) + * \param[in] start_offset Offset of first pin to scan (relative to + * configured positive input) + * + * \return Status of the pin scan configuration set request. + * + * \retval STATUS_OK Pin scan mode has been set successfully + * \retval STATUS_ERR_INVALID_ARG Number of input pins to scan or offset has + * an invalid value + */ +static inline enum status_code adc_set_pin_scan_mode( + struct adc_module *const module_inst, + uint8_t inputs_to_scan, + const uint8_t start_offset) + +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Adc *const adc_module = module_inst->hw; + + if (inputs_to_scan > 0) { + /* + * Number of input sources included is the value written to INPUTSCAN + * plus 1. + */ + inputs_to_scan--; + } + + if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || + start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { + /* Invalid number of input pins */ + return STATUS_ERR_INVALID_ARG; + } + + while (adc_is_syncing(module_inst)) { + /* Wait for synchronization */ + } + + /* Set pin scan mode */ + adc_module->INPUTCTRL.reg = + (adc_module->INPUTCTRL.reg & + ~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) | + (start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) | + (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos); + + return STATUS_OK; +} + +/** + * \brief Disables pin scan mode + * + * Disables pin scan mode. The next conversion will be made on only one pin + * (the configured positive input pin). + * + * \param[in] module_inst Pointer to the ADC software instance struct + */ +static inline void adc_disable_pin_scan_mode( + struct adc_module *const module_inst) +{ + /* Disable pin scan mode */ + adc_set_pin_scan_mode(module_inst, 0, 0); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* ADC_FEATURE_H_INCLUDED */ + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/adc/adc.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/adc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/adc/adc.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/adc.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/TARGET_SAMD21/dac/dac_sam_d_c/dac.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/TARGET_SAMD21/dac/dac_sam_d_c/dac.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/TARGET_SAMD21/dac/dac_sam_d_c/dac_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac_feature.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/TARGET_SAMD21/dac/dac_sam_d_c/dac_feature.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac_feature.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac.c new file mode 100644 index 0000000000..05d5ed2a12 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac.c @@ -0,0 +1,790 @@ +/** + * \file + * + * \brief SAM Peripheral Digital-to-Analog Converter Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include "dac.h" +#include +#include + +/** + * \internal Writes a DAC configuration to the hardware module. + * + * Writes out a given configuration to the hardware module. + * + * \param[out] module_inst Pointer to the DAC software instance struct + * \param[in] config Pointer to the configuration struct + * + */ +static void _dac_set_config( + struct dac_module *const module_inst, + struct dac_config *const config) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(config); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + /* Set selected DAC start on event to be disable when enabling the module */ + module_inst->start_on_event[DAC_CHANNEL_0] = false; + module_inst->start_on_event[DAC_CHANNEL_1] = false; + + uint32_t new_ctrlb = 0; + + /* Enable DAC in differential mode if configured */ + if (config->differential_mode) { + new_ctrlb |= DAC_CTRLB_DIFF; + } + + /* Set reference voltage */ + new_ctrlb |= config->reference; + + /* Apply the new configuration to the hardware module */ + dac_module->CTRLB.reg = new_ctrlb; +} + +/** + * \brief Determines if the hardware module(s) are currently synchronizing to the bus. + * + * Checks to see if the underlying hardware peripheral module(s) are currently + * synchronizing across multiple clock domains to the hardware bus. This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * + * \param[in] dev_inst Pointer to the DAC software instance struct + * + * \return Synchronization status of the underlying hardware module(s). + * + * \retval true If the module synchronization is ongoing + * \retval false If the module has completed synchronization + */ +bool dac_is_syncing( + struct dac_module *const dev_inst) +{ + /* Sanity check arguments */ + Assert(dev_inst); + + Dac *const dac_module = dev_inst->hw; + + if (dac_module->SYNCBUSY.reg) { + return true; + } + + return false; +} + +/** + * \brief Initializes a DAC configuration structure to defaults. + * + * Initializes a given DAC configuration structure to a set of + * known default values. This function should be called on any new + * instance of the configuration structures before being modified by the + * user application. + * + * The default configuration is as follows: + * \li 1V from internal bandgap reference + * \li Drive the DAC output to the VOUT pin + * \li Right adjust data + * \li GCLK generator 0 (GCLK main) clock source + * \li The output buffer is disabled when the chip enters STANDBY sleep + * mode + * + * \param[out] config Configuration structure to initialize to default values + */ +void dac_get_config_defaults( + struct dac_config *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Default configuration values */ + config->differential_mode = false; + config->reference = DAC_REFERENCE_INTREF; + config->clock_source = GCLK_GENERATOR_0; +} + +/** + * \brief Initialize the DAC device struct. + * + * Use this function to initialize the Digital to Analog Converter. Resets the + * underlying hardware module and configures it. + * + * \note The DAC channel must be configured separately. + * + * \param[out] module_inst Pointer to the DAC software instance struct + * \param[in] module Pointer to the DAC module instance + * \param[in] config Pointer to the config struct, created by the user + * application + * + * \return Status of initialization. + * \retval STATUS_OK Module initiated correctly + * \retval STATUS_ERR_DENIED If module is enabled + * \retval STATUS_BUSY If module is busy resetting + */ +enum status_code dac_init( + struct dac_module *const module_inst, + Dac *const module, + struct dac_config *const config) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module); + Assert(config); + + /* Initialize device instance */ + module_inst->hw = module; + + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC); + + /* Check if module is enabled. */ + if (module->CTRLA.reg & DAC_CTRLA_ENABLE) { + return STATUS_ERR_DENIED; + } + + /* Check if reset is in progress. */ + if (module->CTRLA.reg & DAC_CTRLA_SWRST) { + return STATUS_BUSY; + } + + /* Configure GCLK channel and enable clock */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = config->clock_source; + system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf); + system_gclk_chan_enable(DAC_GCLK_ID); + + /* Write configuration to module */ + _dac_set_config(module_inst, config); + + /* Store reference selection for later use */ + module_inst->reference = config->reference; + +#if DAC_CALLBACK_MODE == true + for (uint8_t i = 0; i < DAC_CHANNEL_N; i++) { + for (uint8_t j = 0; j < DAC_CALLBACK_N; j++) { + module_inst->callback[i][j] = NULL; + } + }; + + _dac_instances[0] = module_inst; +#endif + + return STATUS_OK; +} + +/** + * \brief Resets the DAC module. + * + * This function will reset the DAC module to its power on default values and + * disable it. + * + * \param[in] module_inst Pointer to the DAC software instance struct + */ +void dac_reset( + struct dac_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + while (dac_is_syncing(module_inst)) { + /* Wait until the synchronization is complete */ + } + + /* Software reset the module */ + dac_module->CTRLA.reg |= DAC_CTRLA_SWRST; +} + +/** + * \brief Enable the DAC module. + * + * Enables the DAC interface and the selected output. If any internal reference + * is selected it will be enabled. + * + * \param[in] module_inst Pointer to the DAC software instance struct + * + */ +void dac_enable( + struct dac_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + while (dac_is_syncing(module_inst)) { + /* Wait until the synchronization is complete */ + } + + /* Enable the module */ + dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE; + + /* Enable internal bandgap reference if selected in the configuration */ + if (module_inst->reference == DAC_REFERENCE_INTREF) { + system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT); + } + + if(dac_module->DACCTRL[DAC_CHANNEL_0].reg & DAC_DACCTRL_ENABLE) { + while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_0 + 1))) { + }; + } else if(dac_module->DACCTRL[DAC_CHANNEL_1].reg & DAC_DACCTRL_ENABLE) { + while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_1 + 1))) { + }; + } +} + +/** + * \brief Disable the DAC module. + * + * Disables the DAC interface and the output buffer. + * + * \param[in] module_inst Pointer to the DAC software instance struct + * + */ +void dac_disable( + struct dac_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + while (dac_is_syncing(module_inst)) { + /* Wait until the synchronization is complete */ + } + + /* Disable DAC */ + dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE; +} + +/** + * \brief Enables a DAC event input or output. + * + * Enables one or more input or output events to or from the DAC module. See + * \ref dac_events "Struct dac_events" for a list of events this module supports. + * + * \note Events cannot be altered while the module is enabled. + * + * \param[in] module_inst Software instance for the DAC peripheral + * \param[in] events Struct containing flags of events to enable + */ +void dac_enable_events( + struct dac_module *const module_inst, + struct dac_events *const events) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(events); + + Dac *const dac_module = module_inst->hw; + + uint32_t event_mask = 0; + + /* Configure Enable Inversion of input event */ + if (events->generate_event_on_chan0_falling_edge) { + event_mask |= DAC_EVCTRL_INVEI0; + } + + /* Configure Enable Inversion of input event */ + if (events->generate_event_on_chan1_falling_edge) { + event_mask |= DAC_EVCTRL_INVEI1; + } + + /* Configure Buffer Empty event */ + if (events->generate_event_on_chan0_buffer_empty) { + event_mask |= DAC_EVCTRL_EMPTYEO0; + } + + /* Configure Buffer Empty event */ + if (events->generate_event_on_chan1_buffer_empty) { + event_mask |= DAC_EVCTRL_EMPTYEO1; + } + + /* Configure Conversion Start event */ + if (events->on_event_chan0_start_conversion) { + event_mask |= DAC_EVCTRL_STARTEI0; + module_inst->start_on_event[DAC_CHANNEL_0] = true; + } + + /* Configure Conversion Start event */ + if (events->on_event_chan1_start_conversion) { + event_mask |= DAC_EVCTRL_STARTEI1; + module_inst->start_on_event[DAC_CHANNEL_1] = true; + } + + dac_module->EVCTRL.reg |= event_mask; +} + +/** + * \brief Disables a DAC event input or output. + * + * Disables one or more input or output events to or from the DAC module. See + * \ref dac_events "Struct dac_events" for a list of events this module supports. + * + * \note Events cannot be altered while the module is enabled. + * + * \param[in] module_inst Software instance for the DAC peripheral + * \param[in] events Struct containing flags of events to disable + */ +void dac_disable_events( + struct dac_module *const module_inst, + struct dac_events *const events) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(events); + + Dac *const dac_module = module_inst->hw; + + uint32_t event_mask = 0; + + /* Configure Buffer Empty event */ + if (events->on_event_chan0_start_conversion) { + event_mask |= DAC_EVCTRL_EMPTYEO0; + } + + /* Configure Buffer Empty event */ + if (events->on_event_chan1_start_conversion) { + event_mask |= DAC_EVCTRL_EMPTYEO1; + } + + /* Configure Conversion Start event */ + if (events->generate_event_on_chan0_buffer_empty) { + event_mask |= DAC_EVCTRL_STARTEI0; + module_inst->start_on_event[DAC_CHANNEL_0] = false; + } + + /* Configure Conversion Start event */ + if (events->generate_event_on_chan0_buffer_empty) { + event_mask |= DAC_EVCTRL_STARTEI1; + module_inst->start_on_event[DAC_CHANNEL_1] = false; + } + + dac_module->EVCTRL.reg &= ~event_mask; +} + +void dac_chan_get_config_defaults( + struct dac_chan_config *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Dac channel default configuration values */ + config->left_adjust = false; + config->current = DAC_CURRENT_12M; + config->run_in_standby = false; + config->dither_mode = false; + config->refresh_period = 1; +} + + +/** + * \brief Writes a DAC channel configuration to the hardware module. + * + * Writes out a given channel configuration to the hardware module. + * + * \note The DAC device instance structure must be initialized before calling + * this function. + * + * \param[in] module_inst Pointer to the DAC software instance struct + * \param[in] channel Channel to configure + * \param[in] config Pointer to the configuration struct + * + */ +void dac_chan_set_config( + struct dac_module *const module_inst, + const enum dac_channel channel, + struct dac_chan_config *const config) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(config); + + /* MUX the DAC VOUT pin */ + struct system_pinmux_config pin_conf; + system_pinmux_get_config_defaults(&pin_conf); + + pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; + + if(channel == DAC_CHANNEL_0) { + /* Set up the DAC VOUT0 pin */ + pin_conf.mux_position = MUX_PA02B_DAC_VOUT0; + system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT0, &pin_conf); + } else if(channel == DAC_CHANNEL_1) { + /* Set up the DAC VOUT1 pin */ + pin_conf.mux_position = MUX_PA05B_DAC_VOUT1; + system_pinmux_pin_set_config(PIN_PA05B_DAC_VOUT1, &pin_conf); + } + + Dac *const dac_module = module_inst->hw; + + uint32_t new_dacctrl = 0; + + /* Left adjust data if configured */ + if (config->left_adjust) { + new_dacctrl |= DAC_DACCTRL_LEFTADJ; + } + + /* Set current control */ + new_dacctrl |= config->current; + + /* Enable DAC in standby sleep mode if configured */ + if (config->run_in_standby) { + new_dacctrl |= DAC_DACCTRL_RUNSTDBY; + } + + /* Voltage pump disable if configured */ + if (config->dither_mode) { + new_dacctrl |= DAC_DACCTRL_DITHER; + } + + new_dacctrl |= DAC_DACCTRL_REFRESH(config->refresh_period); + + /* Apply the new configuration to the hardware module */ + dac_module->DACCTRL[channel].reg = new_dacctrl; +} + +/** + * \brief Enable a DAC channel. + * + * Enables the selected DAC channel. + * + * \param[in] module_inst Pointer to the DAC software instance struct + * \param[in] channel Channel to enable + * + */ +void dac_chan_enable( + struct dac_module *const module_inst, + enum dac_channel channel) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + /* Enable the module */ + dac_module->DACCTRL[channel].reg |= DAC_DACCTRL_ENABLE; +} + +/** + * \brief Disable a DAC channel. + * + * Disables the selected DAC channel. + * + * \param[in] module_inst Pointer to the DAC software instance struct + * \param[in] channel Channel to disable + * + */ +void dac_chan_disable( + struct dac_module *const module_inst, + enum dac_channel channel) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + /* Enable the module */ + dac_module->DACCTRL[channel].reg &= ~DAC_DACCTRL_ENABLE; + +} + +/** + * \brief Write to the DAC. + * + * This function writes to the DATA or DATABUF register. + * If the conversion is not event-triggered, the data will be written to + * the DATA register and the conversion will start. + * If the conversion is event-triggered, the data will be written to DATABUF + * and transferred to the DATA register and converted when a Start Conversion + * Event is issued. + * Conversion data must be right or left adjusted according to configuration + * settings. + * \note To be event triggered, the enable_start_on_event must be + * enabled in the configuration. + * + * \param[in] module_inst Pointer to the DAC software device struct + * \param[in] channel DAC channel to write to + * \param[in] data Conversion data + * + * \return Status of the operation. + * \retval STATUS_OK If the data was written + */ +enum status_code dac_chan_write( + struct dac_module *const module_inst, + enum dac_channel channel, + const uint16_t data) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + while (dac_is_syncing(module_inst)) { + /* Wait until the synchronization is complete */ + } + + if (module_inst->start_on_event[channel]) { + /* Write the new value to the buffered DAC data register */ + dac_module->DATABUF[channel].reg = data; + } else { + /* Write the new value to the DAC data register */ + dac_module->DATA[channel].reg = data; + } + + return STATUS_OK; +} + +/** + * \brief Write to the DAC. + * + * This function converts a specific number of digital data. + * The conversion should be event-triggered, the data will be written to DATABUF + * and transferred to the DATA register and converted when a Start Conversion + * Event is issued. + * Conversion data must be right or left adjusted according to configuration + * settings. + * \note To be event triggered, the enable_start_on_event must be + * enabled in the configuration. + * + * \param[in] module_inst Pointer to the DAC software device struct + * \param[in] channel DAC channel to write to + * \param[in] buffer Pointer to the digital data write buffer to be converted + * \param[in] length Length of the write buffer + * + * \return Status of the operation. + * \retval STATUS_OK If the data was written or no data conversion required + * \retval STATUS_ERR_UNSUPPORTED_DEV The DAC is not configured as using event trigger + * \retval STATUS_BUSY The DAC is busy and can not do the conversion + */ +enum status_code dac_chan_write_buffer_wait( + struct dac_module *const module_inst, + enum dac_channel channel, + uint16_t *buffer, + uint32_t length) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + while (dac_is_syncing(module_inst)) { + /* Wait until the synchronization is complete */ + } + + /* Zero length request */ + if (length == 0) { + /* No data to be converted */ + return STATUS_OK; + } + +#if DAC_CALLBACK_MODE == true + /* Check if busy */ + if (module_inst->job_status[channel] == STATUS_BUSY) { + return STATUS_BUSY; + } +#endif + + /* Only support event triggered conversion */ + if (module_inst->start_on_event[channel] == false) { + return STATUS_ERR_UNSUPPORTED_DEV; + } + + /* Blocks while buffer is being transferred */ + while (length--) { + /* Convert one data */ + dac_chan_write(module_inst, channel, buffer[length]); + + /* Wait until Transmit is complete or timeout */ + for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) { + if(channel == DAC_CHANNEL_0) { + if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY0) { + break; + } else if (i == DAC_TIMEOUT) { + return STATUS_ERR_TIMEOUT; + } + } else if(channel == DAC_CHANNEL_1) { + if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY1) { + break; + } else if (i == DAC_TIMEOUT) { + return STATUS_ERR_TIMEOUT; + } + } + } + } + + return STATUS_OK; +} + +/** + * \brief Retrieves the status of DAC channel end of conversion. + * + * Checks if the conversion is completed or not and returns boolean flag + * of status. + * + * \param[in] module_inst Pointer to the DAC software instance struct + * \param[in] channel Channel to disable + * + * \retval true Conversion is complete, VOUT is stable + * \retval false No conversion completed since last load of DATA + */ +bool dac_chan_is_end_of_conversion( + struct dac_module *const module_inst, + enum dac_channel channel) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + if(dac_module->STATUS.reg & DAC_STATUS_EOC(channel + 1)) { + return true; + } else { + return false; + } +} + +/** + * \brief Retrieves the current module status. + * + * Checks the status of the module and returns it as a bitmask of status + * flags. + * + * \param[in] module_inst Pointer to the DAC software device struct + * + * \return Bitmask of status flags. + * + * \retval DAC_STATUS_CHANNEL_0_EMPTY Data has been transferred from DATABUF + * to DATA by a start conversion event + * and DATABUF is ready for new data + * \retval DAC_STATUS_CHANNEL_0_UNDERRUN A start conversion event has occurred + * when DATABUF is empty + * + */ +uint32_t dac_get_status( + struct dac_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + uint8_t intflags = dac_module->INTFLAG.reg; + uint32_t status_flags = 0; + + if (intflags & DAC_INTFLAG_EMPTY0) { + status_flags |= DAC_STATUS_CHANNEL_0_EMPTY; + } + + if (intflags & DAC_INTFLAG_EMPTY1) { + status_flags |= DAC_STATUS_CHANNEL_1_EMPTY; + } + + if (intflags & DAC_INTFLAG_UNDERRUN0) { + status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN; + } + + if (intflags & DAC_INTFLAG_UNDERRUN1) { + status_flags |= DAC_STATUS_CHANNEL_1_UNDERRUN; + } + + return status_flags; +} + +/** + * \brief Clears a module status flag. + * + * Clears the given status flag of the module. + * + * \param[in] module_inst Pointer to the DAC software device struct + * \param[in] status_flags Bit mask of status flags to clear + * + */ +void dac_clear_status( + struct dac_module *const module_inst, + uint32_t status_flags) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + Dac *const dac_module = module_inst->hw; + + uint32_t intflags = 0; + + if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) { + intflags |= DAC_INTFLAG_EMPTY0; + } + + if (status_flags & DAC_STATUS_CHANNEL_1_EMPTY) { + intflags |= DAC_INTFLAG_EMPTY1; + } + + if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) { + intflags |= DAC_INTFLAG_UNDERRUN0; + } + + if (status_flags & DAC_STATUS_CHANNEL_1_UNDERRUN) { + intflags |= DAC_INTFLAG_UNDERRUN1; + } + + dac_module->INTFLAG.reg = intflags; +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac_feature.h new file mode 100644 index 0000000000..584d77cfd8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac_feature.h @@ -0,0 +1,611 @@ +/** + * \file + * + * \brief SAM Peripheral Digital-to-Analog Converter Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef DAC_FEATURE_H_INCLUDED +#define DAC_FEATURE_H_INCLUDED + +/** + * \defgroup asfdoc_sam0_dac_group SAM Digital-to-Analog (DAC) Driver + * + * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the conversion of + * digital values to analog voltage. The following driver API modes are covered + * by this manual: + * + * - Polled APIs + * \if DAC_CALLBACK_MODE + * - Callback APIs + * \endif + * + * The following peripheral is used by this module: + * - DAC (Digital-to-Analog Converter) + * + * The following devices can use this module: + * - Atmel | SMART SAM L21 + * + * The outline of this documentation is as follows: + * - \ref asfdoc_sam0_dac_prerequisites + * - \ref asfdoc_sam0_dac_module_overview + * - \ref asfdoc_sam0_dac_special_considerations + * - \ref asfdoc_sam0_dac_extra_info + * - \ref asfdoc_sam0_dac_examples + * - \ref asfdoc_sam0_dac_api_overview + * + * + * \section asfdoc_sam0_dac_prerequisites Prerequisites + * + * There are no prerequisites for this module. + * + * + * \section asfdoc_sam0_dac_module_overview Module Overview + * + * The Digital-to-Analog converter converts a digital value to an analog voltage. + * The DAC Controller can operate as two independent DACs or as a single DAC + * in differential mode. Each DAC has a 12-bit resolution and it is capable of + * converting up to 1M samples per second (Msps). + * + * A common use of DAC is to generate audio signals by connecting the DAC + * output to a speaker, or to generate a reference voltage; either for an + * external circuit or an internal peripheral such as the Analog Comparator. + * + * After being set up, the DAC will convert new digital values written to the + * conversion data register (DATA0 or DATA1) to an analog value either on the + * DAC output (VOUT0 or VOUT1) pin of the device, or internally for use as an + * input to the AC, ADC, and other analog modules. + * + * Writing the DATA register will start a new conversion. It is also possible + * to trigger the conversion from the event system. + * + * A simplified block diagram of the DAC can be seen in + * \ref asfdoc_sam0_dac_module_block_diagram "the figure below". + * + * \anchor asfdoc_sam0_dac_module_block_diagram + * \image html dac_block_diagram_saml.svg "DAC Block Diagram" + * + * \subsection asfdoc_sam0_dac_conversion_range Conversion Range + * The conversion range is between GND and the selected voltage reference. + * Available voltage references are: + * \li Voltage supply (VDDANA) + * \li Internal bandgap reference (INTREF) + * \li Unbuffered External voltage reference (VREFPU) + * \li Buffered External voltage reference (VREFPB) + * + * \note Internal references will be enabled by the driver, but not disabled. + * Any reference not used by the application should be disabled by the application. + * + * The output voltage from a DAC channel is given as: + * \f[ + * V_{OUTx} = \frac{DATAx}{0x3FF} \times VREF + * \f] + * The differential output voltage is given as: + * \f[ + * V_{OUT} = \frac{DATA0}{0x1FF} \times VREF = (V_{OUT0}-V_{OUT1}) + * \f] + * + * \subsection asfdoc_sam0_dac_conversion Conversion + * The conversion digital value written to the DATA register will be converted + * to an analog value. Writing the DATA register will start a new conversion. + * It is also possible to write the conversion value to the DATABUF register, + * the writing of the DATA register can then be triggered from the event + * system, which will load the value from DATABUF to DATA. + * + * \subsection asfdoc_sam0_dac_analog_output Analog Output + * The analog output value can be output to the VOUTx converted by DACx, and + * each data conversion can be started independently. + * + * In differential mode, DAC0 and DAC1 are operating synchronously to convert + * value. VOUT0 is the positive output and VOUT1 the negative output. + * + * VOUT0 signal is internally connected so that it can be used as input for + * AC, ADC, or OPAMP modules when DAC0 is enabled. + * \note The pin VOUT0 will be dedicated to internal input and cannot be + * configured as alternate function. + * + * \subsection asfdoc_sam0_dac_events Events + * Events generation and event actions are configurable in the DAC. + * The DAC has one event line input and one event output: Start Conversion + * and Data Buffer Empty. + * + * If the Start Conversion input event is enabled in the module configuration, + * an incoming event will load data from the data buffer to the data register + * and start a new conversion. This method synchronizes conversions with + * external events (such as those from a timer module) and ensures regular and + * fixed conversion intervals. + * + * If the Data Buffer Empty output event is enabled in the module configuration, + * events will be generated when the DAC data buffer register becomes empty and + * new data can be loaded to the buffer. + * + * \note The connection of events between modules requires the use of the + * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" + * to route output event of one module to the the input event of another. + * For more information on event routing, refer to the event driver + * documentation. + * + * \subsection asfdoc_sam0_dac_data_adjust Left and Right Adjusted Values + * The 12-bit input value to the DAC is contained in a 16-bit register. This + * can be configured to be either left or right adjusted. In + * \ref asfdoc_sam0_dac_module_adj_modes "the figure below" both options are + * shown, and the position of the most (MSB) and the least (LSB) significant bits + * are indicated. The unused bits should always be written to zero. + * + * \anchor asfdoc_sam0_dac_module_adj_modes + * \dot + * digraph { + * subgraph cluster_right { + * msbl [label="MSB", shape=none, group="msbl"]; + * lsbl [label="LSB", shape=none]; + * node [shape=none]; + * color="white"; + * reg_left [label=< + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
      1514131211109876543210
      DATA[11:0]
      + * >]; + * msbl -> reg_left:msb:n; + * lsbl -> reg_left:lsb; + * label ="Left adjusted.\n"; + * } + * subgraph cluster_left { + * rankdir=TB; + * msb [label="MSB", shape=none]; + * lsb [label="LSB", shape=none]; + * color="white"; + * node [shape=none]; + * reg_right [label=< + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
      1514131211109876543210
      DATA[11:0]
      + * >]; + * msb -> reg_right:msb; + * lsb -> reg_right:lsb:n; + * label = "Right adjusted.\n"; + * graph [shape=none]; + * } + * } + * \enddot + * + * \subsection asfdoc_sam0_dac_clk_sources Clock Sources + * The clock for the DAC interface (CLK_DAC) is generated by the Power Manager. + * This clock is turned on by default, and can be enabled and disabled in the + * Power Manager. + * + * Additionally, an asynchronous clock source (GCLK_DAC) is required. + * These clocks are normally disabled by default. The selected clock source + * must be enabled in the Power Manager before it can be used by the DAC. + * The DAC core operates asynchronously from the user interface and + * peripheral bus. As a consequence, the DAC needs two clock cycles of both + * CLK_DAC and GCLK_DAC to synchronize the values written to some of the + * control and data registers. + * The oscillator source for the GCLK_DAC clock is selected in the Supply + * Control Interface (SUPC). + * + * \section asfdoc_sam0_dac_special_considerations Special Considerations + * + * \subsection asfdoc_sam0_dac_special_considerations_sleep Sleep Mode + * The DAC can do conversions in Active or Idle modes, and will continue the + * conversions in standby sleep mode if the RUNSTDBY bit in the DACCTRLx + * register is set. Otherwise, the DACx will stop conversions. + * + * If DACx conversion is stopped in standby sleep mode, DACx is disabled to + * reduce power consumption. When exiting standby sleep mode, DACx is enabled + * therefore startup time is required before starting a new conversion. + * + * \subsection asfdoc_sam0_dac_special_considerations_conversion_time Conversion Time + * DAC conversion time is approximately 2.85µs. The user must ensure that new + * data is not written to the DAC before the last conversion is complete. + * Conversions should be triggered by a periodic event from a Timer/Counter or + * another peripheral. + * + * + * \section asfdoc_sam0_dac_extra_info Extra Information + * + * For extra information, see \ref asfdoc_sam0_dac_extra. This includes: + * - \ref asfdoc_sam0_dac_extra_acronyms + * - \ref asfdoc_sam0_dac_extra_dependencies + * - \ref asfdoc_sam0_dac_extra_errata + * - \ref asfdoc_sam0_dac_extra_history + * + * + * \section asfdoc_sam0_dac_examples Examples + * + * For a list of examples related to this driver, see + * \ref asfdoc_sam0_dac_exqsg. + * + * + * \section asfdoc_sam0_dac_api_overview API Overview + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + + +/** + * \name DAC Status Flags + * + * DAC status flags, returned by \ref dac_get_status() and cleared by + * \ref dac_clear_status(). + * @{ + */ + +/** Data Buffer Empty Channel 0 - Set when data is transferred from DATABUF + * to DATA by a start conversion event and DATABUF is ready for new data. + */ +#define DAC_STATUS_CHANNEL_0_EMPTY (1UL << 0) + +/** Data Buffer Empty Channel 1 - Set when data is transferred from DATABUF + * to DATA by a start conversion event and DATABUF is ready for new data. + */ +#define DAC_STATUS_CHANNEL_1_EMPTY (1UL << 1) + +/** Underrun Channel 0 - Set when a start conversion event occurs when + * DATABUF is empty. + */ +#define DAC_STATUS_CHANNEL_0_UNDERRUN (1UL << 2) + +/** Underrun Channel 1 - Set when a start conversion event occurs when + * DATABUF is empty. + */ +#define DAC_STATUS_CHANNEL_1_UNDERRUN (1UL << 3) + +/** @} */ + +/** + * \brief DAC reference voltage enum. + * + * Enum for the possible reference voltages for the DAC. + */ +enum dac_reference { + /** Unbuffered external voltage reference */ + DAC_REFERENCE_VREFPU = DAC_CTRLB_REFSEL(0), + /** Analog VCC as reference */ + DAC_REFERENCE_VDDANA = DAC_CTRLB_REFSEL(1), + /** Buffered external voltage reference */ + DAC_REFERENCE_VREFPB = DAC_CTRLB_REFSEL(2), + /** Internal bandgap reference */ + DAC_REFERENCE_INTREF = DAC_CTRLB_REFSEL(3), +}; + +/** + * \brief DAC current control enum. + * + * Enum for the current in output buffer according the conversion rate. + */ +enum dac_current_ctrl { + /** 1MHz < GCLK_DAC < 12MHz */ + DAC_CURRENT_12M = DAC_DACCTRL_CCTRL(0), + /** 100KHz < GCLK_DAC < 1MHz */ + DAC_CURRENT_1M = DAC_DACCTRL_CCTRL(1), + /** 10KHz < GCLK_DAC < 100KHz */ + DAC_CURRENT_100K = DAC_DACCTRL_CCTRL(2), + /** GCLK_DAC < 10KHz */ + DAC_CURRENT_10K = DAC_DACCTRL_CCTRL(3), +}; + +/** + * \brief DAC channel selection enum. + * + * Enum for the DAC channel selection. + */ +enum dac_channel { + /** DAC output channel 0 */ + DAC_CHANNEL_0, + /** DAC output channel 1 */ + DAC_CHANNEL_1, +#if !defined(__DOXYGEN__) + DAC_CHANNEL_N, +#endif +}; + +/** + * \brief DAC software device instance structure. + * + * DAC software instance structure, used to retain software state information + * of an associated hardware module instance. + * + * \note The fields of this structure should not be altered by the user + * application; they are reserved for module-internal use only. + */ +struct dac_module { +#if !defined(__DOXYGEN__) + /** DAC hardware module */ + Dac *hw; + /** Reference selection */ + enum dac_reference reference; + /** DAC event selection */ + bool start_on_event[DAC_CHANNEL_N]; +# if DAC_CALLBACK_MODE == true + /** Pointer to buffer used for ADC results */ + volatile uint16_t *job_buffer[DAC_CHANNEL_N]; + /** Remaining number of conversions in current job */ + volatile uint16_t remaining_conversions[DAC_CHANNEL_N]; + /** Transferred number of conversions in current job */ + volatile uint16_t transferred_conversions[DAC_CHANNEL_N]; + /** DAC callback enable */ + bool callback_enable[DAC_CHANNEL_N][DAC_CALLBACK_N]; + /** DAC registered callback functions */ + dac_callback_t callback[DAC_CHANNEL_N][DAC_CALLBACK_N]; + /** Holds the status of the ongoing or last conversion job */ + volatile enum status_code job_status[DAC_CHANNEL_N]; +# endif +#endif +}; + +/** + * \brief DAC configuration structure. + * + * Configuration structure for a DAC instance. This structure should be + * initialized by the \ref dac_get_config_defaults() + * function before being modified by the user application. + */ +struct dac_config { + /** Differential mode enable data */ + bool differential_mode; + /** Reference voltage */ + enum dac_reference reference; + /** GCLK generator used to clock the peripheral */ + enum gclk_generator clock_source; +}; + +/** + * \brief DAC channel configuration structure. + * + * Configuration for a DAC channel. This structure should be initialized by the + * \ref dac_chan_get_config_defaults() function before being modified by the + * user application. + */ +struct dac_chan_config { + /** Left adjusted data */ + bool left_adjust; + /** Current control data */ + enum dac_current_ctrl current; + /** + * The DAC behaves as in normal mode when the chip enters STANDBY sleep + * mode + */ + bool run_in_standby; + /** Dither mode enable data */ + bool dither_mode; + /** + * The DAC conversion refreshed periodically when used to generate a static + * voltage + */ + uint8_t refresh_period; +}; + +/** + * \brief DAC event enable/disable structure. + * + * Event flags for the DAC module. This is used to enable and + * disable events via \ref dac_enable_events() and \ref dac_disable_events(). + */ +struct dac_events { + /** Start a new DAC0 conversion */ + bool on_event_chan0_start_conversion; + /** Start a new DAC1 conversion */ + bool on_event_chan1_start_conversion; + /** Enable event generation on DAC0 data buffer empty */ + bool generate_event_on_chan0_buffer_empty; + /** Enable event generation on DAC1 data buffer empty */ + bool generate_event_on_chan1_buffer_empty; + /** Enable the falling edge of the input event for DAC0 */ + bool generate_event_on_chan0_falling_edge; + /** Enable the falling edge of the input event for DAC1 */ + bool generate_event_on_chan1_falling_edge; +}; + +/** + * \name Status Management (Channel) + * @{ + */ +bool dac_chan_is_end_of_conversion( + struct dac_module *const module_inst, + enum dac_channel channel); +/** @} */ + +/** @} */ + +/** + * \page asfdoc_sam0_dac_extra Extra Information for DAC Driver + * + * \section asfdoc_sam0_dac_extra_acronyms Acronyms + * The table below presents the acronyms used in this module: + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
      AcronymDescription
      ADCAnalog-to-Digital Converter
      ACAnalog Comparator
      DACDigital-to-Analog Converter
      LSBLeast Significant Bit
      MSBMost Significant Bit
      DMADirect Memory Access
      + * + * + * \section asfdoc_sam0_dac_extra_dependencies Dependencies + * This driver has the following dependency: + * + * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" + * + * + * \section asfdoc_sam0_dac_extra_errata Errata + * There are no errata related to this driver. + * + * + * \section asfdoc_sam0_dac_extra_history Module History + * An overview of the module history is presented in the table below, with + * details on the enhancements and fixes made to the module since its first + * release. The current version of this corresponds to the newest version in + * the table. + * + * + * + * + * + * + * + * + *
      Changelog
      Initial Release
      + */ + +/** + * \page asfdoc_sam0_dac_exqsg Examples for DAC Driver + * + * This is a list of the available Quick Start guides (QSGs) and example + * applications for \ref asfdoc_sam0_dac_group. QSGs are simple examples with + * step-by-step instructions to configure and use this driver in a selection of + * use cases. Note that a QSG can be compiled as a standalone application or be + * added to the user application. + * + * - \subpage asfdoc_sam0_dac_basic_use_case + * \if DAC_CALLBACK_MODE + * - \subpage asfdoc_sam0_dac_basic_use_case_callback + * \endif + * \if DAC_DMA_USE_MODE_SELECTION + * - \subpage asfdoc_sam0_adc_dma_use_case_dac_in_dma + * \endif + * + * \if DAC_DMA_USE_MODE_SELECTION + * \page asfdoc_sam0_adc_dma_use_case_dac_in_dma Quick Start Guide for Using DMA with ADC/DAC + * For this examples, see + * \ref asfdoc_sam0_adc_dma_use_case + * \endif + * + * \page asfdoc_sam0_dac_document_revision_history Document Revision History + * + * + * + * + * + * + * + * + * + *
      Doc. Rev. + * Date + * Comments + *
      42450A07/2015Initial document release
      + */ +#ifdef __cplusplus +} +#endif + + +#endif /* DAC_FEATURE_H_INCLUDED */ + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/TARGET_SAMD21/dac/dac.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/dac.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/TARGET_SAMD21/dac/dac.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/dac.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/dma/dma.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/dma/dma.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/dma/dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/dma/dma.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/dma/dma_crc.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma_crc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/dma/dma_crc.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma_crc.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/extint/extint_sam_d_r/extint.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMD21/extint.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/extint/extint_sam_d_r/extint.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMD21/extint.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAML21/extint.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAML21/extint.c new file mode 100644 index 0000000000..e7b3610023 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAML21/extint.c @@ -0,0 +1,481 @@ +/** + * \file + * + * \brief SAM External Interrupt Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include +#include +#include +#include + +#if !defined(EXTINT_CLOCK_SELECTION) || defined(__DOXYGEN__) +# warning EXTINT_CLOCK_SELECTION is not defined, assuming EXTINT_CLK_GCLK. + +/** Configuration option, setting the EIC clock source which can be used for + * EIC edge detection or filtering. This option may be overridden in the module + * configuration header file \c conf_extint.h. + */ +# define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK +#endif + +#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) +#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__) +# warning EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0. + +/** Configuration option, setting the EIC clock source which can be used for + * EIC edge detection or filtering. This option may be overridden in the module + * configuration header file \c conf_extint.h. + */ +# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 +#endif +#endif + +/** + * \internal + * Internal driver device instance struct. + */ +struct _extint_module _extint_dev; + +/** + * \brief Determin if the general clock is required. + * + * \param[in] filter_input_signal Filter the raw input signal to prevent noise + * \param[in] detection_criteria Edge detection mode to use (\ref extint_detect) + */ +#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \ + ((filter_input_signal) ? true : (\ + (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\ + (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\ + (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false)))) + +static void _extint_enable(void); +static void _extint_disable(void); + +/** + * \brief Determines if the hardware module(s) are currently synchronizing to the bus. + * + * Checks to see if the underlying hardware peripheral module(s) are currently + * synchronizing across multiple clock domains to the hardware bus, This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * + * \return Synchronization status of the underlying hardware module(s). + * + * \retval true If the module synchronization is ongoing + * \retval false If the module has completed synchronization + */ +static inline bool extint_is_syncing(void) +{ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + if((eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) + || (eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST)) { + return true; + } + } + return false; +} + +/** + * \internal + * \brief Initializes and enables the External Interrupt driver. + * + * Enable the clocks used by External Interrupt driver. + * + * Resets the External Interrupt driver, resetting all hardware + * module registers to their power-on defaults, then enable it for further use. + * + * Reset the callback list if callback mode is used. + * + * This function must be called before attempting to use any NMI or standard + * external interrupt channel functions. + * + * \note When SYSTEM module is used, this function will be invoked by + * \ref system_init() automatically if the module is included. + */ +void _system_extint_init(void); +void _system_extint_init(void) +{ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_EIC); + +#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) + /* Configure the generic clock for the module and enable it */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE; + system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf); + + /* Enable the clock anyway, since when needed it will be requested + * by External Interrupt driver */ + system_gclk_chan_enable(EIC_GCLK_ID); +#endif + + /* Reset all EIC hardware modules. */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRLA.reg |= EIC_CTRLA_SWRST; + } + + while (extint_is_syncing()) { + /* Wait for all hardware modules to complete synchronization */ + } + +#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK; + } +#else + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K; + } +#endif + + /* Reset the software module */ +#if EXTINT_CALLBACK_MODE == true + /* Clear callback registration table */ + for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) { + _extint_dev.callbacks[j] = NULL; + } + system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC); +#endif + + /* Enables the driver for further use */ + _extint_enable(); +} + +/** + * \internal + * \brief Enables the External Interrupt driver. + * + * Enables EIC modules. + * Registered callback list will not be affected if callback mode is used. + */ +void _extint_enable(void) +{ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + /* Enable all EIC hardware modules. */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRLA.reg |= EIC_CTRLA_ENABLE; + } + + while (extint_is_syncing()) { + /* Wait for all hardware modules to complete synchronization */ + } +} + +/** + * \internal + * \brief Disables the External Interrupt driver. + * + * Disables EIC modules that were previously started via a call to + * \ref _extint_enable(). + * Registered callback list will not be affected if callback mode is used. + */ +void _extint_disable(void) +{ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + /* Disable all EIC hardware modules. */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + } + + while (extint_is_syncing()) { + /* Wait for all hardware modules to complete synchronization */ + } +} + +/** + * \brief Initializes an External Interrupt channel configuration structure to defaults. + * + * Initializes a given External Interrupt channel configuration structure to a + * set of known default values. This function should be called on all new + * instances of these configuration structures before being modified by the + * user application. + * + * The default configuration is as follows: + * \li Input filtering disabled + * \li Internal pull-up enabled + * \li Detect falling edges of a signal + * \li Asynchronous edge detection is disabled + * + * \param[out] config Configuration structure to initialize to default values + */ +void extint_chan_get_config_defaults( + struct extint_chan_conf *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Default configuration values */ + config->gpio_pin = 0; + config->gpio_pin_mux = 0; + config->gpio_pin_pull = EXTINT_PULL_UP; + config->filter_input_signal = false; + config->detection_criteria = EXTINT_DETECT_FALLING; + config->enable_async_edge_detection = false; +} + +/** + * \brief Writes an External Interrupt channel configuration to the hardware module. + * + * Writes out a given configuration of an External Interrupt channel + * configuration to the hardware module. If the channel is already configured, + * the new configuration will replace the existing one. + * + * \param[in] channel External Interrupt channel to configure + * \param[in] config Configuration settings for the channel + + */ +void extint_chan_set_config( + const uint8_t channel, + const struct extint_chan_conf *const config) +{ + /* Sanity check arguments */ + Assert(config); + _extint_disable(); +#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) + /* Sanity check clock requirements */ + Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && + _extint_is_gclk_required(config->filter_input_signal, + config->detection_criteria))); +#endif + struct system_pinmux_config pinmux_config; + system_pinmux_get_config_defaults(&pinmux_config); + + pinmux_config.mux_position = config->gpio_pin_mux; + pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; + system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); + + /* Get a pointer to the module hardware instance */ + Eic *const EIC_module = _extint_get_eic_from_channel(channel); + + uint32_t config_pos = (4 * (channel % 8)); + uint32_t new_config; + + /* Determine the channel's new edge detection configuration */ + new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos); + + /* Enable the hardware signal filter if requested in the config */ + if (config->filter_input_signal) { + new_config |= EIC_CONFIG_FILTEN0; + } + + /* Clear the existing and set the new channel configuration */ + EIC_module->CONFIG[channel / 8].reg + = (EIC_module->CONFIG[channel / 8].reg & + ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | + (new_config << config_pos); + + /* Config asynchronous edge detection */ + if (config->enable_async_edge_detection) { + EIC_module->EIC_ASYNCH.reg |= (1UL << channel); + } else { + EIC_module->EIC_ASYNCH.reg &= (EIC_EIC_ASYNCH_MASK & (~(1UL << channel))); + } + + _extint_enable(); +} + +/** + * \brief Writes an External Interrupt NMI channel configuration to the hardware module. + * + * Writes out a given configuration of an External Interrupt NMI channel + * configuration to the hardware module. If the channel is already configured, + * the new configuration will replace the existing one. + * + * \param[in] nmi_channel External Interrupt NMI channel to configure + * \param[in] config Configuration settings for the channel + * + * \returns Status code indicating the success or failure of the request. + * \retval STATUS_OK Configuration succeeded + * \retval STATUS_ERR_PIN_MUX_INVALID An invalid pin mux value was supplied + * \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested + */ +enum status_code extint_nmi_set_config( + const uint8_t nmi_channel, + const struct extint_nmi_conf *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Sanity check clock requirements */ + Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && + _extint_is_gclk_required(config->filter_input_signal, + config->detection_criteria))); + + struct system_pinmux_config pinmux_config; + system_pinmux_get_config_defaults(&pinmux_config); + + pinmux_config.mux_position = config->gpio_pin_mux; + pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; + pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; + system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); + + /* Get a pointer to the module hardware instance */ + Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel); + + uint32_t new_config; + + /* Determine the NMI's new edge detection configuration */ + new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos); + + /* Enable the hardware signal filter if requested in the config */ + if (config->filter_input_signal) { + new_config |= EIC_NMICTRL_NMIFILTEN; + } + + /* Enable asynchronous edge detection if requested in the config */ + if (config->enable_async_edge_detection) { + new_config |= EIC_NMICTRL_NMIASYNCH; + } + + /* Disable EIC and general clock to configure NMI */ + _extint_disable(); +#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) + system_gclk_chan_disable(EIC_GCLK_ID); +#else + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK; + system_gclk_chan_disable(EIC_GCLK_ID); + } +#endif + + EIC_module->NMICTRL.reg = new_config; + + /* Enable the EIC clock and EIC after configure NMI */ +#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) + system_gclk_chan_enable(EIC_GCLK_ID); +#else + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K; + } +#endif + _extint_enable(); + + return STATUS_OK; +} + +/** + * \brief Enables an External Interrupt event output. + * + * Enables one or more output events from the External Interrupt module. See + * \ref extint_events "here" for a list of events this module supports. + * + * \note Events cannot be altered while the module is enabled. + * + * \param[in] events Struct containing flags of events to enable + */ +void extint_enable_events( + struct extint_events *const events) +{ + /* Sanity check arguments */ + Assert(events); + + /* Array of available EICs. */ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + _extint_disable(); + + /* Update the event control register for each physical EIC instance */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + uint32_t event_mask = 0; + + /* Create an enable mask for the current EIC module */ + for (uint32_t j = 0; j < 32; j++) { + if (events->generate_event_on_detect[(32 * i) + j]) { + event_mask |= (1UL << j); + } + } + + /* Enable the masked events */ + eics[i]->EVCTRL.reg |= event_mask; + } + _extint_enable(); +} + +/** + * \brief Disables an External Interrupt event output. + * + * Disables one or more output events from the External Interrupt module. See + * \ref extint_events "here" for a list of events this module supports. + * + * \note Events cannot be altered while the module is enabled. + * + * \param[in] events Struct containing flags of events to disable + */ +void extint_disable_events( + struct extint_events *const events) +{ + /* Sanity check arguments */ + Assert(events); + + /* Array of available EICs. */ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + _extint_disable(); + + /* Update the event control register for each physical EIC instance */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + uint32_t event_mask = 0; + + /* Create a disable mask for the current EIC module */ + for (uint32_t j = 0; j < 32; j++) { + if (events->generate_event_on_detect[(32 * i) + j]) { + event_mask |= (1UL << j); + } + } + + /* Disable the masked events */ + eics[i]->EVCTRL.reg &= ~event_mask; + } + _extint_enable(); +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMR21/extint.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMR21/extint.c new file mode 100644 index 0000000000..aab86fedf9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/TARGET_SAMR21/extint.c @@ -0,0 +1,425 @@ +/** + * \file + * + * \brief SAM External Interrupt Driver + * + * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include +#include +#include +#include + +#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__) +# warning EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0. + +/** Configuration option, setting the EIC clock source which can be used for + * EIC edge detection or filtering. This option may be overridden in the module + * configuration header file \c conf_extint.h. + */ +# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 +#endif + +/** + * \internal + * Internal driver device instance struct. + */ +struct _extint_module _extint_dev; + +/** + * \brief Determin if the general clock is required + * + * \param[in] filter_input_signal Filter the raw input signal to prevent noise + * \param[in] detection_criteria Edge detection mode to use (\ref extint_detect) + */ +#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \ + ((filter_input_signal) ? true : (\ + (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\ + (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\ + (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false)))) + +static void _extint_enable(void); +static void _extint_disable(void); + +/** + * \brief Determines if the hardware module(s) are currently synchronizing to the bus. + * + * Checks to see if the underlying hardware peripheral module(s) are currently + * synchronizing across multiple clock domains to the hardware bus, This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * + * \return Synchronization status of the underlying hardware module(s). + * + * \retval true If the module synchronization is ongoing + * \retval false If the module has completed synchronization + */ +static inline bool extint_is_syncing(void) +{ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) { + return true; + } + } + return false; +} +/** + * \internal + * \brief Initializes and enables the External Interrupt driver. + * + * Enable the clocks used by External Interrupt driver. + * + * Resets the External Interrupt driver, resetting all hardware + * module registers to their power-on defaults, then enable it for further use. + * + * Reset the callback list if callback mode is used. + * + * This function must be called before attempting to use any NMI or standard + * external interrupt channel functions. + * + * \note When SYSTEM module is used, this function will be invoked by + * \ref system_init() automatically if the module is included. + */ +void _system_extint_init(void); +void _system_extint_init(void) +{ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC); + + /* Configure the generic clock for the module and enable it */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE; + system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf); + + /* Enable the clock anyway, since when needed it will be requested + * by External Interrupt driver */ + system_gclk_chan_enable(EIC_GCLK_ID); + + /* Reset all EIC hardware modules. */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRL.reg |= EIC_CTRL_SWRST; + } + + while (extint_is_syncing()) { + /* Wait for all hardware modules to complete synchronization */ + } + + /* Reset the software module */ +#if EXTINT_CALLBACK_MODE == true + /* Clear callback registration table */ + for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) { + _extint_dev.callbacks[j] = NULL; + } + system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC); +#endif + + /* Enables the driver for further use */ + _extint_enable(); +} + +/** + * \internal + * \brief Enables the External Interrupt driver. + * + * Enables EIC modules. + * Registered callback list will not be affected if callback mode is used. + */ +void _extint_enable(void) +{ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + /* Enable all EIC hardware modules. */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRL.reg |= EIC_CTRL_ENABLE; + } + + while (extint_is_syncing()) { + /* Wait for all hardware modules to complete synchronization */ + } +} + +/** + * \internal + * \brief Disables the External Interrupt driver. + * + * Disables EIC modules that were previously started via a call to + * \ref _extint_enable(). + * Registered callback list will not be affected if callback mode is used. + */ +void _extint_disable(void) +{ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + /* Disable all EIC hardware modules. */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE; + } + + while (extint_is_syncing()) { + /* Wait for all hardware modules to complete synchronization */ + } +} + +/** + * \brief Initializes an External Interrupt channel configuration structure to defaults. + * + * Initializes a given External Interrupt channel configuration structure to a + * set of known default values. This function should be called on all new + * instances of these configuration structures before being modified by the + * user application. + * + * The default configuration is as follows: + * \li Wake the device if an edge detection occurs whilst in sleep + * \li Input filtering disabled + * \li Internal pull-up enabled + * \li Detect falling edges of a signal + * + * \param[out] config Configuration structure to initialize to default values + */ +void extint_chan_get_config_defaults( + struct extint_chan_conf *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Default configuration values */ + config->gpio_pin = 0; + config->gpio_pin_mux = 0; + config->gpio_pin_pull = EXTINT_PULL_UP; + config->wake_if_sleeping = true; + config->filter_input_signal = false; + config->detection_criteria = EXTINT_DETECT_FALLING; +} + +/** + * \brief Writes an External Interrupt channel configuration to the hardware module. + * + * Writes out a given configuration of an External Interrupt channel + * configuration to the hardware module. If the channel is already configured, + * the new configuration will replace the existing one. + * + * \param[in] channel External Interrupt channel to configure + * \param[in] config Configuration settings for the channel + + */ +void extint_chan_set_config( + const uint8_t channel, + const struct extint_chan_conf *const config) +{ + /* Sanity check arguments */ + Assert(config); + /* Sanity check clock requirements */ + Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && + _extint_is_gclk_required(config->filter_input_signal, + config->detection_criteria))); + + struct system_pinmux_config pinmux_config; + system_pinmux_get_config_defaults(&pinmux_config); + + pinmux_config.mux_position = config->gpio_pin_mux; + pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; + system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); + + /* Get a pointer to the module hardware instance */ + Eic *const EIC_module = _extint_get_eic_from_channel(channel); + + uint32_t config_pos = (4 * (channel % 8)); + uint32_t new_config; + + /* Determine the channel's new edge detection configuration */ + new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos); + + /* Enable the hardware signal filter if requested in the config */ + if (config->filter_input_signal) { + new_config |= EIC_CONFIG_FILTEN0; + } + + /* Clear the existing and set the new channel configuration */ + EIC_module->CONFIG[channel / 8].reg + = (EIC_module->CONFIG[channel / 8].reg & + ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | + (new_config << config_pos); + + /* Set the channel's new wake up mode setting */ + if (config->wake_if_sleeping) { + EIC_module->WAKEUP.reg |= (1UL << channel); + } else { + EIC_module->WAKEUP.reg &= ~(1UL << channel); + } +} + +/** + * \brief Writes an External Interrupt NMI channel configuration to the hardware module. + * + * Writes out a given configuration of an External Interrupt NMI channel + * configuration to the hardware module. If the channel is already configured, + * the new configuration will replace the existing one. + * + * \param[in] nmi_channel External Interrupt NMI channel to configure + * \param[in] config Configuration settings for the channel + * + * \returns Status code indicating the success or failure of the request. + * \retval STATUS_OK Configuration succeeded + * \retval STATUS_ERR_PIN_MUX_INVALID An invalid pinmux value was supplied + * \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested + */ +enum status_code extint_nmi_set_config( + const uint8_t nmi_channel, + const struct extint_nmi_conf *const config) +{ + /* Sanity check arguments */ + Assert(config); + /* Sanity check clock requirements */ + Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && + _extint_is_gclk_required(config->filter_input_signal, + config->detection_criteria))); + + struct system_pinmux_config pinmux_config; + system_pinmux_get_config_defaults(&pinmux_config); + + pinmux_config.mux_position = config->gpio_pin_mux; + pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; + pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; + pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; + system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); + + /* Get a pointer to the module hardware instance */ + Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel); + + uint32_t new_config; + + /* Determine the NMI's new edge detection configuration */ + new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos); + + /* Enable the hardware signal filter if requested in the config */ + if (config->filter_input_signal) { + new_config |= EIC_NMICTRL_NMIFILTEN; + } + + /* Disable EIC and general clock to configure NMI */ + _extint_disable(); + system_gclk_chan_disable(EIC_GCLK_ID); + + EIC_module->NMICTRL.reg = new_config; + + /* Enable the general clock and EIC after configure NMI */ + system_gclk_chan_enable(EIC_GCLK_ID); + _extint_enable(); + + return STATUS_OK; +} + +/** + * \brief Enables an External Interrupt event output. + * + * Enables one or more output events from the External Interrupt module. See + * \ref extint_events "here" for a list of events this module supports. + * + * \note Events cannot be altered while the module is enabled. + * + * \param[in] events Struct containing flags of events to enable + */ +void extint_enable_events( + struct extint_events *const events) +{ + /* Sanity check arguments */ + Assert(events); + + /* Array of available EICs. */ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + /* Update the event control register for each physical EIC instance */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + uint32_t event_mask = 0; + + /* Create an enable mask for the current EIC module */ + for (uint32_t j = 0; j < 32; j++) { + if (events->generate_event_on_detect[(32 * i) + j]) { + event_mask |= (1UL << j); + } + } + + /* Enable the masked events */ + eics[i]->EVCTRL.reg |= event_mask; + } +} + +/** + * \brief Disables an External Interrupt event output. + * + * Disables one or more output events from the External Interrupt module. See + * \ref extint_events "here" for a list of events this module supports. + * + * \note Events cannot be altered while the module is enabled. + * + * \param[in] events Struct containing flags of events to disable + */ +void extint_disable_events( + struct extint_events *const events) +{ + /* Sanity check arguments */ + Assert(events); + + /* Array of available EICs. */ + Eic *const eics[EIC_INST_NUM] = EIC_INSTS; + + /* Update the event control register for each physical EIC instance */ + for (uint32_t i = 0; i < EIC_INST_NUM; i++) { + uint32_t event_mask = 0; + + /* Create a disable mask for the current EIC module */ + for (uint32_t j = 0; j < 32; j++) { + if (events->generate_event_on_detect[(32 * i) + j]) { + event_mask |= (1UL << j); + } + } + + /* Disable the masked events */ + eics[i]->EVCTRL.reg &= ~event_mask; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/extint/extint.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/extint/extint.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/extint/extint_callback.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/extint/extint_callback.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/extint/extint_callback.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/extint/extint_callback.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/extint/extint_callback.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/port/port.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/port/port.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/port/port.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/port/port.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/port/port.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/rtc/rtc_sam_d_r/rtc_count.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMD21/rtc_count.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/rtc/rtc_sam_d_r/rtc_count.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMD21/rtc_count.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/module_config/conf_rtc.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/module_config/conf_rtc.h new file mode 100644 index 0000000000..f337c7ec4b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/module_config/conf_rtc.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief SAM RTC Driver Configuration Header + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CONF_RTC_H_INCLUDED +#define CONF_RTC_H_INCLUDED + +/** Select RTC clock. Use 1.024kHz from 32kHz internal ULP oscillator(OSCULP32K) + * for RTC clock. + */ +# define RTC_CLOCK_SOURCE RTC_CLOCK_SELECTION_ULP1K + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/rtc_count.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/rtc_count.c new file mode 100644 index 0000000000..e6b10d71b6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAML21/rtc_count.c @@ -0,0 +1,795 @@ +/** + * \file + * + * \brief SAM RTC Driver (Count Mode) + * + * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include "rtc_count.h" +#include +#include +#include "conf_rtc.h" + +#if !defined(__DOXYGEN__) +struct rtc_module *_rtc_instance[RTC_INST_NUM]; +#endif + +#if !defined(RTC_CLOCK_SOURCE) +# warning RTC_CLOCK_SOURCE is not defined, assuming RTC_CLOCK_SELECTION_ULP1K. +# define RTC_CLOCK_SOURCE RTC_CLOCK_SELECTION_ULP1K +#endif + +/** + * \brief Determines if the hardware module(s) are currently synchronizing to the bus. + * + * Checks to see if the underlying hardware peripheral module(s) are currently + * synchronizing across multiple clock domains to the hardware bus, This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * + * \param[in] module RTC hardware module + * + * \return Synchronization status of the underlying hardware module(s). + * + * \retval true if the module synchronization is ongoing + * \retval false if the module has completed synchronization + */ +static bool rtc_count_is_syncing(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + if (rtc_module->MODE0.SYNCBUSY.reg) { + return true; + } + + return false; +} + +/** + * \brief Enables the RTC module. + * + * Enables the RTC module once it has been configured, ready for use. Most + * module configuration parameters cannot be altered while the module is enabled. + * + * \param[in,out] module RTC hardware module + */ +void rtc_count_enable(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + +#if RTC_COUNT_ASYNC == true + system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC); +#endif + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Enable RTC module. */ + rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } +} + +/** + * \brief Disables the RTC module. + * + * Disables the RTC module. + * + * \param[in,out] module RTC hardware module + */ +void rtc_count_disable(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + +#if RTC_COUNT_ASYNC == true + system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC); +#endif + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Disable RTC module. */ + rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } +} + +/** + * \brief Resets the RTC module. + * Resets the RTC to hardware defaults. + * + * \param[in,out] module Pointer to the software instance struct + */ +void rtc_count_reset(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Disable module before reset. */ + rtc_count_disable(module); + +#if RTC_COUNT_ASYNC == true + module->registered_callback = 0; + module->enabled_callback = 0; +#endif + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Initiate software reset. */ + rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } +} + +/** + * \internal Applies the given configuration. + * + * Sets the configurations given from the configuration structure to the + * hardware module + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] config Pointer to the configuration structure + * + * \return Status of the configuration procedure. + * \retval STATUS_OK RTC configurations was set successfully + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given + */ +static enum status_code _rtc_count_set_config( + struct rtc_module *const module, + const struct rtc_count_config *const config) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + +#if SAML21 + rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0) | config->prescaler + | (config->enable_read_sync << RTC_MODE0_CTRLA_SYNCDIS_Pos); +#endif +#if (SAMC20) || (SAMC21) + rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0) | config->prescaler + | (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos); +#endif + + /* Set mode and clear on match if applicable. */ + switch (config->mode) { + case RTC_COUNT_MODE_32BIT: + /* Set 32-bit mode and clear on match if applicable. */ + rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(0); + + /* Check if clear on compare match should be set. */ + if (config->clear_on_match) { + /* Set clear on match. */ + rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + } + /* Set compare values. */ + for (uint8_t i = 0; i < RTC_COMP32_NUM; i++) { + rtc_count_set_compare(module, config->compare_values[i], + (enum rtc_count_compare)i); + } + break; + + case RTC_COUNT_MODE_16BIT: + /* Set 16bit mode. */ + rtc_module->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(1); + + /* Check if match on clear is set, and return invalid + * argument if set. */ + if (config->clear_on_match) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + /* Set compare values. */ + for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) { + rtc_count_set_compare(module, config->compare_values[i], + (enum rtc_count_compare)i); + } + break; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + /* Return status OK if everything was configured. */ + return STATUS_OK; +} + +/** + * \brief Initializes the RTC module with given configurations. + * + * Initializes the module, setting up all given configurations to provide + * the desired functionality of the RTC. + * + * \param[out] module Pointer to the software instance struct + * \param[in] hw Pointer to hardware instance + * \param[in] config Pointer to the configuration structure + * + * \return Status of the initialization procedure. + * \retval STATUS_OK If the initialization was run stressfully + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given + */ +enum status_code rtc_count_init( + struct rtc_module *const module, + Rtc *const hw, + const struct rtc_count_config *const config) +{ + /* Sanity check arguments */ + Assert(module); + Assert(hw); + Assert(config); + + /* Initialize device instance */ + module->hw = hw; + + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_RTC); + + /* Select RTC clock */ + OSC32KCTRL->RTCCTRL.reg = RTC_CLOCK_SOURCE; + + /* Reset module to hardware defaults. */ + rtc_count_reset(module); + + /* Save conf_struct internally for continued use. */ + module->mode = config->mode; + +# if (RTC_INST_NUM == 1) + _rtc_instance[0] = module; +# else + /* Register this instance for callbacks*/ + _rtc_instance[_rtc_get_inst_index(hw)] = module; +# endif + + /* Set config and return status. */ + return _rtc_count_set_config(module, config); +} + +/** + * \brief Set the current count value to desired value. + * + * Sets the value of the counter to the specified value. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] count_value The value to be set in count register + * + * \return Status of setting the register. + * \retval STATUS_OK If everything was executed correctly + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + */ +enum status_code rtc_count_set_count( + struct rtc_module *const module, + const uint32_t count_value) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Set count according to mode */ + switch(module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Write value to register. */ + rtc_module->MODE0.COUNT.reg = count_value; + break; + case RTC_COUNT_MODE_16BIT: + /* Check if 16-bit value is provided. */ + if(count_value > 0xffff) { + return STATUS_ERR_INVALID_ARG; + } + + /* Write value to register. */ + rtc_module->MODE1.COUNT.reg = (uint32_t)count_value; + + break; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + return STATUS_OK; +} + +/** + * \brief Get the current count value. + * + * \param[in,out] module Pointer to the software instance struct + * + * Returns the current count value. + * + * \return The current counter value as a 32-bit unsigned integer. + */ +uint32_t rtc_count_get_count(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Initialize return value. */ + uint32_t ret_val; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Read value based on mode. */ + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Return count value in 32-bit mode. */ + ret_val = rtc_module->MODE0.COUNT.reg; + + break; + + case RTC_COUNT_MODE_16BIT: + /* Return count value in 16-bit mode. */ + ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg; + + break; + + default: + Assert(false); + /* Counter not initialized. Assume counter value 0.*/ + ret_val = 0; + break; + } + + return ret_val; +} + +/** + * \brief Set the compare value for the specified compare. + * + * Sets the value specified by the implementer to the requested compare. + * + * \note Compare 4 and 5 are only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] comp_value The value to be written to the compare + * \param[in] comp_index Index of the compare to set + * + * \return Status indicating if compare was successfully set. + * \retval STATUS_OK If compare was successfully set + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode + */ +enum status_code rtc_count_set_compare( + struct rtc_module *const module, + const uint32_t comp_value, + const enum rtc_count_compare comp_index) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Set compare values based on operation mode. */ + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Check sanity of comp_index. */ + if ((uint32_t)comp_index > RTC_COMP32_NUM) { + return STATUS_ERR_INVALID_ARG; + } + + /* Set compare value for COMP. */ + rtc_module->MODE0.COMP[comp_index].reg = comp_value; + + break; + + case RTC_COUNT_MODE_16BIT: + /* Check sanity of comp_index. */ + if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { + return STATUS_ERR_INVALID_ARG; + } + + /* Check that 16-bit value is provided. */ + if (comp_value > 0xffff) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + /* Set compare value for COMP. */ + rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff; + + break; + + default: + Assert(false); + return STATUS_ERR_BAD_FORMAT; + } + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Return status if everything is OK. */ + return STATUS_OK; +} + +/** + * \brief Get the current compare value of specified compare. + * + * Retrieves the current value of the specified compare. + * + * \note Compare 4 and 5 are only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[out] comp_value Pointer to 32-bit integer that will be populated with + * the current compare value + * \param[in] comp_index Index of compare to check + * + * \return Status of the reading procedure. + * \retval STATUS_OK If the value was read correctly + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode + */ +enum status_code rtc_count_get_compare( + struct rtc_module *const module, + uint32_t *const comp_value, + const enum rtc_count_compare comp_index) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Check sanity of comp_index. */ + if ((uint32_t)comp_index > RTC_COMP32_NUM) { + return STATUS_ERR_INVALID_ARG; + } + + /* Get compare value for COMP. */ + *comp_value = rtc_module->MODE0.COMP[comp_index].reg; + + break; + + case RTC_COUNT_MODE_16BIT: + /* Check sanity of comp_index. */ + if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { + return STATUS_ERR_INVALID_ARG; + } + + /* Get compare value for COMP. */ + *comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg; + + break; + + default: + Assert(false); + return STATUS_ERR_BAD_FORMAT; + } + /* Return status showing everything is OK. */ + return STATUS_OK; +} + +/** + * \brief Retrieves the value of period. + * + * Retrieves the value of the period for the 16-bit mode counter. + * + * \note Only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[out] period_value Pointer to value for return argument + * + * \return Status of getting the period value. + * \retval STATUS_OK If the period value was read correctly + * \retval STATUS_ERR_UNSUPPORTED_DEV If incorrect mode was set + */ +enum status_code rtc_count_get_period( + struct rtc_module *const module, + uint16_t *const period_value) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Check that correct mode is set. */ + if (module->mode != RTC_COUNT_MODE_16BIT) { + return STATUS_ERR_UNSUPPORTED_DEV; + } + + /* Returns the value. */ + *period_value = rtc_module->MODE1.PER.reg; + + return STATUS_OK; +} + +/** + * \brief Set the given value to the period. + * + * Sets the given value to the period. + * + * \note Only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] period_value The value to set to the period + * + * \return Status of setting the period value. + * \retval STATUS_OK If the period was set correctly + * \retval STATUS_ERR_UNSUPPORTED_DEV If module is not operated in 16-bit mode + */ +enum status_code rtc_count_set_period( + struct rtc_module *const module, + const uint16_t period_value) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Check that correct mode is set. */ + if (module->mode != RTC_COUNT_MODE_16BIT) { + return STATUS_ERR_UNSUPPORTED_DEV; + } + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Write value to register. */ + rtc_module->MODE1.PER.reg = period_value; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + return STATUS_OK; +} + +/** + * \brief Check if RTC compare match has occurred. + * + * Checks the compare flag to see if a match has occurred. The compare flag is + * set when there is a compare match between counter and the compare. + * + * \note Compare 4 and 5 are only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] comp_index Index of compare to check current flag + */ +bool rtc_count_is_compare_match( + struct rtc_module *const module, + const enum rtc_count_compare comp_index) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Check sanity. */ + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Check sanity for 32-bit mode. */ + if (comp_index > RTC_COMP32_NUM) { + return false; + } + + break; + + case RTC_COUNT_MODE_16BIT: + /* Check sanity for 16-bit mode. */ + if (comp_index > RTC_NUM_OF_COMP16) { + return false; + } + + break; + + default: + Assert(false); + return false; + } + + /* Set status of INTFLAG as return argument. */ + return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP(1 << comp_index)) ? true : false; +} + +/** + * \brief Clears RTC compare match flag. + * + * Clears the compare flag. The compare flag is set when there is a compare + * match between the counter and the compare. + * + * \note Compare 4 and 5 are only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] comp_index Index of compare to check current flag + * + * \return Status indicating if flag was successfully cleared. + * \retval STATUS_OK If flag was successfully cleared + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode + */ +enum status_code rtc_count_clear_compare_match( + struct rtc_module *const module, + const enum rtc_count_compare comp_index) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Check sanity. */ + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Check sanity for 32-bit mode. */ + if (comp_index > RTC_COMP32_NUM) { + return STATUS_ERR_INVALID_ARG; + } + + break; + + case RTC_COUNT_MODE_16BIT: + /* Check sanity for 16-bit mode. */ + if (comp_index > RTC_NUM_OF_COMP16) { + return STATUS_ERR_INVALID_ARG; + } + + break; + + default: + Assert(false); + return STATUS_ERR_BAD_FORMAT; + } + + /* Clear INTFLAG. */ + rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index); + + return STATUS_OK; +} + +/** + * \brief Calibrate for too-slow or too-fast oscillator. + * + * When used, the RTC will compensate for an inaccurate oscillator. The + * RTC module will add or subtract cycles from the RTC prescaler to adjust the + * frequency in approximately 1 PPM steps. The provided correction value should + * be between 0 and 127, allowing for a maximum 127 PPM correction. + * + * If no correction is needed, set value to zero. + * + * \note Can only be used when the RTC is operated in 1Hz. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] value Ranging from -127 to 127 used for the correction + * + * \return Status of the calibration procedure. + * \retval STATUS_OK If calibration was executed correctly + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + */ +enum status_code rtc_count_frequency_correction( + struct rtc_module *const module, + const int8_t value) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Check if valid argument. */ + if (abs(value) > 0x7F) { + /* Value bigger than allowed, return invalid argument. */ + return STATUS_ERR_INVALID_ARG; + } + + uint32_t new_correction_value; + + /* Load the new correction value as a positive value, sign added later */ + new_correction_value = abs(value); + + /* Convert to positive value and adjust register sign bit. */ + if (value < 0) { + new_correction_value |= RTC_FREQCORR_SIGN; + } + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Set value. */ + rtc_module->MODE0.FREQCORR.reg = new_correction_value; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + return STATUS_OK; +} + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMR21/rtc_count.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMR21/rtc_count.c new file mode 100644 index 0000000000..e5fcc0daf8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/TARGET_SAMR21/rtc_count.c @@ -0,0 +1,773 @@ +/** + * \file + * + * \brief SAM RTC Driver (Count Mode) + * + * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include "rtc_count.h" +#include + +#if !defined(__DOXYGEN__) +struct rtc_module *_rtc_instance[RTC_INST_NUM]; +#endif + +/** + * \brief Determines if the hardware module(s) are currently synchronizing to the bus. + * + * Checks to see if the underlying hardware peripheral module(s) are currently + * synchronizing across multiple clock domains to the hardware bus, This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * + * \param[in] module RTC hardware module + * + * \return Synchronization status of the underlying hardware module(s). + * + * \retval true if the module synchronization is ongoing + * \retval false if the module has completed synchronization + */ +static bool rtc_count_is_syncing(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + if (rtc_module->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) { + return true; + } + + return false; +} + +/** + * \brief Enables the RTC module. + * + * Enables the RTC module once it has been configured, ready for use. Most + * module configuration parameters cannot be altered while the module is enabled. + * + * \param[in,out] module RTC hardware module + */ +void rtc_count_enable(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + +#if RTC_COUNT_ASYNC == true + system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC); +#endif + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Enable RTC module. */ + rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE; +} + +/** + * \brief Disables the RTC module. + * + * Disables the RTC module. + * + * \param[in,out] module RTC hardware module + */ +void rtc_count_disable(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + +#if RTC_COUNT_ASYNC == true + system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC); +#endif + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Disable RTC module. */ + rtc_module->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE; +} + +/** + * \brief Resets the RTC module. + * Resets the RTC to hardware defaults. + * + * \param[in,out] module Pointer to the software instance struct + */ +void rtc_count_reset(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Disable module before reset. */ + rtc_count_disable(module); + +#if RTC_COUNT_ASYNC == true + module->registered_callback = 0; + module->enabled_callback = 0; +#endif + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Initiate software reset. */ + rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST; +} + +/** + * \internal Applies the given configuration. + * + * Sets the configurations given from the configuration structure to the + * hardware module. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] config Pointer to the configuration structure. + * + * \return Status of the configuration procedure. + * \retval STATUS_OK RTC configurations was set successfully. + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given. + */ +static enum status_code _rtc_count_set_config( + struct rtc_module *const module, + const struct rtc_count_config *const config) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + rtc_module->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE(0) | config->prescaler; + + /* Set mode and clear on match if applicable. */ + switch (config->mode) { + case RTC_COUNT_MODE_32BIT: + /* Set 32bit mode and clear on match if applicable. */ + rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(0); + + /* Check if clear on compare match should be set. */ + if (config->clear_on_match) { + /* Set clear on match. */ + rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR; + } + /* Set compare values. */ + for (uint8_t i = 0; i < RTC_NUM_OF_COMP32; i++) { + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + rtc_count_set_compare(module, config->compare_values[i], + (enum rtc_count_compare)i); + } + break; + + case RTC_COUNT_MODE_16BIT: + /* Set 16bit mode. */ + rtc_module->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(1); + + /* Check if match on clear is set, and return invalid + * argument if set. */ + if (config->clear_on_match) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + /* Set compare values. */ + for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) { + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + rtc_count_set_compare(module, config->compare_values[i], + (enum rtc_count_compare)i); + } + break; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + /* Check to set continuously clock read update mode. */ + if (config->continuously_update) { + /* Set continuously mode. */ + rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT; + } + + /* Return status OK if everything was configured. */ + return STATUS_OK; +} + +/** + * \brief Initializes the RTC module with given configurations. + * + * Initializes the module, setting up all given configurations to provide + * the desired functionality of the RTC. + * + * \param[out] module Pointer to the software instance struct + * \param[in] hw Pointer to hardware instance + * \param[in] config Pointer to the configuration structure + * + * \return Status of the initialization procedure. + * \retval STATUS_OK If the initialization was run stressfully + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given + */ +enum status_code rtc_count_init( + struct rtc_module *const module, + Rtc *const hw, + const struct rtc_count_config *const config) +{ + /* Sanity check arguments */ + Assert(module); + Assert(hw); + Assert(config); + + /* Initialize device instance */ + module->hw = hw; + + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC); + + /* Set up GCLK */ + struct system_gclk_chan_config gclk_chan_conf; + system_gclk_chan_get_config_defaults(&gclk_chan_conf); + gclk_chan_conf.source_generator = GCLK_GENERATOR_2; + system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf); + system_gclk_chan_enable(RTC_GCLK_ID); + + /* Reset module to hardware defaults. */ + rtc_count_reset(module); + + /* Save conf_struct internally for continued use. */ + module->mode = config->mode; + module->continuously_update = config->continuously_update; + +# if (RTC_INST_NUM == 1) + _rtc_instance[0] = module; +# else + /* Register this instance for callbacks*/ + _rtc_instance[_rtc_get_inst_index(hw)] = module; +# endif + + /* Set config and return status. */ + return _rtc_count_set_config(module, config); +} + +/** + * \brief Set the current count value to desired value. + * + * Sets the value of the counter to the specified value. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] count_value The value to be set in count register + * + * \return Status of setting the register. + * \retval STATUS_OK If everything was executed correctly + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + */ +enum status_code rtc_count_set_count( + struct rtc_module *const module, + const uint32_t count_value) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Set count according to mode */ + switch(module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Write value to register. */ + rtc_module->MODE0.COUNT.reg = count_value; + + break; + + case RTC_COUNT_MODE_16BIT: + /* Check if 16-bit value is provided. */ + if(count_value > 0xffff) { + return STATUS_ERR_INVALID_ARG; + } + + /* Write value to register. */ + rtc_module->MODE1.COUNT.reg = (uint32_t)count_value; + + break; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + return STATUS_OK; +} + +/** + * \brief Get the current count value. + * + * \param[in,out] module Pointer to the software instance struct + * + * Returns the current count value. + * + * \return The current counter value as a 32-bit unsigned integer. + */ +uint32_t rtc_count_get_count(struct rtc_module *const module) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Initialize return value. */ + uint32_t ret_val; + + /* Change of read method based on value of continuously_update value in + * the configuration structure. */ + if(!(module->continuously_update)) { + /* Request read on count register. */ + rtc_module->MODE0.READREQ.reg = RTC_READREQ_RREQ; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + } + + /* Read value based on mode. */ + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Return count value in 32-bit mode. */ + ret_val = rtc_module->MODE0.COUNT.reg; + + break; + + case RTC_COUNT_MODE_16BIT: + /* Return count value in 16-bit mode. */ + ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg; + + break; + + default: + Assert(false); + /* Counter not initialized. Assume counter value 0.*/ + ret_val = 0; + break; + } + + return ret_val; +} + +/** + * \brief Set the compare value for the specified compare. + * + * Sets the value specified by the implementer to the requested compare. + * + * \note Compare 4 and 5 are only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] comp_value The value to be written to the compare + * \param[in] comp_index Index of the compare to set + * + * \return Status indicating if compare was successfully set. + * \retval STATUS_OK If compare was successfully set + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode + */ +enum status_code rtc_count_set_compare( + struct rtc_module *const module, + const uint32_t comp_value, + const enum rtc_count_compare comp_index) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Set compare values based on operation mode. */ + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Check sanity of comp_index. */ + if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) { + return STATUS_ERR_INVALID_ARG; + } + + /* Set compare value for COMP. */ + rtc_module->MODE0.COMP[comp_index].reg = comp_value; + + break; + + case RTC_COUNT_MODE_16BIT: + /* Check sanity of comp_index. */ + if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { + return STATUS_ERR_INVALID_ARG; + } + + /* Check that 16-bit value is provided. */ + if (comp_value > 0xffff) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + /* Set compare value for COMP. */ + rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff; + + break; + + default: + Assert(false); + return STATUS_ERR_BAD_FORMAT; + } + + /* Return status if everything is OK. */ + return STATUS_OK; +} + +/** + * \brief Get the current compare value of specified compare. + * + * Retrieves the current value of the specified compare. + * + * \note Compare 4 and 5 are only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[out] comp_value Pointer to 32-bit integer that will be populated with + * the current compare value + * \param[in] comp_index Index of compare to check + * + * \return Status of the reading procedure. + * \retval STATUS_OK If the value was read correctly + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode + */ +enum status_code rtc_count_get_compare( + struct rtc_module *const module, + uint32_t *const comp_value, + const enum rtc_count_compare comp_index) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Check sanity of comp_index. */ + if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) { + return STATUS_ERR_INVALID_ARG; + } + + /* Get compare value for COMP. */ + *comp_value = rtc_module->MODE0.COMP[comp_index].reg; + + break; + + case RTC_COUNT_MODE_16BIT: + /* Check sanity of comp_index. */ + if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) { + return STATUS_ERR_INVALID_ARG; + } + + /* Get compare value for COMP. */ + *comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg; + + break; + + default: + Assert(false); + return STATUS_ERR_BAD_FORMAT; + } + /* Return status showing everything is OK. */ + return STATUS_OK; +} + +/** + * \brief Retrieves the value of period. + * + * Retrieves the value of the period for the 16-bit mode counter. + * + * \note Only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[out] period_value Pointer to value for return argument + * + * \return Status of getting the period value. + * \retval STATUS_OK If the period value was read correctly + * \retval STATUS_ERR_UNSUPPORTED_DEV If incorrect mode was set + */ +enum status_code rtc_count_get_period( + struct rtc_module *const module, + uint16_t *const period_value) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Check that correct mode is set. */ + if (module->mode != RTC_COUNT_MODE_16BIT) { + return STATUS_ERR_UNSUPPORTED_DEV; + } + + /* Returns the value. */ + *period_value = rtc_module->MODE1.PER.reg; + + return STATUS_OK; +} + +/** + * \brief Set the given value to the period. + * + * Sets the given value to the period. + * + * \note Only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] period_value The value to set to the period + * + * \return Status of setting the period value. + * \retval STATUS_OK If the period was set correctly + * \retval STATUS_ERR_UNSUPPORTED_DEV If module is not operated in 16-bit mode + */ +enum status_code rtc_count_set_period( + struct rtc_module *const module, + const uint16_t period_value) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Check that correct mode is set. */ + if (module->mode != RTC_COUNT_MODE_16BIT) { + return STATUS_ERR_UNSUPPORTED_DEV; + } + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Write value to register. */ + rtc_module->MODE1.PER.reg = period_value; + + return STATUS_OK; +} + +/** + * \brief Check if RTC compare match has occurred. + * + * Checks the compare flag to see if a match has occurred. The compare flag is + * set when there is a compare match between counter and the compare. + * + * \note Compare 4 and 5 are only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] comp_index Index of compare to check current flag + */ +bool rtc_count_is_compare_match( + struct rtc_module *const module, + const enum rtc_count_compare comp_index) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Check sanity. */ + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Check sanity for 32-bit mode. */ + if (comp_index > RTC_NUM_OF_COMP32) { + return false; + } + + break; + + case RTC_COUNT_MODE_16BIT: + /* Check sanity for 16-bit mode. */ + if (comp_index > RTC_NUM_OF_COMP16) { + return false; + } + + break; + + default: + Assert(false); + return false; + } + + /* Set status of INTFLAG as return argument. */ + return (rtc_module->MODE0.INTFLAG.reg & (1 << comp_index)) ? true : false; +} + +/** + * \brief Clears RTC compare match flag. + * + * Clears the compare flag. The compare flag is set when there is a compare + * match between the counter and the compare. + * + * \note Compare 4 and 5 are only available in 16-bit mode. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] comp_index Index of compare to check current flag + * + * \return Status indicating if flag was successfully cleared. + * \retval STATUS_OK If flag was successfully cleared + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + * \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode + */ +enum status_code rtc_count_clear_compare_match( + struct rtc_module *const module, + const enum rtc_count_compare comp_index) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Check sanity. */ + switch (module->mode) { + case RTC_COUNT_MODE_32BIT: + /* Check sanity for 32-bit mode. */ + if (comp_index > RTC_NUM_OF_COMP32) { + return STATUS_ERR_INVALID_ARG; + } + + break; + + case RTC_COUNT_MODE_16BIT: + /* Check sanity for 16-bit mode. */ + if (comp_index > RTC_NUM_OF_COMP16) { + return STATUS_ERR_INVALID_ARG; + } + + break; + + default: + Assert(false); + return STATUS_ERR_BAD_FORMAT; + } + + /* Clear INTFLAG. */ + rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index); + + return STATUS_OK; +} + +/** + * \brief Calibrate for too-slow or too-fast oscillator. + * + * When used, the RTC will compensate for an inaccurate oscillator. The + * RTC module will add or subtract cycles from the RTC prescaler to adjust the + * frequency in approximately 1 PPM steps. The provided correction value should + * be between 0 and 127, allowing for a maximum 127 PPM correction. + * + * If no correction is needed, set value to zero. + * + * \note Can only be used when the RTC is operated in 1Hz. + * + * \param[in,out] module Pointer to the software instance struct + * \param[in] value Ranging from -127 to 127 used for the correction + * + * \return Status of the calibration procedure. + * \retval STATUS_OK If calibration was executed correctly + * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided + */ +enum status_code rtc_count_frequency_correction( + struct rtc_module *const module, + const int8_t value) +{ + /* Sanity check arguments */ + Assert(module); + Assert(module->hw); + + Rtc *const rtc_module = module->hw; + + /* Check if valid argument. */ + if (abs(value) > 0x7F) { + /* Value bigger than allowed, return invalid argument. */ + return STATUS_ERR_INVALID_ARG; + } + + uint32_t new_correction_value; + + /* Load the new correction value as a positive value, sign added later */ + new_correction_value = abs(value); + + /* Convert to positive value and adjust register sign bit. */ + if (value < 0) { + new_correction_value |= RTC_FREQCORR_SIGN; + } + + while (rtc_count_is_syncing(module)) { + /* Wait for synchronization */ + } + + /* Set value. */ + rtc_module->MODE0.FREQCORR.reg = new_correction_value; + + return STATUS_OK; +} + diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/rtc/rtc_count.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/rtc_count.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/rtc/rtc_count.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/rtc/rtc_count.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_common.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_common.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_common.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_common.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_master.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_master.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_master_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master_interrupt.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_master_interrupt.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_master_interrupt.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master_interrupt.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master_interrupt.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_slave.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_slave.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_slave.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_sam0/i2c_slave.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_slave.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_slave.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_slave_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave_interrupt.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/i2c/i2c_slave_interrupt.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/i2c/i2c_slave_interrupt.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom_interrupt.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom_interrupt.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom_interrupt.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_interrupt.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom_pinout.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_pinout.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/sercom_pinout.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/sercom_pinout.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/usart/usart.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/usart/usart.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/usart/usart.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/usart/usart.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/usart/usart_interrupt.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/usart/usart_interrupt.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/usart/usart_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/sercom/usart/usart_interrupt.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/sercom/usart/usart_interrupt.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/services/delay/delay.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/delay.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/services/delay/delay.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/delay.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/services/delay/sam0/systick_counter.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/services/delay/sam0/systick_counter.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/services/delay/sam0/systick_counter.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/services/delay/sam0/systick_counter.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/services/delay/sam0/systick_counter.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock_samd21_r21/clock.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock_samd21_r21/clock.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock_samd21_r21/clock_config_check.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_config_check.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock_samd21_r21/clock_config_check.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_config_check.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock_samd21_r21/clock_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_feature.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock_samd21_r21/clock_feature.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_feature.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock_samd21_r21/gclk.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/gclk.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock_samd21_r21/gclk.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/gclk.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock.c new file mode 100644 index 0000000000..f9190af4eb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock.c @@ -0,0 +1,1021 @@ +/** + * \file + * + * \brief SAM L21 Clock Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include +#include +#include + + +/** + * \internal + * \brief DFLL-specific data container. + */ +struct _system_clock_dfll_config { + uint32_t control; + uint32_t val; + uint32_t mul; +}; + +/** + * \internal + * \brief DPLL-specific data container. + */ +struct _system_clock_dpll_config { + uint32_t frequency; +}; + + +/** + * \internal + * \brief XOSC-specific data container. + */ +struct _system_clock_xosc_config { + uint32_t frequency; +}; + +/** + * \internal + * \brief System clock module data container. + */ +struct _system_clock_module { + volatile struct _system_clock_dfll_config dfll; + volatile struct _system_clock_dpll_config dpll; + + volatile struct _system_clock_xosc_config xosc; + volatile struct _system_clock_xosc_config xosc32k; +}; + +/** + * \internal + * \brief Internal module instance to cache configuration values. + */ +static struct _system_clock_module _system_clock_inst = { + .dfll = { + .control = 0, + .val = 0, + .mul = 0, + }, + .dpll = { + .frequency = 0, + }, + .xosc = { + .frequency = 0, + }, + .xosc32k = { + .frequency = 0, + }, +}; + +/** + * \internal + * \brief Wait for sync to the DFLL control registers. + */ +static inline void _system_dfll_wait_for_sync(void) +{ + while (!(OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY)) { + /* Wait for DFLL sync */ + } +} + +/** + * \internal + * \brief Wait for sync to the OSC32K control registers. + */ +static inline void _system_osc32k_wait_for_sync(void) +{ + while (!(OSC32KCTRL->STATUS.reg & OSC32KCTRL_STATUS_OSC32KRDY)) { + /* Wait for OSC32K sync */ + } +} + +/** + * \internal + * \brief OSC16M frequency selection. + * Frequency selection can be done only when OSC16M is disabled,thus, + * OSCULP32K is temporarily used as a new clocksource for mainclock . + * + */ +static inline void _system_clock_source_osc16m_freq_sel(void) +{ + struct system_gclk_gen_config gclk_conf; + struct system_clock_source_osc16m_config osc16m_conf; + + /* Select OSCULP32K as new clock source for mainclock temporarily */ + system_gclk_gen_get_config_defaults(&gclk_conf); + gclk_conf.source_clock = SYSTEM_CLOCK_SOURCE_ULP32K; + system_gclk_gen_set_config(GCLK_GENERATOR_0, &gclk_conf); + + /* GCLK0 is enabled after POR */ + + /* Disable OSC16M clock*/ + system_clock_source_disable(SYSTEM_CLOCK_SOURCE_OSC16M); + + /* Switch to new frequency selection and enable OSC16M */ + system_clock_source_osc16m_get_config_defaults(&osc16m_conf); + osc16m_conf.fsel = CONF_CLOCK_OSC16M_FREQ_SEL; + osc16m_conf.on_demand = 0; + osc16m_conf.run_in_standby = CONF_CLOCK_OSC16M_RUN_IN_STANDBY; + system_clock_source_osc16m_set_config(&osc16m_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC16M); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_OSC16M)); + + /* Select OSC16M for mainclock again */ + system_gclk_gen_get_config_defaults(&gclk_conf); + gclk_conf.source_clock = SYSTEM_CLOCK_SOURCE_OSC16M; + system_gclk_gen_set_config(GCLK_GENERATOR_0, &gclk_conf); + if (CONF_CLOCK_OSC16M_ON_DEMAND) { + OSCCTRL->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND; + } +} + +static inline void _system_clock_source_dfll_set_config_errata_9905(void) +{ + + /* Disable ONDEMAND mode while writing configurations */ + OSCCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~OSCCTRL_DFLLCTRL_ONDEMAND; + _system_dfll_wait_for_sync(); + + OSCCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; + OSCCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; + + /* Write full configuration to DFLL control register */ + OSCCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; +} + +/** + * \brief Retrieve the frequency of a clock source. + * + * Determines the current operating frequency of a given clock source. + * + * \param[in] clock_source Clock source to get the frequency of + * + * \returns Frequency of the given clock source, in Hz. + */ +uint32_t system_clock_source_get_hz( + const enum system_clock_source clock_source) +{ + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_XOSC: + return _system_clock_inst.xosc.frequency; + + case SYSTEM_CLOCK_SOURCE_OSC16M: + return (OSCCTRL->OSC16MCTRL.bit.FSEL+1)*4000000UL; + + case SYSTEM_CLOCK_SOURCE_OSC32K: + return 32768UL; + + case SYSTEM_CLOCK_SOURCE_ULP32K: + return 32768UL; + + case SYSTEM_CLOCK_SOURCE_XOSC32K: + return _system_clock_inst.xosc32k.frequency; + + case SYSTEM_CLOCK_SOURCE_DFLL: + + /* Check if the DFLL has been configured */ + if (!(_system_clock_inst.dfll.control & OSCCTRL_DFLLCTRL_ENABLE)) + return 0; + + /* Make sure that the DFLL module is ready */ + _system_dfll_wait_for_sync(); + + /* Check if operating in closed loop mode */ + if (_system_clock_inst.dfll.control & OSCCTRL_DFLLCTRL_MODE) { + return system_gclk_chan_get_hz(OSCCTRL_GCLK_ID_DFLL48) * + (_system_clock_inst.dfll.mul & 0xffff); + } + + return 48000000UL; + + case SYSTEM_CLOCK_SOURCE_DPLL: + if (!(OSCCTRL->DPLLCTRLA.reg & OSCCTRL_DPLLCTRLA_ENABLE)) { + return 0; + } + + return _system_clock_inst.dpll.frequency; + + default: + return 0; + } +} + +/** + * \brief Configure the internal OSC16M oscillator clock source. + * + * Configures the 16MHz (nominal) internal RC oscillator with the given + * configuration settings. + * + * \note Frequency selection can be done only when OSC16M is disabled. + * + * \param[in] config OSC16M configuration structure containing the new config + */ +void system_clock_source_osc16m_set_config( + struct system_clock_source_osc16m_config *const config) +{ + OSCCTRL_OSC16MCTRL_Type temp = OSCCTRL->OSC16MCTRL; + + /* Use temporary struct to reduce register access */ + temp.bit.FSEL = config->fsel; + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + + OSCCTRL->OSC16MCTRL = temp; +} + +/** + * \brief Configure the internal OSC32K oscillator clock source. + * + * Configures the 32KHz (nominal) internal RC oscillator with the given + * configuration settings. + * + * \param[in] config OSC32K configuration structure containing the new config + */ +void system_clock_source_osc32k_set_config( + struct system_clock_source_osc32k_config *const config) +{ + OSC32KCTRL_OSC32K_Type temp = OSC32KCTRL->OSC32K; + + + /* Update settings via a temporary struct to reduce register access */ + temp.bit.EN1K = config->enable_1khz_output; + temp.bit.EN32K = config->enable_32khz_output; + temp.bit.STARTUP = config->startup_time; + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + temp.bit.WRTLOCK = config->write_once; + + OSC32KCTRL->OSC32K = temp; +} + +/** + * \brief Configure the internal OSCULP32K oscillator clock source. + * + * Configures the Ultra Low Power 32KHz internal RC oscillator with the given + * configuration settings. + * + * \note The OSCULP32K is enabled by default after a Power On Reset (POR) and + * will always run except during POR. + * + * \param[in] config OSCULP32K configuration structure containing the new config + */ +void system_clock_source_osculp32k_set_config( + struct system_clock_source_osculp32k_config *const config) +{ + OSC32KCTRL_OSCULP32K_Type temp = OSC32KCTRL->OSCULP32K; + /* Update settings via a temporary struct to reduce register access */ + temp.bit.WRTLOCK = config->write_once; + OSC32KCTRL->OSCULP32K = temp; +} + +/** + * \brief Configure the external oscillator clock source. + * + * Configures the external oscillator clock source with the given configuration + * settings. + * + * \param[in] config External oscillator configuration structure containing + * the new config + */ +void system_clock_source_xosc_set_config( + struct system_clock_source_xosc_config *const config) +{ + OSCCTRL_XOSCCTRL_Type temp = OSCCTRL->XOSCCTRL; + + temp.bit.STARTUP = config->startup_time; + + if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { + temp.bit.XTALEN = 1; + } else { + temp.bit.XTALEN = 0; + } + + temp.bit.AMPGC = config->auto_gain_control; + + /* Set gain if automatic gain control is not selected */ + if (!config->auto_gain_control) { + if (config->frequency <= 2000000) { + temp.bit.GAIN = 0; + } else if (config->frequency <= 4000000) { + temp.bit.GAIN = 1; + } else if (config->frequency <= 8000000) { + temp.bit.GAIN = 2; + } else if (config->frequency <= 16000000) { + temp.bit.GAIN = 3; + } else if (config->frequency <= 30000000) { + temp.bit.GAIN = 4; + } + + } + + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + + /* Store XOSC frequency for internal use */ + _system_clock_inst.xosc.frequency = config->frequency; + + OSCCTRL->XOSCCTRL = temp; +} + +/** + * \brief Configure the XOSC32K external 32KHz oscillator clock source. + * + * Configures the external 32KHz oscillator clock source with the given + * configuration settings. + * + * \param[in] config XOSC32K configuration structure containing the new config + */ +void system_clock_source_xosc32k_set_config( + struct system_clock_source_xosc32k_config *const config) +{ + OSC32KCTRL_XOSC32K_Type temp = OSC32KCTRL->XOSC32K; + + temp.bit.STARTUP = config->startup_time; + + if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { + temp.bit.XTALEN = 1; + } else { + temp.bit.XTALEN = 0; + } + + temp.bit.EN1K = config->enable_1khz_output; + temp.bit.EN32K = config->enable_32khz_output; + + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + temp.bit.WRTLOCK = config->write_once; + + /* Cache the new frequency in case the user needs to check the current + * operating frequency later */ + _system_clock_inst.xosc32k.frequency = config->frequency; + + OSC32KCTRL->XOSC32K = temp; +} + +/** + * \brief Configure the DFLL clock source. + * + * Configures the Digital Frequency Locked Loop clock source with the given + * configuration settings. + * + * \note The DFLL will be running when this function returns, as the DFLL module + * needs to be enabled in order to perform the module configuration. + * + * \param[in] config DFLL configuration structure containing the new config + */ +void system_clock_source_dfll_set_config( + struct system_clock_source_dfll_config *const config) +{ + _system_clock_inst.dfll.val = + OSCCTRL_DFLLVAL_COARSE(config->coarse_value) | + OSCCTRL_DFLLVAL_FINE(config->fine_value); + + _system_clock_inst.dfll.control = + (uint32_t)config->wakeup_lock | + (uint32_t)config->stable_tracking | + (uint32_t)config->quick_lock | + (uint32_t)config->chill_cycle | + ((uint32_t)config->on_demand << OSCCTRL_DFLLCTRL_ONDEMAND_Pos) | + ((uint32_t)config->run_in_stanby << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos); + + if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + + _system_clock_inst.dfll.mul = + OSCCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | + OSCCTRL_DFLLMUL_FSTEP(config->fine_max_step) | + OSCCTRL_DFLLMUL_MUL(config->multiply_factor); + + /* Enable the closed loop mode */ + _system_clock_inst.dfll.control |= config->loop_mode; + } + if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { + + _system_clock_inst.dfll.mul = + OSCCTRL_DFLLMUL_MUL(config->multiply_factor); + + /* Enable the USB recovery mode */ + _system_clock_inst.dfll.control |= config->loop_mode | + OSCCTRL_DFLLCTRL_BPLCKC; + } +} + +/** + * \brief Configure the DPLL clock source. + * + * Configures the Digital Phase-Locked Loop clock source with the given + * configuration settings. + * + * \note The DPLL will be running when this function returns, as the DPLL module + * needs to be enabled in order to perform the module configuration. + * + * \param[in] config DPLL configuration structure containing the new config + */ +void system_clock_source_dpll_set_config( + struct system_clock_source_dpll_config *const config) +{ + + uint32_t tmpldr; + uint8_t tmpldrfrac; + uint32_t refclk; + + refclk = config->reference_frequency; + + /* Only reference clock REF1 can be divided */ + if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { + refclk = refclk / (2 * (config->reference_divider + 1)); + } + + /* Calculate LDRFRAC and LDR */ + tmpldr = (config->output_frequency << 4) / refclk; + tmpldrfrac = tmpldr & 0x0f; + tmpldr = (tmpldr >> 4) - 1; + + OSCCTRL->DPLLCTRLA.reg = + ((uint32_t)config->on_demand << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) | + ((uint32_t)config->run_in_standby << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos); + + OSCCTRL->DPLLRATIO.reg = + OSCCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | + OSCCTRL_DPLLRATIO_LDR(tmpldr); + + while(OSCCTRL->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) { + } + + OSCCTRL->DPLLCTRLB.reg = + OSCCTRL_DPLLCTRLB_DIV(config->reference_divider) | + ((uint32_t)config->lock_bypass << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | + OSCCTRL_DPLLCTRLB_LTIME(config->lock_time) | + OSCCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | + ((uint32_t)config->wake_up_fast << OSCCTRL_DPLLCTRLB_WUF_Pos) | + ((uint32_t)config->low_power_enable << OSCCTRL_DPLLCTRLB_LPEN_Pos) | + OSCCTRL_DPLLCTRLB_FILTER(config->filter); + + OSCCTRL->DPLLPRESC.reg = OSCCTRL_DPLLPRESC_PRESC(config->prescaler); + while(OSCCTRL->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) { + } + /* + * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) + */ + _system_clock_inst.dpll.frequency = + (refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4; +} + +/** + * \brief Writes the calibration values for a given oscillator clock source. + * + * Writes an oscillator calibration value to the given oscillator control + * registers. The acceptable ranges are: + * + * For OSC32K: + * - 7 bits (max value 128) + * For OSC16MHZ: + * - 8 bits (Max value 255) + * For OSCULP: + * - 5 bits (Max value 32) + * + * \note The frequency range parameter applies only when configuring the 8MHz + * oscillator and will be ignored for the other oscillators. + * + * \param[in] clock_source Clock source to calibrate + * \param[in] calibration_value Calibration value to write + * \param[in] freq_range Frequency range (8MHz oscillator only) + * + * \retval STATUS_OK The calibration value was written + * successfully. + * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock + * source. + */ +enum status_code system_clock_source_write_calibration( + const enum system_clock_source clock_source, + const uint16_t calibration_value, + const uint8_t freq_select) +{ + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC16M: + //to enable DSU test mode and add calibration value + return STATUS_OK; + + case SYSTEM_CLOCK_SOURCE_OSC32K: + + if (calibration_value > 128) { + return STATUS_ERR_INVALID_ARG; + } + + _system_osc32k_wait_for_sync(); + OSC32KCTRL->OSC32K.bit.CALIB = calibration_value; + break; + + case SYSTEM_CLOCK_SOURCE_ULP32K: + + if (calibration_value > 32) { + return STATUS_ERR_INVALID_ARG; + } + + OSC32KCTRL->OSCULP32K.bit.CALIB = calibration_value; + break; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + break; + } + + return STATUS_OK; +} + +/** + * \brief Enables a clock source. + * + * Enables a clock source which has been previously configured. + * + * \param[in] clock_source Clock source to enable + * + * \retval STATUS_OK Clock source was enabled successfully and + * is ready + * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this + * device + */ +enum status_code system_clock_source_enable( + const enum system_clock_source clock_source) +{ + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC16M: + OSCCTRL->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ENABLE; + return STATUS_OK; + + case SYSTEM_CLOCK_SOURCE_OSC32K: + OSC32KCTRL->OSC32K.reg |= OSC32KCTRL_OSC32K_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC: + OSCCTRL->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC32K: + OSC32KCTRL->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_DFLL: + _system_clock_inst.dfll.control |= OSCCTRL_DFLLCTRL_ENABLE; + _system_clock_source_dfll_set_config_errata_9905(); + break; + + case SYSTEM_CLOCK_SOURCE_DPLL: + OSCCTRL->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + while(OSCCTRL->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) { + } + break; + + case SYSTEM_CLOCK_SOURCE_ULP32K: + /* Always enabled */ + return STATUS_OK; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + return STATUS_OK; +} + +/** + * \brief Disables a clock source. + * + * Disables a clock source that was previously enabled. + * + * \param[in] clock_source Clock source to disable + * + * \retval STATUS_OK Clock source was disabled successfully + * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was + * given + */ +enum status_code system_clock_source_disable( + const enum system_clock_source clock_source) +{ + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC16M: + OSCCTRL->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_OSC32K: + OSC32KCTRL->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC: + OSCCTRL->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC32K: + OSC32KCTRL->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_DFLL: + _system_clock_inst.dfll.control &= ~OSCCTRL_DFLLCTRL_ENABLE; + OSCCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; + break; + case SYSTEM_CLOCK_SOURCE_DPLL: + OSCCTRL->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + break; + case SYSTEM_CLOCK_SOURCE_ULP32K: + /* Not possible to disable */ + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + + } + + return STATUS_OK; + } + + /** + * \brief Checks if a clock source is ready. + * + * Checks if a given clock source is ready to be used. + * + * \param[in] clock_source Clock source to check if ready + * + * \returns Ready state of the given clock source. + * + * \retval true Clock source is enabled and ready + * \retval false Clock source is disabled or not yet ready + */ + bool system_clock_source_is_ready( + const enum system_clock_source clock_source) +{ + uint32_t mask = 0; + + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC16M: + mask = OSCCTRL_STATUS_OSC16MRDY; + return ((OSCCTRL->STATUS.reg & mask) == mask); + + case SYSTEM_CLOCK_SOURCE_OSC32K: + mask = OSC32KCTRL_STATUS_OSC32KRDY; + return ((OSC32KCTRL->STATUS.reg & mask) == mask); + + case SYSTEM_CLOCK_SOURCE_XOSC: + mask = OSCCTRL_STATUS_XOSCRDY; + return ((OSCCTRL->STATUS.reg & mask) == mask); + + case SYSTEM_CLOCK_SOURCE_XOSC32K: + mask = OSC32KCTRL_STATUS_XOSC32KRDY; + return ((OSC32KCTRL->STATUS.reg & mask) == mask); + + case SYSTEM_CLOCK_SOURCE_DFLL: + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + mask = (OSCCTRL_STATUS_DFLLRDY | + OSCCTRL_STATUS_DFLLLCKF | OSCCTRL_STATUS_DFLLLCKC); + } else { + mask = OSCCTRL_STATUS_DFLLRDY; + } + return ((OSCCTRL->STATUS.reg & mask) == mask); + + case SYSTEM_CLOCK_SOURCE_DPLL: + return ((OSCCTRL->DPLLSTATUS.reg & + (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK)) == + (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK)); + case SYSTEM_CLOCK_SOURCE_ULP32K: + /* Not possible to disable */ + return true; + + default: + return false; + } +} + +/* Include some checks for conf_clocks.h validation */ +#include "clock_config_check.h" + +#if !defined(__DOXYGEN__) +/** \internal + * + * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h. + */ +# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \ + if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \ + struct system_gclk_gen_config gclk_conf; \ + system_gclk_gen_get_config_defaults(&gclk_conf); \ + gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \ + gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \ + gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \ + gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \ + system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \ + system_gclk_gen_enable(GCLK_GENERATOR_##n); \ + } + +/** \internal + * + * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h, + * provided that it is not the main Generic Clock Generator channel. + */ +# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \ + if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); } +#endif + +/** + * \brief Initialize clock system based on the configuration in conf_clocks.h. + * + * This function will apply the settings in conf_clocks.h when run from the user + * application. All clock sources and GCLK generators are running when this function + * returns. + * + * \note OSC16M is always enabled and if user selects other clocks for GCLK generators, + * the OSC16M default enable can be disabled after system_clock_init. Make sure the + * clock switches successfully before disabling OSC8M. + */ +void system_clock_init(void) +{ + /* Various bits in the INTFLAG register can be set to one at startup. + This will ensure that these bits are cleared */ + OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; + SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY | SUPC_INTFLAG_BOD33DET; + + system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); + + /* Switch to PL2 to be sure configuration of GCLK0 is safe */ + system_switch_performance_level(SYSTEM_PERFORMANCE_LEVEL_2); + + /* XOSC */ +#if CONF_CLOCK_XOSC_ENABLE == true + struct system_clock_source_xosc_config xosc_conf; + system_clock_source_xosc_get_config_defaults(&xosc_conf); + + xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; + xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; + xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; + xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; + xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; + xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; + + system_clock_source_xosc_set_config(&xosc_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); +#endif + + /* XOSC32K */ +#if CONF_CLOCK_XOSC32K_ENABLE == true + struct system_clock_source_xosc32k_config xosc32k_conf; + system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); + + xosc32k_conf.frequency = 32768UL; + xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; + xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; + xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; + xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; + xosc32k_conf.on_demand = false; + xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; + + system_clock_source_xosc32k_set_config(&xosc32k_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); + if (CONF_CLOCK_XOSC32K_ON_DEMAND) { + OSC32KCTRL->XOSC32K.bit.ONDEMAND = 1; + } +#endif + + /* OSCK32K */ +#if CONF_CLOCK_OSC32K_ENABLE == true + + struct system_clock_source_osc32k_config osc32k_conf; + system_clock_source_osc32k_get_config_defaults(&osc32k_conf); + + osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; + osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; + osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; + osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; + osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; + + system_clock_source_osc32k_set_config(&osc32k_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); +#endif + + /* OSC16M */ + if (CONF_CLOCK_OSC16M_FREQ_SEL == SYSTEM_OSC16M_4M) { + OSCCTRL->OSC16MCTRL.bit.ONDEMAND = CONF_CLOCK_OSC16M_ON_DEMAND ; + OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = CONF_CLOCK_OSC16M_RUN_IN_STANDBY; + } else { + _system_clock_source_osc16m_freq_sel(); + } + + /* DFLL Config (Open and Closed Loop) */ +#if CONF_CLOCK_DFLL_ENABLE == true + struct system_clock_source_dfll_config dfll_conf; + system_clock_source_dfll_get_config_defaults(&dfll_conf); + + dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; + dfll_conf.on_demand = false; + dfll_conf.run_in_stanby = CONF_CLOCK_DFLL_RUN_IN_STANDBY; + + /* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping + in DFLL.COARSE helps to output a frequency close to 48 MHz.*/ +#define NVM_DFLL_COARSE_POS 26 /* DFLL48M Coarse calibration value bit position.*/ +#define NVM_DFLL_COARSE_SIZE 6 /* DFLL48M Coarse calibration value bit size.*/ + + uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP5) + + (NVM_DFLL_COARSE_POS / 32)) + >> (NVM_DFLL_COARSE_POS % 32)) + & ((1 << NVM_DFLL_COARSE_SIZE) - 1); + /* In some revision chip, the Calibration value is not correct */ + if (coarse == 0x3f) { + coarse = 0x1f; + } + + dfll_conf.coarse_value = coarse; + + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { + dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; + } + +# if CONF_CLOCK_DFLL_QUICK_LOCK == true + dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; +# else + dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; +# endif + +# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true + dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; +# else + dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; +# endif + +# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true + dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; +# else + dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; +# endif + +# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true + dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; +# else + dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; +# endif + + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; + } + + dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; + dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; + + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { + dfll_conf.fine_value = 0x1ff; + dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; + dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; + dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; + dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; + + dfll_conf.multiply_factor = 48000; + } + + system_clock_source_dfll_set_config(&dfll_conf); +#endif + + /* GCLK */ +#if CONF_CLOCK_CONFIGURE_GCLK == true + system_gclk_init(); + + /* Configure all GCLK generators except for the main generator, which + * is configured later after all other clock systems are set up */ + MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); +# if CONF_CLOCK_DFLL_ENABLE == true + /* Enable DFLL reference clock if in closed loop mode */ + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + struct system_gclk_chan_config dfll_gclk_chan_conf; + + system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); + dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; + system_gclk_chan_set_config(OSCCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); + system_gclk_chan_enable(OSCCTRL_GCLK_ID_DFLL48); + } +# endif + +# if CONF_CLOCK_DPLL_ENABLE == true + /* Enable DPLL internal lock timer and reference clock */ + struct system_gclk_chan_config dpll_gclk_chan_conf; + system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf); + if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) { + dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR; + system_gclk_chan_set_config(OSCCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf); + system_gclk_chan_enable(OSCCTRL_GCLK_ID_FDPLL32K); + } + + if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { + dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR; + system_gclk_chan_set_config(OSCCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf); + system_gclk_chan_enable(OSCCTRL_GCLK_ID_FDPLL); + } +# endif +#endif + + /* DFLL Enable (Open and Closed Loop) */ +#if CONF_CLOCK_DFLL_ENABLE == true + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); + if (CONF_CLOCK_DFLL_ON_DEMAND) { + OSCCTRL->DFLLCTRL.bit.ONDEMAND = 1; + } +#endif + + /* DPLL */ +# if (CONF_CLOCK_DPLL_ENABLE == true) + + /* Enable DPLL reference clock */ + if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) { + /* XOSC32K should have been enabled for GCLK_XOSC32 */ + Assert(CONF_CLOCK_XOSC32K_ENABLE); + } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { + /* XOSC should have been enabled for GCLK_XOSC */ + Assert(CONF_CLOCK_XOSC_ENABLE); + } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { + /* GCLK should have been enabled */ + Assert(CONF_CLOCK_CONFIGURE_GCLK); + } else { + Assert(false); + } + + struct system_clock_source_dpll_config dpll_config; + system_clock_source_dpll_get_config_defaults(&dpll_config); + + dpll_config.on_demand = false; + dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; + dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; + dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; + dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; + + dpll_config.filter = CONF_CLOCK_DPLL_FILTER; + dpll_config.lock_time = CONF_CLOCK_DPLL_LOCK_TIME; + + dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; + dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; + dpll_config.reference_divider = CONF_CLOCK_DPLL_REFERENCE_DIVIDER; + dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; + dpll_config.prescaler = CONF_CLOCK_DPLL_PRESCALER; + + system_clock_source_dpll_set_config(&dpll_config); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); + if (CONF_CLOCK_DPLL_ON_DEMAND) { + OSCCTRL->DPLLCTRLA.bit.ONDEMAND = 1; + } + +# endif + + /* CPU and BUS clocks */ + system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); + system_main_clock_set_failure_detect(CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT); + system_low_power_clock_set_divider(CONF_CLOCK_LOW_POWER_DIVIDER); + system_backup_clock_set_divider(CONF_CLOCK_BACKUP_DIVIDER); + + /* GCLK 0 */ +#if CONF_CLOCK_CONFIGURE_GCLK == true + /* Configure the main GCLK last as it might depend on other generators */ + _CONF_CLOCK_GCLK_CONFIG(0, ~); +#endif + + /* If CPU frequency is less than 12MHz, scale down performance level to PL0 */ + uint32_t cpu_freq = system_cpu_clock_get_hz(); + if (cpu_freq <= 12000000) { + system_switch_performance_level(SYSTEM_PERFORMANCE_LEVEL_0); + } +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_config_check.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_config_check.h new file mode 100644 index 0000000000..62156d8126 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_config_check.h @@ -0,0 +1,459 @@ +/** + * \file + * + * \brief SAM L21 Clock Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CLOCK_CONFIG_CHECK_H +# define CLOCK_CONFIG_CHECK_H + +#if !defined(CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT) +# error CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_FLASH_WAIT_STATES) +# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_CPU_DIVIDER) +# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_LOW_POWER_DIVIDER) +# error CONF_CLOCK_LOW_POWER_DIVIDER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_BACKUP_DIVIDER) +# error CONF_CLOCK_BACK_DIVIDER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC16M_FREQ_SEL) +# error CONF_CLOCK_OSC16M_FREQ_SEL not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC16M_ON_DEMAND) +# error CONF_CLOCK_OSC16M_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC16M_RUN_IN_STANDBY) +# error CONF_CLOCK_OSC16M_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_ENABLE) +# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL) +# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY) +# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME) +# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL) +# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_ON_DEMAND) +# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY) +# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ENABLE) +# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL) +# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME) +# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT) +# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT) +# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND) +# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY) +# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ENABLE) +# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME) +# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT) +# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT) +# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND) +# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY) +# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_ENABLE) +# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_LOOP_MODE) +# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_ON_DEMAND) +# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_FINE_VALUE) +# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_RUN_IN_STANDBY) +# error CONF_CLOCK_DFLL_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR) +# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR) +# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK) +# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK) +# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP) +# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE) +# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE) +# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE) +# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_ENABLE) +# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_ON_DEMAND) +# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY) +# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS) +# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST) +# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE) +# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOCK_TIME) +# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK) +# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_FILTER) +# error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY) +# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER) +# error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY) +# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_PRESCALER) +# error CONF_CLOCK_DPLL_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR) +# error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR) +# error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h +#endif + + +#if !defined(CONF_CLOCK_CONFIGURE_GCLK) +# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_ENABLE) +# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_PRESCALER) +# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_ENABLE) +# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_PRESCALER) +# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_ENABLE) +# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_PRESCALER) +# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_ENABLE) +# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_PRESCALER) +# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_ENABLE) +# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_PRESCALER) +# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_ENABLE) +# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_PRESCALER) +# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_ENABLE) +# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_PRESCALER) +# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_ENABLE) +# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_PRESCALER) +# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_ENABLE) +# error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_PRESCALER) +# error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#endif /* CLOCK_CONFIG_CHECK_H */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_feature.h new file mode 100644 index 0000000000..79abcf751c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_feature.h @@ -0,0 +1,1488 @@ +/** + * \file + * + * \brief SAM L21 Clock Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED +#define SYSTEM_CLOCK_FEATURE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management (SYSTEM CLOCK) Driver + * + * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration + * and management of the device's clocking related functions. This includes + * the various clock sources, bus clocks, and generic clocks within the device, + * with functions to manage the enabling, disabling, source selection, and + * prescaling of clocks to various internal peripherals. + * + * The following peripherals are used by this module: + * + * - GCLK (Generic Clock Management) + * - PM (Power Management) + * - OSCCTRL (Oscillators Controller) + * - OSC32KCTRL (32K Oscillators Controller) + * - MCLK (Main Clock) + * + * The following devices can use this module: + * - Atmel | SMART SAM L21 + * + * The outline of this documentation is as follows: + * - \ref asfdoc_sam0_system_clock_prerequisites + * - \ref asfdoc_sam0_system_clock_module_overview + * - \ref asfdoc_sam0_system_clock_special_considerations + * - \ref asfdoc_sam0_system_clock_extra_info + * - \ref asfdoc_sam0_system_clock_examples + * - \ref asfdoc_sam0_system_clock_api_overview + * + * + * \section asfdoc_sam0_system_clock_prerequisites Prerequisites + * + * There are no prerequisites for this module. + * + * + * \section asfdoc_sam0_system_clock_module_overview Module Overview + * The SAM devices contain a sophisticated clocking system, which is designed + * to give the maximum flexibility to the user application. This system allows + * a system designer to tune the performance and power consumption of the device + * in a dynamic manner, to achieve the best trade-off between the two for a + * particular application. + * + * This driver provides a set of functions for the configuration and management + * of the various clock related functionalities within the device. + * + * + * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources + * The SAM devices have a number of master clock source modules, each of + * which being capable of producing a stabilized output frequency which can then + * be fed into the various peripherals and modules within the device. + * + * Possible clock source modules include internal R/C oscillators, internal + * DFLL modules, as well as external crystal oscillators and/or clock inputs. + * + * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks + * The CPU and AHB/APBx buses are clocked by the same physical clock source + * (referred in this module as the Main Clock). + * The CPU and bus clocks are divided into a number of clock domains. Each clock domain can + * run at different frequencies. + * + * There are three clock domains: + * + * - CPU Clock Domain + * - Low Power Clock Domain(LP Clock Domain) + * - Backup Clock Domain(BUP Clock Domain) + * + * Each clock domain (CPU, LP, BUP) can be changed on the fly. To ensure + * correct operation, frequencies must be selected so that BUPDIV ≥ LPDIV ≥ HSDIV. + * Also, frequencies must never exceed the specified maximum frequency for each clock domain. + * A module may be connected to several clock domains (for instance, AHB and APB). + * + * The general main clock tree for the CPU and associated buses is shown in + * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below". + * + * \anchor asfdoc_sam0_system_clock_module_clock_tree + * \dot + * digraph overview { + * rankdir=LR; + * clk_src [label="Clock Sources", shape=none, height=0]; + * node [label="CPU Bus" shape=ellipse] cpu_bus; + * node [label="AHB Bus" shape=ellipse] ahb_bus; + * node [label="APBx Bus" shape=ellipse] apb_bus; + * node [label="Main Bus\nPrescaler" shape=square] main_prescaler; + * node [label="CPU Clock\nPrescaler" shape=square] cpu_prescaler; + * node [label="Low Power Clock\nPrescaler" shape=square] low_power_prescaler; + * node [label="Backup clock\nPrescaler" shape=square] backup_prescaler; + * node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux; + * + * clk_src -> main_clock_mux; + * main_clock_mux -> main_prescaler; + * main_prescaler -> cpu_prescaler; + * main_prescaler -> low_power_prescaler; + * main_prescaler -> backup_prescaler; + * cpu_prescaler -> cpu_bus; + * cpu_prescaler -> ahb_bus; + * cpu_prescaler -> apb_bus; + * low_power_prescaler -> ahb_bus; + * low_power_prescaler -> apb_bus; + * backup_prescaler -> apb_bus; + * } + * \enddot + * + * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking + * To save power, the input clock to one or more peripherals on the AHB and APBx + * buses can be masked away. When masked, no clock is passed into the module. + * Disabling of clocks of unused modules will prevent all access to the masked + * module, but will reduce the overall device power consumption. + * + * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks + * Within the SAM devices are a number of Generic Clocks; these are used to + * provide clocks to the various peripheral clock domains in the device in a + * standardized manner. One or more master source clocks can be selected as the + * input clock to a Generic Clock Generator, which can prescale down the input + * frequency to a slower rate for use in a peripheral. + * + * Additionally, a number of individually selectable Generic Clock Channels are + * provided, which multiplex and gate the various generator outputs for one or + * more peripherals within the device. This setup allows for a single common + * generator to feed one or more channels, which can then be enabled or disabled + * individually as required. + * + * \anchor asfdoc_sam0_system_clock_module_chain_overview + * \dot + * digraph overview { + * rankdir=LR; + * node [label="Clock\nSource a" shape=square] system_clock_source; + * node [label="Generator n" shape=square] clock_gen; + * node [label="Channel x" shape=square] clock_chan0; + * node [label="Channel y" shape=square] clock_chan1; + * node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0; + * node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1; + * + * system_clock_source -> clock_gen; + * clock_gen -> clock_chan0; + * clock_chan0 -> peripheral0; + * clock_gen -> clock_chan1; + * clock_chan1 -> peripheral1; + * } + * \enddot + * + * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example + * An example setup of a complete clock chain within the device is shown in + * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below". + * + * \anchor asfdoc_sam0_system_clock_module_chain_example_fig + * \dot + * digraph overview { + * rankdir=LR; + * node [label="External\nOscillator" shape=square] system_clock_source0; + * node [label="Generator 0" shape=square] clock_gen0; + * node [label="Channel x" shape=square] clock_chan0; + * node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0; + * + * system_clock_source0 -> clock_gen0; + * clock_gen0 -> clock_chan0; + * clock_chan0 -> peripheral0; + * node [label="16MHz R/C\nOscillator (OSC16M)" shape=square fillcolor=white] system_clock_source1; + * node [label="Generator 1" shape=square] clock_gen1; + * node [label="Channel y" shape=square] clock_chan1; + * node [label="Channel z" shape=square] clock_chan2; + * node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1; + * node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2; + * + * system_clock_source1 -> clock_gen1; + * clock_gen1 -> clock_chan1; + * clock_gen1 -> clock_chan2; + * clock_chan1 -> peripheral1; + * clock_chan2 -> peripheral2; + * } + * \enddot + * + * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators + * Each Generic Clock generator within the device can source its input clock + * from one of the provided Source Clocks, and prescale the output for one or + * more Generic Clock Channels in a one-to-many relationship. The generators + * thus allow for several clocks to be generated of different frequencies, + * power usages, and accuracies, which can be turned on and off individually to + * disable the clocks to multiple peripherals as a group. + * + * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels + * To connect a Generic Clock Generator to a peripheral within the + * device, a Generic Clock Channel is used. Each peripheral or + * peripheral group has an associated Generic Clock Channel, which serves as the + * clock input for the peripheral(s). To supply a clock to the peripheral + * module(s), the associated channel must be connected to a running Generic + * Clock Generator and the channel enabled. + * + * \section asfdoc_sam0_system_clock_special_considerations Special Considerations + * + * There are no special considerations for this module. + * + * + * \section asfdoc_sam0_system_clock_extra_info Extra Information + * + * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes: + * - \ref asfdoc_sam0_system_clock_extra_acronyms + * - \ref asfdoc_sam0_system_clock_extra_dependencies + * - \ref asfdoc_sam0_system_clock_extra_errata + * - \ref asfdoc_sam0_system_clock_extra_history + * + * + * \section asfdoc_sam0_system_clock_examples Examples + * + * For a list of examples related to this driver, see + * \ref asfdoc_sam0_system_clock_exqsg. + * + * + * \section asfdoc_sam0_system_clock_api_overview API Overview + * @{ + */ + +#include +#include + + + +/** + * \brief Available start-up times for the XOSC32K. + * + * Available external 32KHz oscillator start-up times, as a number of external + * clock cycles. + */ +enum system_xosc32k_startup { + /** Wait 2048 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC32K_STARTUP_2048, + /** Wait 4096 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC32K_STARTUP_4096, + /** Wait 16384 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC32K_STARTUP_16384, + /** Wait 32768 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC32K_STARTUP_32768, + /** Wait 65536 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC32K_STARTUP_65536, + /** Wait 131072 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC32K_STARTUP_131072, + /** Wait 262144 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC32K_STARTUP_262144, +}; + +/** + * \brief Available start-up times for the XOSC. + * + * Available external oscillator start-up times, as a number of external clock + * cycles. + */ +enum system_xosc_startup { + /** Wait one clock cycle until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_1, + /** Wait two clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_2, + /** Wait four clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_4, + /** Wait eight clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_8, + /** Wait 16 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_16, + /** Wait 32 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_32, + /** Wait 64 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_64, + /** Wait 128 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_128, + /** Wait 256 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_256, + /** Wait 512 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_512, + /** Wait 1024 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_1024, + /** Wait 2048 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_2048, + /** Wait 4096 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_4096, + /** Wait 8192 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_8192, + /** Wait 16384 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_16384, + /** Wait 32768 clock cycles until the clock source is considered stable */ + SYSTEM_XOSC_STARTUP_32768, +}; + +/** + * \brief Available start-up times for the OSC32K. + * + * Available internal 32KHz oscillator start-up times, as a number of internal + * OSC32K clock cycles. + */ +enum system_osc32k_startup { + /** Wait three clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_3, + /** Wait four clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_4, + /** Wait six clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_6, + /** Wait ten clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_10, + /** Wait 18 clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_18, + /** Wait 34 clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_34, + /** Wait 66 clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_66, + /** Wait 130 clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_130, +}; + +/** + * \brief Frequency selection for the internal 16MHz system clock. + * + * Available frequency selection for the internal 16MHz (nominal) system clock. + */ +enum system_osc16m_fsel { + /** Frequency Selection 4MHz */ + SYSTEM_OSC16M_4M, + /** Frequency Selection 8MHz */ + SYSTEM_OSC16M_8M, + /** Frequency Selection 12MHz */ + SYSTEM_OSC16M_12M, + /** Frequency Selection 16MHz */ + SYSTEM_OSC16M_16M, +}; + + + +/** + * \brief Main CPU, Lowpower and Backup clock division. + * + * Available division ratios for the CPU and Lowpower and Backup clocks. + */ +enum system_main_clock_div { + /** Divide Main clock by one */ + SYSTEM_MAIN_CLOCK_DIV_1, + /** Divide Main clock by two */ + SYSTEM_MAIN_CLOCK_DIV_2, + /** Divide Main clock by four */ + SYSTEM_MAIN_CLOCK_DIV_4, + /** Divide Main clock by eight */ + SYSTEM_MAIN_CLOCK_DIV_8, + /** Divide Main clock by 16 */ + SYSTEM_MAIN_CLOCK_DIV_16, + /** Divide Main clock by 32 */ + SYSTEM_MAIN_CLOCK_DIV_32, + /** Divide Main clock by 64 */ + SYSTEM_MAIN_CLOCK_DIV_64, + /** Divide Main clock by 128 */ + SYSTEM_MAIN_CLOCK_DIV_128, +}; + +/** + * \brief External clock source types. + * + * Available external clock source types. + */ +enum system_clock_external { + /** The external clock source is a crystal oscillator */ + SYSTEM_CLOCK_EXTERNAL_CRYSTAL, + /** The connected clock source is an external logic level clock signal */ + SYSTEM_CLOCK_EXTERNAL_CLOCK, +}; + +/** + * \brief Operating modes of the DFLL clock source. + * + * Available operating modes of the DFLL clock source module. + */ +enum system_clock_dfll_loop_mode { + /** The DFLL is operating in open loop mode with no feedback */ + SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, + /** The DFLL is operating in closed loop mode with frequency feedback from + * a low frequency reference clock + */ + SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = OSCCTRL_DFLLCTRL_MODE, + +#ifdef OSCCTRL_DFLLCTRL_USBCRM + /** The DFLL is operating in USB recovery mode with frequency feedback + * from USB SOF + */ + SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = OSCCTRL_DFLLCTRL_USBCRM, +#endif +}; + +/** + * \brief Locking behavior for the DFLL during device wake-up. + * + * DFLL lock behavior modes on device wake-up from sleep. + */ +enum system_clock_dfll_wakeup_lock { + /** Keep DFLL lock when the device wakes from sleep */ + SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, + /** Lose DFLL lock when the devices wakes from sleep */ + SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = OSCCTRL_DFLLCTRL_LLAW, +}; + +/** + * \brief Fine tracking behavior for the DFLL once a lock has been acquired. + * + * DFLL fine tracking behavior modes after a lock has been acquired. + */ +enum system_clock_dfll_stable_tracking { + /** Keep tracking after the DFLL has gotten a fine lock */ + SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, + /** Stop tracking after the DFLL has gotten a fine lock */ + SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = OSCCTRL_DFLLCTRL_STABLE, +}; + +/** + * \brief Chill cycle behavior of the DFLL module. + * + * DFLL chill cycle behavior modes of the DFLL module. A chill cycle is a period + * of time when the DFLL output frequency is not measured by the unit, to allow + * the output to stabilize after a change in the input clock source. + */ +enum system_clock_dfll_chill_cycle { + /** Enable a chill cycle, where the DFLL output frequency is not measured */ + SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, + /** Disable a chill cycle, where the DFLL output frequency is not measured */ + SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = OSCCTRL_DFLLCTRL_CCDIS, +}; + +/** + * \brief QuickLock settings for the DFLL module. + * + * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of + * the DFLL output frequency at the expense of accuracy. + */ +enum system_clock_dfll_quick_lock { + /** Enable the QuickLock feature for looser lock requirements on the DFLL */ + SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, + /** Disable the QuickLock feature for strict lock requirements on the DFLL */ + SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = OSCCTRL_DFLLCTRL_QLDIS, +}; + +/** + * \brief Available clock sources in the system. + * + * Clock sources available to the GCLK generators + */ +enum system_clock_source { + /** Internal 16MHz RC oscillator */ + SYSTEM_CLOCK_SOURCE_OSC16M = GCLK_SOURCE_OSC16M, + /** Internal 32KHz RC oscillator */ + SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K, + /** External oscillator */ + SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC , + /** External 32KHz oscillator */ + SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K, + /** Digital Frequency Locked Loop (DFLL) */ + SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M, + /** Internal Ultra Low Power 32KHz oscillator */ + SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K, + /** Generator input pad */ + SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN, + /** Generic clock generator one output */ + SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1, + + /** Digital Phase Locked Loop (DPLL) */ + SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL, +}; + +/** + * \brief List of APB peripheral buses. + * + * Available bus clock domains on the APB bus. + */ +enum system_clock_apb_bus { + /** Peripheral bus A on the APB bus */ + SYSTEM_CLOCK_APB_APBA, + /** Peripheral bus B on the APB bus */ + SYSTEM_CLOCK_APB_APBB, + /** Peripheral bus C on the APB bus */ + SYSTEM_CLOCK_APB_APBC, + /** Peripheral bus D on the APB bus */ + SYSTEM_CLOCK_APB_APBD, + /** Peripheral bus E on the APB bus */ + SYSTEM_CLOCK_APB_APBE, +}; + +/** + * \brief Configuration structure for XOSC. + * + * External oscillator clock configuration structure. + */ +struct system_clock_source_xosc_config { + /** External clock type */ + enum system_clock_external external_clock; + /** Crystal oscillator start-up time */ + enum system_xosc_startup startup_time; + /** Enable automatic amplitude gain control */ + bool auto_gain_control; + /** External clock/crystal frequency */ + uint32_t frequency; + /** Keep the XOSC enabled in standby sleep mode */ + bool run_in_standby; + /** Run On Demand. If this is set the XOSC won't run + * until requested by a peripheral */ + bool on_demand; +}; + +/** + * \brief Configuration structure for XOSC32K. + * + * External 32KHz oscillator clock configuration structure. + */ +struct system_clock_source_xosc32k_config { + /** External clock type */ + enum system_clock_external external_clock; + /** Crystal oscillator start-up time */ + enum system_xosc32k_startup startup_time; + /** Enable 1KHz output */ + bool enable_1khz_output; + /** Enable 32KHz output */ + bool enable_32khz_output; + /** External clock/crystal frequency */ + uint32_t frequency; + /** Keep the XOSC32K enabled in standby sleep mode */ + bool run_in_standby; + /** Run On Demand. If this is set the XOSC32K won't run + * until requested by a peripheral */ + bool on_demand; + /** Lock configuration after it has been written, + * a device reset will release the lock */ + bool write_once; +}; + +/** + * \brief Configuration structure for OSC16M. + * + * Internal 16MHz (nominal) oscillator configuration structure. + */ +struct system_clock_source_osc16m_config { + /** Internal 16MHz RC oscillator prescaler */ + enum system_osc16m_fsel fsel; + /** Keep the OSC16M enabled in standby sleep mode */ + bool run_in_standby; + /** Run On Demand. If this is set the OSC16M won't run + * until requested by a peripheral */ + bool on_demand; +}; + +/** + * \brief Configuration structure for OSCULP32K. + * + * Internal 32KHz Ultra Low Power oscillator configuration structure. + */ +struct system_clock_source_osculp32k_config { + /** Lock configuration after it has been written, + * a device reset will release the lock */ + bool write_once; +}; + +/** + * \brief Configuration structure for OSCULP32K. + * + * Internal 32KHz oscillator configuration structure. + */ +struct system_clock_source_osc32k_config { + /** Start-up time */ + enum system_osc32k_startup startup_time; + /** Enable 1KHz output */ + bool enable_1khz_output; + /** Enable 32KHz output */ + bool enable_32khz_output; + /** Keep the OSC32K enabled in standby sleep mode */ + bool run_in_standby; + /** Run On Demand. If this is set the OSC32K won't run + * until requested by a peripheral */ + bool on_demand; + /** Lock configuration after it has been written, + * a device reset will release the lock */ + bool write_once; +}; + +/** + * \brief Configuration structure for DFLL. + * + * DFLL oscillator configuration structure. + */ +struct system_clock_source_dfll_config { + /** Loop mode */ + enum system_clock_dfll_loop_mode loop_mode; + /** Run On Demand. If this is set the DFLL won't run + * until requested by a peripheral */ + bool on_demand; + /** Run in stanby*/ + bool run_in_stanby; + /** Enable quick lock */ + enum system_clock_dfll_quick_lock quick_lock; + /** Enable chill cycle */ + enum system_clock_dfll_chill_cycle chill_cycle; + /** DFLL lock state on wakeup */ + enum system_clock_dfll_wakeup_lock wakeup_lock; + /** DFLL tracking after fine lock */ + enum system_clock_dfll_stable_tracking stable_tracking; + /** Coarse calibration value (Open loop mode) */ + uint8_t coarse_value; + /** Fine calibration value (Open loop mode) */ + uint16_t fine_value; + /** Coarse adjustment maximum step size (Closed loop mode) */ + uint8_t coarse_max_step; + /** Fine adjustment maximum step size (Closed loop mode) */ + uint16_t fine_max_step; + /** DFLL multiply factor (Closed loop mode) */ + uint16_t multiply_factor; +}; + +/** + * \name External Oscillator Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for XOSC. + * + * Fills a configuration structure with the default configuration for an + * external oscillator module: + * - External Crystal + * - Start-up time of 16384 external clock cycles + * - Automatic crystal gain control mode enabled + * - Frequency of 12MHz + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_xosc_get_config_defaults( + struct system_clock_source_xosc_config *const config) +{ + Assert(config); + + config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; + config->startup_time = SYSTEM_XOSC_STARTUP_16384; + config->auto_gain_control = true; + config->frequency = 12000000UL; + config->run_in_standby = false; + config->on_demand = true; +} + +void system_clock_source_xosc_set_config( + struct system_clock_source_xosc_config *const config); + +/** + * @} + */ + + +/** + * \name External 32KHz Oscillator Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for XOSC32K. + * + * Fills a configuration structure with the default configuration for an + * external 32KHz oscillator module: + * - External Crystal + * - Start-up time of 16384 external clock cycles + * - Automatic crystal gain control mode disabled + * - Frequency of 32.768KHz + * - 1KHz clock output disabled + * - 32KHz clock output enabled + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * - Don't lock registers after configuration has been written + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_xosc32k_get_config_defaults( + struct system_clock_source_xosc32k_config *const config) +{ + Assert(config); + + config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; + config->startup_time = SYSTEM_XOSC32K_STARTUP_16384; + config->frequency = 32768UL; + config->enable_1khz_output = false; + config->enable_32khz_output = true; + config->run_in_standby = false; + config->on_demand = true; + config->write_once = false; +} + +void system_clock_source_xosc32k_set_config( + struct system_clock_source_xosc32k_config *const config); +/** + * @} + */ + + +/** + * \name Internal 32KHz Oscillator Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for OSC32K. + * + * Fills a configuration structure with the default configuration for an + * internal 32KHz oscillator module: + * - 1KHz clock output enabled + * - 32KHz clock output enabled + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * - Set start-up time to 130 cycles + * - Don't lock registers after configuration has been written + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_osc32k_get_config_defaults( + struct system_clock_source_osc32k_config *const config) +{ + Assert(config); + + config->enable_1khz_output = true; + config->enable_32khz_output = true; + config->run_in_standby = false; + config->on_demand = true; + config->startup_time = SYSTEM_OSC32K_STARTUP_130; + config->write_once = false; +} + +void system_clock_source_osc32k_set_config( + struct system_clock_source_osc32k_config *const config); + +/** + * @} + */ + +/** + * \name Internal Ultra Low Power 32KHz Oscillator Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for OSCULP32K. + * + * Fills a configuration structure with the default configuration for an + * internal Ultra Low Power 32KHz oscillator module: + * - 1KHz clock output enabled + * - 32KHz clock output enabled + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_osculp32k_get_config_defaults( + struct system_clock_source_osculp32k_config *const config) +{ + Assert(config); + + config->write_once = false; +} + +void system_clock_source_osculp32k_set_config( + struct system_clock_source_osculp32k_config *const config); + +/** + * @} + */ + + +/** + * \name Internal 16MHz Oscillator Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for OSC16M. + * + * Fills a configuration structure with the default configuration for an + * internal 16MHz (nominal) oscillator module: + * - Clock output frequency select 4MHz + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_osc16m_get_config_defaults( + struct system_clock_source_osc16m_config *const config) +{ + Assert(config); + + config->fsel = SYSTEM_OSC16M_4M; + config->run_in_standby = false; + config->on_demand = true; +} + +void system_clock_source_osc16m_set_config( + struct system_clock_source_osc16m_config *const config); + +/** + * @} + */ + + +/** + * \name Internal DFLL Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for DFLL. + * + * Fills a configuration structure with the default configuration for a + * DFLL oscillator module: + * - Open loop mode + * - QuickLock mode enabled + * - Chill cycle enabled + * - Output frequency lock maintained during device wake-up + * - Continuous tracking of the output frequency + * - Default tracking values at the mid-points for both coarse and fine + * tracking parameters + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_dfll_get_config_defaults( + struct system_clock_source_dfll_config *const config) +{ + Assert(config); + + config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN; + config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; + config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; + config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; + config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; + config->on_demand = true; + config->run_in_stanby = false; + + /* Open loop mode calibration value */ + config->coarse_value = 0x1f / 4; /* Midpoint */ + config->fine_value = 0xff / 4; /* Midpoint */ + + /* Closed loop mode */ + config->coarse_max_step = 1; + config->fine_max_step = 1; + config->multiply_factor = 12; /* Multiply 4MHz by 12 to get 48MHz */ +} + +void system_clock_source_dfll_set_config( + struct system_clock_source_dfll_config *const config); + +/** + * @} + */ + +/** + * \name Clock Source Management + * @{ + */ +enum status_code system_clock_source_write_calibration( + const enum system_clock_source system_clock_source, + const uint16_t calibration_value, + const uint8_t freq_range); + +enum status_code system_clock_source_enable( + const enum system_clock_source system_clock_source); + +enum status_code system_clock_source_disable( + const enum system_clock_source clk_source); + +bool system_clock_source_is_ready( + const enum system_clock_source clk_source); + +uint32_t system_clock_source_get_hz( + const enum system_clock_source clk_source); + +/** + * @} + */ + +/** + * \name Main Clock Management + * @{ + */ + +/** + * \brief Enable or disable the main clock failure detection. + * + * This mechanism allows switching automatically the main clock to the safe + * RCSYS clock, when the main clock source is considered off. + * + * This may happen for instance when an external crystal is selected as the + * clock source of the main clock and the crystal dies. The mechanism is to + * detect, during a RCSYS period, at least one rising edge of the main clock. + * If no rising edge is seen the clock is considered failed. + * As soon as the detector is enabled, the clock failure detector + * (CFD) will monitor the divided main clock. When a clock failure is detected, + * the main clock automatically switches to the RCSYS clock and the CFD + * interrupt is generated if enabled. + * + * \note The failure detect must be disabled if the system clock is the same or + * slower than 32KHz as it will believe the system clock has failed with + * a too slow clock. + * + * \param[in] enable Boolean \c true to enable, \c false to disable detection + */ +static inline void system_main_clock_set_failure_detect( + const bool enable) +{ + if (enable) { + MCLK->CTRLA.reg |= MCLK_CTRLA_CFDEN; + } else { + MCLK->CTRLA.reg &= ~MCLK_CTRLA_CFDEN; + } +} + +/** + * \brief Set main CPU clock divider. + * + * Sets the clock divider used on the main clock to provide the CPU clock. + * + * \param[in] divider CPU clock divider to set + */ +static inline void system_cpu_clock_set_divider( + const enum system_main_clock_div divider) +{ + Assert(((uint32_t)divider & MCLK_CPUDIV_CPUDIV_Msk) == divider); + MCLK->CPUDIV.reg = (uint32_t)divider; + +} + +/** + * \brief Set Low-Power Clock divider. + * + * Sets the clock divider used on the main clock to provide the CPU clock. + * + * \param[in] divider CPU clock divider to set + */ +static inline void system_low_power_clock_set_divider( + const enum system_main_clock_div divider) +{ + Assert(((uint32_t)divider & MCLK_LPDIV_LPDIV_Msk) == divider); + MCLK->LPDIV.reg = (uint32_t)divider; + +} + +/** + * \brief Set Backup Clock divider. + * + * Sets the clock divider used on the main clock to provide the CPU clock. + * + * \param[in] divider CPU clock divider to set + */ +static inline void system_backup_clock_set_divider( + const enum system_main_clock_div divider) +{ + Assert(((uint32_t)divider & MCLK_BUPDIV_BUPDIV_Msk) == divider); + MCLK->BUPDIV.reg = (uint32_t)divider; + +} + + +/** + * \brief Retrieves the current frequency of the CPU core. + * + * Retrieves the operating frequency of the CPU core, obtained from the main + * generic clock and the set CPU bus divider. + * + * \return Current CPU frequency in Hz. + */ +static inline uint32_t system_cpu_clock_get_hz(void) +{ + return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1)); + +} + +/** + * \brief Retrieves the current frequency of Low-Power clock. + * + * Retrieves the operating frequency of Low-Power, obtained from Low-Power + * clock and the set Low-Power clock divider. + * + * \return Current CPU frequency in Hz. + */ +static inline uint32_t system_low_power_clock_get_hz(void) +{ + return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->LPDIV.reg - 1)); + +} + +/** + * \brief Retrieves the current frequency of backup clock. + * + * Retrieves the operating frequency of backup clock, obtained from backup + * clock and the set backup clock divider. + * + * \return Current CPU frequency in Hz. + */ +static inline uint32_t system_backup_clock_get_hz(void) +{ + return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->BUPDIV.reg - 1)); + +} + + +/** + * @} + */ + +/** + * \name Bus Clock Masking + * @{ + */ + +/** + * \brief Set bits in the clock mask for the AHB bus. + * + * This function will set bits in the clock mask for the AHB bus. + * Any bits set to 1 will enable that clock, 0 bits in the mask + * will be ignored + * + * \param[in] ahb_mask AHB clock mask to enable + */ +static inline void system_ahb_clock_set_mask( + const uint32_t ahb_mask) +{ + MCLK->AHBMASK.reg |= ahb_mask; +} + +/** + * \brief Clear bits in the clock mask for the AHB bus. + * + * This function will clear bits in the clock mask for the AHB bus. + * Any bits set to 1 will disable that clock, zero bits in the mask + * will be ignored. + * + * \param[in] ahb_mask AHB clock mask to disable + */ +static inline void system_ahb_clock_clear_mask( + const uint32_t ahb_mask) +{ + MCLK->AHBMASK.reg &= ~ahb_mask; +} + +/** + * \brief Set bits in the clock mask for an APBx bus. + * + * This function will set bits in the clock mask for an APBx bus. + * Any bits set to 1 will enable the corresponding module clock, zero bits in + * the mask will be ignored. + * + * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from + * the device header files + * \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_* + * constants from the device header files + * + * \returns Status indicating the result of the clock mask change operation. + * + * \retval STATUS_ERR_INVALID_ARG Invalid bus given + * \retval STATUS_OK The clock mask was set successfully + */ +static inline enum status_code system_apb_clock_set_mask( + const enum system_clock_apb_bus bus, + const uint32_t mask) +{ + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + MCLK->APBAMASK.reg |= mask; + break; + + case SYSTEM_CLOCK_APB_APBB: + MCLK->APBBMASK.reg |= mask; + break; + + case SYSTEM_CLOCK_APB_APBC: + MCLK->APBCMASK.reg |= mask; + break; + case SYSTEM_CLOCK_APB_APBD: + MCLK->APBDMASK.reg |= mask; + break; + case SYSTEM_CLOCK_APB_APBE: + MCLK->APBEMASK.reg |= mask; + break; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + + } + + return STATUS_OK; + } + + /** + * \brief Clear bits in the clock mask for an APBx bus. + * + * This function will clear bits in the clock mask for an APBx bus. + * Any bits set to 1 will disable the corresponding module clock, zero bits in + * the mask will be ignored. + * + * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from + * the device header files + * \param[in] bus Bus to clear clock mask bits + * + * \returns Status indicating the result of the clock mask change operation. + * + * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given. + * \retval STATUS_OK The clock mask was changed successfully. + */ + static inline enum status_code system_apb_clock_clear_mask( + const enum system_clock_apb_bus bus, + const uint32_t mask) +{ + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + MCLK->APBAMASK.reg &= ~mask; + break; + + case SYSTEM_CLOCK_APB_APBB: + MCLK->APBBMASK.reg &= ~mask; + break; + + case SYSTEM_CLOCK_APB_APBC: + MCLK->APBCMASK.reg &= ~mask; + break; + case SYSTEM_CLOCK_APB_APBD: + MCLK->APBDMASK.reg &= ~mask; + break; + case SYSTEM_CLOCK_APB_APBE: + MCLK->APBEMASK.reg &= ~mask; + break; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + return STATUS_OK; + } + + /** + * @} + */ + + /** + * \brief Reference clock source of the DPLL module. + */ + enum system_clock_source_dpll_reference_clock { + /** Select XOSC32K as clock reference */ + SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K, + /** Select XOSC as clock reference */ + SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC, + /** Select GCLK as clock reference */ + SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, +}; + +/** + * \brief Lock time-out value of the DPLL module. + */ +enum system_clock_source_dpll_lock_time { + /** Set no time-out as default */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, + /** Set time-out if no lock within 8ms */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04, + /** Set time-out if no lock within 9ms */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS, + /** Set time-out if no lock within 10ms */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS, + /** Set time-out if no lock within 11ms */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS, +}; + +/** + * \brief Filter type of the DPLL module. + */ +enum system_clock_source_dpll_filter { + /** Default filter mode */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT, + /** Low bandwidth filter */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER, + /** High bandwidth filter */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER, + /** High damping filter */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER, +}; + +/** + * \brief DPLL Output Clock Prescaler. + */ +enum system_clock_source_dpll_prescaler { + /** DPLL output is divided by 1 */ + SYSTEM_CLOCK_SOURCE_DPLL_DIV_1, + /** DPLL output is divided by 2 */ + SYSTEM_CLOCK_SOURCE_DPLL_DIV_2, + /** DPLL output is divided by 4 */ + SYSTEM_CLOCK_SOURCE_DPLL_DIV_4, +}; + +/** + * \brief Configuration structure for DPLL. + * + * DPLL oscillator configuration structure. + */ +struct system_clock_source_dpll_config { + /** Run On Demand. If this is set the DPLL won't run + * until requested by a peripheral */ + bool on_demand; + /** Keep the DPLL enabled in standby sleep mode */ + bool run_in_standby; + /** Bypass lock signal */ + bool lock_bypass; + /** Wake up fast. If this is set DPLL output clock is enabled after + * the start-up time */ + bool wake_up_fast; + /** Enable low power mode */ + bool low_power_enable; + + /** Output frequency of the clock */ + uint32_t output_frequency; + /** Reference frequency of the clock */ + uint32_t reference_frequency; + /** Devider of reference clock */ + uint16_t reference_divider; + + /** Filter type of the DPLL module */ + enum system_clock_source_dpll_filter filter; + /** Lock time-out value of the DPLL module */ + enum system_clock_source_dpll_lock_time lock_time; + /** Reference clock source of the DPLL module */ + enum system_clock_source_dpll_reference_clock reference_clock; + /** DPLL prescaler */ + enum system_clock_source_dpll_prescaler prescaler; +}; + +/** + * \name Internal DPLL Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for DPLL. + * + * Fills a configuration structure with the default configuration for a + * DPLL oscillator module: + * - Run only when requested by peripheral (on demand) + * - Don't run in STANDBY sleep mode + * - Lock bypass disabled + * - Fast wake up disabled + * - Low power mode disabled + * - Output frequency is 48MHz + * - Reference clock frequency is 32768Hz + * - Not divide reference clock + * - Select REF0 as reference clock + * - Set lock time to default mode + * - Use default filter + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_dpll_get_config_defaults( + struct system_clock_source_dpll_config *const config) +{ + config->on_demand = true; + config->run_in_standby = false; + config->lock_bypass = false; + config->wake_up_fast = false; + config->low_power_enable = false; + + config->output_frequency = 48000000; + config->reference_frequency = 32768; + config->reference_divider = 1; + config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK; + config->prescaler = SYSTEM_CLOCK_SOURCE_DPLL_DIV_1; + + config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT; + config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT; +}; + +void system_clock_source_dpll_set_config( + struct system_clock_source_dpll_config *const config); + +/* @} */ + +/** + * \name System Clock Initialization + * @{ + */ + +void system_clock_init(void); + +/** + * @} + */ + +/** + * \name System Flash Wait States + * @{ + */ + +/** + * \brief Set flash controller wait states. + * + * Will set the number of wait states that are used by the onboard + * flash memory. The number of wait states depend on both device + * supply voltage and CPU speed. The required number of wait states + * can be found in the electrical characteristics of the device. + * + * \param[in] wait_states Number of wait states to use for internal flash + */ +static inline void system_flash_set_waitstates(uint8_t wait_states) +{ + Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) == + ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos)); + + NVMCTRL->CTRLB.bit.RWS = wait_states; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver + * + * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms + * Below is a table listing the acronyms used in this module, along with their + * intended meanings. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
      AcronymDescription
      DFLLDigital Frequency Locked Loop
      MUXMultiplexer
      MCLKMain Clock
      OSC32KInternal 32KHz Oscillator
      OSC16MInternal 16MHz Oscillator
      PLLPhase Locked Loop
      OSCOscillator
      XOSCExternal Oscillator
      XOSC32KExternal 32KHz Oscillator
      AHBAdvanced High-performance Bus
      APBAdvanced Peripheral Bus
      DPLLDigital Phase Locked Loop
      + * + * + * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies + * This driver has the following dependencies: + * + * - None + * + * + * \section asfdoc_sam0_system_clock_extra_errata Errata + * + * - This driver implements experimental workaround for errata 9905 + * + * "The DFLL clock must be requested before being configured. Otherwise a + * write access to a DFLL register can freeze the device." + * This driver will enable and configure the DFLL before the ONDEMAND bit is set. + * + * + * \section asfdoc_sam0_system_clock_extra_history Module History + * An overview of the module history is presented in the table below, with + * details on the enhancements and fixes made to the module since its first + * release. The current version of this corresponds to the newest version in + * the table. + * + * + * + * + * + * + * + * + *
      Changelog
      Initial Release
      + */ + +/** + * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver + * + * This is a list of the available Quick Start guides (QSGs) and example + * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple + * examples with step-by-step instructions to configure and use this driver in + * a selection of use cases. Note that a QSG can be compiled as a standalone + * application or be added to the user application. + * + * - \subpage asfdoc_sam0_system_clock_basic_use_case + * - \subpage asfdoc_sam0_system_gclk_basic_use_case + * + * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History + * + * + * + * + * + * + * + * + * + *
      Doc. Rev. + * Date + * Comments + *
      42452A06/2015Initial document release
      + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/gclk.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/gclk.c new file mode 100644 index 0000000000..7e0d083bfb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/gclk.c @@ -0,0 +1,464 @@ +/** + * \file + * + * \brief SAM L21 Generic Clock Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include +#include +#include + + +/** + * \brief Determines if the hardware module(s) are currently synchronizing to the bus. + * + * Checks to see if the underlying hardware peripheral module(s) are currently + * synchronizing across multiple clock domains to the hardware bus, This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * \param[in] generator Generic Clock Generator index to sync + * + * \return Synchronization status of the underlying hardware module(s). + * + * \retval false if the module has completed synchronization + * \retval true if the module synchronization is ongoing + */ +static inline bool system_gclk_is_syncing(const uint8_t generator) +{ + + if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )) { + return true; + } + + return false; +} + + +/** + * \brief Initializes the GCLK driver. + * + * Initializes the Generic Clock module, disabling and resetting all active + * Generic Clock Generators and Channels to their power-on default values. + */ +void system_gclk_init(void) +{ + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_GCLK); + + /* Software reset the module to ensure it is re-initialized correctly */ + GCLK->CTRLA.reg = GCLK_CTRLA_SWRST; + while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) { + /* Wait for reset to complete */ + } +} + +/** + * \brief Writes a Generic Clock Generator configuration to the hardware module. + * + * Writes out a given configuration of a Generic Clock Generator configuration + * to the hardware module. + * + * \note Changing the clock source on the fly (on a running + * generator) can take additional time if the clock source is configured + * to only run on-demand (ONDEMAND bit is set) and it is not currently + * running (no peripheral is requesting the clock source). In this case + * the GCLK will request the new clock while still keeping a request to + * the old clock source until the new clock source is ready. + * + * \note This function will not start a generator that is not already running; + * to start the generator, call \ref system_gclk_gen_enable() + * after configuring a generator. + * + * \param[in] generator Generic Clock Generator index to configure + * \param[in] config Configuration settings for the generator + */ +void system_gclk_gen_set_config( + const uint8_t generator, + struct system_gclk_gen_config *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Cache new register configurations to minimize sync requirements. */ + uint32_t new_genctrl_config ; + + + /* Select the requested source clock for the generator */ + new_genctrl_config = config->source_clock << GCLK_GENCTRL_SRC_Pos; + + /* Configure the clock to be either high or low when disabled */ + if (config->high_when_disabled) { + new_genctrl_config |= GCLK_GENCTRL_OOV; + } + + /* Configure if the clock output to I/O pin should be enabled. */ + if (config->output_enable) { + new_genctrl_config |= GCLK_GENCTRL_OE; + } + + /* Set division factor */ + if (config->division_factor > 1) { + /* Check if division is a power of two */ + if (((config->division_factor & (config->division_factor - 1)) == 0)) { + /* Determine the index of the highest bit set to get the + * division factor that must be loaded into the division + * register */ + + uint32_t div2_count = 0; + + uint32_t mask; + for (mask = (1UL << 1); mask < config->division_factor; + mask <<= 1) { + div2_count++; + } + + /* Set binary divider power of 2 division factor */ + new_genctrl_config |= div2_count << GCLK_GENCTRL_DIV_Pos; + new_genctrl_config |= GCLK_GENCTRL_DIVSEL; + } else { + /* Set integer division factor */ + + new_genctrl_config |= + (config->division_factor) << GCLK_GENCTRL_DIV_Pos; + + /* Enable non-binary division with increased duty cycle accuracy */ + new_genctrl_config |= GCLK_GENCTRL_IDC; + } + + } + + /* Enable or disable the clock in standby mode */ + if (config->run_in_standby) { + new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY; + } + + while (system_gclk_is_syncing(generator)) { + /* Wait for synchronization */ + }; + + system_interrupt_enter_critical_section(); + + GCLK->GENCTRL[generator].reg = new_genctrl_config | (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN); + + while (system_gclk_is_syncing(generator)) { + /* Wait for synchronization */ + }; + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Enables a Generic Clock Generator that was previously configured. + * + * Starts the clock generation of a Generic Clock Generator that was previously + * configured via a call to \ref system_gclk_gen_set_config(). + * + * \param[in] generator Generic Clock Generator index to enable + */ +void system_gclk_gen_enable( + const uint8_t generator) +{ + while (system_gclk_is_syncing(generator)) { + /* Wait for synchronization */ + }; + + system_interrupt_enter_critical_section(); + + /* Enable generator */ + GCLK->GENCTRL[generator].reg |= GCLK_GENCTRL_GENEN; + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Disables a Generic Clock Generator that was previously enabled. + * + * Stops the clock generation of a Generic Clock Generator that was previously + * started via a call to \ref system_gclk_gen_enable(). + * + * \param[in] generator Generic Clock Generator index to disable + */ +void system_gclk_gen_disable( + const uint8_t generator) +{ + while (system_gclk_is_syncing(generator)) { + /* Wait for synchronization */ + }; + + system_interrupt_enter_critical_section(); + + /* Disable generator */ + GCLK->GENCTRL[generator].reg &= ~GCLK_GENCTRL_GENEN; + while (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN) { + /* Wait for clock to become disabled */ + } + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Determins if the specified Generic Clock Generator is enabled. + * + * \param[in] generator Generic Clock Generator index to check + * + * \return The enabled status. + * \retval true The Generic Clock Generator is enabled + * \retval false The Generic Clock Generator is disabled + */ +bool system_gclk_gen_is_enabled( + const uint8_t generator) +{ + bool enabled; + + system_interrupt_enter_critical_section(); + + /* Obtain the enabled status */ + enabled = (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN); + + system_interrupt_leave_critical_section(); + + return enabled; +} + +/** + * \brief Retrieves the clock frequency of a Generic Clock generator. + * + * Determines the clock frequency (in Hz) of a specified Generic Clock + * generator, used as a source to a Generic Clock Channel module. + * + * \param[in] generator Generic Clock Generator index + * + * \return The frequency of the generic clock generator, in Hz. + */ +uint32_t system_gclk_gen_get_hz( + const uint8_t generator) +{ + while (system_gclk_is_syncing(generator)) { + /* Wait for synchronization */ + }; + + system_interrupt_enter_critical_section(); + + /* Get the frequency of the source connected to the GCLK generator */ + uint32_t gen_input_hz = system_clock_source_get_hz( + (enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC); + + uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL; + uint32_t divider = GCLK->GENCTRL[generator].bit.DIV; + + system_interrupt_leave_critical_section(); + + /* Check if the generator is using fractional or binary division */ + if (!divsel && divider > 1) { + gen_input_hz /= divider; + } else if (divsel) { + gen_input_hz >>= (divider+1); + } + + return gen_input_hz; +} + +/** + * \brief Writes a Generic Clock configuration to the hardware module. + * + * Writes out a given configuration of a Generic Clock configuration to the + * hardware module. If the clock is currently running, it will be stopped. + * + * \note Once called the clock will not be running; to start the clock, + * call \ref system_gclk_chan_enable() after configuring a clock channel. + * + * \param[in] channel Generic Clock channel to configure + * \param[in] config Configuration settings for the clock + * + */ +void system_gclk_chan_set_config( + const uint8_t channel, + struct system_gclk_chan_config *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Disable generic clock channel */ + system_gclk_chan_disable(channel); + + /* Configure the peripheral channel */ + GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator); + + +} + +/** + * \brief Enables a Generic Clock that was previously configured. + * + * Starts the clock generation of a Generic Clock that was previously + * configured via a call to \ref system_gclk_chan_set_config(). + * + * \param[in] channel Generic Clock channel to enable + */ +void system_gclk_chan_enable( + const uint8_t channel) +{ + system_interrupt_enter_critical_section(); + + /* Enable the peripheral channel */ + GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN; + + while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) { + /* Wait for clock synchronization */ + } + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Disables a Generic Clock that was previously enabled. + * + * Stops the clock generation of a Generic Clock that was previously started + * via a call to \ref system_gclk_chan_enable(). + * + * \param[in] channel Generic Clock channel to disable + */ +void system_gclk_chan_disable( + const uint8_t channel) +{ + system_interrupt_enter_critical_section(); + + /* Sanity check WRTLOCK */ + Assert(!GCLK->PCHCTRL[channel].bit.WRTLOCK); + + /* Disable the peripheral channel */ + GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN; + + while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) { + /* Wait for clock synchronization */ + } + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Determins if the specified Generic Clock channel is enabled. + * + * \param[in] channel Generic Clock Channel index + * + * \return The enabled status. + * \retval true The Generic Clock channel is enabled + * \retval false The Generic Clock channel is disabled + */ +bool system_gclk_chan_is_enabled( + const uint8_t channel) +{ + bool enabled; + + system_interrupt_enter_critical_section(); + + /* Select the requested generic clock channel */ + enabled = GCLK->PCHCTRL[channel].bit.CHEN; + + system_interrupt_leave_critical_section(); + + return enabled; +} + +/** + * \brief Locks a Generic Clock channel from further configuration writes. + * + * Locks a generic clock channel from further configuration writes. It is only + * possible to unlock the channel configuration through a power on reset. + * + * \param[in] channel Generic Clock channel to enable + */ +void system_gclk_chan_lock( + const uint8_t channel) +{ + system_interrupt_enter_critical_section(); + + GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_WRTLOCK; + system_interrupt_leave_critical_section(); +} + +/** + * \brief Determins if the specified Generic Clock channel is locked. + * + * \param[in] channel Generic Clock Channel index + * + * \return The lock status. + * \retval true The Generic Clock channel is locked + * \retval false The Generic Clock channel is not locked + */ +bool system_gclk_chan_is_locked( + const uint8_t channel) +{ + bool locked; + + system_interrupt_enter_critical_section(); + locked = GCLK->PCHCTRL[channel].bit.WRTLOCK; + system_interrupt_leave_critical_section(); + + return locked; +} + +/** + * \brief Retrieves the clock frequency of a Generic Clock channel. + * + * Determines the clock frequency (in Hz) of a specified Generic Clock + * channel, used as a source to a device peripheral module. + * + * \param[in] channel Generic Clock Channel index + * + * \return The frequency of the generic clock channel, in Hz. + */ +uint32_t system_gclk_chan_get_hz( + const uint8_t channel) +{ + uint8_t gen_id; + + system_interrupt_enter_critical_section(); + /* Select the requested generic clock channel */ + gen_id = GCLK->PCHCTRL[channel].bit.GEN; + system_interrupt_leave_critical_section(); + + /* Return the clock speed of the associated GCLK generator */ + return system_gclk_gen_get_hz(gen_id); +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock.c new file mode 100644 index 0000000000..5df062f884 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock.c @@ -0,0 +1,1031 @@ +/** + * \file + * + * \brief SAM D21/R21/DA0/DA1 Clock Driver + * + * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include +#include +#include + +#ifndef SYSCTRL_FUSES_OSC32K_ADDR +#if (SAMR21) || (SAMD) +# define SYSCTRL_FUSES_OSC32K_ADDR FUSES_OSC32K_CAL_ADDR +# define SYSCTRL_FUSES_OSC32K_Pos FUSES_OSC32K_CAL_Pos +#elif (SAML21) +# define SYSCTRL_FUSES_OSC32K_ADDR NVMCTRL_OTP4 +# define SYSCTRL_FUSES_OSC32K_Pos 6 + +#else +# define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR +# define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos +#endif +#endif + +/** + * \internal + * \brief DFLL-specific data container. + */ +struct _system_clock_dfll_config { + uint32_t control; + uint32_t val; + uint32_t mul; +}; + +/** + * \internal + * \brief DPLL-specific data container. + */ +struct _system_clock_dpll_config { + uint32_t frequency; +}; + + +/** + * \internal + * \brief XOSC-specific data container. + */ +struct _system_clock_xosc_config { + uint32_t frequency; +}; + +/** + * \internal + * \brief System clock module data container. + */ +struct _system_clock_module { + volatile struct _system_clock_dfll_config dfll; + +#ifdef FEATURE_SYSTEM_CLOCK_DPLL + volatile struct _system_clock_dpll_config dpll; +#endif + + volatile struct _system_clock_xosc_config xosc; + volatile struct _system_clock_xosc_config xosc32k; +}; + +/** + * \internal + * \brief Internal module instance to cache configuration values. + */ +static struct _system_clock_module _system_clock_inst = { + .dfll = { + .control = 0, + .val = 0, + .mul = 0, + }, + +#ifdef FEATURE_SYSTEM_CLOCK_DPLL + .dpll = { + .frequency = 0, + }, +#endif + .xosc = { + .frequency = 0, + }, + .xosc32k = { + .frequency = 0, + }, +}; + +/** + * \internal + * \brief Wait for sync to the DFLL control registers. + */ +static inline void _system_dfll_wait_for_sync(void) +{ + while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) { + /* Wait for DFLL sync */ + } +} + +/** + * \internal + * \brief Wait for sync to the OSC32K control registers. + */ +static inline void _system_osc32k_wait_for_sync(void) +{ + while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) { + /* Wait for OSC32K sync */ + } +} + +static inline void _system_clock_source_dfll_set_config_errata_9905(void) +{ + + /* Disable ONDEMAND mode while writing configurations */ + SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND; + _system_dfll_wait_for_sync(); + + SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; + SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; + + /* Write full configuration to DFLL control register */ + SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; +} + +/** + * \brief Retrieve the frequency of a clock source. + * + * Determines the current operating frequency of a given clock source. + * + * \param[in] clock_source Clock source to get the frequency + * + * \returns Frequency of the given clock source, in Hz. + */ +uint32_t system_clock_source_get_hz( + const enum system_clock_source clock_source) +{ + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_XOSC: + return _system_clock_inst.xosc.frequency; + + case SYSTEM_CLOCK_SOURCE_OSC8M: + return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC; + + case SYSTEM_CLOCK_SOURCE_OSC32K: + return 32768UL; + + case SYSTEM_CLOCK_SOURCE_ULP32K: + return 32768UL; + + case SYSTEM_CLOCK_SOURCE_XOSC32K: + return _system_clock_inst.xosc32k.frequency; + + case SYSTEM_CLOCK_SOURCE_DFLL: + + /* Check if the DFLL has been configured */ + if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE)) + return 0; + + /* Make sure that the DFLL module is ready */ + _system_dfll_wait_for_sync(); + + /* Check if operating in closed loop mode */ + if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) { + return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) * + (_system_clock_inst.dfll.mul & 0xffff); + } + + return 48000000UL; + +#ifdef FEATURE_SYSTEM_CLOCK_DPLL + case SYSTEM_CLOCK_SOURCE_DPLL: + if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) { + return 0; + } + + return _system_clock_inst.dpll.frequency; +#endif + + default: + return 0; + } +} + +/** + * \brief Configure the internal OSC8M oscillator clock source. + * + * Configures the 8MHz (nominal) internal RC oscillator with the given + * configuration settings. + * + * \param[in] config OSC8M configuration structure containing the new config + */ +void system_clock_source_osc8m_set_config( + struct system_clock_source_osc8m_config *const config) +{ + SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; + + /* Use temporary struct to reduce register access */ + temp.bit.PRESC = config->prescaler; + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + + SYSCTRL->OSC8M = temp; +} + +/** + * \brief Configure the internal OSC32K oscillator clock source. + * + * Configures the 32KHz (nominal) internal RC oscillator with the given + * configuration settings. + * + * \param[in] config OSC32K configuration structure containing the new config + */ +void system_clock_source_osc32k_set_config( + struct system_clock_source_osc32k_config *const config) +{ + SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K; + + /* Update settings via a temporary struct to reduce register access */ + temp.bit.EN1K = config->enable_1khz_output; + temp.bit.EN32K = config->enable_32khz_output; + temp.bit.STARTUP = config->startup_time; + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + temp.bit.WRTLOCK = config->write_once; + + SYSCTRL->OSC32K = temp; +} + +/** + * \brief Configure the external oscillator clock source. + * + * Configures the external oscillator clock source with the given configuration + * settings. + * + * \param[in] config External oscillator configuration structure containing + * the new config + */ +void system_clock_source_xosc_set_config( + struct system_clock_source_xosc_config *const config) +{ + SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC; + + temp.bit.STARTUP = config->startup_time; + + if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { + temp.bit.XTALEN = 1; + } else { + temp.bit.XTALEN = 0; + } + + temp.bit.AMPGC = config->auto_gain_control; + + /* Set gain if automatic gain control is not selected */ + if (!config->auto_gain_control) { + if (config->frequency <= 2000000) { + temp.bit.GAIN = 0; + } else if (config->frequency <= 4000000) { + temp.bit.GAIN = 1; + } else if (config->frequency <= 8000000) { + temp.bit.GAIN = 2; + } else if (config->frequency <= 16000000) { + temp.bit.GAIN = 3; + } else if (config->frequency <= 30000000) { + temp.bit.GAIN = 4; + } + + } + + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + + /* Store XOSC frequency for internal use */ + _system_clock_inst.xosc.frequency = config->frequency; + + SYSCTRL->XOSC = temp; +} + +/** + * \brief Configure the XOSC32K external 32KHz oscillator clock source. + * + * Configures the external 32KHz oscillator clock source with the given + * configuration settings. + * + * \param[in] config XOSC32K configuration structure containing the new config + */ +void system_clock_source_xosc32k_set_config( + struct system_clock_source_xosc32k_config *const config) +{ + SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K; + + temp.bit.STARTUP = config->startup_time; + + if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { + temp.bit.XTALEN = 1; + } else { + temp.bit.XTALEN = 0; + } + + temp.bit.AAMPEN = config->auto_gain_control; + temp.bit.EN1K = config->enable_1khz_output; + temp.bit.EN32K = config->enable_32khz_output; + + temp.bit.ONDEMAND = config->on_demand; + temp.bit.RUNSTDBY = config->run_in_standby; + temp.bit.WRTLOCK = config->write_once; + + /* Cache the new frequency in case the user needs to check the current + * operating frequency later */ + _system_clock_inst.xosc32k.frequency = config->frequency; + + SYSCTRL->XOSC32K = temp; +} + +/** + * \brief Configure the DFLL clock source. + * + * Configures the Digital Frequency Locked Loop clock source with the given + * configuration settings. + * + * \note The DFLL will be running when this function returns, as the DFLL module + * needs to be enabled in order to perform the module configuration. + * + * \param[in] config DFLL configuration structure containing the new config + */ +void system_clock_source_dfll_set_config( + struct system_clock_source_dfll_config *const config) +{ + _system_clock_inst.dfll.val = + SYSCTRL_DFLLVAL_COARSE(config->coarse_value) | + SYSCTRL_DFLLVAL_FINE(config->fine_value); + + _system_clock_inst.dfll.control = + (uint32_t)config->wakeup_lock | + (uint32_t)config->stable_tracking | + (uint32_t)config->quick_lock | + (uint32_t)config->chill_cycle | + ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos); + + if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + + _system_clock_inst.dfll.mul = + SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | + SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) | + SYSCTRL_DFLLMUL_MUL(config->multiply_factor); + + /* Enable the closed loop mode */ + _system_clock_inst.dfll.control |= config->loop_mode; + } + if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { + + _system_clock_inst.dfll.mul = + SYSCTRL_DFLLMUL_MUL(config->multiply_factor); + + /* Enable the USB recovery mode */ + _system_clock_inst.dfll.control |= config->loop_mode | + SYSCTRL_DFLLCTRL_BPLCKC; + } +} + +#ifdef FEATURE_SYSTEM_CLOCK_DPLL +/** + * \brief Configure the DPLL clock source. + * + * Configures the Digital Phase-Locked Loop clock source with the given + * configuration settings. + * + * \note The DPLL will be running when this function returns, as the DPLL module + * needs to be enabled in order to perform the module configuration. + * + * \param[in] config DPLL configuration structure containing the new config + */ +void system_clock_source_dpll_set_config( + struct system_clock_source_dpll_config *const config) +{ + + uint32_t tmpldr; + uint8_t tmpldrfrac; + uint32_t refclk; + + refclk = config->reference_frequency; + + /* Only reference clock REF1 can be divided */ + if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { + refclk = refclk / (2 * (config->reference_divider + 1)); + } + + /* Calculate LDRFRAC and LDR */ + tmpldr = (config->output_frequency << 4) / refclk; + tmpldrfrac = tmpldr & 0x0f; + tmpldr = (tmpldr >> 4) - 1; + + SYSCTRL->DPLLCTRLA.reg = + ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) | + ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos); + + SYSCTRL->DPLLRATIO.reg = + SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | + SYSCTRL_DPLLRATIO_LDR(tmpldr); + + SYSCTRL->DPLLCTRLB.reg = + SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) | + ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) | + SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) | + SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | + ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) | + ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) | + SYSCTRL_DPLLCTRLB_FILTER(config->filter); + + /* + * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) + */ + _system_clock_inst.dpll.frequency = + (refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4; +} +#endif + +/** + * \brief Writes the calibration values for a given oscillator clock source. + * + * Writes an oscillator calibration value to the given oscillator control + * registers. The acceptable ranges are: + * + * For OSC32K: + * - 7 bits (max value 128) + * For OSC8MHZ: + * - 8 bits (Max value 255) + * For OSCULP: + * - 5 bits (Max value 32) + * + * \note The frequency range parameter applies only when configuring the 8MHz + * oscillator and will be ignored for the other oscillators. + * + * \param[in] clock_source Clock source to calibrate + * \param[in] calibration_value Calibration value to write + * \param[in] freq_range Frequency range (8MHz oscillator only) + * + * \retval STATUS_OK The calibration value was written + * successfully. + * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock + * source. + */ +enum status_code system_clock_source_write_calibration( + const enum system_clock_source clock_source, + const uint16_t calibration_value, + const uint8_t freq_range) +{ + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC8M: + + if (calibration_value > 0xfff || freq_range > 4) { + return STATUS_ERR_INVALID_ARG; + } + + SYSCTRL->OSC8M.bit.CALIB = calibration_value; + SYSCTRL->OSC8M.bit.FRANGE = freq_range; + break; + + case SYSTEM_CLOCK_SOURCE_OSC32K: + + if (calibration_value > 128) { + return STATUS_ERR_INVALID_ARG; + } + + _system_osc32k_wait_for_sync(); + SYSCTRL->OSC32K.bit.CALIB = calibration_value; + break; + + case SYSTEM_CLOCK_SOURCE_ULP32K: + + if (calibration_value > 32) { + return STATUS_ERR_INVALID_ARG; + } + + SYSCTRL->OSCULP32K.bit.CALIB = calibration_value; + break; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + break; + } + + return STATUS_OK; +} + +/** + * \brief Enables a clock source. + * + * Enables a clock source which has been previously configured. + * + * \param[in] clock_source Clock source to enable + * + * \retval STATUS_OK Clock source was enabled successfully and + * is ready + * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this + * device + */ +enum status_code system_clock_source_enable( + const enum system_clock_source clock_source) +{ + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC8M: + SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; + return STATUS_OK; + + case SYSTEM_CLOCK_SOURCE_OSC32K: + SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC: + SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC32K: + SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_DFLL: + _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE; + _system_clock_source_dfll_set_config_errata_9905(); + break; + +#ifdef FEATURE_SYSTEM_CLOCK_DPLL + case SYSTEM_CLOCK_SOURCE_DPLL: + SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; + break; +#endif + + case SYSTEM_CLOCK_SOURCE_ULP32K: + /* Always enabled */ + return STATUS_OK; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + return STATUS_OK; + } + + /** + * \brief Disables a clock source. + * + * Disables a clock source that was previously enabled. + * + * \param[in] clock_source Clock source to disable + * + * \retval STATUS_OK Clock source was disabled successfully + * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was + * given + */ + enum status_code system_clock_source_disable( + const enum system_clock_source clock_source) +{ + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC8M: + SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_OSC32K: + SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC: + SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC32K: + SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; + break; + + case SYSTEM_CLOCK_SOURCE_DFLL: + _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE; + SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; + break; + +#ifdef FEATURE_SYSTEM_CLOCK_DPLL + case SYSTEM_CLOCK_SOURCE_DPLL: + SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; + break; +#endif + + case SYSTEM_CLOCK_SOURCE_ULP32K: + /* Not possible to disable */ + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + + } + + return STATUS_OK; + } + + /** + * \brief Checks if a clock source is ready. + * + * Checks if a given clock source is ready to be used. + * + * \param[in] clock_source Clock source to check if ready + * + * \returns Ready state of the given clock source. + * + * \retval true Clock source is enabled and ready + * \retval false Clock source is disabled or not yet ready + */ + bool system_clock_source_is_ready( + const enum system_clock_source clock_source) +{ + uint32_t mask = 0; + + switch (clock_source) { + case SYSTEM_CLOCK_SOURCE_OSC8M: + mask = SYSCTRL_PCLKSR_OSC8MRDY; + break; + + case SYSTEM_CLOCK_SOURCE_OSC32K: + mask = SYSCTRL_PCLKSR_OSC32KRDY; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC: + mask = SYSCTRL_PCLKSR_XOSCRDY; + break; + + case SYSTEM_CLOCK_SOURCE_XOSC32K: + mask = SYSCTRL_PCLKSR_XOSC32KRDY; + break; + + case SYSTEM_CLOCK_SOURCE_DFLL: + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + mask = (SYSCTRL_PCLKSR_DFLLRDY | + SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC); + } else { + mask = SYSCTRL_PCLKSR_DFLLRDY; + } + break; + +#ifdef FEATURE_SYSTEM_CLOCK_DPLL + case SYSTEM_CLOCK_SOURCE_DPLL: + return ((SYSCTRL->DPLLSTATUS.reg & + (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) == + (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)); +#endif + + case SYSTEM_CLOCK_SOURCE_ULP32K: + /* Not possible to disable */ + return true; + + default: + return false; + } + + return ((SYSCTRL->PCLKSR.reg & mask) == mask); +} + +/* Include some checks for conf_clocks.h validation */ +#include "clock_config_check.h" + +#if !defined(__DOXYGEN__) +/** \internal + * + * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h. + */ +# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \ + if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \ + struct system_gclk_gen_config gclk_conf; \ + system_gclk_gen_get_config_defaults(&gclk_conf); \ + gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \ + gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \ + gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \ + gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \ + system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \ + system_gclk_gen_enable(GCLK_GENERATOR_##n); \ + } + +/** \internal + * + * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h, + * provided that it is not the main Generic Clock Generator channel. + */ +# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \ + if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); } +#endif + +/** \internal + * + * Switch all peripheral clock to a not enabled general clock + * to save power. + */ +static void _switch_peripheral_gclk(void) +{ + uint32_t gclk_id; + struct system_gclk_chan_config gclk_conf; + +#if CONF_CLOCK_GCLK_1_ENABLE == false + gclk_conf.source_generator = GCLK_GENERATOR_1; +#elif CONF_CLOCK_GCLK_2_ENABLE == false + gclk_conf.source_generator = GCLK_GENERATOR_2; +#elif CONF_CLOCK_GCLK_3_ENABLE == false + gclk_conf.source_generator = GCLK_GENERATOR_3; +#elif CONF_CLOCK_GCLK_4_ENABLE == false + gclk_conf.source_generator = GCLK_GENERATOR_4; +#elif CONF_CLOCK_GCLK_5_ENABLE == false + gclk_conf.source_generator = GCLK_GENERATOR_5; +#elif CONF_CLOCK_GCLK_6_ENABLE == false + gclk_conf.source_generator = GCLK_GENERATOR_6; +#elif CONF_CLOCK_GCLK_7_ENABLE == false + gclk_conf.source_generator = GCLK_GENERATOR_7; +#else + gclk_conf.source_generator = GCLK_GENERATOR_7; +#endif + + for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) { + system_gclk_chan_set_config(gclk_id, &gclk_conf); + } +} + +/** + * \brief Initialize clock system based on the configuration in conf_clocks.h. + * + * This function will apply the settings in conf_clocks.h when run from the user + * application. All clock sources and GCLK generators are running when this function + * returns. + * + * \note OSC8M is always enabled and if user selects other clocks for GCLK generators, + * the OSC8M default enable can be disabled after system_clock_init. Make sure the + * clock switch successfully before disabling OSC8M. + */ +void system_clock_init(void) +{ + /* Various bits in the INTFLAG register can be set to one at startup. + This will ensure that these bits are cleared */ + SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | + SYSCTRL_INTFLAG_DFLLRDY; + + system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); + + /* Switch all peripheral clock to a not enabled general clock to save power. */ + _switch_peripheral_gclk(); + + /* XOSC */ +#if CONF_CLOCK_XOSC_ENABLE == true + struct system_clock_source_xosc_config xosc_conf; + system_clock_source_xosc_get_config_defaults(&xosc_conf); + + xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; + xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; + xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; + xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; + xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; + xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; + + system_clock_source_xosc_set_config(&xosc_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); +#endif + + + /* XOSC32K */ +#if CONF_CLOCK_XOSC32K_ENABLE == true + struct system_clock_source_xosc32k_config xosc32k_conf; + system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); + + xosc32k_conf.frequency = 32768UL; + xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; + xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; + xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL; + xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; + xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; + xosc32k_conf.on_demand = false; + xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; + + system_clock_source_xosc32k_set_config(&xosc32k_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); + if (CONF_CLOCK_XOSC32K_ON_DEMAND) { + SYSCTRL->XOSC32K.bit.ONDEMAND = 1; + } +#endif + + + /* OSCK32K */ +#if CONF_CLOCK_OSC32K_ENABLE == true + SYSCTRL->OSC32K.bit.CALIB = + ((*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> + SYSCTRL_FUSES_OSC32K_Pos) & 0x7Ful); + + struct system_clock_source_osc32k_config osc32k_conf; + system_clock_source_osc32k_get_config_defaults(&osc32k_conf); + + osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; + osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; + osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; + osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; + osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; + + system_clock_source_osc32k_set_config(&osc32k_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); +#endif + + + /* DFLL Config (Open and Closed Loop) */ +#if CONF_CLOCK_DFLL_ENABLE == true + struct system_clock_source_dfll_config dfll_conf; + system_clock_source_dfll_get_config_defaults(&dfll_conf); + + dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; + dfll_conf.on_demand = false; + + /* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping + in DFLL.COARSE helps to output a frequency close to 48 MHz.*/ +#define NVM_DFLL_COARSE_POS 58 /* DFLL48M Coarse calibration value bit position.*/ +#define NVM_DFLL_COARSE_SIZE 6 /* DFLL48M Coarse calibration value bit size.*/ + + uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) + + (NVM_DFLL_COARSE_POS / 32)) + >> (NVM_DFLL_COARSE_POS % 32)) + & ((1 << NVM_DFLL_COARSE_SIZE) - 1); + /* In some revision chip, the coarse calibration value is not correct. */ + if (coarse == 0x3f) { + coarse = 0x1f; + } + dfll_conf.coarse_value = coarse; + + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { + dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; + } + +# if CONF_CLOCK_DFLL_QUICK_LOCK == true + dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; +# else + dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; +# endif + +# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true + dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; +# else + dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; +# endif + +# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true + dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; +# else + dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; +# endif + +# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true + dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; +# else + dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; +# endif + + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; + } + + dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; + dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; + + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { + dfll_conf.fine_value = 0x1ff; + dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; + dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; + dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; + dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; + + dfll_conf.multiply_factor = 48000; + } + + system_clock_source_dfll_set_config(&dfll_conf); +#endif + + + /* OSC8M */ + struct system_clock_source_osc8m_config osc8m_conf; + system_clock_source_osc8m_get_config_defaults(&osc8m_conf); + + osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER; + osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND; + osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY; + + system_clock_source_osc8m_set_config(&osc8m_conf); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M); + + + /* GCLK */ +#if CONF_CLOCK_CONFIGURE_GCLK == true + system_gclk_init(); + + /* Configure all GCLK generators except for the main generator, which + * is configured later after all other clock systems are set up */ + MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); + +# if CONF_CLOCK_DFLL_ENABLE == true + /* Enable DFLL reference clock if in closed loop mode */ + if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { + struct system_gclk_chan_config dfll_gclk_chan_conf; + + system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); + dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; + system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); + system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48); + } +# endif + +# if CONF_CLOCK_DPLL_ENABLE == true + /* Enable DPLL internal lock timer and reference clock */ + struct system_gclk_chan_config dpll_gclk_chan_conf; + system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf); + if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) { + dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR; + system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf); + system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL32K); + } + + if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { + dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR; + system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf); + system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL); + } +# endif +#endif + + + /* DFLL Enable (Open and Closed Loop) */ +#if CONF_CLOCK_DFLL_ENABLE == true + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); + if (CONF_CLOCK_DFLL_ON_DEMAND) { + SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1; + } +#endif + + /* DPLL */ +#ifdef FEATURE_SYSTEM_CLOCK_DPLL +# if (CONF_CLOCK_DPLL_ENABLE == true) + + /* Enable DPLL reference clock */ + if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) { + /* XOSC32K should have been enabled for DPLL_REF0 */ + Assert(CONF_CLOCK_XOSC32K_ENABLE); + } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { + /* XOSC should have been enabled for DPLL_REF1 */ + Assert(CONF_CLOCK_XOSC_ENABLE); + } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { + /* GCLK should have been enabled */ + Assert(CONF_CLOCK_CONFIGURE_GCLK); + } else { + Assert(false); + } + + struct system_clock_source_dpll_config dpll_config; + system_clock_source_dpll_get_config_defaults(&dpll_config); + + dpll_config.on_demand = false; + dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; + dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; + dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; + dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; + + dpll_config.filter = CONF_CLOCK_DPLL_FILTER; + dpll_config.lock_time = CONF_CLOCK_DPLL_LOCK_TIME; + + dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; + dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; + dpll_config.reference_divider = CONF_CLOCK_DPLL_REFERENCE_DIVIDER; + dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; + + system_clock_source_dpll_set_config(&dpll_config); + system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); + while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); + if (CONF_CLOCK_DPLL_ON_DEMAND) { + SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1; + } + +# endif +#endif + + /* CPU and BUS clocks */ + system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); + + system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER); + system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER); + system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER); + + /* GCLK 0 */ +#if CONF_CLOCK_CONFIGURE_GCLK == true + /* Configure the main GCLK last as it might depend on other generators */ + _CONF_CLOCK_GCLK_CONFIG(0, ~); +#endif +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_config_check.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_config_check.h new file mode 100644 index 0000000000..fd4757e282 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_config_check.h @@ -0,0 +1,454 @@ +/** + * \file + * + * \brief SAM D21/R21/DA0/DA1 Clock Driver + * + * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CLOCK_CONFIG_CHECK_H +# define CLOCK_CONFIG_CHECK_H + +#if !defined(CONF_CLOCK_FLASH_WAIT_STATES) +# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_CPU_DIVIDER) +# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_APBA_DIVIDER) +# error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_APBB_DIVIDER) +# error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_APBC_DIVIDER) +# error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC8M_PRESCALER) +# error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND) +# error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY) +# error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_ENABLE) +# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL) +# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY) +# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME) +# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL) +# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_ON_DEMAND) +# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY) +# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ENABLE) +# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL) +# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME) +# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL) +# error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT) +# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT) +# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND) +# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY) +# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ENABLE) +# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME) +# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT) +# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT) +# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND) +# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY) +# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_ENABLE) +# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_LOOP_MODE) +# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_ON_DEMAND) +# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_FINE_VALUE) +# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR) +# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR) +# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK) +# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK) +# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP) +# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE) +# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE) +# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE) +# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_ENABLE) +# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_ON_DEMAND) +# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY) +# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS) +# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST) +# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE) +# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOCK_TIME) +# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK) +# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_FILTER) +# error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY) +# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER) +# error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY) +# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR) +# error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR) +# error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_CONFIGURE_GCLK) +# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_ENABLE) +# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_PRESCALER) +# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_ENABLE) +# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_PRESCALER) +# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_ENABLE) +# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_PRESCALER) +# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_ENABLE) +# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_PRESCALER) +# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_ENABLE) +# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_PRESCALER) +# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_ENABLE) +# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_PRESCALER) +# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_ENABLE) +# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_PRESCALER) +# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_ENABLE) +# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_PRESCALER) +# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_ENABLE) +# error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY) +# error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE) +# error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_PRESCALER) +# error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h +#endif + +#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE) +# error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h +#endif + +#endif /* CLOCK_CONFIG_CHECK_H */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_feature.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_feature.h new file mode 100644 index 0000000000..b647b7f694 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/clock_feature.h @@ -0,0 +1,1492 @@ +/** + * \file + * + * \brief SAM Clock Driver + * + * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED +#define SYSTEM_CLOCK_FEATURE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management Driver (SYSTEM CLOCK) + * + * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration + * and management of the device's clocking related functions. This includes + * the various clock sources, bus clocks, and generic clocks within the device, + * with functions to manage the enabling, disabling, source selection, and + * prescaling of clocks to various internal peripherals. + * + * The following peripherals are used by this module: + * + * - GCLK (Generic Clock Management) + * - PM (Power Management) + * - SYSCTRL (Clock Source Control) + * + * The following devices can use this module: + * - Atmel | SMART SAM D20/D21 + * - Atmel | SMART SAM R21 + * - Atmel | SMART SAM D10/D11 + * - Atmel | SMART SAM DA0/DA1 + * + * The outline of this documentation is as follows: + * - \ref asfdoc_sam0_system_clock_prerequisites + * - \ref asfdoc_sam0_system_clock_module_overview + * - \ref asfdoc_sam0_system_clock_special_considerations + * - \ref asfdoc_sam0_system_clock_extra_info + * - \ref asfdoc_sam0_system_clock_examples + * - \ref asfdoc_sam0_system_clock_api_overview + * + * + * \section asfdoc_sam0_system_clock_prerequisites Prerequisites + * + * There are no prerequisites for this module. + * + * + * \section asfdoc_sam0_system_clock_module_overview Module Overview + * The SAM devices contain a sophisticated clocking system, which is designed + * to give the maximum flexibility to the user application. This system allows + * a system designer to tune the performance and power consumption of the device + * in a dynamic manner, to achieve the best trade-off between the two for a + * particular application. + * + * This driver provides a set of functions for the configuration and management + * of the various clock related functionality within the device. + * + * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition + * + * + * + * + * + * + * + * + * + *
      Driver Feature MacroSupported devices
      FEATURE_SYSTEM_CLOCK_DPLLSAMD21, SAMR21, SAMD10, SAMD11, SAMDAx
      + * \note The specific features are only available in the driver when the + * selected device supports those features. + * + * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources + * The SAM devices have a number of master clock source modules, each of + * which being capable of producing a stabilized output frequency, which can then + * be fed into the various peripherals and modules within the device. + * + * Possible clock source modules include internal R/C oscillators, internal + * DFLL modules, as well as external crystal oscillators and/or clock inputs. + * + * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks + * The CPU and AHB/APBx buses are clocked by the same physical clock source + * (referred in this module as the Main Clock), however the APBx buses may + * have additional prescaler division ratios set to give each peripheral bus a + * different clock speed. + * + * The general main clock tree for the CPU and associated buses is shown in + * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below". + * + * \anchor asfdoc_sam0_system_clock_module_clock_tree + * \dot + * digraph overview { + * rankdir=LR; + * clk_src [label="Clock Sources", shape=none, height=0]; + * node [label="CPU Bus" shape=ellipse] cpu_bus; + * node [label="AHB Bus" shape=ellipse] ahb_bus; + * node [label="APBA Bus" shape=ellipse] apb_a_bus; + * node [label="APBB Bus" shape=ellipse] apb_b_bus; + * node [label="APBC Bus" shape=ellipse] apb_c_bus; + * node [label="Main Bus\nPrescaler" shape=square] main_prescaler; + * node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler; + * node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler; + * node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler; + * node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux; + * + * clk_src -> main_clock_mux; + * main_clock_mux -> main_prescaler; + * main_prescaler -> cpu_bus; + * main_prescaler -> ahb_bus; + * main_prescaler -> apb_a_prescaler; + * main_prescaler -> apb_b_prescaler; + * main_prescaler -> apb_c_prescaler; + * apb_a_prescaler -> apb_a_bus; + * apb_b_prescaler -> apb_b_bus; + * apb_c_prescaler -> apb_c_bus; + * } + * \enddot + * + * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking + * To save power, the input clock to one or more peripherals on the AHB and APBx + * buses can be masked away - when masked, no clock is passed into the module. + * Disabling of clocks of unused modules will prevent all access to the masked + * module, but will reduce the overall device power consumption. + * + * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks + * Within the SAM devices there are a number of Generic Clocks; these are used to + * provide clocks to the various peripheral clock domains in the device in a + * standardized manner. One or more master source clocks can be selected as the + * input clock to a Generic Clock Generator, which can prescale down the input + * frequency to a slower rate for use in a peripheral. + * + * Additionally, a number of individually selectable Generic Clock Channels are + * provided, which multiplex and gate the various generator outputs for one or + * more peripherals within the device. This setup allows for a single common + * generator to feed one or more channels, which can then be enabled or disabled + * individually as required. + * + * \anchor asfdoc_sam0_system_clock_module_chain_overview + * \dot + * digraph overview { + * rankdir=LR; + * node [label="Clock\nSource a" shape=square] system_clock_source; + * node [label="Generator 1" shape=square] clock_gen; + * node [label="Channel x" shape=square] clock_chan0; + * node [label="Channel y" shape=square] clock_chan1; + * node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0; + * node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1; + * + * system_clock_source -> clock_gen; + * clock_gen -> clock_chan0; + * clock_chan0 -> peripheral0; + * clock_gen -> clock_chan1; + * clock_chan1 -> peripheral1; + * } + * \enddot + * + * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example + * An example setup of a complete clock chain within the device is shown in + * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below". + * + * \anchor asfdoc_sam0_system_clock_module_chain_example_fig + * \dot + * digraph overview { + * rankdir=LR; + * node [label="External\nOscillator" shape=square] system_clock_source0; + * node [label="Generator 0" shape=square] clock_gen0; + * node [label="Channel x" shape=square] clock_chan0; + * node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0; + * + * system_clock_source0 -> clock_gen0; + * clock_gen0 -> clock_chan0; + * clock_chan0 -> peripheral0; + * node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1; + * node [label="Generator 1" shape=square] clock_gen1; + * node [label="Channel y" shape=square] clock_chan1; + * node [label="Channel z" shape=square] clock_chan2; + * node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1; + * node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2; + * + * system_clock_source1 -> clock_gen1; + * clock_gen1 -> clock_chan1; + * clock_gen1 -> clock_chan2; + * clock_chan1 -> peripheral1; + * clock_chan2 -> peripheral2; + * } + * \enddot + * + * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators + * Each Generic Clock generator within the device can source its input clock + * from one of the provided Source Clocks, and prescale the output for one or + * more Generic Clock Channels in a one-to-many relationship. The generators + * thus allow for several clocks to be generated of different frequencies, + * power usages, and accuracies, which can be turned on and off individually to + * disable the clocks to multiple peripherals as a group. + * + * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels + * To connect a Generic Clock Generator to a peripheral within the + * device, a Generic Clock Channel is used. Each peripheral or + * peripheral group has an associated Generic Clock Channel, which serves as the + * clock input for the peripheral(s). To supply a clock to the peripheral + * module(s), the associated channel must be connected to a running Generic + * Clock Generator and the channel enabled. + * + * \section asfdoc_sam0_system_clock_special_considerations Special Considerations + * + * There are no special considerations for this module. + * + * + * \section asfdoc_sam0_system_clock_extra_info Extra Information + * + * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes: + * - \ref asfdoc_sam0_system_clock_extra_acronyms + * - \ref asfdoc_sam0_system_clock_extra_dependencies + * - \ref asfdoc_sam0_system_clock_extra_errata + * - \ref asfdoc_sam0_system_clock_extra_history + * + * + * \section asfdoc_sam0_system_clock_examples Examples + * + * For a list of examples related to this driver, see + * \ref asfdoc_sam0_system_clock_exqsg. + * + * + * \section asfdoc_sam0_system_clock_api_overview API Overview + * @{ + */ + +#include +#include + +/** + * \name Driver Feature Definition + * Define system clock features set according to different device family. + * @{ + */ +#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAMDA1) || defined(__DOXYGEN__) +/** Digital Phase Locked Loop (DPLL) feature support. */ +# define FEATURE_SYSTEM_CLOCK_DPLL +#endif +/*@}*/ + +/** + * \brief Available start-up times for the XOSC32K. + * + * Available external 32KHz oscillator start-up times, as a number of external + * clock cycles. + */ +enum system_xosc32k_startup { + /** Wait zero clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_0, + /** Wait 32 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_32, + /** Wait 2048 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_2048, + /** Wait 4096 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_4096, + /** Wait 16384 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_16384, + /** Wait 32768 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_32768, + /** Wait 65536 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_65536, + /** Wait 131072 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC32K_STARTUP_131072, +}; + +/** + * \brief Available start-up times for the XOSC. + * + * Available external oscillator start-up times, as a number of external clock + * cycles. + */ +enum system_xosc_startup { + /** Wait one clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_1, + /** Wait two clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_2, + /** Wait four clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_4, + /** Wait eight clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_8, + /** Wait 16 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_16, + /** Wait 32 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_32, + /** Wait 64 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_64, + /** Wait 128 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_128, + /** Wait 256 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_256, + /** Wait 512 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_512, + /** Wait 1024 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_1024, + /** Wait 2048 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_2048, + /** Wait 4096 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_4096, + /** Wait 8192 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_8192, + /** Wait 16384 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_16384, + /** Wait 32768 clock cycles until the clock source is considered stable. */ + SYSTEM_XOSC_STARTUP_32768, +}; + +/** + * \brief Available start-up times for the OSC32K. + * + * Available internal 32KHz oscillator start-up times, as a number of internal + * OSC32K clock cycles. + */ +enum system_osc32k_startup { + /** Wait three clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_3, + /** Wait four clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_4, + /** Wait six clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_6, + /** Wait ten clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_10, + /** Wait 18 clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_18, + /** Wait 34 clock cycles until the clock source is considered stable */ + SYSTEM_OSC32K_STARTUP_34, + /** Wait 66 clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_66, + /** Wait 130 clock cycles until the clock source is considered stable. */ + SYSTEM_OSC32K_STARTUP_130, +}; + +/** + * \brief Division prescalers for the internal 8MHz system clock. + * + * Available prescalers for the internal 8MHz (nominal) system clock. + */ +enum system_osc8m_div { + /** Do not divide the 8MHz RC oscillator output. */ + SYSTEM_OSC8M_DIV_1, + /** Divide the 8MHz RC oscillator output by two. */ + SYSTEM_OSC8M_DIV_2, + /** Divide the 8MHz RC oscillator output by four. */ + SYSTEM_OSC8M_DIV_4, + /** Divide the 8MHz RC oscillator output by eight. */ + SYSTEM_OSC8M_DIV_8, +}; + +/** + * \brief Frequency range for the internal 8MHz RC oscillator. + * + * Internal 8MHz RC oscillator frequency range setting + */ +enum system_osc8m_frequency_range { + /** Frequency range 4MHz to 6MHz. */ + SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6, + /** Frequency range 6MHz to 8MHz. */ + SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8, + /** Frequency range 8MHz to 11MHz. */ + SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11, + /** Frequency range 11MHz to 15MHz. */ + SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15, +}; + +/** + * \brief Main CPU and APB/AHB bus clock source prescaler values. + * + * Available division ratios for the CPU and APB/AHB bus clocks. + */ +enum system_main_clock_div { + /** Divide Main clock by one. */ + SYSTEM_MAIN_CLOCK_DIV_1, + /** Divide Main clock by two. */ + SYSTEM_MAIN_CLOCK_DIV_2, + /** Divide Main clock by four. */ + SYSTEM_MAIN_CLOCK_DIV_4, + /** Divide Main clock by eight. */ + SYSTEM_MAIN_CLOCK_DIV_8, + /** Divide Main clock by 16. */ + SYSTEM_MAIN_CLOCK_DIV_16, + /** Divide Main clock by 32. */ + SYSTEM_MAIN_CLOCK_DIV_32, + /** Divide Main clock by 64. */ + SYSTEM_MAIN_CLOCK_DIV_64, + /** Divide Main clock by 128. */ + SYSTEM_MAIN_CLOCK_DIV_128, +}; + +/** + * \brief External clock source types. + * + * Available external clock source types. + */ +enum system_clock_external { + /** The external clock source is a crystal oscillator. */ + SYSTEM_CLOCK_EXTERNAL_CRYSTAL, + /** The connected clock source is an external logic level clock signal. */ + SYSTEM_CLOCK_EXTERNAL_CLOCK, +}; + +/** + * \brief Operating modes of the DFLL clock source. + * + * Available operating modes of the DFLL clock source module. + */ +enum system_clock_dfll_loop_mode { + /** The DFLL is operating in open loop mode with no feedback. */ + SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, + /** The DFLL is operating in closed loop mode with frequency feedback from + * a low frequency reference clock. + */ + SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE, + +#ifdef SYSCTRL_DFLLCTRL_USBCRM + /** The DFLL is operating in USB recovery mode with frequency feedback + * from USB SOF. + */ + SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM, +#endif +}; + +/** + * \brief Locking behavior for the DFLL during device wake-up. + * + * DFLL lock behavior modes on device wake-up from sleep. + */ +enum system_clock_dfll_wakeup_lock { + /** Keep DFLL lock when the device wakes from sleep. */ + SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, + /** Lose DFLL lock when the devices wakes from sleep. */ + SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW, +}; + +/** + * \brief Fine tracking behavior for the DFLL once a lock has been acquired. + * + * DFLL fine tracking behavior modes after a lock has been acquired. + */ +enum system_clock_dfll_stable_tracking { + /** Keep tracking after the DFLL has gotten a fine lock. */ + SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, + /** Stop tracking after the DFLL has gotten a fine lock. */ + SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE, +}; + +/** + * \brief Chill-cycle behavior of the DFLL module. + * + * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period + * of time when the DFLL output frequency is not measured by the unit, to allow + * the output to stabilize after a change in the input clock source. + */ +enum system_clock_dfll_chill_cycle { + /** Enable a chill cycle, where the DFLL output frequency is not measured. */ + SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, + /** Disable a chill cycle, where the DFLL output frequency is not measured. */ + SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS, +}; + +/** + * \brief QuickLock settings for the DFLL module. + * + * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of + * the DFLL output frequency at the expense of accuracy. + */ +enum system_clock_dfll_quick_lock { + /** Enable the QuickLock feature for looser lock requirements on the DFLL. */ + SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, + /** Disable the QuickLock feature for strict lock requirements on the DFLL. */ + SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS, +}; + +/** + * \brief Available clock sources in the system. + * + * Clock sources available to the GCLK generators. + */ +enum system_clock_source { + /** Internal 8MHz RC oscillator. */ + SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M, + /** Internal 32KHz RC oscillator. */ + SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K, + /** External oscillator. */ + SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC , + /** External 32KHz oscillator. */ + SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K, + /** Digital Frequency Locked Loop (DFLL). */ + SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M, + /** Internal Ultra Low Power 32KHz oscillator. */ + SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K, + /** Generator input pad. */ + SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN, + /** Generic clock generator one output. */ + SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1, +#ifdef FEATURE_SYSTEM_CLOCK_DPLL + /** Digital Phase Locked Loop (DPLL). + * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it. + */ + SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL, +#endif +}; + +/** + * \brief List of APB peripheral buses. + * + * Available bus clock domains on the APB bus. + */ +enum system_clock_apb_bus { + /** Peripheral bus A on the APB bus. */ + SYSTEM_CLOCK_APB_APBA, + /** Peripheral bus B on the APB bus. */ + SYSTEM_CLOCK_APB_APBB, + /** Peripheral bus C on the APB bus. */ + SYSTEM_CLOCK_APB_APBC, +}; + +/** + * \brief Configuration structure for XOSC. + * + * External oscillator clock configuration structure. + */ +struct system_clock_source_xosc_config { + /** External clock type. */ + enum system_clock_external external_clock; + /** Crystal oscillator start-up time. */ + enum system_xosc_startup startup_time; + /** Enable automatic amplitude gain control. */ + bool auto_gain_control; + /** External clock/crystal frequency. */ + uint32_t frequency; + /** Keep the XOSC enabled in standby sleep mode. */ + bool run_in_standby; + /** Run On Demand. If this is set the XOSC won't run + * until requested by a peripheral. */ + bool on_demand; +}; + +/** + * \brief Configuration structure for XOSC32K. + * + * External 32KHz oscillator clock configuration structure. + */ +struct system_clock_source_xosc32k_config { + /** External clock type. */ + enum system_clock_external external_clock; + /** Crystal oscillator start-up time. */ + enum system_xosc32k_startup startup_time; + /** Enable automatic amplitude control. */ + bool auto_gain_control; + /** Enable 1KHz output. */ + bool enable_1khz_output; + /** Enable 32KHz output. */ + bool enable_32khz_output; + /** External clock/crystal frequency. */ + uint32_t frequency; + /** Keep the XOSC32K enabled in standby sleep mode. */ + bool run_in_standby; + /** Run On Demand. If this is set the XOSC32K won't run + * until requested by a peripheral. */ + bool on_demand; + /** Lock configuration after it has been written, + * a device reset will release the lock. */ + bool write_once; +}; + +/** + * \brief Configuration structure for OSC8M. + * + * Internal 8MHz (nominal) oscillator configuration structure. + */ +struct system_clock_source_osc8m_config { + /** Internal 8MHz RC oscillator prescaler. */ + enum system_osc8m_div prescaler; + /** Keep the OSC8M enabled in standby sleep mode. */ + bool run_in_standby; + /** Run On Demand. If this is set the OSC8M won't run + * until requested by a peripheral. */ + bool on_demand; +}; + +/** + * \brief Configuration structure for OSC32K. + * + * Internal 32KHz (nominal) oscillator configuration structure. + */ +struct system_clock_source_osc32k_config { + /** Startup time. */ + enum system_osc32k_startup startup_time; + /** Enable 1KHz output. */ + bool enable_1khz_output; + /** Enable 32KHz output. */ + bool enable_32khz_output; + /** Keep the OSC32K enabled in standby sleep mode. */ + bool run_in_standby; + /** Run On Demand. If this is set the OSC32K won't run + * until requested by a peripheral. */ + bool on_demand; + /** Lock configuration after it has been written, + * a device reset will release the lock. */ + bool write_once; +}; + +/** + * \brief Configuration structure for DFLL. + * + * DFLL oscillator configuration structure. + */ +struct system_clock_source_dfll_config { + /** Loop mode. */ + enum system_clock_dfll_loop_mode loop_mode; + /** Run On Demand. If this is set the DFLL won't run + * until requested by a peripheral. */ + bool on_demand; + /** Enable Quick Lock. */ + enum system_clock_dfll_quick_lock quick_lock; + /** Enable Chill Cycle. */ + enum system_clock_dfll_chill_cycle chill_cycle; + /** DFLL lock state on wakeup. */ + enum system_clock_dfll_wakeup_lock wakeup_lock; + /** DFLL tracking after fine lock. */ + enum system_clock_dfll_stable_tracking stable_tracking; + /** Coarse calibration value (Open loop mode). */ + uint8_t coarse_value; + /** Fine calibration value (Open loop mode). */ + uint16_t fine_value; + /** Coarse adjustment maximum step size (Closed loop mode). */ + uint8_t coarse_max_step; + /** Fine adjustment maximum step size (Closed loop mode). */ + uint16_t fine_max_step; + /** DFLL multiply factor (Closed loop mode. */ + uint16_t multiply_factor; +}; + +/** + * \name External Oscillator Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for XOSC. + * + * Fills a configuration structure with the default configuration for an + * external oscillator module: + * - External Crystal + * - Start-up time of 16384 external clock cycles + * - Automatic crystal gain control mode enabled + * - Frequency of 12MHz + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_xosc_get_config_defaults( + struct system_clock_source_xosc_config *const config) +{ + Assert(config); + + config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; + config->startup_time = SYSTEM_XOSC_STARTUP_16384; + config->auto_gain_control = true; + config->frequency = 12000000UL; + config->run_in_standby = false; + config->on_demand = true; +} + +void system_clock_source_xosc_set_config( + struct system_clock_source_xosc_config *const config); + +/** + * @} + */ + + +/** + * \name External 32KHz Oscillator Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for XOSC32K. + * + * Fills a configuration structure with the default configuration for an + * external 32KHz oscillator module: + * - External Crystal + * - Start-up time of 16384 external clock cycles + * - Automatic crystal gain control mode disabled + * - Frequency of 32.768KHz + * - 1KHz clock output disabled + * - 32KHz clock output enabled + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * - Don't lock registers after configuration has been written + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_xosc32k_get_config_defaults( + struct system_clock_source_xosc32k_config *const config) +{ + Assert(config); + + config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; + config->startup_time = SYSTEM_XOSC32K_STARTUP_16384; + config->auto_gain_control = false; + config->frequency = 32768UL; + config->enable_1khz_output = false; + config->enable_32khz_output = true; + config->run_in_standby = false; + config->on_demand = true; + config->write_once = false; +} + +void system_clock_source_xosc32k_set_config( + struct system_clock_source_xosc32k_config *const config); +/** + * @} + */ + + +/** + * \name Internal 32KHz Oscillator Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for OSC32K. + * + * Fills a configuration structure with the default configuration for an + * internal 32KHz oscillator module: + * - 1KHz clock output enabled + * - 32KHz clock output enabled + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * - Set startup time to 130 cycles + * - Don't lock registers after configuration has been written + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_osc32k_get_config_defaults( + struct system_clock_source_osc32k_config *const config) +{ + Assert(config); + + config->enable_1khz_output = true; + config->enable_32khz_output = true; + config->run_in_standby = false; + config->on_demand = true; + config->startup_time = SYSTEM_OSC32K_STARTUP_130; + config->write_once = false; +} + +void system_clock_source_osc32k_set_config( + struct system_clock_source_osc32k_config *const config); + +/** + * @} + */ + + +/** + * \name Internal 8MHz Oscillator Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for OSC8M. + * + * Fills a configuration structure with the default configuration for an + * internal 8MHz (nominal) oscillator module: + * - Clock output frequency divided by a factor of eight + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_osc8m_get_config_defaults( + struct system_clock_source_osc8m_config *const config) +{ + Assert(config); + + config->prescaler = SYSTEM_OSC8M_DIV_8; + config->run_in_standby = false; + config->on_demand = true; +} + +void system_clock_source_osc8m_set_config( + struct system_clock_source_osc8m_config *const config); + +/** + * @} + */ + + +/** + * \name Internal DFLL Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for DFLL. + * + * Fills a configuration structure with the default configuration for a + * DFLL oscillator module: + * - Open loop mode + * - QuickLock mode enabled + * - Chill cycle enabled + * - Output frequency lock maintained during device wake-up + * - Continuous tracking of the output frequency + * - Default tracking values at the mid-points for both coarse and fine + * tracking parameters + * - Don't run in STANDBY sleep mode + * - Run only when requested by peripheral (on demand) + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_dfll_get_config_defaults( + struct system_clock_source_dfll_config *const config) +{ + Assert(config); + + config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN; + config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; + config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; + config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; + config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; + config->on_demand = true; + + /* Open loop mode calibration value */ + config->coarse_value = 0x1f / 4; /* Midpoint */ + config->fine_value = 0xff / 4; /* Midpoint */ + + /* Closed loop mode */ + config->coarse_max_step = 1; + config->fine_max_step = 1; + config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */ +} + +void system_clock_source_dfll_set_config( + struct system_clock_source_dfll_config *const config); + +/** + * @} + */ + +/** + * \name Clock Source Management + * @{ + */ +enum status_code system_clock_source_write_calibration( + const enum system_clock_source system_clock_source, + const uint16_t calibration_value, + const uint8_t freq_range); + +enum status_code system_clock_source_enable( + const enum system_clock_source system_clock_source); + +enum status_code system_clock_source_disable( + const enum system_clock_source clk_source); + +bool system_clock_source_is_ready( + const enum system_clock_source clk_source); + +uint32_t system_clock_source_get_hz( + const enum system_clock_source clk_source); + +/** + * @} + */ + +/** + * \name Main Clock Management + * @{ + */ + +/** + * \brief Set main CPU clock divider. + * + * Sets the clock divider used on the main clock to provide the CPU clock. + * + * \param[in] divider CPU clock divider to set + */ +static inline void system_cpu_clock_set_divider( + const enum system_main_clock_div divider) +{ + Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider); + PM->CPUSEL.reg = (uint32_t)divider; +} + +/** + * \brief Retrieves the current frequency of the CPU core. + * + * Retrieves the operating frequency of the CPU core, obtained from the main + * generic clock and the set CPU bus divider. + * + * \return Current CPU frequency in Hz. + */ +static inline uint32_t system_cpu_clock_get_hz(void) +{ + return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg); +} + +/** + * \brief Set APBx clock divider. + * + * Set the clock divider used on the main clock to provide the clock for the + * given APBx bus. + * + * \param[in] divider APBx bus divider to set + * \param[in] bus APBx bus to set divider + * + * \returns Status of the clock division change operation. + * + * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given + * \retval STATUS_OK The APBx clock was set successfully + */ +static inline enum status_code system_apb_clock_set_divider( + const enum system_clock_apb_bus bus, + const enum system_main_clock_div divider) +{ + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + PM->APBASEL.reg = (uint32_t)divider; + break; + case SYSTEM_CLOCK_APB_APBB: + PM->APBBSEL.reg = (uint32_t)divider; + break; + case SYSTEM_CLOCK_APB_APBC: + PM->APBCSEL.reg = (uint32_t)divider; + break; + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + return STATUS_OK; + } + + /** + * \brief Retrieves the current frequency of a ABPx. + * + * Retrieves the operating frequency of an APBx bus, obtained from the main + * generic clock and the set APBx bus divider. + * + * \return Current APBx bus frequency in Hz. + */ + static inline uint32_t system_apb_clock_get_hz( + const enum system_clock_apb_bus bus) +{ + uint16_t bus_divider = 0; + + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + bus_divider = PM->APBASEL.reg; + break; + case SYSTEM_CLOCK_APB_APBB: + bus_divider = PM->APBBSEL.reg; + break; + case SYSTEM_CLOCK_APB_APBC: + bus_divider = PM->APBCSEL.reg; + break; + default: + Assert(false); + return 0; + } + + return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider); +} + + +/** + * @} + */ + +/** + * \name Bus Clock Masking + * @{ + */ + +/** + * \brief Set bits in the clock mask for the AHB bus. + * + * This function will set bits in the clock mask for the AHB bus. + * Any bits set to 1 will enable that clock, 0 bits in the mask + * will be ignored. + * + * \param[in] ahb_mask AHB clock mask to enable + */ +static inline void system_ahb_clock_set_mask( + const uint32_t ahb_mask) +{ + PM->AHBMASK.reg |= ahb_mask; +} + +/** + * \brief Clear bits in the clock mask for the AHB bus. + * + * This function will clear bits in the clock mask for the AHB bus. + * Any bits set to 1 will disable that clock, 0 bits in the mask + * will be ignored. + * + * \param[in] ahb_mask AHB clock mask to disable + */ +static inline void system_ahb_clock_clear_mask( + const uint32_t ahb_mask) +{ + PM->AHBMASK.reg &= ~ahb_mask; +} + +/** + * \brief Set bits in the clock mask for an APBx bus. + * + * This function will set bits in the clock mask for an APBx bus. + * Any bits set to 1 will enable the corresponding module clock, zero bits in + * the mask will be ignored. + * + * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from + * the device header files + * \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_* + * constants from the device header files + * + * \returns Status indicating the result of the clock mask change operation. + * + * \retval STATUS_ERR_INVALID_ARG Invalid bus given + * \retval STATUS_OK The clock mask was set successfully + */ +static inline enum status_code system_apb_clock_set_mask( + const enum system_clock_apb_bus bus, + const uint32_t mask) +{ + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + PM->APBAMASK.reg |= mask; + break; + + case SYSTEM_CLOCK_APB_APBB: + PM->APBBMASK.reg |= mask; + break; + + case SYSTEM_CLOCK_APB_APBC: + PM->APBCMASK.reg |= mask; + break; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + + } + + return STATUS_OK; + } + + /** + * \brief Clear bits in the clock mask for an APBx bus. + * + * This function will clear bits in the clock mask for an APBx bus. + * Any bits set to 1 will disable the corresponding module clock, zero bits in + * the mask will be ignored. + * + * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from + * the device header files + * \param[in] bus Bus to clear clock mask bits + * + * \returns Status indicating the result of the clock mask change operation. + * + * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given + * \retval STATUS_OK The clock mask was changed successfully + */ + static inline enum status_code system_apb_clock_clear_mask( + const enum system_clock_apb_bus bus, + const uint32_t mask) +{ + switch (bus) { + case SYSTEM_CLOCK_APB_APBA: + PM->APBAMASK.reg &= ~mask; + break; + + case SYSTEM_CLOCK_APB_APBB: + PM->APBBMASK.reg &= ~mask; + break; + + case SYSTEM_CLOCK_APB_APBC: + PM->APBCMASK.reg &= ~mask; + break; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + return STATUS_OK; + } + + /** + * @} + */ + +#ifdef FEATURE_SYSTEM_CLOCK_DPLL + /** + * \brief Reference clock source of the DPLL module. + */ + enum system_clock_source_dpll_reference_clock { + /** Select XOSC32K as clock reference. */ + SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K, + /** Select XOSC as clock reference. */ + SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC, + /** Select GCLK as clock reference. */ + SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, +}; + +/** + * \brief Lock time-out value of the DPLL module. + */ +enum system_clock_source_dpll_lock_time { + /** Set no time-out as default. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, + /** Set time-out if no lock within 8ms. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04, + /** Set time-out if no lock within 9ms. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS, + /** Set time-out if no lock within 10ms. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS, + /** Set time-out if no lock within 11ms. */ + SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS, +}; + +/** + * \brief Filter type of the DPLL module. + */ +enum system_clock_source_dpll_filter { + /** Default filter mode. */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT, + /** Low bandwidth filter. */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER, + /** High bandwidth filter. */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER, + /** High damping filter. */ + SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER, +}; + +/** + * \brief Configuration structure for DPLL. + * + * DPLL oscillator configuration structure. + */ +struct system_clock_source_dpll_config { + /** Run On Demand. If this is set the DPLL won't run + * until requested by a peripheral. */ + bool on_demand; + /** Keep the DPLL enabled in standby sleep mode. */ + bool run_in_standby; + /** Bypass lock signal. */ + bool lock_bypass; + /** Wake up fast. If this is set DPLL output clock is enabled after + * the startup time. */ + bool wake_up_fast; + /** Enable low power mode. */ + bool low_power_enable; + + /** Output frequency of the clock. */ + uint32_t output_frequency; + /** Reference frequency of the clock. */ + uint32_t reference_frequency; + /** Devider of reference clock. */ + uint16_t reference_divider; + + /** Filter type of the DPLL module. */ + enum system_clock_source_dpll_filter filter; + /** Lock time-out value of the DPLL module. */ + enum system_clock_source_dpll_lock_time lock_time; + /** Reference clock source of the DPLL module. */ + enum system_clock_source_dpll_reference_clock reference_clock; +}; + +/** + * \name Internal DPLL Management + * @{ + */ + +/** + * \brief Retrieve the default configuration for DPLL. + * + * Fills a configuration structure with the default configuration for a + * DPLL oscillator module: + * - Run only when requested by peripheral (on demand) + * - Don't run in STANDBY sleep mode + * - Lock bypass disabled + * - Fast wake up disabled + * - Low power mode disabled + * - Output frequency is 48MHz + * - Reference clock frequency is 32768Hz + * - Not divide reference clock + * - Select REF0 as reference clock + * - Set lock time to default mode + * - Use default filter + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_clock_source_dpll_get_config_defaults( + struct system_clock_source_dpll_config *const config) +{ + config->on_demand = true; + config->run_in_standby = false; + config->lock_bypass = false; + config->wake_up_fast = false; + config->low_power_enable = false; + + config->output_frequency = 48000000; + config->reference_frequency = 32768; + config->reference_divider = 1; + config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K; + + config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT; + config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT; +}; + +void system_clock_source_dpll_set_config( + struct system_clock_source_dpll_config *const config); + +/* @} */ +#endif + +/** + * \name System Clock Initialization + * @{ + */ + +void system_clock_init(void); + +/** + * @} + */ + +/** + * \name System Flash Wait States + * @{ + */ + +/** + * \brief Set flash controller wait states. + * + * Will set the number of wait states that are used by the onboard + * flash memory. The number of wait states depend on both device + * supply voltage and CPU speed. The required number of wait states + * can be found in the electrical characteristics of the device. + * + * \param[in] wait_states Number of wait states to use for internal flash + */ +static inline void system_flash_set_waitstates(uint8_t wait_states) +{ + Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) == + ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos)); + + NVMCTRL->CTRLB.bit.RWS = wait_states; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver + * + * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms + * Below is a table listing the acronyms used in this module, along with their + * intended meanings. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
      AcronymDescription
      DFLLDigital Frequency Locked Loop
      MUXMultiplexer
      OSC32KInternal 32KHz Oscillator
      OSC8MInternal 8MHz Oscillator
      PLLPhase Locked Loop
      OSCOscillator
      XOSCExternal Oscillator
      XOSC32KExternal 32KHz Oscillator
      AHBAdvanced High-performance Bus
      APBAdvanced Peripheral Bus
      DPLLDigital Phase Locked Loop
      + * + * + * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies + * This driver has the following dependencies: + * + * - None + * + * + * \section asfdoc_sam0_system_clock_extra_errata Errata + * + * - This driver implements experimental workaround for errata 9905 + * + * "The DFLL clock must be requested before being configured otherwise a + * write access to a DFLL register can freeze the device." + * This driver will enable and configure the DFLL before the ONDEMAND bit is set. + * + * + * \section asfdoc_sam0_system_clock_extra_history Module History + * An overview of the module history is presented in the table below, with + * details on the enhancements and fixes made to the module since its first + * release. The current version of this corresponds to the newest version in + * the table. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
      Changelog
      + * \li Corrected OSC32K startup time definitions + * \li Support locking of OSC32K and XOSC32K config register (default: false) + * \li Added DPLL support, functions added: + * \c system_clock_source_dpll_get_config_defaults() and + * \c system_clock_source_dpll_set_config() + * \li Moved gclk channel locking feature out of the config struct + * functions added: + * \c system_gclk_chan_lock(), + * \c system_gclk_chan_is_locked() + * \c system_gclk_chan_is_enabled() and + * \c system_gclk_gen_is_enabled() + *
      Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled + * and configured to a failed/not running clock generator
      + * \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false + * \li Fixed system_flash_set_waitstates() failing with an assertion + * if an odd number of wait states provided + *
      + * \li Updated dfll configuration function to implement workaround for + * errata 9905 in the DFLL module + * \li Updated \c system_clock_init() to reset interrupt flags before + * they are used + * \li Fixed \c system_clock_source_get_hz() to return correcy DFLL + * frequency number + *
      \li Fixed \c system_clock_source_is_ready not returning the correct + * state for \c SYSTEM_CLOCK_SOURCE_OSC8M + * \li Renamed the various \c system_clock_source_*_get_default_config() + * functions to \c system_clock_source_*_get_config_defaults() to + * match the remainder of ASF + * \li Added OSC8M calibration constant loading from the device signature + * row when the oscillator is initialized + * \li Updated default configuration of the XOSC32 to disable Automatic + * Gain Control due to silicon errata + *
      Initial Release
      + */ + +/** + * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver + * + * This is a list of the available Quick Start guides (QSGs) and example + * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple + * examples with step-by-step instructions to configure and use this driver in + * a selection of use cases. Note that QSGs can be compiled as a standalone + * application or be added to the user application. + * + * - \subpage asfdoc_sam0_system_clock_basic_use_case + * - \subpage asfdoc_sam0_system_gclk_basic_use_case + * + * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
      Doc. Rev. + * Date + * Comments + *
      E04/2015Added support for SAMDAx.
      D12/2014Added support for SAMR21 and SAMD10/D11.
      C01/2014Added support for SAMD21.
      B06/2013Corrected documentation typos. Fixed missing steps in the Basic + * Use Case Quick Start Guide.
      A06/2013Initial release
      + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/gclk.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/gclk.c new file mode 100644 index 0000000000..607818c2ed --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMR21/gclk.c @@ -0,0 +1,515 @@ +/** + * \file + * + * \brief SAM D21/R21/DA0/DA1 Generic Clock Driver + * + * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include +#include +#include + +/** + * \brief Determines if the hardware module(s) are currently synchronizing to the bus. + * + * Checks to see if the underlying hardware peripheral module(s) are currently + * synchronizing across multiple clock domains to the hardware bus, This + * function can be used to delay further operations on a module until such time + * that it is ready, to prevent blocking delays for synchronization in the + * user application. + * + * \return Synchronization status of the underlying hardware module(s). + * + * \retval false if the module has completed synchronization + * \retval true if the module synchronization is ongoing + */ +static inline bool system_gclk_is_syncing(void) +{ + if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) { + return true; + } + + return false; +} + +/** + * \brief Initializes the GCLK driver. + * + * Initializes the Generic Clock module, disabling and resetting all active + * Generic Clock Generators and Channels to their power-on default values. + */ +void system_gclk_init(void) +{ + /* Turn on the digital interface clock */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK); + + /* Software reset the module to ensure it is re-initialized correctly */ + GCLK->CTRL.reg = GCLK_CTRL_SWRST; + while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) { + /* Wait for reset to complete */ + } +} + +/** + * \brief Writes a Generic Clock Generator configuration to the hardware module. + * + * Writes out a given configuration of a Generic Clock Generator configuration + * to the hardware module. + * + * \note Changing the clock source on the fly (on a running + * generator) can take additional time if the clock source is configured + * to only run on-demand (ONDEMAND bit is set) and it is not currently + * running (no peripheral is requesting the clock source). In this case + * the GCLK will request the new clock while still keeping a request to + * the old clock source until the new clock source is ready. + * + * \note This function will not start a generator that is not already running; + * to start the generator, call \ref system_gclk_gen_enable() + * after configuring a generator. + * + * \param[in] generator Generic Clock Generator index to configure + * \param[in] config Configuration settings for the generator + */ +void system_gclk_gen_set_config( + const uint8_t generator, + struct system_gclk_gen_config *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Cache new register configurations to minimize sync requirements. */ + uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos); + uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos); + + /* Select the requested source clock for the generator */ + new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos; + + /* Configure the clock to be either high or low when disabled */ + if (config->high_when_disabled) { + new_genctrl_config |= GCLK_GENCTRL_OOV; + } + + /* Configure if the clock output to I/O pin should be enabled. */ + if (config->output_enable) { + new_genctrl_config |= GCLK_GENCTRL_OE; + } + + /* Set division factor */ + if (config->division_factor > 1) { + /* Check if division is a power of two */ + if (((config->division_factor & (config->division_factor - 1)) == 0)) { + /* Determine the index of the highest bit set to get the + * division factor that must be loaded into the division + * register */ + + uint32_t div2_count = 0; + + uint32_t mask; + for (mask = (1UL << 1); mask < config->division_factor; + mask <<= 1) { + div2_count++; + } + + /* Set binary divider power of 2 division factor */ + new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos; + new_genctrl_config |= GCLK_GENCTRL_DIVSEL; + } else { + /* Set integer division factor */ + + new_gendiv_config |= + (config->division_factor) << GCLK_GENDIV_DIV_Pos; + + /* Enable non-binary division with increased duty cycle accuracy */ + new_genctrl_config |= GCLK_GENCTRL_IDC; + } + + } + + /* Enable or disable the clock in standby mode */ + if (config->run_in_standby) { + new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY; + } + + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + + system_interrupt_enter_critical_section(); + + GCLK->GENDIV.reg = new_gendiv_config; + + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Enables a Generic Clock Generator that was previously configured. + * + * Starts the clock generation of a Generic Clock Generator that was previously + * configured via a call to \ref system_gclk_gen_set_config(). + * + * \param[in] generator Generic Clock Generator index to enable + */ +void system_gclk_gen_enable( + const uint8_t generator) +{ + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + + system_interrupt_enter_critical_section(); + + /* Select the requested generator */ + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + + /* Enable generator */ + GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN; + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Disables a Generic Clock Generator that was previously enabled. + * + * Stops the clock generation of a Generic Clock Generator that was previously + * started via a call to \ref system_gclk_gen_enable(). + * + * \param[in] generator Generic Clock Generator index to disable + */ +void system_gclk_gen_disable( + const uint8_t generator) +{ + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + + system_interrupt_enter_critical_section(); + + /* Select the requested generator */ + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + + /* Disable generator */ + GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; + while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) { + /* Wait for clock to become disabled */ + } + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Determins if the specified Generic Clock Generator is enabled. + * + * \param[in] generator Generic Clock Generator index to check + * + * \return The enabled status. + * \retval true The Generic Clock Generator is enabled + * \retval false The Generic Clock Generator is disabled + */ +bool system_gclk_gen_is_enabled( + const uint8_t generator) +{ + bool enabled; + + system_interrupt_enter_critical_section(); + + /* Select the requested generator */ + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + /* Obtain the enabled status */ + enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); + + system_interrupt_leave_critical_section(); + + return enabled; +} + +/** + * \brief Retrieves the clock frequency of a Generic Clock generator. + * + * Determines the clock frequency (in Hz) of a specified Generic Clock + * generator, used as a source to a Generic Clock Channel module. + * + * \param[in] generator Generic Clock Generator index + * + * \return The frequency of the generic clock generator, in Hz. + */ +uint32_t system_gclk_gen_get_hz( + const uint8_t generator) +{ + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + + system_interrupt_enter_critical_section(); + + /* Select the appropriate generator */ + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + + /* Get the frequency of the source connected to the GCLK generator */ + uint32_t gen_input_hz = system_clock_source_get_hz( + (enum system_clock_source)GCLK->GENCTRL.bit.SRC); + + *((uint8_t*)&GCLK->GENCTRL.reg) = generator; + + uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL; + + /* Select the appropriate generator division register */ + *((uint8_t*)&GCLK->GENDIV.reg) = generator; + while (system_gclk_is_syncing()) { + /* Wait for synchronization */ + }; + + uint32_t divider = GCLK->GENDIV.bit.DIV; + + system_interrupt_leave_critical_section(); + + /* Check if the generator is using fractional or binary division */ + if (!divsel && divider > 1) { + gen_input_hz /= divider; + } else if (divsel) { + gen_input_hz >>= (divider+1); + } + + return gen_input_hz; +} + +/** + * \brief Writes a Generic Clock configuration to the hardware module. + * + * Writes out a given configuration of a Generic Clock configuration to the + * hardware module. If the clock is currently running, it will be stopped. + * + * \note Once called the clock will not be running; to start the clock, + * call \ref system_gclk_chan_enable() after configuring a clock channel. + * + * \param[in] channel Generic Clock channel to configure + * \param[in] config Configuration settings for the clock + * + */ +void system_gclk_chan_set_config( + const uint8_t channel, + struct system_gclk_chan_config *const config) +{ + /* Sanity check arguments */ + Assert(config); + + /* Cache the new config to reduce sync requirements */ + uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos); + + /* Select the desired generic clock generator */ + new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos; + + /* Disable generic clock channel */ + system_gclk_chan_disable(channel); + + /* Write the new configuration */ + GCLK->CLKCTRL.reg = new_clkctrl_config; +} + +/** + * \brief Enables a Generic Clock that was previously configured. + * + * Starts the clock generation of a Generic Clock that was previously + * configured via a call to \ref system_gclk_chan_set_config(). + * + * \param[in] channel Generic Clock channel to enable + */ +void system_gclk_chan_enable( + const uint8_t channel) +{ + system_interrupt_enter_critical_section(); + + /* Select the requested generator channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + + /* Enable the generic clock */ + GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN; + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Disables a Generic Clock that was previously enabled. + * + * Stops the clock generation of a Generic Clock that was previously started + * via a call to \ref system_gclk_chan_enable(). + * + * \param[in] channel Generic Clock channel to disable + */ +void system_gclk_chan_disable( + const uint8_t channel) +{ + system_interrupt_enter_critical_section(); + + /* Select the requested generator channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + + /* Sanity check WRTLOCK */ + Assert(!GCLK->CLKCTRL.bit.WRTLOCK); + + /* Switch to known-working source so that the channel can be disabled */ + uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN; + GCLK->CLKCTRL.bit.GEN = 0; + + /* Disable the generic clock */ + GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN; + while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) { + /* Wait for clock to become disabled */ + } + + /* Restore previous configured clock generator */ + GCLK->CLKCTRL.bit.GEN = prev_gen_id; + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Determins if the specified Generic Clock channel is enabled. + * + * \param[in] channel Generic Clock Channel index + * + * \return The enabled status. + * \retval true The Generic Clock channel is enabled + * \retval false The Generic Clock channel is disabled + */ +bool system_gclk_chan_is_enabled( + const uint8_t channel) +{ + bool enabled; + + system_interrupt_enter_critical_section(); + + /* Select the requested generic clock channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + enabled = GCLK->CLKCTRL.bit.CLKEN; + + system_interrupt_leave_critical_section(); + + return enabled; +} + +/** + * \brief Locks a Generic Clock channel from further configuration writes. + * + * Locks a generic clock channel from further configuration writes. It is only + * possible to unlock the channel configuration through a power on reset. + * + * \param[in] channel Generic Clock channel to enable + */ +void system_gclk_chan_lock( + const uint8_t channel) +{ + system_interrupt_enter_critical_section(); + + /* Select the requested generator channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + + /* Lock the generic clock */ + GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK; + + system_interrupt_leave_critical_section(); +} + +/** + * \brief Determins if the specified Generic Clock channel is locked. + * + * \param[in] channel Generic Clock Channel index + * + * \return The lock status. + * \retval true The Generic Clock channel is locked + * \retval false The Generic Clock channel is not locked + */ +bool system_gclk_chan_is_locked( + const uint8_t channel) +{ + bool locked; + + system_interrupt_enter_critical_section(); + + /* Select the requested generic clock channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + locked = GCLK->CLKCTRL.bit.WRTLOCK; + + system_interrupt_leave_critical_section(); + + return locked; +} + +/** + * \brief Retrieves the clock frequency of a Generic Clock channel. + * + * Determines the clock frequency (in Hz) of a specified Generic Clock + * channel, used as a source to a device peripheral module. + * + * \param[in] channel Generic Clock Channel index + * + * \return The frequency of the generic clock channel, in Hz. + */ +uint32_t system_gclk_chan_get_hz( + const uint8_t channel) +{ + uint8_t gen_id; + + system_interrupt_enter_critical_section(); + + /* Select the requested generic clock channel */ + *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; + gen_id = GCLK->CLKCTRL.bit.GEN; + + system_interrupt_leave_critical_section(); + + /* Return the clock speed of the associated GCLK generator */ + return system_gclk_gen_get_hz(gen_id); +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/clock.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/clock.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/clock.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/gclk.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/gclk.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/clock/gclk.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/gclk.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/interrupt/system_interrupt_SAMD21/system_interrupt_features.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMD21/system_interrupt_features.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/interrupt/system_interrupt_SAMD21/system_interrupt_features.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMD21/system_interrupt_features.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAML21/system_interrupt_features.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAML21/system_interrupt_features.h new file mode 100644 index 0000000000..2b565282f9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAML21/system_interrupt_features.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief SAM L21 System Interrupt Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED +#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED + +#if !defined(__DOXYGEN__) + +/* Generates a interrupt vector table enum list entry for a given module type + and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */ +# define _MODULE_IRQn(n, module) \ + SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn, + +/* Generates interrupt vector table enum list entries for all instances of a + given module type on the selected device. */ +# define _SYSTEM_INTERRUPT_MODULES(name) \ + MREPEAT(name##_INST_NUM, _MODULE_IRQn, name) + +# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f +# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000003 + +# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0 + +# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 30 +#endif + +/** + * \addtogroup asfdoc_sam0_system_interrupt_group + * @{ + */ + +/** + * \brief Table of possible system interrupt/exception vector numbers. + * + * Table of all possible interrupt and exception vector indexes within the + * SAML21 device. + */ +#if defined(__DOXYGEN__) +/** \note The actual enumeration name is "system_interrupt_vector". */ +enum system_interrupt_vector_saml21 { +#else +enum system_interrupt_vector { +#endif + /** Interrupt vector index for a NMI interrupt. */ + SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn, + /** Interrupt vector index for a Hard Fault memory access exception. */ + SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn, + /** Interrupt vector index for a Supervisor Call exception. */ + SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn, + /** Interrupt vector index for a Pending Supervisor interrupt. */ + SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn, + /** Interrupt vector index for a System Tick interrupt. */ + SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn, + + /** Interrupt vector index for MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_SYSTEM = SYSTEM_IRQn, + /** Interrupt vector index for a Watch Dog peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn, + /** Interrupt vector index for a Real Time Clock peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn, + /** Interrupt vector index for an External Interrupt peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn, + /** Interrupt vector index for a Non Volatile Memory Controller interrupt. */ + SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn, + /** Interrupt vector index for a Direct Memory Access interrupt. */ + SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn, + /** Interrupt vector index for a Universal Serial Bus interrupt. */ + SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn, + /** Interrupt vector index for an Event System interrupt. */ + SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn, +#if defined(__DOXYGEN__) + /** Interrupt vector index for a SERCOM peripheral interrupt. + * + * Each specific device may contain several SERCOM peripherals; each module + * instance will have its own entry in the table, with the instance number + * substituted for "n" in the entry name (e.g. + * \c SYSTEM_INTERRUPT_MODULE_SERCOM0). + */ + SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn, + + /** Interrupt vector index for a Timer/Counter Control peripheral interrupt. + * + * Each specific device may contain several TCC peripherals; each module + * instance will have its own entry in the table, with the instance number + * substituted for "n" in the entry name (e.g. + * \c SYSTEM_INTERRUPT_MODULE_TCC0). + */ + SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn, + + /** Interrupt vector index for a Timer/Counter peripheral interrupt. + * + * Each specific device may contain several TC peripherals; each module + * instance will have its own entry in the table, with the instance number + * substituted for "n" in the entry name (e.g. + * \c SYSTEM_INTERRUPT_MODULE_TC3). + */ + SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn, +#else + _SYSTEM_INTERRUPT_MODULES(SERCOM) + + _SYSTEM_INTERRUPT_MODULES(TCC) +#if (SAML21J) + _SYSTEM_INTERRUPT_MODULES(TC) +#else + SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn, + SYSTEM_INTERRUPT_MODULE_TC1 = TC1_IRQn, + SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn, +#endif +#endif + + /** Interrupt vector index for an Analog Comparator peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn, + /** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn, + /** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */ + SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn, + /** Interrupt vector index for a Peripheral Touch Controller peripheral + * interrupt. */ + SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn, + /** Interrupt vector index for a AES peripheral + * interrupt. */ + SYSTEM_INTERRUPT_MODULE_AES = AES_IRQn, + /** Interrupt vector index for a TRNG peripheral + * interrupt. */ + SYSTEM_INTERRUPT_MODULE_TRNG = TRNG_IRQn, + /** Interrupt vector index for a PICOP peripheral + * interrupt. */ + SYSTEM_INTERRUPT_MODULE_PICOP = PICOP_IRQn, +}; + +/** @} */ + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/interrupt/system_interrupt_SAMR21/system_interrupt_features.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMR21/system_interrupt_features.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/interrupt/system_interrupt_SAMR21/system_interrupt_features.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/TARGET_SAMR21/system_interrupt_features.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/interrupt/system_interrupt.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/interrupt/system_interrupt.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/interrupt/system_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/interrupt/system_interrupt.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/interrupt/system_interrupt.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/pinmux/pinmux.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/pinmux/pinmux.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/pinmux/pinmux.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/pinmux/pinmux.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/pinmux/pinmux.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/power/power_sam_d_r/power.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMD21/power.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/power/power_sam_d_r/power.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMD21/power.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAML21/power.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAML21/power.h new file mode 100644 index 0000000000..8bce873c26 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAML21/power.h @@ -0,0 +1,889 @@ +/** + * \file + * + * \brief SAM L21 Power functionality + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef POWER_H_INCLUDED +#define POWER_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup asfdoc_sam0_system_group + * @{ + */ + +/** + * \brief Device sleep modes. + * + * List of available sleep modes in the device. A table of clocks available in + * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode. + */ +enum system_sleepmode { + /** IDLE sleep mode */ + SYSTEM_SLEEPMODE_IDLE = PM_SLEEPCFG_SLEEPMODE(0x2), + /** STANDBY sleep mode */ + SYSTEM_SLEEPMODE_STANDBY = PM_SLEEPCFG_SLEEPMODE_STANDBY, + /** BACKUP sleep mode */ + SYSTEM_SLEEPMODE_BACKUP = PM_SLEEPCFG_SLEEPMODE_BACKUP, + /** OFF sleep mode */ + SYSTEM_SLEEPMODE_OFF = PM_SLEEPCFG_SLEEPMODE_OFF, +}; + +/** + * \brief Performance level. + * + * List of performance levels. Performance level technique consists of + * adjusting the regulator output voltage to reduce power consumption. + */ +enum system_performance_level { + /** Performance level 0 */ + SYSTEM_PERFORMANCE_LEVEL_0 = PM_PLCFG_PLSEL_PL0, + /** Performance level 2 */ + SYSTEM_PERFORMANCE_LEVEL_2 = PM_PLCFG_PLSEL_PL2, +}; + +/** + * \brief RAM Back-biasing mode. + * + * List of RAM back bias modes. By default, in standby sleep mode, + * RAM is in low power mode (back biased) if its power domain is in + * retention state. This behavior can be changed by configuring the Back Bias + * bit groups in STDBYCFG(STDBYCFG.BBIASxx). + */ +enum system_ram_back_bias_mode { + /** Retention Back biasing mode */ + SYSTEM_RAM_BACK_BIAS_RETENTION = 0, + /** Standby Back Biasing mode */ + SYSTEM_RAM_BACK_BIAS_STANDBY, + /** Standby OFF mode */ + SYSTEM_RAM_BACK_BIAS_STANDBY_OFF, + /** Always OFF mode */ + SYSTEM_RAM_BACK_BIAS_OFF, +}; + +/** + * \brief Linked power domain. + * + * List of linked power domains. Power domains can be linked to each other. + * It allows a power domain (PDn) to be kept in active state if the inferior + * power domain (PDn-1) is in active state too. + */ +enum system_linked_power_domain { + /** Power domains PD0/PD1/PD2 are not linked */ + SYSTEM_LINKED_POWER_DOMAIN_DEFAULT = PM_STDBYCFG_LINKPD_DEFAULT_Val, + /** Power domains PD0 and PD1 are linked */ + SYSTEM_LINKED_POWER_DOMAIN_PD01 = PM_STDBYCFG_LINKPD_PD01_Val, + /** Power domains PD1 and PD2 are linked */ + SYSTEM_LINKED_POWER_DOMAIN_PD12 = PM_STDBYCFG_LINKPD_PD12_Val, + /** All Power domains are linked */ + SYSTEM_LINKED_POWER_DOMAIN_PD012 = PM_STDBYCFG_LINKPD_PD012_Val, +}; + +/** + * \brief Power domain. + * + * List of power domains. Power domain gating technique consists of turning + * on or off power domain voltage to save power while keeping other domains + * powered up. + */ +enum system_power_domain { + /** All power domains switching are handled by hardware */ + SYSTEM_POWER_DOMAIN_DEFAULT = PM_STDBYCFG_PDCFG_DEFAULT_Val, + /** Power domain 0 (PD0) is forced ACTIVE */ + SYSTEM_POWER_DOMAIN_PD0 = PM_STDBYCFG_PDCFG_PD0_Val, + /** Power domain 0 and 1 (PD0 and PD1) are forced ACTIVE */ + SYSTEM_POWER_DOMAIN_PD01 = PM_STDBYCFG_PDCFG_PD01_Val, + /** All power domains are forced ACTIVE */ + SYSTEM_POWER_DOMAIN_PD012 = PM_STDBYCFG_PDCFG_PD012_Val, +}; + +/** + * \brief Voltage regulator. + * + * Voltage regulators selection. In active mode, the voltage regulator + * can be chosen on the fly between a LDO or a Buck converter. + */ +enum system_voltage_regulator_sel { + /** The voltage regulator in active mode is a LDO voltage regulator */ + SYSTEM_VOLTAGE_REGULATOR_LDO = SUPC_VREG_SEL_LDO_Val, + /** The voltage regulator in active mode is a buck converter */ + SYSTEM_VOLTAGE_REGULATOR_BUCK = SUPC_VREG_SEL_BUCK_Val, +}; + +/** + * \brief Low power efficiency. + * + * Low power mode efficiency. + */ +enum system_voltage_regulator_low_power_efficiency { + /** The voltage regulator in Low power mode has the default efficiency and + support the whole VDD range (1.62V to 3.6V) */ + SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT, + /** The voltage regulator in Low power mode has the highest efficiency and + support the limited VDD range (2.5V to 3.6V) */ + SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_HIGHTEST, +}; + +/** + * \brief Voltage reference value. + * + * Voltage references selection. + */ +enum system_voltage_references_sel { + /** 1.0V voltage reference typical value */ + SYSTEM_VOLTAGE_REFERENCE_1V0 = SUPC_VREF_SEL_1V0_Val, + /** 1.1V voltage reference typical value */ + SYSTEM_VOLTAGE_REFERENCE_1V1 = SUPC_VREF_SEL_1V1_Val, + /** 1.2V voltage reference typical value */ + SYSTEM_VOLTAGE_REFERENCE_1V2 = SUPC_VREF_SEL_1V2_Val, + /** 1.25V voltage reference typical value */ + SYSTEM_VOLTAGE_REFERENCE_1V25 = SUPC_VREF_SEL_1V25_Val, + /** 2.0V voltage reference typical value */ + SYSTEM_VOLTAGE_REFERENCE_2V0 = SUPC_VREF_SEL_2V0_Val, + /** 2.2V voltage reference typical value */ + SYSTEM_VOLTAGE_REFERENCE_2V2 = SUPC_VREF_SEL_2V2_Val, + /** 2.4V voltage reference typical value */ + SYSTEM_VOLTAGE_REFERENCE_2V4 = SUPC_VREF_SEL_2V4_Val, + /** 2.5V voltage reference typical value */ + SYSTEM_VOLTAGE_REFERENCE_2V5 = SUPC_VREF_SEL_2V5_Val, +}; + +/** + * \brief Battery power switch configuration enum. + * + * Enum for Battery power switch modes. + */ +enum system_battery_power_switch { + /** The backup domain is always supplied by main power */ + SYSTEM_BATTERY_POWER_SWITCH_NONE = SUPC_BBPS_CONF_NONE_Val, + /** The power switch is handled by the automatic power switch */ + SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC = SUPC_BBPS_CONF_APWS_Val, + /** The backup domain is always supplied by battery backup power */ + SYSTEM_BATTERY_POWER_SWITCH_FORCED = SUPC_BBPS_CONF_FORCED_Val, + /** The power switch is handled by the BOD33 */ + SYSTEM_BATTERY_POWER_SWITCH_BOD33 = SUPC_BBPS_CONF_BOD33_Val, +}; + +/** + * \brief Voltage reference. + * + * List of available voltage references (VREF) that may be used within the + * device. + */ +enum system_voltage_reference { + /** Temperature sensor voltage reference */ + SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE, + /** Voltage reference output */ + SYSTEM_VOLTAGE_REFERENCE_OUTPUT, +}; + +/** + * \brief Backup IO enum. + * + * List of Backup input and output pins. + * If enabled (\ref system_backup_pin_output_enable), the pins can be driven + * by the SUPC. + */ +enum system_backup_pin { + /** Power Supply OK status pin */ + SYSTEM_BACKUP_PIN_PSOK = (0x1 << 0), + /** Backup output pin 0 */ + SYSTEM_BACKUP_PIN_OUT_0 = (0x1 << 1), + /** Backup output pin 1 */ + SYSTEM_BACKUP_PIN_OUT_1 = (0x1 << 2) +}; + +/** + * \brief Standby configuration. + * + * Configuration structure for standby mode. + */ +struct system_standby_config { + /** Power domain */ + enum system_power_domain power_domain; + /** Enable dynamic power gating for power domain 0 */ + bool enable_dpgpd0; + /** Enable dynamic power gating for power domain 1 */ + bool enable_dpgpd1; + /** Automatic VREG switching disable */ + bool disable_avregsd; + /** Linked power domain */ + enum system_linked_power_domain linked_power_domain; + /** Back bias for HMCRAMCHS */ + enum system_ram_back_bias_mode hmcramchs_back_bias; + /** Back bias for HMCRAMCLP */ + enum system_ram_back_bias_mode hmcramclp_back_bias; +}; + +/** + * \brief Voltage Regulator System (VREG) Control configuration. + * + * Configuration structure for VREG. + */ +struct system_voltage_regulator_config { + /** Voltage scaling period */ + uint8_t voltage_scale_period; + /** Voltage scaling voltage step */ + uint8_t voltage_scale_step; + /** Run in standby in standby sleep mode */ + bool run_in_standby; + /** Voltage Regulator Selection */ + enum system_voltage_regulator_sel regulator_sel; + /** Low power efficiency */ + enum system_voltage_regulator_low_power_efficiency low_power_efficiency; +}; + +/** + * \brief Voltage References System (VREF) Control configuration. + * + * Configuration structure for VREF. + */ +struct system_voltage_references_config { + /** Voltage References Selection */ + enum system_voltage_references_sel sel; + /** On Demand Control */ + bool on_demand; + /** Run in standby */ + bool run_in_standby; +}; + +/** + * \brief Battery Backup Power Switch (BBPS) Control configuration. + * + * Configuration structure for Battery Backup Power Switch (BBPS). + */ +struct system_battery_backup_power_switch_config { + /** Enable device wake up when BBPS switches from + battery backup power to main power */ + bool wake_enabled; + /** Battery backup power switch configuration */ + enum system_battery_power_switch battery_power_switch; +}; + +/** + * \name Voltage Regulator + * @{ + */ + +/** + * \brief Retrieve the default configuration for voltage regulator. + * + * Fills a configuration structure with the default configuration: + * - Voltage scaling period is 1μs + * - Voltage scaling voltage step is 2*min_step + * - The voltage regulator is in low power mode in Standby sleep mode + * - The voltage regulator in active mode is an LDO voltage regulator + * - The voltage regulator in Low power mode has the default efficiency + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_voltage_regulator_get_config_defaults( + struct system_voltage_regulator_config *const config) +{ + Assert(config); + config->voltage_scale_period = 0; + config->voltage_scale_step = 0; + config->run_in_standby = false; + config->regulator_sel = SYSTEM_VOLTAGE_REGULATOR_LDO; + config->low_power_efficiency = SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT; +} + +/** + * \brief Configure voltage regulator. + * + * Configures voltage regulator with the given configuration. + * + * \param[in] config Voltage regulator configuration structure containing + * the new config + */ +static inline void system_voltage_regulator_set_config( + struct system_voltage_regulator_config *const config) +{ + Assert(config); + SUPC->VREG.bit.VSPER = config->voltage_scale_period; + SUPC->VREG.bit.VSVSTEP = config->voltage_scale_step; + SUPC->VREG.bit.RUNSTDBY = config->run_in_standby; + SUPC->VREG.bit.SEL = config->regulator_sel; + SUPC->VREG.bit.LPEFF = config->low_power_efficiency; + while(!(SUPC->STATUS.reg & SUPC_STATUS_VREGRDY)) { + ; + } +} + +/** +* \brief Enable the selected voltage regulator. + * + * Enables the selected voltage regulator source. + */ +static inline void system_voltage_regulator_enable(void) +{ + SUPC->VREG.reg |= SUPC_VREG_ENABLE; +} + +/** + * \brief Disable the selected voltage regulator. + * + * Disables the selected voltage regulator. + */ +static inline void system_voltage_regulator_disable(void) +{ + SUPC->VREG.reg &= ~SUPC_VREG_ENABLE; +} + +/** + * @} + */ + +/** + * \name Voltage References + * @{ + */ + +/** + * \brief Retrieve the default configuration for voltage reference. + * + * Fill a configuration structure with the default configuration: + * - 1.0V voltage reference typical value + * - On demand control disabled + * - The voltage reference and the temperature sensor are halted during standby sleep mode + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_voltage_reference_get_config_defaults( + struct system_voltage_references_config *const config) +{ + Assert(config); + config->sel = SYSTEM_VOLTAGE_REFERENCE_1V0; + config->on_demand = false; + config->run_in_standby = false; +} + +/** + * \brief Configure voltage reference. + * + * Configures voltage reference with the given configuration. + * + * \param[in] config Voltage reference configuration structure containing + * the new config + */ +static inline void system_voltage_reference_set_config( + struct system_voltage_references_config *const config) +{ + Assert(config); + SUPC->VREF.bit.SEL = config->sel; + SUPC->VREF.bit.ONDEMAND = config->on_demand; + SUPC->VREF.bit.RUNSTDBY = config->run_in_standby; +} + +/** + * \brief Enable the selected voltage reference. + * + * Enables the selected voltage reference source, making the voltage reference + * available on a pin as well as an input source to the analog peripherals. + * + * \param[in] vref Voltage reference to enable + */ +static inline void system_voltage_reference_enable( + const enum system_voltage_reference vref) +{ + switch (vref) { + case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: + SUPC->VREF.reg |= SUPC_VREF_TSEN; + break; + case SYSTEM_VOLTAGE_REFERENCE_OUTPUT: + SUPC->VREF.reg |= SUPC_VREF_VREFOE; + break; + default: + Assert(false); + return; + } +} + +/** + * \brief Disable the selected voltage reference. + * + * Disables the selected voltage reference source. + * + * \param[in] vref Voltage reference to disable + */ +static inline void system_voltage_reference_disable( + const enum system_voltage_reference vref) +{ + switch (vref) { + case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: + SUPC->VREF.reg &= ~SUPC_VREF_TSEN; + break; + case SYSTEM_VOLTAGE_REFERENCE_OUTPUT: + SUPC->VREF.reg &= ~SUPC_VREF_VREFOE; + break; + default: + Assert(false); + return; + } +} + +/** + * @} + */ + +/** + * \name Battery Backup Power Switch + * @{ + */ + +/** + * \brief Retrieve the default configuration for battery backup power switch control. + * + * Fills a configuration structure with the default configuration: + * - The main Power Supply OK status is not available on the PSOK pin + * - The device is not woken up when switched from battery backup power to main power + * - The backup domain is always supplied by main power + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_battery_backup_power_switch_get_config_defaults( + struct system_battery_backup_power_switch_config *const config) +{ + Assert(config); + config->wake_enabled = false; + config->battery_power_switch = SYSTEM_BATTERY_POWER_SWITCH_NONE; +} + +/** + * \brief Configure battery backup power switch. + * + * Configures battery backup power switch with the given configuration. + * + * \param[in] config Battery backup power switch configuration structure containing + * the new config + */ +static inline void system_battery_backup_power_switch_set_config( + struct system_battery_backup_power_switch_config *const config) +{ + Assert(config); + uint32_t new_config = SUPC->BBPS.reg & SUPC_BBPS_PSOKEN; + + if(config->wake_enabled) { + new_config |= SUPC_BBPS_WAKEEN; + } + + new_config |= SUPC_BBPS_CONF(config->battery_power_switch); + + SUPC->BBPS.reg = new_config; + + if (config->battery_power_switch == SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC) { + while (!(SUPC->STATUS.reg & SUPC_STATUS_APWSRDY)) { + ; + } + } +} + +/** + * @} + */ + +/** + * \name Output Pins in Backup Mode + * @{ + */ + +/** + * \brief Enable the backup pin output. + * + * The output is enabled and driven by the SUPC. + * + * \param[in] pin Backup pin index + */ +static inline void system_backup_pin_output_enable( + enum system_backup_pin pin) +{ + if (pin == SYSTEM_BACKUP_PIN_PSOK) { + SUPC->BBPS.reg |= SUPC_BBPS_PSOKEN; + } else { + SUPC->BKOUT.reg |= SUPC_BKOUT_EN(pin >> 1); + } +} + +/** + * \brief Disable the backup pin output. + * + * The output is not enabled. + * + * \param[in] pin Backup pin index + */ +static inline void system_backup_pin_output_disable( + enum system_backup_pin pin) +{ + if (pin == SYSTEM_BACKUP_PIN_PSOK) { + SUPC->BBPS.reg &= ~SUPC_BBPS_PSOKEN; + } else { + SUPC->BKOUT.reg &= ~SUPC_BKOUT_EN(pin >> 1); + } +} + +/** + * \brief Check if backup pin output is enabled. + * + * \param[in] pin Backup pin index + * + * \return The enabled status. + * \retval true The output is enabled + * \retval false The output is not enabled + */ +static inline bool system_backup_pin_output_is_enabled( + enum system_backup_pin pin) +{ + bool enabled = false; + + if (pin == SYSTEM_BACKUP_PIN_PSOK) { + if (SUPC->BBPS.reg & SUPC_BBPS_PSOKEN) { + enabled = true; + } + } else { + if (SUPC->BKOUT.reg & SUPC_BKOUT_EN(pin >> 1)) { + enabled = true; + } + } + return enabled; +} + +/** + * \brief Enable the backup pin toggle on RTC event. + * + * Toggle output on RTC event is enabled. + * + * \param[in] pin Backup pin index + */ +static inline void system_backup_pin_output_enable_rtc_toggle( + enum system_backup_pin pin) +{ + Assert(pin != SYSTEM_BACKUP_PIN_PSOK); + + SUPC->BKOUT.reg |= SUPC_BKOUT_RTCTGL(pin >> 1); +} + +/** + * \brief Disable the backup pin toggle on RTC event. + * + * Toggle output on RTC event is disabled. + * + * \param[in] pin Backup pin index + */ +static inline void system_backup_pin_output_disable_rtc_toggle( + enum system_backup_pin pin) +{ + Assert(pin != SYSTEM_BACKUP_PIN_PSOK); + + SUPC->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(pin >> 1); +} + +/** + * \brief Set the backup pin. + * + * Set the corresponding output pin. + * + * \param[in] pin Backup pin index + */ +static inline void system_backup_pin_output_set( + enum system_backup_pin pin) +{ + Assert(pin != SYSTEM_BACKUP_PIN_PSOK); + + SUPC->BKOUT.reg |= SUPC_BKOUT_SET(pin >> 1); +} + +/** + * \brief Clear the backup pin. + * + * Clear the corresponding output. + * + * \param[in] pin Backup pin index + */ +static inline void system_backup_pin_output_clear( + enum system_backup_pin pin) +{ + Assert(pin != SYSTEM_BACKUP_PIN_PSOK); + + SUPC->BKOUT.reg |= SUPC_BKOUT_CLR(pin >> 1); +} + +/** + * \brief Get the backup I/O input values. + * + * Get the backup I/O data input values. If the corresponding pin is enabled, + * the I/O input value is given on the pin. + * + * \param[in] pin Backup pin index + * + * \return The backup I/O input level value. + */ +static inline bool system_backup_pin_output_get(enum system_backup_pin pin) +{ + Assert(pin != SYSTEM_BACKUP_PIN_PSOK); + + return (SUPC->BKIN.reg & SUPC_BKIN_BKIN(pin >> 1)); +} + +/** + * @} + */ + +/** + * \name Device Sleep Control + * @{ + */ + +/** + * \brief Set the sleep mode of the device. + * + * Sets the sleep mode of the device; the configured sleep mode will be entered + * upon the next call of the \ref system_sleep() function. + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode. + * + * \param[in] sleep_mode Sleep mode to configure for the next sleep operation + */ +static inline void system_set_sleepmode( + const enum system_sleepmode sleep_mode) +{ + PM->SLEEPCFG.reg = sleep_mode; + while(PM->SLEEPCFG.reg != sleep_mode) ; +} + +/** + * \brief Put the system to sleep waiting for interrupt. + * + * Executes a device DSB (Data Synchronization Barrier) instruction to ensure + * all ongoing memory accesses have completed. Further, a WFI (Wait For Interrupt) + * instruction is executed to place the device into the sleep mode specified by + * \ref system_set_sleepmode. + */ +static inline void system_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * @} + */ + +/** + * \name Performance Level Control + * @{ + */ + +/** + * \brief Switch performance level. + * + * The bus frequency must be reduced prior to scaling down the performance level, + * in order to not exceed the maximum frequency allowed for the performance level. + * + * When scaling up the performance level (for example from PL0 to PL2), the bus + * frequency can be increased first when the performance level transition is + * completed. Check the performance level status before increasing the frequency. + * + * \param[in] performance_level Performance level to switch + * + * \retval STATUS_ERR_INVALID_ARG Invalid parameter + * \retval STATUS_OK Successfully + */ +static inline enum status_code system_switch_performance_level( + const enum system_performance_level performance_level) +{ + + if (performance_level == (enum system_performance_level)PM->PLCFG.reg) { + return STATUS_OK; + } + + /* Clear performance level status */ + PM->INTFLAG.reg = PM_INTFLAG_PLRDY; + + /* Switch performance level */ + PM->PLCFG.reg = performance_level; + + /* Waiting performance level ready */ + while (!PM->INTFLAG.reg) { + ; + } + return STATUS_OK; +} + +/** + * \brief Get performance level. + * + * Get performance level. + * + * \return Current performance level. + */ +static inline enum system_performance_level system_get_performance_level(void) +{ + return (enum system_performance_level)PM->PLCFG.reg; +} + +/** + * \brief Get performance level status. + * + * Get performance level status. + * \return Performance level status: Written to one when the performance level is ready. + */ +static inline uint8_t system_get_performance_level_status(void) +{ + return PM->INTFLAG.reg; +} + +/** + * \brief Clear performance level status. + * + * Clear performance level status. + */ +static inline void system_clear_performance_level_status(void) +{ + PM->INTFLAG.reg = PM_INTFLAG_PLRDY; +} + +/** + * @} + */ + +/** + * \name Standby Configuration + * @{ + */ + +/** + * \brief Retrieve the default configuration for standby. + * + * Fills a configuration structure with the default configuration for standby: + * - Retention back biasing mode for HMCRAMCLP + * - Retention back biasing mode for HMCRAMCHS + * - Power domains PD0/PD1/PD2 are not linked + * - Automatic VREG switching is used + * - Dynamic power gating for power domain 1 is disabled + * - Dynamic power gating for power domain 0 is disabled + * - All power domains switching are handled by hardware + * + * \param[out] config Configuration structure to fill with default values + */ +static inline void system_standby_get_config_defaults( + struct system_standby_config *const config) +{ + Assert(config); + config->power_domain = SYSTEM_POWER_DOMAIN_DEFAULT; + config->enable_dpgpd0 = false; + config->enable_dpgpd1 = false; + config->disable_avregsd = false; + config->linked_power_domain = SYSTEM_LINKED_POWER_DOMAIN_DEFAULT; + config->hmcramchs_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION; + config->hmcramclp_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION; +} + +/** + * \brief Configure standby mode. + * + * Configures standby with the given configuration. + * + * \param[in] config Standby configuration structure containing + * the new config + */ +static inline void system_standby_set_config( + struct system_standby_config *const config) +{ + Assert(config); + PM->STDBYCFG.reg = PM_STDBYCFG_PDCFG(config->power_domain) + | (config->enable_dpgpd0 << PM_STDBYCFG_DPGPD0_Pos) + | (config->enable_dpgpd1 << PM_STDBYCFG_DPGPD1_Pos) + | (config->disable_avregsd << PM_STDBYCFG_AVREGSD_Pos) + | PM_STDBYCFG_LINKPD(config->linked_power_domain) + | PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias) + | PM_STDBYCFG_BBIASLP(config->hmcramclp_back_bias); +} + +/** + * @} + */ + +/** + * \name I/O Retention + * @{ + */ + +/** + * \brief Enable I/O retention. + * + * Enable I/O retention. After waking up from Backup mode, I/O lines are held + * until the bit is written to 0. + */ +static inline void system_io_retension_enable(void) +{ + PM->CTRLA.reg = PM_CTRLA_IORET; +} + +/** + * \brief Disable I/O retention. + * + * Disable IO retention. After waking up from Backup mode, I/O lines are not held. + */ +static inline void system_io_retension_disable(void) +{ + PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET); +} + +/** + * @} + */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* POWER_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMR21/power.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMR21/power.h new file mode 100644 index 0000000000..c0920ab668 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/power/TARGET_SAMR21/power.h @@ -0,0 +1,224 @@ +/** + * \file + * + * \brief SAM Power related functionality + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef POWER_H_INCLUDED +#define POWER_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup asfdoc_sam0_system_group + * @{ + */ + +/** + * \brief Voltage references within the device. + * + * List of available voltage references (VREF) that may be used within the + * device. + */ +enum system_voltage_reference { + /** Temperature sensor voltage reference. */ + SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE, + /** Bandgap voltage reference. */ + SYSTEM_VOLTAGE_REFERENCE_BANDGAP, +}; + +/** + * \brief Device sleep modes. + * + * List of available sleep modes in the device. A table of clocks available in + * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode. + */ +enum system_sleepmode { + /** IDLE 0 sleep mode. */ + SYSTEM_SLEEPMODE_IDLE_0, + /** IDLE 1 sleep mode. */ + SYSTEM_SLEEPMODE_IDLE_1, + /** IDLE 2 sleep mode. */ + SYSTEM_SLEEPMODE_IDLE_2, + /** Standby sleep mode. */ + SYSTEM_SLEEPMODE_STANDBY, +}; + + + +/** + * \name Voltage References + * @{ + */ + +/** + * \brief Enable the selected voltage reference + * + * Enables the selected voltage reference source, making the voltage reference + * available on a pin as well as an input source to the analog peripherals. + * + * \param[in] vref Voltage reference to enable + */ +static inline void system_voltage_reference_enable( + const enum system_voltage_reference vref) +{ + switch (vref) { + case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: + SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN; + break; + + case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: + SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN; + break; + + default: + Assert(false); + return; + } +} + +/** + * \brief Disable the selected voltage reference + * + * Disables the selected voltage reference source. + * + * \param[in] vref Voltage reference to disable + */ +static inline void system_voltage_reference_disable( + const enum system_voltage_reference vref) +{ + switch (vref) { + case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: + SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN; + break; + + case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: + SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN; + break; + + default: + Assert(false); + return; + } +} + +/** + * @} + */ + + +/** + * \name Device Sleep Control + * @{ + */ + +/** + * \brief Set the sleep mode of the device + * + * Sets the sleep mode of the device; the configured sleep mode will be entered + * upon the next call of the \ref system_sleep() function. + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode. + * + * \param[in] sleep_mode Sleep mode to configure for the next sleep operation + * + * \retval STATUS_OK Operation completed successfully + * \retval STATUS_ERR_INVALID_ARG The requested sleep mode was invalid or not + * available + */ +static inline enum status_code system_set_sleepmode( + const enum system_sleepmode sleep_mode) +{ +#if (SAMD20 || SAMD21) + /* Errata: Make sure that the Flash does not power all the way down + * when in sleep mode. */ + NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val; +#endif + + switch (sleep_mode) { + case SYSTEM_SLEEPMODE_IDLE_0: + case SYSTEM_SLEEPMODE_IDLE_1: + case SYSTEM_SLEEPMODE_IDLE_2: + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + PM->SLEEP.reg = sleep_mode; + break; + + case SYSTEM_SLEEPMODE_STANDBY: + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + break; + + default: + return STATUS_ERR_INVALID_ARG; + } + + return STATUS_OK; +} + +/** + * \brief Put the system to sleep waiting for interrupt + * + * Executes a device DSB (Data Synchronization Barrier) instruction to ensure + * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt) + * instruction to place the device into the sleep mode specified by + * \ref system_set_sleepmode until woken by an interrupt. + */ +static inline void system_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * @} + */ + +/** @} */ +#ifdef __cplusplus +} +#endif + +#endif /* POWER_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/reset/reset_sam_d_r/reset.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/reset/reset_sam_d_r/reset.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h new file mode 100644 index 0000000000..e8200b54bf --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h @@ -0,0 +1,253 @@ +/** + * \file + * + * \brief SAM Reset functionality + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef RESET_H_INCLUDED +#define RESET_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup asfdoc_sam0_system_group + * @{ + */ + +/** + * \brief Reset causes of the system. + * + * List of possible reset causes of the system. + */ +enum system_reset_cause { + /** The system was last reset by a backup reset */ + SYSTEM_RESET_CAUSE_BACKUP = RSTC_RCAUSE_BACKUP, + /** The system was last reset by a software reset */ + SYSTEM_RESET_CAUSE_SOFTWARE = RSTC_RCAUSE_SYST, + /** The system was last reset by the watchdog timer */ + SYSTEM_RESET_CAUSE_WDT = RSTC_RCAUSE_WDT, + /** The system was last reset because the external reset line was pulled low */ + SYSTEM_RESET_CAUSE_EXTERNAL_RESET = RSTC_RCAUSE_EXT, + /** The system was last reset by the BOD33 */ + SYSTEM_RESET_CAUSE_BOD33 = RSTC_RCAUSE_BOD33, + /** The system was last reset by the BOD12 */ + SYSTEM_RESET_CAUSE_BOD12 = RSTC_RCAUSE_BOD12, + /** The system was last reset by the POR (Power on reset) */ + SYSTEM_RESET_CAUSE_POR = RSTC_RCAUSE_POR, +}; + +/** + * \brief Backup exit source after a backup reset occurs. + * + * List of possible backup exit source. + */ +enum system_reset_backup_exit_source { + /** The backup exit source was external wakeup */ + SYSTEM_RESET_BACKKUP_EXIT_EXTWAKE = RSTC_BKUPEXIT_EXTWAKE, + /** The backup exit source was RTC interrupt */ + SYSTEM_RESET_BACKKUP_EXIT_RTC = RSTC_BKUPEXIT_RTC, + /** The backup exit source was battery backup power switch */ + SYSTEM_RESET_BACKKUP_EXIT_BBPS = RSTC_BKUPEXIT_BBPS, +}; + +/** + * \brief Wakeup debounce counter value. + * + * Wakeup debounce counter value when waking up by external wakeup pin from backup mode. + */ +enum system_wakeup_debounce_count { + /** No debouncing */ + SYSTEM_WAKEUP_DEBOUNCE_OFF = RSTC_WKDBCONF_WKDBCNT_OFF, + /** Input pin shall be active for at least two 32KHz clock periods */ + SYSTEM_WAKEUP_DEBOUNCE_2CK32 = RSTC_WKDBCONF_WKDBCNT_2K32, + /** Input pin shall be active for at least three 32KHz clock periods */ + SYSTEM_WAKEUP_DEBOUNCE_3CK32 = RSTC_WKDBCONF_WKDBCNT_3CK32, + /** Input pin shall be active for at least 32 32KHz clock periods */ + SYSTEM_WAKEUP_DEBOUNCE_32CK32 = RSTC_WKDBCONF_WKDBCNT_32CK32, + /** Input pin shall be active for at least 512 32KHz clock periods */ + SYSTEM_WAKEUP_DEBOUNCE_512CK32 = RSTC_WKDBCONF_WKDBCNT_512CK32, + /** Input pin shall be active for at least 4096 32KHz clock periods */ + SYSTEM_WAKEUP_DEBOUNCE_4096CK32 = RSTC_WKDBCONF_WKDBCNT_4096CK32, + /** Input pin shall be active for at least 32768 32KHz clock periods */ + SYSTEM_WAKEUP_DEBOUNCE_32768CK32 = RSTC_WKDBCONF_WKDBCNT_32768CK32, +}; + +/** + * \name Reset Control + * @{ + */ + +/** + * \brief Reset the MCU. + * + * Resets the MCU and all associated peripherals and registers, except RTC, + * OSC32KCTRL, RSTC, GCLK (if WRTLOCK is set), and I/O retention state of PM. + * + */ +static inline void system_reset(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Get the reset cause. + * + * Retrieves the cause of the last system reset. + * + * \return An enum value indicating the cause of the last system reset. + */ +static inline enum system_reset_cause system_get_reset_cause(void) +{ + return (enum system_reset_cause)RSTC->RCAUSE.reg; +} + +/** + * @} + */ + +/** + * \name Backup Exit Control + * @{ + */ + +/** + * \brief Get the backup exit source. + * + * Get the backup exit source when a backup reset occurs. + * + * \return An enum value indicating the latest backup exit source. + */ +static inline enum system_reset_backup_exit_source system_get_backup_exit_source(void) +{ + return (enum system_reset_backup_exit_source)RSTC->BKUPEXIT.reg; +} + +/** + * \brief Set wakeup debounce counter. + * + * Set the wakeup debounce counter value with the given count. + * + * \param[in] wakeup_debounce_count Wakeup debounce counter value + */ +static inline void system_set_pin_wakeup_debounce_counter( + const enum system_wakeup_debounce_count wakeup_debounce_count) +{ + RSTC->WKDBCONF.reg = wakeup_debounce_count; +} + +/** + * \brief Set low polarity of wakeup input pin. + * + * Set low polarity with the given wakeup input pin mask. + * + * \param[in] pin_mask Input pin mask + */ +static inline void system_set_pin_wakeup_polarity_low(const uint16_t pin_mask) +{ + RSTC->WKPOL.reg &= ~(RSTC_WKPOL_WKPOL(pin_mask)); +} + +/** + * \brief Set high polarity of wakeup input pin. + * + * Set high polarity with the given wakeup input pin mask. + * + * \param[in] pin_mask Input pin mask + */ +static inline void system_set_pin_wakeup_polarity_high(const uint16_t pin_mask) +{ + RSTC->WKPOL.reg |= RSTC_WKPOL_WKPOL(pin_mask); +} + +/** + * \brief Enable wakeup of input pin from the backup mode. + * + * Enable pin wakeup from the backup mode with the given pin mask. + * + * \param[in] pin Input pin mask + */ +static inline void system_enable_pin_wakeup(const uint16_t pin_mask) +{ + RSTC->WKEN.reg |= RSTC_WKEN_WKEN(pin_mask); +} + +/** + * \brief Disable wakeup of input pin from the backup mode. + * + * Disable pin wakeup from the backup mode with the given pin mask. + * + * \param[in] pin Input pin mask + */ +static inline void system_disable_pin_wakeup(const uint16_t pin_mask) +{ + RSTC->WKEN.reg &= ~(RSTC_WKEN_WKEN(pin_mask)); +} + +/** + * \brief Check whether any of the enabled wake up pins are active and caused the wakeup. + * + * Check whether any of the enabled wake up pins are active and caused the wakeup + * from backup sleep mode when exiting backup mode. + * + * \return Pin mask, the corresponding pin is active when its pin mask is 1. + */ +static inline uint16_t system_get_pin_wakeup_cause(void) +{ + return (RSTC_WKCAUSE_MASK & (RSTC->WKCAUSE.reg >> RSTC_WKCAUSE_WKCAUSE_Pos)); +} + +/** + * @} + */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* RESET_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h new file mode 100644 index 0000000000..698ec7d364 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h @@ -0,0 +1,119 @@ +/** + * \file + * + * \brief SAM Reset related functionality + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef RESET_H_INCLUDED +#define RESET_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup asfdoc_sam0_system_group + * @{ + */ + +/** + * \brief Reset causes of the system. + * + * List of possible reset causes of the system. + */ +enum system_reset_cause { + /** The system was last reset by a software reset. */ + SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST, + /** The system was last reset by the watchdog timer. */ + SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT, + /** The system was last reset because the external reset line was pulled low. */ + SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT, + /** The system was last reset by the BOD33. */ + SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33, + /** The system was last reset by the BOD12. */ + SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12, + /** The system was last reset by the POR (Power on reset). */ + SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR, +}; + + +/** + * \name Reset Control + * @{ + */ + +/** + * \brief Reset the MCU. + * + * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources, + * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set). + * + */ +static inline void system_reset(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Return the reset cause. + * + * Retrieves the cause of the last system reset. + * + * \return An enum value indicating the cause of the last system reset. + */ +static inline enum system_reset_cause system_get_reset_cause(void) +{ + return (enum system_reset_cause)PM->RCAUSE.reg; +} + +/** + * @} + */ + +/** @} */ +#ifdef __cplusplus +} +#endif + +#endif /* RESET_H_INCLUDED */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/system.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/system.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/system.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/system/system.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/system.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tc/tc_sam_d_r/tc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMD21/tc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tc/tc_sam_d_r/tc.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMD21/tc.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAML21/tc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAML21/tc.c new file mode 100644 index 0000000000..05ecf901c5 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAML21/tc.c @@ -0,0 +1,717 @@ +/** + * \file + * + * \brief SAM TC - Timer Counter Driver + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "tc.h" + +#if TC_ASYNC == true +# include "tc_interrupt.h" +# include +#endif + +/** + * \internal Find the index of given TC module instance. + * + * \param[in] TC module instance pointer. + * + * \return Index of the given TC module instance. + */ +uint8_t _tc_get_inst_index( + Tc *const hw) +{ + /* List of available TC modules. */ + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + + /* Find index for TC instance. */ + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + if (hw == tc_modules[i]) { + return i; + } + } + + /* Invalid data given. */ + Assert(false); + return 0; +} + + +/** + * \brief Initializes a hardware TC module instance. + * + * Enables the clock and initializes the TC module, based on the given + * configuration values. + * + * \param[in,out] module_inst Pointer to the software module instance struct + * \param[in] hw Pointer to the TC hardware module + * \param[in] config Pointer to the TC configuration options struct + * + * \return Status of the initialization procedure. + * + * \retval STATUS_OK The module was initialized successfully + * \retval STATUS_BUSY Hardware module was busy when the + * initialization procedure was attempted + * \retval STATUS_INVALID_ARG An invalid configuration option or argument + * was supplied + * \retval STATUS_ERR_DENIED Hardware module was already enabled, or the + * hardware module is configured in 32-bit + * slave mode + */ +enum status_code tc_init( + struct tc_module *const module_inst, + Tc *const hw, + const struct tc_config *const config) +{ + /* Sanity check arguments */ + Assert(hw); + Assert(module_inst); + Assert(config); + + /* Temporary variable to hold all updates to the CTRLA + * register before they are written to it */ + uint32_t ctrla_tmp = 0; + /* Temporary variable to hold all updates to the CTRLBSET + * register before they are written to it */ + uint8_t ctrlbset_tmp = 0; + /* Temporary variable to hold TC instance number */ + uint8_t instance = _tc_get_inst_index(hw); + +#if (SAMC20) || (SAMC21) + /* Array of GLCK ID for different TC instances */ + uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID}; + /* Array of MCLK APB mask bit position for different TC instances */ + uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0, + SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1, + SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2, + SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3, + SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC4 + }; +#elif (SAML21J) + /* Array of GLCK ID for different TC instances */ + uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID}; + /* Array of MCLK APB mask bit position for different TC instances */ + uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0, + SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1, + SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2, + SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3, + SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4 + }; +#else + /* Array of GLCK ID for different TC instances */ + uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC4_GCLK_ID}; + /* Array of PM APB mask bit position for different TC instances */ + uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0, + SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1, + SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4 + }; +#endif + + struct system_pinmux_config pin_config; + struct system_gclk_chan_config gclk_chan_config; + +#if TC_ASYNC == true + /* Initialize parameters */ + for (uint8_t i = 0; i < TC_CALLBACK_N; i++) { + module_inst->callback[i] = NULL; + } + module_inst->register_callback_mask = 0x00; + module_inst->enable_callback_mask = 0x00; + + /* Register this instance for callbacks*/ + _tc_instances[instance] = module_inst; +#endif + + /* Associate the given device instance with the hardware module */ + module_inst->hw = hw; + + module_inst->double_buffering_enabled = config->double_buffering_enabled; + + /* Check if odd numbered TC modules are being configured in 32-bit + * counter size. Only even numbered counters are allowed to be + * configured in 32-bit counter size. + */ + if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && + ((instance + TC_INSTANCE_OFFSET) & 0x01)) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } + + /* Make the counter size variable in the module_inst struct reflect + * the counter size in the module + */ + module_inst->counter_size = config->counter_size; + + if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) { + /* We are in the middle of a reset. Abort. */ + return STATUS_BUSY; + } + + if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) { + /* Module is used as a slave */ + return STATUS_ERR_DENIED; + } + + if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { + /* Module must be disabled before initialization. Abort. */ + return STATUS_ERR_DENIED; + } + + /* Set up the TC PWM out pin for channel 0 */ + if (config->pwm_channel[0].enabled) { + system_pinmux_get_config_defaults(&pin_config); + pin_config.mux_position = config->pwm_channel[0].pin_mux; + pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; + system_pinmux_pin_set_config( + config->pwm_channel[0].pin_out, &pin_config); + } + + /* Set up the TC PWM out pin for channel 1 */ + if (config->pwm_channel[1].enabled) { + system_pinmux_get_config_defaults(&pin_config); + pin_config.mux_position = config->pwm_channel[1].pin_mux; + pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; + system_pinmux_pin_set_config( + config->pwm_channel[1].pin_out, &pin_config); + } + + /* Enable the user interface clock in the MCLK */ + system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[instance*2], + inst_mclk_apbmask[2*instance+1]); + + /* Enable the slave counter if counter_size is 32-bit */ + if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && (instance+1 < TC_INST_NUM)) { + /* Enable the user interface clock in the MCLK */ + system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[instance*2+1], + inst_mclk_apbmask[2*instance+2]); + } + + + /* Setup clock for module */ + system_gclk_chan_get_config_defaults(&gclk_chan_config); + gclk_chan_config.source_generator = config->clock_source; + system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config); + system_gclk_chan_enable(inst_gclk_id[instance]); + + /* Set ctrla register */ + ctrla_tmp = + (uint32_t)config->counter_size | + (uint32_t)config->reload_action | + (uint32_t)config->clock_prescaler; + + for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { + if (config->enable_capture_on_channel[i] == true) { + ctrla_tmp |= (TC_CTRLA_CAPTEN(1) << i); + } + } + + for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { + if (config->enable_capture_on_IO[i] == true) { + ctrla_tmp |= (TC_CTRLA_COPEN(1) << i); + } + } + + ctrla_tmp |= (config->run_in_standby << TC_CTRLA_RUNSTDBY_Pos) + |(config->on_demand << TC_CTRLA_ONDEMAND_Pos); + + /* Write configuration to register */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + hw->COUNT8.CTRLA.reg = ctrla_tmp; + + /* Write configuration to register */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + hw->COUNT8.WAVE.reg = config->wave_generation; + + /* Set ctrlb register */ + if (config->oneshot) { + ctrlbset_tmp = TC_CTRLBSET_ONESHOT; + } + + if (config->count_direction) { + ctrlbset_tmp |= TC_CTRLBSET_DIR; + } + + /* Clear old ctrlb configuration */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + hw->COUNT8.CTRLBCLR.reg = 0xFF; + + /* Check if we actually need to go into a wait state. */ + if (ctrlbset_tmp) { + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + /* Write configuration to register */ + hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp; + } + + /* Set drvvtrl register*/ + hw->COUNT8.DRVCTRL.reg = config->waveform_invert_output; + + /* Write configuration to register */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Switch for TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT8.COUNT.reg = + config->counter_8_bit.value; + + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT8.PER.reg = + config->counter_8_bit.period; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT8.CC[0].reg = + config->counter_8_bit.compare_capture_channel[0]; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT8.CC[1].reg = + config->counter_8_bit.compare_capture_channel[1]; + + return STATUS_OK; + + case TC_COUNTER_SIZE_16BIT: + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT16.COUNT.reg + = config->counter_16_bit.value; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT16.CC[0].reg = + config->counter_16_bit.compare_capture_channel[0]; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT16.CC[1].reg = + config->counter_16_bit.compare_capture_channel[1]; + + return STATUS_OK; + + case TC_COUNTER_SIZE_32BIT: + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT32.COUNT.reg + = config->counter_32_bit.value; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT32.CC[0].reg = + config->counter_32_bit.compare_capture_channel[0]; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT32.CC[1].reg = + config->counter_32_bit.compare_capture_channel[1]; + + return STATUS_OK; + } + + Assert(false); + return STATUS_ERR_INVALID_ARG; +} + +/** + * \brief Sets TC module count value. + * + * Sets the current timer count value of a initialized TC module. The + * specified TC module may be started or stopped. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] count New timer count value to set + * + * \return Status of the count update procedure. + * + * \retval STATUS_OK The timer count was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified + */ +enum status_code tc_set_count_value( + const struct tc_module *const module_inst, + const uint32_t count) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance*/ + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Write to based on the TC counter_size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + tc_module->COUNT8.COUNT.reg = (uint8_t)count; + return STATUS_OK; + + case TC_COUNTER_SIZE_16BIT: + tc_module->COUNT16.COUNT.reg = (uint16_t)count; + return STATUS_OK; + + case TC_COUNTER_SIZE_32BIT: + tc_module->COUNT32.COUNT.reg = (uint32_t)count; + return STATUS_OK; + + default: + return STATUS_ERR_INVALID_ARG; + } +} + +/** + * \brief Get TC module count value. + * + * Retrieves the current count value of a TC module. The specified TC module + * may be started or stopped. + * + * \param[in] module_inst Pointer to the software module instance struct + * + * \return Count value of the specified TC module. + */ +uint32_t tc_get_count_value( + const struct tc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Read synchronization */ + tc_sync_read_count(module_inst); + + /* Get a pointer to the module's hardware instance */ + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Read from based on the TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + return (uint32_t)tc_module->COUNT8.COUNT.reg; + + case TC_COUNTER_SIZE_16BIT: + return (uint32_t)tc_module->COUNT16.COUNT.reg; + + case TC_COUNTER_SIZE_32BIT: + return tc_module->COUNT32.COUNT.reg; + } + + Assert(false); + return 0; +} + +/** + * \brief Gets the TC module capture value. + * + * Retrieves the capture value in the indicated TC module capture channel. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] channel_index Index of the Compare Capture channel to read + * + * \return Capture value stored in the specified timer channel. + */ +uint32_t tc_get_capture_value( + const struct tc_module *const module_inst, + const enum tc_compare_capture_channel channel_index) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Read out based on the TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + return tc_module->COUNT8.CC[channel_index].reg; + } + + case TC_COUNTER_SIZE_16BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + return tc_module->COUNT16.CC[channel_index].reg; + } + + case TC_COUNTER_SIZE_32BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + return tc_module->COUNT32.CC[channel_index].reg; + } + } + + Assert(false); + return 0; +} + +/** + * \brief Sets a TC module compare value. + * + * Writes a compare value to the given TC module compare/capture channel. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] channel_index Index of the compare channel to write to + * \param[in] compare New compare value to set + * + * \return Status of the compare update procedure. + * + * \retval STATUS_OK The compare value was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied + */ +enum status_code tc_set_compare_value( + const struct tc_module *const module_inst, + const enum tc_compare_capture_channel channel_index, + const uint32_t compare) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + Assert(compare); + + /* Get a pointer to the module's hardware instance */ + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Read out based on the TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + if (module_inst->double_buffering_enabled) { + tc_module->COUNT8.CCBUF[channel_index].reg = + (uint8_t)compare; + } else { + tc_module->COUNT8.CC[channel_index].reg = + (uint8_t)compare; + } + return STATUS_OK; + } + case TC_COUNTER_SIZE_16BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + if (module_inst->double_buffering_enabled) { + tc_module->COUNT16.CCBUF[channel_index].reg = + (uint16_t)compare; + } else { + tc_module->COUNT16.CC[channel_index].reg = + (uint16_t)compare; + } + return STATUS_OK; + } + + case TC_COUNTER_SIZE_32BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + if (module_inst->double_buffering_enabled) { + tc_module->COUNT32.CCBUF[channel_index].reg = + (uint32_t)compare; + } else { + tc_module->COUNT32.CC[channel_index].reg = + (uint32_t)compare; + } + return STATUS_OK; + } + } + + return STATUS_ERR_INVALID_ARG; +} + +/** + * \brief Resets the TC module. + * + * Resets the TC module, restoring all hardware module registers to their + * default values and disabling the module. The TC module will not be + * accessible while the reset is being performed. + * + * \note When resetting a 32-bit counter only the master TC module's instance + * structure should be passed to the function. + * + * \param[in] module_inst Pointer to the software module instance struct + * + * \return Status of the procedure. + * \retval STATUS_OK The module was reset successfully + * \retval STATUS_ERR_UNSUPPORTED_DEV A 32-bit slave TC module was passed to + * the function. Only use reset on master + * TC + */ +enum status_code tc_reset( + const struct tc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + + if (tc_module->STATUS.reg & TC_STATUS_SLAVE) { + return STATUS_ERR_UNSUPPORTED_DEV; + } + + /* Disable this module if it is running */ + if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { + tc_disable(module_inst); + while (tc_is_syncing(module_inst)) { + /* wait while module is disabling */ + } + } + + /* Reset this TC module */ + tc_module->CTRLA.reg |= TC_CTRLA_SWRST; + + return STATUS_OK; +} + +/** + * \brief Set the timer TOP/period value. + * + * For 8-bit counter size this function writes the top value to the period + * register. + * + * For 16- and 32-bit counter size this function writes the top value to + * Capture Compare register 0. The value in this register can not be used for + * any other purpose. + * + * \note This function is designed to be used in PWM or frequency + * match modes only. When the counter is set to 16- or 32-bit counter + * size. In 8-bit counter size it will always be possible to change the + * top value even in normal mode. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] top_value New timer TOP value to set + * + * \return Status of the TOP set procedure. + * + * \retval STATUS_OK The timer TOP value was updated successfully + * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the + * module instance is invalid + */ +enum status_code tc_set_top_value ( + const struct tc_module *const module_inst, + const uint32_t top_value) +{ + Assert(module_inst); + Assert(module_inst->hw); + Assert(top_value); + + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + if (module_inst->double_buffering_enabled) { + tc_module->COUNT8.PERBUF.reg = (uint8_t)top_value; + } else { + tc_module->COUNT8.PER.reg = (uint8_t)top_value; + } + return STATUS_OK; + + case TC_COUNTER_SIZE_16BIT: + if (module_inst->double_buffering_enabled) { + tc_module->COUNT16.CCBUF[0].reg = (uint16_t)top_value; + } else { + tc_module->COUNT16.CC[0].reg = (uint16_t)top_value; + } + return STATUS_OK; + + case TC_COUNTER_SIZE_32BIT: + if (module_inst->double_buffering_enabled) { + tc_module->COUNT32.CCBUF[0].reg = (uint32_t)top_value; + } else { + tc_module->COUNT32.CC[0].reg = (uint32_t)top_value; + } + return STATUS_OK; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMR21/tc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMR21/tc.c new file mode 100644 index 0000000000..00702905be --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/TARGET_SAMR21/tc.c @@ -0,0 +1,684 @@ +/** + * \file + * + * \brief SAM TC - Timer Counter Driver + * + * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "tc.h" + +#if TC_ASYNC == true +# include "tc_interrupt.h" +# include + +/** \internal + * Converts a given TC index to its interrupt vector index. + */ +# define _TC_INTERRUPT_VECT_NUM(n, unused) \ + SYSTEM_INTERRUPT_MODULE_TC##n, +#endif + +#if !defined(__DOXYGEN__) +# define _TC_GCLK_ID(n,unused) TPASTE3(TC,n,_GCLK_ID) , +# define _TC_PM_APBCMASK(n,unused) TPASTE2(PM_APBCMASK_TC,n) , + +# define TC_INST_GCLK_ID { MRECURSION(TC_INST_NUM, _TC_GCLK_ID, TC_INST_MAX_ID) } +# define TC_INST_PM_APBCMASK { MRECURSION(TC_INST_NUM, _TC_PM_APBCMASK, TC_INST_MAX_ID) } + +#endif + +/** + * \internal Find the index of given TC module instance. + * + * \param[in] TC module instance pointer. + * + * \return Index of the given TC module instance. + */ +uint8_t _tc_get_inst_index( + Tc *const hw) +{ + /* List of available TC modules. */ + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + + /* Find index for TC instance. */ + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + if (hw == tc_modules[i]) { + return i; + } + } + + /* Invalid data given. */ + Assert(false); + return 0; +} + + +/** + * \brief Initializes a hardware TC module instance. + * + * Enables the clock and initializes the TC module, based on the given + * configuration values. + * + * \param[in,out] module_inst Pointer to the software module instance struct + * \param[in] hw Pointer to the TC hardware module + * \param[in] config Pointer to the TC configuration options struct + * + * \return Status of the initialization procedure. + * + * \retval STATUS_OK The module was initialized successfully + * \retval STATUS_BUSY Hardware module was busy when the + * initialization procedure was attempted + * \retval STATUS_INVALID_ARG An invalid configuration option or argument + * was supplied + * \retval STATUS_ERR_DENIED Hardware module was already enabled, or the + * hardware module is configured in 32-bit + * slave mode + */ +enum status_code tc_init( + struct tc_module *const module_inst, + Tc *const hw, + const struct tc_config *const config) +{ + /* Sanity check arguments */ + Assert(hw); + Assert(module_inst); + Assert(config); + + /* Temporary variable to hold all updates to the CTRLA + * register before they are written to it */ + uint16_t ctrla_tmp = 0; + /* Temporary variable to hold all updates to the CTRLBSET + * register before they are written to it */ + uint8_t ctrlbset_tmp = 0; + /* Temporary variable to hold all updates to the CTRLC + * register before they are written to it */ + uint8_t ctrlc_tmp = 0; + /* Temporary variable to hold TC instance number */ + uint8_t instance = _tc_get_inst_index(hw); + + /* Array of GLCK ID for different TC instances */ + uint8_t inst_gclk_id[] = TC_INST_GCLK_ID; + /* Array of PM APBC mask bit position for different TC instances */ + uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK; + + struct system_pinmux_config pin_config; + struct system_gclk_chan_config gclk_chan_config; + +#if TC_ASYNC == true + /* Initialize parameters */ + for (uint8_t i = 0; i < TC_CALLBACK_N; i++) { + module_inst->callback[i] = NULL; + } + module_inst->register_callback_mask = 0x00; + module_inst->enable_callback_mask = 0x00; + + /* Register this instance for callbacks*/ + _tc_instances[instance] = module_inst; +#endif + + /* Associate the given device instance with the hardware module */ + module_inst->hw = hw; + +#if SAMD10 || SAMD11 + /* Check if even numbered TC modules are being configured in 32-bit + * counter size. Only odd numbered counters are allowed to be + * configured in 32-bit counter size. + */ + if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && + !((instance + TC_INSTANCE_OFFSET) & 0x01)) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } +#else + /* Check if odd numbered TC modules are being configured in 32-bit + * counter size. Only even numbered counters are allowed to be + * configured in 32-bit counter size. + */ + if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && + ((instance + TC_INSTANCE_OFFSET) & 0x01)) { + Assert(false); + return STATUS_ERR_INVALID_ARG; + } +#endif + + /* Make the counter size variable in the module_inst struct reflect + * the counter size in the module + */ + module_inst->counter_size = config->counter_size; + + if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) { + /* We are in the middle of a reset. Abort. */ + return STATUS_BUSY; + } + + if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) { + /* Module is used as a slave */ + return STATUS_ERR_DENIED; + } + + if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { + /* Module must be disabled before initialization. Abort. */ + return STATUS_ERR_DENIED; + } + + /* Set up the TC PWM out pin for channel 0 */ + if (config->pwm_channel[0].enabled) { + system_pinmux_get_config_defaults(&pin_config); + pin_config.mux_position = config->pwm_channel[0].pin_mux; + pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; + system_pinmux_pin_set_config( + config->pwm_channel[0].pin_out, &pin_config); + } + + /* Set up the TC PWM out pin for channel 1 */ + if (config->pwm_channel[1].enabled) { + system_pinmux_get_config_defaults(&pin_config); + pin_config.mux_position = config->pwm_channel[1].pin_mux; + pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; + system_pinmux_pin_set_config( + config->pwm_channel[1].pin_out, &pin_config); + } + + /* Enable the user interface clock in the PM */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, + inst_pm_apbmask[instance]); + + /* Enable the slave counter if counter_size is 32-bit */ + if ((config->counter_size == TC_COUNTER_SIZE_32BIT)) { + /* Enable the user interface clock in the PM */ + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, + inst_pm_apbmask[instance + 1]); + } + + /* Setup clock for module */ + system_gclk_chan_get_config_defaults(&gclk_chan_config); + gclk_chan_config.source_generator = config->clock_source; + system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config); + system_gclk_chan_enable(inst_gclk_id[instance]); + + /* Set ctrla register */ + ctrla_tmp = + (uint32_t)config->counter_size | + (uint32_t)config->wave_generation | + (uint32_t)config->reload_action | + (uint32_t)config->clock_prescaler; + + if (config->run_in_standby) { + ctrla_tmp |= TC_CTRLA_RUNSTDBY; + } + + /* Write configuration to register */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + hw->COUNT8.CTRLA.reg = ctrla_tmp; + + /* Set ctrlb register */ + if (config->oneshot) { + ctrlbset_tmp = TC_CTRLBSET_ONESHOT; + } + + if (config->count_direction) { + ctrlbset_tmp |= TC_CTRLBSET_DIR; + } + + /* Clear old ctrlb configuration */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + hw->COUNT8.CTRLBCLR.reg = 0xFF; + + /* Check if we actually need to go into a wait state. */ + if (ctrlbset_tmp) { + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + /* Write configuration to register */ + hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp; + } + + /* Set ctrlc register*/ + ctrlc_tmp = config->waveform_invert_output; + for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { + if (config->enable_capture_on_channel[i] == true) { + ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i); + } + } + + /* Write configuration to register */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + hw->COUNT8.CTRLC.reg = ctrlc_tmp; + + /* Write configuration to register */ + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Switch for TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT8.COUNT.reg = + config->counter_8_bit.value; + + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT8.PER.reg = + config->counter_8_bit.period; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT8.CC[0].reg = + config->counter_8_bit.compare_capture_channel[0]; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT8.CC[1].reg = + config->counter_8_bit.compare_capture_channel[1]; + + return STATUS_OK; + + case TC_COUNTER_SIZE_16BIT: + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT16.COUNT.reg + = config->counter_16_bit.value; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT16.CC[0].reg = + config->counter_16_bit.compare_capture_channel[0]; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT16.CC[1].reg = + config->counter_16_bit.compare_capture_channel[1]; + + return STATUS_OK; + + case TC_COUNTER_SIZE_32BIT: + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT32.COUNT.reg + = config->counter_32_bit.value; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT32.CC[0].reg = + config->counter_32_bit.compare_capture_channel[0]; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + hw->COUNT32.CC[1].reg = + config->counter_32_bit.compare_capture_channel[1]; + + return STATUS_OK; + } + + Assert(false); + return STATUS_ERR_INVALID_ARG; +} + +/** + * \brief Sets TC module count value. + * + * Sets the current timer count value of a initialized TC module. The + * specified TC module may be started or stopped. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] count New timer count value to set + * + * \return Status of the count update procedure. + * + * \retval STATUS_OK The timer count was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified + */ +enum status_code tc_set_count_value( + const struct tc_module *const module_inst, + const uint32_t count) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance*/ + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Write to based on the TC counter_size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + tc_module->COUNT8.COUNT.reg = (uint8_t)count; + return STATUS_OK; + + case TC_COUNTER_SIZE_16BIT: + tc_module->COUNT16.COUNT.reg = (uint16_t)count; + return STATUS_OK; + + case TC_COUNTER_SIZE_32BIT: + tc_module->COUNT32.COUNT.reg = (uint32_t)count; + return STATUS_OK; + + default: + return STATUS_ERR_INVALID_ARG; + } +} + +/** + * \brief Get TC module count value. + * + * Retrieves the current count value of a TC module. The specified TC module + * may be started or stopped. + * + * \param[in] module_inst Pointer to the software module instance struct + * + * \return Count value of the specified TC module. + */ +uint32_t tc_get_count_value( + const struct tc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Read from based on the TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + return (uint32_t)tc_module->COUNT8.COUNT.reg; + + case TC_COUNTER_SIZE_16BIT: + return (uint32_t)tc_module->COUNT16.COUNT.reg; + + case TC_COUNTER_SIZE_32BIT: + return tc_module->COUNT32.COUNT.reg; + } + + Assert(false); + return 0; +} + +/** + * \brief Gets the TC module capture value. + * + * Retrieves the capture value in the indicated TC module capture channel. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] channel_index Index of the Compare Capture channel to read + * + * \return Capture value stored in the specified timer channel. + */ +uint32_t tc_get_capture_value( + const struct tc_module *const module_inst, + const enum tc_compare_capture_channel channel_index) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Read out based on the TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + return tc_module->COUNT8.CC[channel_index].reg; + } + + case TC_COUNTER_SIZE_16BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + return tc_module->COUNT16.CC[channel_index].reg; + } + + case TC_COUNTER_SIZE_32BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + return tc_module->COUNT32.CC[channel_index].reg; + } + } + + Assert(false); + return 0; +} + +/** + * \brief Sets a TC module compare value. + * + * Writes a compare value to the given TC module compare/capture channel. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] channel_index Index of the compare channel to write to + * \param[in] compare New compare value to set + * + * \return Status of the compare update procedure. + * + * \retval STATUS_OK The compare value was updated successfully + * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied + */ +enum status_code tc_set_compare_value( + const struct tc_module *const module_inst, + const enum tc_compare_capture_channel channel_index, + const uint32_t compare) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module's hardware instance */ + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + /* Read out based on the TC counter size */ + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + tc_module->COUNT8.CC[channel_index].reg = + (uint8_t)compare; + return STATUS_OK; + } + + case TC_COUNTER_SIZE_16BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + tc_module->COUNT16.CC[channel_index].reg = + (uint16_t)compare; + return STATUS_OK; + } + + case TC_COUNTER_SIZE_32BIT: + if (channel_index < + NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { + tc_module->COUNT32.CC[channel_index].reg = + (uint32_t)compare; + return STATUS_OK; + } + } + + return STATUS_ERR_INVALID_ARG; +} + +/** + * \brief Resets the TC module. + * + * Resets the TC module, restoring all hardware module registers to their + * default values and disabling the module. The TC module will not be + * accessible while the reset is being performed. + * + * \note When resetting a 32-bit counter only the master TC module's instance + * structure should be passed to the function. + * + * \param[in] module_inst Pointer to the software module instance struct + * + * \return Status of the procedure. + * \retval STATUS_OK The module was reset successfully + * \retval STATUS_ERR_UNSUPPORTED_DEV A 32-bit slave TC module was passed to + * the function. Only use reset on master + * TC + */ +enum status_code tc_reset( + const struct tc_module *const module_inst) +{ + /* Sanity check arguments */ + Assert(module_inst); + Assert(module_inst->hw); + + /* Get a pointer to the module hardware instance */ + TcCount8 *const tc_module = &(module_inst->hw->COUNT8); + + if (tc_module->STATUS.reg & TC_STATUS_SLAVE) { + return STATUS_ERR_UNSUPPORTED_DEV; + } + + /* Disable this module if it is running */ + if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { + tc_disable(module_inst); + while (tc_is_syncing(module_inst)) { + /* wait while module is disabling */ + } + } + + /* Reset this TC module */ + tc_module->CTRLA.reg |= TC_CTRLA_SWRST; + + return STATUS_OK; +} + +/** + * \brief Set the timer TOP/period value. + * + * For 8-bit counter size this function writes the top value to the period + * register. + * + * For 16- and 32-bit counter size this function writes the top value to + * Capture Compare register 0. The value in this register can not be used for + * any other purpose. + * + * \note This function is designed to be used in PWM or frequency + * match modes only. When the counter is set to 16- or 32-bit counter + * size. In 8-bit counter size it will always be possible to change the + * top value even in normal mode. + * + * \param[in] module_inst Pointer to the software module instance struct + * \param[in] top_value New timer TOP value to set + * + * \return Status of the TOP set procedure. + * + * \retval STATUS_OK The timer TOP value was updated successfully + * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the + * module instance is invalid + */ +enum status_code tc_set_top_value ( + const struct tc_module *const module_inst, + const uint32_t top_value) +{ + Assert(module_inst); + Assert(module_inst->hw); + Assert(top_value); + + Tc *const tc_module = module_inst->hw; + + while (tc_is_syncing(module_inst)) { + /* Wait for sync */ + } + + switch (module_inst->counter_size) { + case TC_COUNTER_SIZE_8BIT: + tc_module->COUNT8.PER.reg = (uint8_t)top_value; + return STATUS_OK; + + case TC_COUNTER_SIZE_16BIT: + tc_module->COUNT16.CC[0].reg = (uint16_t)top_value; + return STATUS_OK; + + case TC_COUNTER_SIZE_32BIT: + tc_module->COUNT32.CC[0].reg = (uint32_t)top_value; + return STATUS_OK; + + default: + Assert(false); + return STATUS_ERR_INVALID_ARG; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tc/tc.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tc/tc.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tc/tc_interrupt.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tc/tc_interrupt.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tc/tc_interrupt.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tc/tc_interrupt.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc_interrupt.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tcc/tcc.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tcc/tcc.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tcc/tcc.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h similarity index 100% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/drivers/tcc/tcc.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_api.c similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_api.c index 501b3d0ab0..c666eb9061 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_irq_api.c similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_irq_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_irq_api.c index 7661b8f32e..aa71317d97 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_irq_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_irq_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_object.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_object.h similarity index 97% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_object.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_object.h index ed9c32c258..3f6d305f6d 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/gpio_object.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_object.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/i2c_api.c similarity index 99% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/i2c_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/i2c_api.c index 0609c865ad..6cfc02ae86 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/i2c_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/objects.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/objects.h similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/objects.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/objects.h index 9de2491519..01ac3f6796 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/objects.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/objects.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -79,6 +79,9 @@ struct analogin_s { #if DEVICE_ANALOGOUT struct dac_s { DACName dac; + PinName pin; + uint32_t channel; + struct dac_module dac_instance; }; #endif diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap.c similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap.c index 4b9c06f425..77f8bce74a 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.c similarity index 94% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.c index 2d487ebf4e..cac0d199b5 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -182,12 +182,21 @@ uint32_t pinmap_pad_sercom(PinName pin, uint32_t sercom_index) uint32_t pinmap_peripheral_sercom(PinName pin, uint32_t sercom_index) { uint32_t sercom_address[6] = { +#if (SAMD21) || (SAMR21) 0x42000800UL, // Base address of SERCOM0 0x42000C00UL, // Base address of SERCOM1 0x42001000UL, // Base address of SERCOM2 0x42001400UL, // Base address of SERCOM3 0x42001800UL, // Base address of SERCOM4 0x42001C00UL // Base address of SERCOM5 +#elif (SAML21) + 0x42000000UL, // Base address of SERCOM0 + 0x42000400UL, // Base address of SERCOM1 + 0x42000800UL, // Base address of SERCOM2 + 0x42000C00UL, // Base address of SERCOM3 + 0x42001000UL, // Base address of SERCOM4 + 0x43000400UL // Base address of SERCOM5 +#endif }; uint32_t index = sercom_index & 0x0F; diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.h similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.h index 78a906199b..4660b8d83a 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pinmap_function.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pinmap_function.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/port_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/port_api.c similarity index 92% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/port_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/port_api.c index ec74674020..aa40378a77 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/port_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/port_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -25,6 +25,13 @@ #elif defined(TARGET_SAMD21J18A) #define PORTA_MASK 0xDBFFFFFF // mask for available pins in Port A #define PORTB_MASK 0xC0C3FFFF // mask for available pins in Port B +#elif defined(TARGET_SAMD21G18A) +#define PORTA_MASK 0xDBFFFFFF // mask for available pins in Port A +#define PORTB_MASK 0x00C00F0C // mask for available pins in Port B +#elif defined(TARGET_SAML21J18A) +#define PORTA_MASK 0xCBFFFFFF // mask for available pins in Port A +#define PORTB_MASK 0xC0C3FFFF // mask for available pins in Port B +#else #endif uint32_t start_pin(PortName port) diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pwmout_api.c similarity index 94% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pwmout_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pwmout_api.c index 7ce7d2a5b1..6206c894af 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/pwmout_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -20,9 +20,6 @@ #include "pinmap_function.h" -/* Compare Channel used for PWM in TCC Modules */ -#define PWMOUT_CTRL_CHANNEL 0 - /* Prescaler values for TCC Module */ const uint32_t tcc_prescaler[] = { TCC_CLOCK_PRESCALER_DIV1, @@ -89,6 +86,7 @@ bool pwmout_init_hw(pwmout_t* obj) PinName pin; uint32_t ch_index = NC; struct tcc_config config_tcc; + uint32_t tcc_channel = NC; /* Sanity check arguments */ MBED_ASSERT(obj); @@ -103,6 +101,15 @@ bool pwmout_init_hw(pwmout_t* obj) /* Pin not supported */ return 0; } + if ((ch_index == 0) || (ch_index == 4)) { + tcc_channel = 0; + } else if ((ch_index == 1) || (ch_index == 5)) { + tcc_channel = 1; + } else if ((ch_index == 2) || (ch_index == 6)) { + tcc_channel = 2; + } else if ((ch_index == 3) || (ch_index == 7)) { + tcc_channel = 3; + } tcc_get_config_defaults(&config_tcc, (Tcc*)pwm); @@ -111,7 +118,7 @@ bool pwmout_init_hw(pwmout_t* obj) config_tcc.counter.period = obj->period; config_tcc.compare.wave_generation = TCC_WAVE_GENERATION_SINGLE_SLOPE_PWM; - config_tcc.compare.match[PWMOUT_CTRL_CHANNEL] = obj->period * obj->duty_cycle; + config_tcc.compare.match[tcc_channel] = obj->period * obj->duty_cycle; config_tcc.pins.enable_wave_out_pin[ch_index] = true; config_tcc.pins.wave_out_pin[ch_index] = pin; diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/rtc_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/rtc_api.c similarity index 89% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/rtc_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/rtc_api.c index 03bac73d59..c789e64a76 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/rtc_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -21,6 +21,11 @@ #include "rtc_count.h" +#if !defined(RTC_CLOCK_SOURCE) +# warning RTC_CLOCK_SOURCE is not defined, assuming RTC_CLOCK_SELECTION_ULP1K. +# define RTC_CLOCK_SOURCE RTC_CLOCK_SELECTION_ULP1K +#endif + /* Global RTC instance*/ static struct rtc_module rtc_instance; @@ -67,7 +72,11 @@ void rtc_free(void) /* Disable the RTC module */ rtc_count_disable(&rtc_instance); /* Disable the RTC clock */ +#if (SAMD21) || (SAMR21) system_gclk_chan_disable(RTC_GCLK_ID); +#elif (SAML21) + system_gclk_chan_disable(RTC_CLOCK_SOURCE); +#endif rtc_inited = 0; } } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.c similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.c index b6c8d5232d..9fec8037d5 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.h b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.h similarity index 95% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.h rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.h index ad4ec165eb..8d093a3dab 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sercom_dma.h +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/sercom_dma.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/serial_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c similarity index 96% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/serial_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c index 99de5959ab..d5e744ccae 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -60,8 +60,11 @@ static inline void usart_syncing(serial_t *obj) { /* Sanity check arguments */ MBED_ASSERT(obj); - +#ifdef FEATURE_USART_SYNC_SCHEME_V2 while(_USART(obj).SYNCBUSY.reg); +#else + while(_USART(obj).SYNCBUSY.reg & SERCOM_USART_STATUS_SYNCBUSY); +#endif } static inline void enable_usart(serial_t *obj) @@ -261,8 +264,23 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) /* Disable USART module */ disable_usart(obj); +#if (SAML21) || (SAMC20) || (SAMC21) +#if (SAML21) + if (sercom_index == 5) { + pm_index = MCLK_APBDMASK_SERCOM5_Pos; + gclk_index = SERCOM5_GCLK_ID_CORE; + } else { + pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + } +#else + pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; +#endif +#else pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; +#endif if (_USART(obj).CTRLA.reg & SERCOM_USART_CTRLA_SWRST) { return; /* The module is busy resetting itself */ @@ -273,7 +291,15 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) } /* Turn on module in PM */ +#if (SAML21) + if (sercom_index == 5) { + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); + } else { + system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); + } +#else system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); +#endif /* Set up the GCLK for the module */ gclk_chan_conf.source_generator = GCLK_GENERATOR_0; @@ -352,8 +378,19 @@ void serial_baud(serial_t *obj, int baudrate) disable_usart(obj); sercom_index = _sercom_get_sercom_inst_index(pUSART_S(obj)); +#if (SAML21) || (SAMC20) || (SAMC21) +#if (SAML21) + if (sercom_index == 5) { + gclk_index = SERCOM5_GCLK_ID_CORE; + } else { + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + } +#else gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - +#endif +#else + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; +#endif gclk_chan_conf.source_generator = GCLK_GENERATOR_0; system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); system_gclk_chan_enable(gclk_index); @@ -871,7 +908,6 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); serial_tx_enable_event(obj, event, true); -// if( hint == DMA_USAGE_NEVER) { //TODO: DMA to be implemented later NVIC_ClearPendingIRQ(get_serial_irq_num(obj)); NVIC_DisableIRQ(get_serial_irq_num(obj)); NVIC_SetVector(get_serial_irq_num(obj), (uint32_t)handler); @@ -881,7 +917,6 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx _USART(obj).INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_DRE; } -// } return 0; } @@ -896,7 +931,6 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt serial_set_char_match(obj, char_match); serial_rx_buffer_set(obj, rx, rx_length, rx_width); -// if( hint == DMA_USAGE_NEVER) { //TODO: DMA to be implemented later NVIC_ClearPendingIRQ(get_serial_irq_num(obj)); NVIC_DisableIRQ(get_serial_irq_num(obj)); NVIC_SetVector(get_serial_irq_num(obj), (uint32_t)handler); @@ -905,7 +939,6 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt if (pUSART_S(obj)) { _USART(obj).INTENSET.reg = SERCOM_USART_INTFLAG_RXC; } -// } return; } @@ -999,7 +1032,6 @@ int serial_rx_irq_handler_asynch(serial_t *obj) int serial_irq_handler_asynch(serial_t *obj) { -//TODO: DMA to be implemented /* Sanity check arguments */ MBED_ASSERT(obj); uint16_t interrupt_status; @@ -1034,7 +1066,6 @@ int serial_irq_handler_asynch(serial_t *obj) void serial_tx_abort_asynch(serial_t *obj) { -//TODO: DMA to be implemented /* Sanity check arguments */ MBED_ASSERT(obj); _USART(obj).INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; @@ -1046,7 +1077,6 @@ void serial_tx_abort_asynch(serial_t *obj) void serial_rx_abort_asynch(serial_t *obj) { -//TODO: DMA to be implemented /* Sanity check arguments */ MBED_ASSERT(obj); _USART(obj).INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sleep_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/sleep_api.c similarity index 91% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sleep_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/sleep_api.c index 00569b8efc..4e0a901fca 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/sleep_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/sleep_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -27,7 +27,11 @@ */ void sleep(void) { +#if (SAMD21) || (SAMR21) system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE_2); +#elif (SAML21) + system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE); +#endif system_sleep(); } diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/spi_api.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/spi_api.c similarity index 94% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/spi_api.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/spi_api.c index 8452569b1e..92c5090391 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/spi_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,6 +22,9 @@ #include "pinmap_function.h" +#define SERCOM_SPI_STATUS_SYNCBUSY_Pos 15 +#define SERCOM_SPI_STATUS_SYNCBUSY (0x1u << SERCOM_SPI_STATUS_SYNCBUSY_Pos) + #define SPI_MOSI_INDEX 0 #define SPI_MISO_INDEX 1 #define SPI_SCLK_INDEX 2 @@ -64,8 +67,13 @@ static inline bool spi_is_syncing(spi_t *obj) /* Sanity check arguments */ MBED_ASSERT(obj); +# ifdef FEATURE_SPI_SYNC_SCHEME_VERSION_2 /* Return synchronization status */ return (_SPI(obj).SYNCBUSY.reg); +# else + /* Return synchronization status */ + return (_SPI(obj).STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY); +# endif } static inline void spi_enable(spi_t *obj) @@ -261,12 +269,31 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel uint32_t pm_index, gclk_index; #if (SAML21) if (sercom_index == 5) { +# ifdef ID_SERCOM5 pm_index = MCLK_APBDMASK_SERCOM5_Pos; gclk_index = SERCOM5_GCLK_ID_CORE; +# else + return STATUS_ERR_INVALID_ARG; +# endif } else { pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; } +#elif (SAMC21) + if (sercom_index == 5) { +# ifdef ID_SERCOM5 + pm_index = MCLK_APBCMASK_SERCOM5_Pos; + gclk_index = SERCOM5_GCLK_ID_CORE; +# else + return STATUS_ERR_INVALID_ARG; +# endif + } else { + pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + } +#elif (SAMC20) + pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; #else pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; @@ -275,7 +302,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel /* Turn on module in PM */ #if (SAML21) if (sercom_index == 5) { +# ifdef ID_SERCOM5 system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); +# else + return STATUS_ERR_INVALID_ARG; +# endif } else { system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); } @@ -427,6 +458,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) void spi_frequency(spi_t *obj, int hz) { uint16_t baud = 0; + uint32_t gclk_index = 0; /* Sanity check arguments */ MBED_ASSERT(obj); @@ -435,7 +467,31 @@ void spi_frequency(spi_t *obj, int hz) /* Find frequency of the internal SERCOMi_GCLK_ID_CORE */ uint32_t sercom_index = _sercom_get_sercom_inst_index(pSPI_SERCOM(obj)); - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; +#if (SAML21) + if (sercom_index == 5) { +# ifdef ID_SERCOM5 + gclk_index = SERCOM5_GCLK_ID_CORE; +# else + return STATUS_ERR_INVALID_ARG; +# endif + } else { + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + } +#elif (SAMC21) + if (sercom_index == 5) { +# ifdef ID_SERCOM5 + gclk_index = SERCOM5_GCLK_ID_CORE; +# else + return STATUS_ERR_INVALID_ARG; +# endif + } else { + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; + } +#elif (SAMC20) + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; +#else + gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; +#endif uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index); /* Get baud value, based on baudrate and the internal clock frequency */ diff --git a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/us_ticker.c similarity index 94% rename from libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/us_ticker.c index da7747c611..4ebb84190b 100644 --- a/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0+/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/us_ticker.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2015 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -23,9 +23,15 @@ #include "tc.h" #include "tc_interrupt.h" +#if (SAMD21) || (SAMR21) #define TICKER_COUNTER_uS TC4 #define TICKER_COUNTER_IRQn TC4_IRQn #define TICKER_COUNTER_Handlr TC4_Handler +#elif (SAML21) /*SAML21 TCC4 does not support 32 bit counter operations*/ +#define TICKER_COUNTER_uS TC0 +#define TICKER_COUNTER_IRQn TC0_IRQn +#define TICKER_COUNTER_Handlr TC0_Handler +#endif static int us_ticker_inited = 0; extern uint8_t g_sys_init; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/us_ticker.c similarity index 98% rename from libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/us_ticker.c rename to libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/us_ticker.c index 93a1512b50..cc2d9b29b8 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/us_ticker.c @@ -55,8 +55,10 @@ static volatile uint32_t msb_counter = 0; static uint32_t timer_ldval = 0; static void timer_isr(void) { - msb_counter++; - PIT_TIMER.TFLG = 1; + if (PIT_TIMER.TFLG == 1) { + msb_counter++; + PIT_TIMER.TFLG = 1; + } } static void timer_init(void) { diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h index a4da0f851a..bdb55e8065 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h @@ -262,8 +262,8 @@ typedef enum { A19 = PTC11, A20 = PTE0, - I2C_SCL = PTB3, - I2C_SDA = PTB2, + I2C_SCL = PTB2, + I2C_SDA = PTB3, SPI_SCK = PTC5, // sclk SPI_DOUT = PTC6, // mosi diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c new file mode 100644 index 0000000000..a41d0bd7aa --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c @@ -0,0 +1,84 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "clk_freqs.h" + +static int us_ticker_inited = 0; + +void us_ticker_init(void) { + if (us_ticker_inited) + return; + us_ticker_inited = 1; + + SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT + PIT->MCR = 0; // Enable PIT + + //Timer on PIT0+1, ticker on PIT 2+3 + //Init timer + PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF; + PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK | PIT_TCTRL_TEN_MASK; // Start timer 1, chained to timer 0 + + // Use channel 0 as a prescaler for channel 1 + uint32_t ldval = (bus_frequency() + 500000) / 1000000 - 1; + PIT->CHANNEL[0].LDVAL = ldval; + PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer + + //Init ticker + PIT->CHANNEL[2].LDVAL = ldval; + PIT->CHANNEL[2].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 2 as prescaler + + NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(PIT3_IRQn); +} + +/****************************************************************************** + * Timer for us timing. + ******************************************************************************/ + +uint32_t us_ticker_read() { + if (!us_ticker_inited) + us_ticker_init(); + + return ~(PIT->CHANNEL[1].CVAL); +} + +/****************************************************************************** + * Ticker Event + ******************************************************************************/ + +void us_ticker_disable_interrupt(void) { + PIT->CHANNEL[3].TCTRL &= ~PIT_TCTRL_TIE_MASK; +} + +void us_ticker_clear_interrupt(void) { + PIT->CHANNEL[3].TFLG = 1; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + int delta = (int)((uint32_t)timestamp - us_ticker_read()); + if (delta <= 0) { + // This event was in the past: + us_ticker_irq_handler(); + return; + } + + PIT->CHANNEL[3].TCTRL = 0; + PIT->CHANNEL[3].LDVAL = delta; + PIT->CHANNEL[3].TCTRL = PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK | PIT_TCTRL_CHN_MASK; + +} diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h index 5b258c90a5..9d05900d4a 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h @@ -39,17 +39,17 @@ typedef enum { p5 = 5, p6 = 6, p7 = 7, - p8 = NC, - p9 = NC, - p10 = NC, - p11 = NC, - p12 = NC, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, p13 = 13, - p14 = NC, - p15 = NC, + p14 = 14, + p15 = 15, p16 = 16, p17 = 17, - p18 = NC, + p18 = 18, p19 = 19, p20 = 20, p21 = 21, @@ -59,13 +59,15 @@ typedef enum { p25 = 25, p26 = 26, p27 = 27, - p28 = NC, + p28 = 28, p29 = 29, p30 = 30, p31 = 31, - LED1 = p7, - LED2 = p13, + LED1 = p4, + LED2 = p5, + LED3 = p6, + LED4 = p13, BUTTON0 = p16, BUTTON1 = p17, @@ -79,23 +81,22 @@ typedef enum { SPI_PSELMOSI0 = p24, SPI_PSELMISO0 = p29, - SPI_PSELSS0 = p6, + SPI_PSELSS0 = p30, SPI_PSELSCK0 = p21, SPIS_PSELMOSI = p24, SPIS_PSELMISO = p29, - SPIS_PSELSS = p6, + SPIS_PSELSS = p30, SPIS_PSELSCK = p21, I2C_SDA0 = p22, I2C_SCL0 = p20, - A0 = p1, - A1 = p2, - A2 = p3, - A3 = p4, - A4 = p5, - A5 = p6, + A0 = p26, + A1 = p27, + A2 = p4, + A3 = p5, + A4 = p6, SWIO = p19, VERF0 = p0, @@ -112,8 +113,7 @@ typedef enum { SPI_PSELMISO1 = NC, SPI_PSELSS1 = NC, SPI_PSELSCK1 = NC, - LED3 = NC, - LED4 = NC + A5 = NC } PinName; typedef enum { diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c index 5804dda1dd..70293f34fa 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c @@ -16,7 +16,8 @@ #include "cmsis.h" - +/* No init flash in this version, 2015/10/27 */ +#if 0 #define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */ #define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */ #define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */ @@ -95,6 +96,8 @@ void flash_powerDown(void) //wait for sleep //wait_us(3); } +/* No init flash in this version, 2015/10/27 */ +#endif void mbed_sdk_init() { @@ -115,9 +118,11 @@ void mbed_sdk_init() {// Do nothing. } - flash_init(); - - //nrf_delay_ms(10); - flash_powerDown(); +/* No init flash in this version, 2015/10/27 */ +// flash_init(); +// +// //nrf_delay_ms(10); +// flash_powerDown(); +/* No init flash in this version, 2015/10/27 */ } diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c index ab6da87545..77b1ddcd38 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c @@ -29,6 +29,10 @@ static const PinMap PinMap_ADC[] = { {p4, ADC0_0, 32}, {p5, ADC0_0, 64}, {p6, ADC0_0, 128}, +#ifndef TARGET_NRF51_DONGLE + {p26, ADC0_0, 1}, + {p27, ADC0_0, 2}, +#endif {NC, NC, 0} }; @@ -61,8 +65,10 @@ uint16_t analogin_read_u16(analogin_t *obj) { NRF_ADC->CONFIG &= ~ADC_CONFIG_PSEL_Msk; NRF_ADC->CONFIG |= obj->adc_pin << ADC_CONFIG_PSEL_Pos; + NRF_ADC->EVENTS_END = 0; NRF_ADC->TASKS_START = 1; - while (((NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) >> ADC_BUSY_BUSY_Pos) == ADC_BUSY_BUSY_Busy) { + + while (!NRF_ADC->EVENTS_END) { } return (uint16_t)NRF_ADC->RESULT; // 10 bit diff --git a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c index c58948e24c..1ebe182dd5 100644 --- a/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c @@ -116,6 +116,19 @@ void timer_init(uint8_t pwmChoice) timer->TASKS_START = 0x01; } +static void timer_free() +{ + NRF_TIMER_Type *timer = Timers[0]; + for(uint8_t i = 1; i < NO_PWMS; i++){ + if(PWM_taken[i]){ + break; + } + if((i == NO_PWMS - 1) && (!PWM_taken[i])) + timer->TASKS_STOP = 0x01; + } +} + + /** @brief Function for initializing the GPIO Tasks/Events peripheral. */ void gpiote_init(PinName pin, uint8_t channel_number) @@ -154,6 +167,14 @@ void gpiote_init(PinName pin, uint8_t channel_number) __NOP(); } +static void gpiote_free(PinName pin,uint8_t channel_number) +{ + NRF_GPIOTE->TASKS_OUT[channel_number] = 0; + NRF_GPIOTE->CONFIG[channel_number] = 0; + NRF_GPIO->PIN_CNF[pin] = (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); + +} + /** @brief Function for initializing the Programmable Peripheral Interconnect peripheral. */ static void ppi_init(uint8_t pwm) @@ -173,6 +194,16 @@ static void ppi_init(uint8_t pwm) (1 << (channel_number + 1)); } +static void ppi_free(uint8_t pwm) +{ + //using ppi channels 0-7 (only 0-7 are available) + uint8_t channel_number = 2*pwm; + + // Disable PPI channels. + NRF_PPI->CHEN &= (~(1 << channel_number)) + & (~(1 << (channel_number+1))); +} + void setModulation(pwmout_t *obj, uint8_t toggle, uint8_t high) { if (high) { @@ -239,11 +270,13 @@ void pwmout_init(pwmout_t *obj, PinName pin) pwmout_write (obj, 0); } -void pwmout_free(pwmout_t *obj) -{ +void pwmout_free(pwmout_t* obj) { MBED_ASSERT(obj->pwm != (PWMName)NC); - PWM_taken[obj->pwm] = 0; pwmout_write(obj, 0); + PWM_taken[obj->pwm] = 0; + timer_free(); + ppi_free(obj->pwm); + gpiote_free(obj->pin,obj->pwm); } void pwmout_write(pwmout_t *obj, float value) diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c index 073d973693..dd3535c6b0 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c @@ -44,7 +44,7 @@ static inline int div_round_up(int x, int y) { void analogin_init(analogin_t *obj, PinName pin) { obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (uint32_t)NC); + MBED_ASSERT(obj->adc != (ADCName)NC); // Power up ADC LPC_SYSCON->PDRUNCFG &= ~ (1 << 4); diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pwmout_api.c index 6d0fbefbb3..2144f8af89 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pwmout_api.c @@ -64,7 +64,7 @@ static LPC_TMR_TypeDef *Timers[3] = { void pwmout_init(pwmout_t* obj, PinName pin) { // determine the channel PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - MBED_ASSERT(pwm != (uint32_t)NC); + MBED_ASSERT(pwm != (PWMName)NC); obj->pwm = pwm; diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c index 7fc8168884..87b2ea39f4 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c @@ -201,6 +201,7 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b case ParityForced1: parity_enable = 1; parity_select = 2; break; case ParityForced0: parity_enable = 1; parity_select = 3; break; default: + parity_enable = 0, parity_select = 0; break; } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h new file mode 100644 index 0000000000..2b4906c1d2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h @@ -0,0 +1,72 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE +} UARTName; + +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_15 +#define STDIO_UART UART_1 + +typedef enum { + SPI_1 = (int)SPI1_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_14 = (int)TIM14_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralPins.c new file mode 100644 index 0000000000..5055b99a1e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralPins.c @@ -0,0 +1,142 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM2 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { +// {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH2 +// {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH3 +// {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH4 + {PA_4, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14)}, // TIM14_CH1 + {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH1 +// {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM16)}, // TIM16_CH1 + {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH2 +// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH1N +// {PA_7, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14)}, // TIM14_CH1 +// {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM17)}, // TIM17_CH1 + {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH4 + {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH3 +// {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH2N +// {PB_1, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_TIM14)}, // TIM14_CH1 + {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH4 +// {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH3N +// {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH2 + {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16)}, // TIM16_CH1N + {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17)}, // TIM17_CH1N + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_1, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_2, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // STDIO TX + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, +// {PA_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // SWCLK + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // STDIO RX + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, +// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h new file mode 100644 index 0000000000..3ce322cf64 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h @@ -0,0 +1,156 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32f0xx_hal_gpio.h and stm32f0xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + + PF_0 = 0x50, + PF_1 = 0x51, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PA_3, + A3 = PA_4, + A4 = PA_5, + A5 = PA_6, + A6 = PA_7, + A7 = PA_2, + D0 = PA_10, + D1 = PA_9, + D2 = PA_12, + D3 = PB_0, + D4 = PB_7, + D5 = PB_6, + D6 = PB_1, + D7 = PF_0, + D8 = PF_1, + D9 = PA_8, + D10 = PA_11, + D11 = PB_5, + D12 = PB_4, + D13 = PB_3, + + // Generic signals namings + LED1 = PB_3, + LED2 = PB_3, + LED3 = PB_3, + LED4 = PB_3, + SERIAL_TX = PA_2, + SERIAL_RX = PA_15, + USBTX = PA_2, + USBRX = PA_15, + I2C_SCL = PA_9, + I2C_SDA = PA_10, + SPI_MOSI = PB_5, + SPI_MISO = PB_4, + SPI_SCK = PB_3, + SPI_CS = PB_1, + PWM_OUT = PB_0, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PortNames.h new file mode 100644 index 0000000000..fe887dfe09 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PortNames.h @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, /* used for compilation needs */ + PortF = 5 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device.h new file mode 100644 index 0000000000..2b4e5438a5 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h new file mode 100644 index 0000000000..d28f670c7e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h @@ -0,0 +1,104 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h new file mode 100644 index 0000000000..62301a7382 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralNames.h @@ -0,0 +1,75 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, +} ADCName; + + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE +} UARTName; + +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_15 +#define STDIO_UART UART_2 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE // for compilation +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_14 = (int)TIM14_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c new file mode 100644 index 0000000000..a1eb25a514 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c @@ -0,0 +1,148 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_12, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C1)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {PF_0, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_11, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C1)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {PF_1, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM2 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { +// {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH2 +// {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH3 +// {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH4 + {PA_4, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14)}, // TIM14_CH1 + {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH1 +// {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM16)}, // TIM16_CH1 + {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH2 +// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH1N +// {PA_7, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14)}, // TIM14_CH1 +// {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM17)}, // TIM17_CH1 + {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH4 + {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH3 +// {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH2N +// {PB_1, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_TIM14)}, // TIM14_CH1 + {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH4 +// {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH3N +// {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH2 + {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16)}, // TIM16_CH1N + {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17)}, // TIM17_CH1N +// {PB_8, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16)}, // TIM16_CH1 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // STDIO TX + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, +// {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_USART2)}, // SWCLK + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // STDIO RX + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, +// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h new file mode 100644 index 0000000000..a5c46f1235 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h @@ -0,0 +1,155 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32f0xx_hal_gpio.h and stm32f0xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + + PF_0 = 0x50, + PF_1 = 0x51, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PA_3, + A3 = PA_4, + A4 = PA_5, + A5 = PA_6, + A6 = PA_7, + A7 = PA_2, + D0 = PA_10, + D1 = PA_9, + D2 = PA_12, + D3 = PB_0, + D4 = PB_7, + D5 = PB_6, + D6 = PB_1, + D7 = PF_0, + D8 = PF_1, + D9 = PA_8, + D10 = PA_11, + D11 = PB_5, + D12 = PB_4, + D13 = PB_3, + + // Generic signals namings + LED1 = PB_3, + LED2 = PB_3, + LED3 = PB_3, + LED4 = PB_3, + SERIAL_TX = PA_2, + SERIAL_RX = PA_15, + USBTX = PA_2, + USBRX = PA_15, + I2C_SCL = PA_9, + I2C_SDA = PA_10, + SPI_MOSI = PB_5, + SPI_MISO = PB_4, + SPI_SCK = PB_3, + SPI_CS = PA_4, + PWM_OUT = PB_0, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PortNames.h new file mode 100644 index 0000000000..fe887dfe09 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PortNames.h @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, /* used for compilation needs */ + PortF = 5 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device.h new file mode 100644 index 0000000000..2b4e5438a5 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h new file mode 100644 index 0000000000..d28f670c7e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h @@ -0,0 +1,104 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c index de8df07aef..c8be431ab7 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,13 +34,13 @@ #include "cmsis.h" #include "pinmap.h" #include "PeripheralPins.h" +#include "mbed_error.h" ADC_HandleTypeDef AdcHandle; int adc_inited = 0; -void analogin_init(analogin_t *obj, PinName pin) -{ +void analogin_init(analogin_t *obj, PinName pin) { // Get the peripheral name from the pin and assign it to the object obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); MBED_ASSERT(obj->adc != (ADCName)NC); @@ -73,15 +73,17 @@ void analogin_init(analogin_t *obj, PinName pin) AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; AdcHandle.Init.DMAContinuousRequests = DISABLE; AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN; - HAL_ADC_Init(&AdcHandle); - + if (HAL_ADC_Init(&AdcHandle) != HAL_OK) { + error("Cannot initialize ADC"); + } // Run the ADC calibration - HAL_ADCEx_Calibration_Start(&AdcHandle); + if (HAL_ADCEx_Calibration_Start(&AdcHandle) != HAL_OK) { + error("Cannot Start ADC_Calibration"); + } } } -static inline uint16_t adc_read(analogin_t *obj) -{ +static inline uint16_t adc_read(analogin_t *obj) { ADC_ChannelConfTypeDef sConfig; AdcHandle.Instance = (ADC_TypeDef *)(obj->adc); @@ -125,6 +127,7 @@ static inline uint16_t adc_read(analogin_t *obj) case PB_1: sConfig.Channel = ADC_CHANNEL_9; break; +#if !defined (TARGET_STM32F031K6) && !defined (TARGET_STM32F042K6) case PC_0: sConfig.Channel = ADC_CHANNEL_10; break; @@ -143,6 +146,7 @@ static inline uint16_t adc_read(analogin_t *obj) case PC_5: sConfig.Channel = ADC_CHANNEL_15; break; +#endif default: return 0; } @@ -162,16 +166,14 @@ static inline uint16_t adc_read(analogin_t *obj) } } -uint16_t analogin_read_u16(analogin_t *obj) -{ +uint16_t analogin_read_u16(analogin_t *obj) { uint16_t value = adc_read(obj); // 12-bit to 16-bit conversion value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); return value; } -float analogin_read(analogin_t *obj) -{ +float analogin_read(analogin_t *obj) { uint16_t value = adc_read(obj); return (float)value * (1.0f / (float)0xFFF); // 12 bits range } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogout_api.c index 6b9b6cdb46..d5094dee2e 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/analogout_api.c @@ -36,11 +36,11 @@ #include "PeripheralPins.h" #define DAC_RANGE (0xFFF) // 12 bits +#define DAC_NB_BITS (12) static DAC_HandleTypeDef DacHandle; -void analogout_init(dac_t *obj, PinName pin) -{ +void analogout_init(dac_t *obj, PinName pin) { DAC_ChannelConfTypeDef sConfig; DacHandle.Instance = DAC; @@ -71,8 +71,7 @@ void analogout_init(dac_t *obj, PinName pin) analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) -{ +void analogout_free(dac_t *obj) { // Reset DAC and disable clock __DAC1_FORCE_RESET(); __DAC1_RELEASE_RESET(); @@ -82,55 +81,47 @@ void analogout_free(dac_t *obj) pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } -static inline void dac_write(dac_t *obj, uint16_t value) -{ +static inline void dac_write(dac_t *obj, int value) { if (obj->pin == PA_4) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); - } else { // PA_5 - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); + } else if (obj->pin == PA_5) { + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); } } -static inline int dac_read(dac_t *obj) -{ +static inline int dac_read(dac_t *obj) { if (obj->pin == PA_4) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); - } else { // PA_5 + } else if (obj->pin == PA_5) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); } + return 0; /* Just silented warning */ } -void analogout_write(dac_t *obj, float value) -{ +void analogout_write(dac_t *obj, float value) { if (value < 0.0f) { dac_write(obj, 0); // Min value } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value + dac_write(obj, (int)DAC_RANGE); // Max value } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); + dac_write(obj, (int)(value * (float)DAC_RANGE)); } } -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> (16 - DAC_NB_BITS)); } -float analogout_read(dac_t *obj) -{ +float analogout_read(dac_t *obj) { uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); + return (float)value * (1.0f / (float)DAC_RANGE); } -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); + return (value << 4) | ((value >> 8) & 0x000F); // Conversion from 12 to 16 bits } #endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_api.c index 9d395df29c..f2c00aec3b 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_api.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,8 +34,7 @@ extern uint32_t Set_GPIO_Clock(uint32_t port_idx); -uint32_t gpio_set(PinName pin) -{ +uint32_t gpio_set(PinName pin) { MBED_ASSERT(pin != (PinName)NC); pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -43,8 +42,7 @@ uint32_t gpio_set(PinName pin) return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask } -void gpio_init(gpio_t *obj, PinName pin) -{ +void gpio_init(gpio_t *obj, PinName pin) { obj->pin = pin; if (pin == (PinName)NC) { return; @@ -63,13 +61,11 @@ void gpio_init(gpio_t *obj, PinName pin) obj->reg_clr = &gpio->BRR; } -void gpio_mode(gpio_t *obj, PinMode mode) -{ +void gpio_mode(gpio_t *obj, PinMode mode) { pin_mode(obj->pin, mode); } -void gpio_dir(gpio_t *obj, PinDirection direction) -{ +void gpio_dir(gpio_t *obj, PinDirection direction) { MBED_ASSERT(obj->pin != (PinName)NC); if (direction == PIN_OUTPUT) { pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0)); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_irq_api.c index 2f08bb5506..9cb790a9e2 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_irq_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_irq_api.c @@ -82,8 +82,7 @@ static uint32_t pin_base_nr[16] = { static gpio_irq_handler irq_handler; -static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) -{ +static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) { gpio_channel_t *gpio_channel = &channels[irq_index]; uint32_t gpio_idx; @@ -113,27 +112,23 @@ static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) } // EXTI lines 0 to 1 -static void gpio_irq0(void) -{ +static void gpio_irq0(void) { handle_interrupt_in(0, 2); } // EXTI lines 2 to 3 -static void gpio_irq1(void) -{ +static void gpio_irq1(void) { handle_interrupt_in(1, 2); } // EXTI lines 4 to 15 -static void gpio_irq2(void) -{ +static void gpio_irq2(void) { handle_interrupt_in(2, 12); } extern uint32_t Set_GPIO_Clock(uint32_t port_idx); -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; uint32_t irq_index; @@ -191,8 +186,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 return 0; } -void gpio_irq_free(gpio_irq_t *obj) -{ +void gpio_irq_free(gpio_irq_t *obj) { gpio_channel_t *gpio_channel = &channels[obj->irq_index]; uint32_t pin_index = STM_PIN(obj->pin); uint32_t gpio_idx = pin_base_nr[pin_index]; @@ -207,8 +201,7 @@ void gpio_irq_free(gpio_irq_t *obj) obj->event = EDGE_NONE; } -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { uint32_t mode = STM_MODE_IT_EVT_RESET; uint32_t pull = GPIO_NOPULL; @@ -255,13 +248,11 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0)); } -void gpio_irq_enable(gpio_irq_t *obj) -{ +void gpio_irq_enable(gpio_irq_t *obj) { NVIC_EnableIRQ(obj->irq_n); } -void gpio_irq_disable(gpio_irq_t *obj) -{ +void gpio_irq_disable(gpio_irq_t *obj) { NVIC_DisableIRQ(obj->irq_n); obj->event = EDGE_NONE; } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/i2c_api.c index 25ac0303ec..d3136a68fe 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/i2c_api.c @@ -45,10 +45,11 @@ I2C_HandleTypeDef I2cHandle; int i2c1_inited = 0; +#if defined(I2C2_BASE) int i2c2_inited = 0; +#endif -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { // Determine the I2C to use I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); @@ -68,6 +69,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) pin_mode(scl, OpenDrain); } +#if defined(I2C2_BASE) // Enable I2C2 clock and pinout if not done if ((obj->i2c == I2C_2) && !i2c2_inited) { i2c2_inited = 1; @@ -78,6 +80,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) pin_mode(sda, OpenDrain); pin_mode(scl, OpenDrain); } +#endif // Reset to clear pending flags if any i2c_reset(obj); @@ -86,8 +89,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) i2c_frequency(obj, 100000); // 100 kHz per default } -void i2c_frequency(i2c_t *obj, int hz) -{ +void i2c_frequency(i2c_t *obj, int hz) { MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); int timeout; @@ -122,8 +124,7 @@ void i2c_frequency(i2c_t *obj, int hz) HAL_I2C_Init(&I2cHandle); } -inline int i2c_start(i2c_t *obj) -{ +inline int i2c_start(i2c_t *obj) { I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); int timeout; @@ -146,8 +147,7 @@ inline int i2c_start(i2c_t *obj) return 0; } -inline int i2c_stop(i2c_t *obj) -{ +inline int i2c_stop(i2c_t *obj) { I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); // Generate the STOP condition @@ -156,8 +156,7 @@ inline int i2c_stop(i2c_t *obj) return 0; } -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); int timeout; @@ -202,8 +201,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) return length; } -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); int timeout; @@ -245,8 +243,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) return count; } -int i2c_byte_read(i2c_t *obj, int last) -{ +int i2c_byte_read(i2c_t *obj, int last) { I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); int timeout; @@ -261,8 +258,7 @@ int i2c_byte_read(i2c_t *obj, int last) return (int)i2c->RXDR; } -int i2c_byte_write(i2c_t *obj, int data) -{ +int i2c_byte_write(i2c_t *obj, int data) { I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); int timeout; @@ -279,8 +275,7 @@ int i2c_byte_write(i2c_t *obj, int data) return 1; } -void i2c_reset(i2c_t *obj) -{ +void i2c_reset(i2c_t *obj) { int timeout; // Wait before reset @@ -291,16 +286,17 @@ void i2c_reset(i2c_t *obj) __I2C1_FORCE_RESET(); __I2C1_RELEASE_RESET(); } +#if defined(I2C2_BASE) if (obj->i2c == I2C_2) { __I2C2_FORCE_RESET(); __I2C2_RELEASE_RESET(); } +#endif } #if DEVICE_I2CSLAVE -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); uint16_t tmpreg = 0; @@ -318,8 +314,7 @@ void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) i2c->OAR1 |= I2C_OAR1_OA1EN; } -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ +void i2c_slave_mode(i2c_t *obj, int enable_slave) { I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); uint16_t tmpreg; @@ -343,8 +338,7 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) #define WriteGeneral 2 // the master is writing to all slave #define WriteAddressed 3 // the master is writing to this slave (slave = receiver) -int i2c_slave_receive(i2c_t *obj) -{ +int i2c_slave_receive(i2c_t *obj) { I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); int retValue = NoData; @@ -362,8 +356,7 @@ int i2c_slave_receive(i2c_t *obj) return (retValue); } -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ +int i2c_slave_read(i2c_t *obj, char *data, int length) { char size = 0; while (size < length) data[size++] = (char)i2c_byte_read(obj, 0); @@ -371,8 +364,7 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) return size; } -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ +int i2c_slave_write(i2c_t *obj, const char *data, int length) { char size = 0; I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c index e9a0f01c73..147f362296 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,14 +27,23 @@ */ #include "cmsis.h" +extern int stdio_uart_inited; + // This function is called after RAM initialization and before main. -void mbed_sdk_init() -{ +void mbed_sdk_init() { + /* Configure the Cube driver */ + SystemCoreClock = 8000000; // At this stage the HSI is used as system clock + + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + // Update the SystemCoreClock variable. SystemCoreClockUpdate(); -#if defined(TARGET_STM32F070RB) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) - // Need to restart HAL driver after the RAM is initialized - HAL_Init(); -#endif + // reset serial next time it is called, now that system clock is set + stdio_uart_inited = 0; + } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pinmap.c index 84600c5ecd..57dc4d04c8 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pinmap.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pinmap.c @@ -50,8 +50,7 @@ static const uint32_t gpio_mode[13] = { }; // Enable GPIO clock and return GPIO base address -uint32_t Set_GPIO_Clock(uint32_t port_idx) -{ +uint32_t Set_GPIO_Clock(uint32_t port_idx) { uint32_t gpio_add = 0; switch (port_idx) { case PortA: @@ -62,18 +61,24 @@ uint32_t Set_GPIO_Clock(uint32_t port_idx) gpio_add = GPIOB_BASE; __GPIOB_CLK_ENABLE(); break; +#if defined(GPIOC_BASE) case PortC: gpio_add = GPIOC_BASE; __GPIOC_CLK_ENABLE(); break; +#endif +#if defined(GPIOD_BASE) case PortD: gpio_add = GPIOD_BASE; __GPIOD_CLK_ENABLE(); break; +#endif +#if defined(GPIOF_BASE) case PortF: gpio_add = GPIOF_BASE; __GPIOF_CLK_ENABLE(); break; +#endif default: error("Pinmap error: wrong port number."); break; @@ -84,8 +89,7 @@ uint32_t Set_GPIO_Clock(uint32_t port_idx) /** * Configure pin (mode, speed, output type and pull-up/pull-down) */ -void pin_function(PinName pin, int data) -{ +void pin_function(PinName pin, int data) { MBED_ASSERT(pin != (PinName)NC); // Get the pin informations @@ -119,8 +123,7 @@ void pin_function(PinName pin, int data) /** * Configure pin pull-up/pull-down */ -void pin_mode(PinName pin, PinMode mode) -{ +void pin_mode(PinName pin, PinMode mode) { MBED_ASSERT(pin != (PinName)NC); uint32_t port_index = STM_PORT(pin); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/port_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/port_api.c index e982858665..e49e804cc8 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/port_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/port_api.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -38,13 +38,11 @@ extern uint32_t Set_GPIO_Clock(uint32_t port_idx); // high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...) // low nibble = pin number -PinName port_pin(PortName port, int pin_n) -{ +PinName port_pin(PortName port, int pin_n) { return (PinName)(pin_n + (port << 4)); } -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { uint32_t port_index = (uint32_t)port; // Enable GPIO clock @@ -61,8 +59,7 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) port_dir(obj, dir); } -void port_dir(port_t *obj, PinDirection dir) -{ +void port_dir(port_t *obj, PinDirection dir) { uint32_t i; obj->direction = dir; for (i = 0; i < 16; i++) { // Process all pins @@ -76,8 +73,7 @@ void port_dir(port_t *obj, PinDirection dir) } } -void port_mode(port_t *obj, PinMode mode) -{ +void port_mode(port_t *obj, PinMode mode) { uint32_t i; for (i = 0; i < 16; i++) { // Process all pins if (obj->mask & (1 << i)) { // If the pin is used @@ -86,13 +82,11 @@ void port_mode(port_t *obj, PinMode mode) } } -void port_write(port_t *obj, int value) -{ +void port_write(port_t *obj, int value) { *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); } -int port_read(port_t *obj) -{ +int port_read(port_t *obj) { if (obj->direction == PIN_OUTPUT) { return (*obj->reg_out & obj->mask); } else { // PIN_INPUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c index 463bb72445..d2504ec910 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c @@ -38,8 +38,7 @@ static TIM_HandleTypeDef TimHandle; -void pwmout_init(pwmout_t* obj, PinName pin) -{ +void pwmout_init(pwmout_t* obj, PinName pin) { // Get the peripheral name from the pin and assign it to the object obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); @@ -54,11 +53,21 @@ void pwmout_init(pwmout_t* obj, PinName pin) #if defined(TIM2_BASE) if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); #endif +#if defined(TIM3_BASE) if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); +#endif +#if defined(TIM14_BASE) if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE(); +#endif +#if defined(TIM15_BASE) if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE(); +#endif +#if defined(TIM16_BASE) if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE(); +#endif +#if defined(TIM17_BASE) if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE(); +#endif // Configure GPIO pinmap_pinout(pin, PinMap_PWM); @@ -70,14 +79,12 @@ void pwmout_init(pwmout_t* obj, PinName pin) pwmout_period_us(obj, 20000); // 20 ms per default } -void pwmout_free(pwmout_t* obj) -{ +void pwmout_free(pwmout_t* obj) { // Configure GPIO pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } -void pwmout_write(pwmout_t* obj, float value) -{ +void pwmout_write(pwmout_t* obj, float value) { TIM_OC_InitTypeDef sConfig; int channel = 0; int complementary_channel = 0; @@ -101,7 +108,41 @@ void pwmout_write(pwmout_t* obj, float value) sConfig.OCIdleState = TIM_OCIDLESTATE_RESET; sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET; -#if defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) +#if defined (TARGET_STM32F031K6) || defined (TARGET_STM32F042K6) + switch (obj->pin) { + // Channels 1 + case PA_4: + case PA_6: + case PA_8: + case PB_4: + channel = TIM_CHANNEL_1; + break; + // Channels 1N + case PB_6: + case PB_7: + channel = TIM_CHANNEL_1; + complementary_channel = 1; + break; + // Channels 2 + case PA_7: + case PA_9: + case PB_5: + channel = TIM_CHANNEL_2; + break; + // Channels 3 + case PA_10: + case PB_0: + channel = TIM_CHANNEL_3; + break; + // Channels 4 + case PA_11: + case PB_1: + channel = TIM_CHANNEL_4; + break; + default: + return; + } +#elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) switch (obj->pin) { // Channels 1 case PA_4: @@ -198,8 +239,7 @@ void pwmout_write(pwmout_t* obj, float value) } } -float pwmout_read(pwmout_t* obj) -{ +float pwmout_read(pwmout_t* obj) { float value = 0; if (obj->period > 0) { value = (float)(obj->pulse) / (float)(obj->period); @@ -207,18 +247,15 @@ float pwmout_read(pwmout_t* obj) return ((value > (float)1.0) ? (float)(1.0) : (value)); } -void pwmout_period(pwmout_t* obj, float seconds) -{ +void pwmout_period(pwmout_t* obj, float seconds) { pwmout_period_us(obj, seconds * 1000000.0f); } -void pwmout_period_ms(pwmout_t* obj, int ms) -{ +void pwmout_period_ms(pwmout_t* obj, int ms) { pwmout_period_us(obj, ms * 1000); } -void pwmout_period_us(pwmout_t* obj, int us) -{ +void pwmout_period_us(pwmout_t* obj, int us) { TimHandle.Instance = (TIM_TypeDef *)(obj->pwm); float dc = pwmout_read(obj); @@ -243,18 +280,15 @@ void pwmout_period_us(pwmout_t* obj, int us) __HAL_TIM_ENABLE(&TimHandle); } -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { pwmout_pulsewidth_us(obj, seconds * 1000000.0f); } -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { pwmout_pulsewidth_us(obj, ms * 1000); } -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { float value = (float)us / (float)obj->period; pwmout_write(obj, value); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/rtc_api.c index 09372b9c32..15b004b5c5 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/rtc_api.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -37,8 +37,7 @@ static int rtc_inited = 0; static RTC_HandleTypeDef RtcHandle; -void rtc_init(void) -{ +void rtc_init(void) { RCC_OscInitTypeDef RCC_OscInitStruct; uint32_t rtc_freq = 0; @@ -95,8 +94,7 @@ void rtc_init(void) } } -void rtc_free(void) -{ +void rtc_free(void) { // Enable Power clock __PWR_CLK_ENABLE(); @@ -121,8 +119,7 @@ void rtc_free(void) rtc_inited = 0; } -int rtc_isenabled(void) -{ +int rtc_isenabled(void) { return rtc_inited; } @@ -143,8 +140,7 @@ int rtc_isenabled(void) tm_yday days since January 1 0-365 tm_isdst Daylight Saving Time flag */ -time_t rtc_read(void) -{ +time_t rtc_read(void) { RTC_DateTypeDef dateStruct; RTC_TimeTypeDef timeStruct; struct tm timeinfo; @@ -171,8 +167,7 @@ time_t rtc_read(void) return t; } -void rtc_write(time_t t) -{ +void rtc_write(time_t t) { RTC_DateTypeDef dateStruct; RTC_TimeTypeDef timeStruct; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c index d8bd3495a0..afd98f83b3 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -42,11 +42,16 @@ static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0, 0, 0, 0}; -#elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) +#elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) || defined (TARGET_STM32F042K6) #define UART_NUM (2) static uint32_t serial_irq_ids[UART_NUM] = {0, 0}; +#elif defined (TARGET_STM32F031K6) +#define UART_NUM (1) + +static uint32_t serial_irq_ids[UART_NUM] = {0}; + #else #define UART_NUM (4) @@ -61,8 +66,7 @@ UART_HandleTypeDef UartHandle; int stdio_uart_inited = 0; serial_t stdio_uart; -static void init_uart(serial_t *obj) -{ +static void init_uart(serial_t *obj) { UartHandle.Instance = (USART_TypeDef *)(obj->uart); UartHandle.Init.BaudRate = obj->baudrate; @@ -86,8 +90,7 @@ static void init_uart(serial_t *obj) HAL_UART_Init(&UartHandle); } -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ +void serial_init(serial_t *obj, PinName tx, PinName rx) { // Determine the UART to use (UART_1, UART_2, ...) UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); @@ -102,10 +105,12 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->index = 0; } +#if defined USART2_BASE if (obj->uart == UART_2) { __USART2_CLK_ENABLE(); obj->index = 1; } +#endif #if defined USART3_BASE if (obj->uart == UART_3) { @@ -177,8 +182,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) } } -void serial_free(serial_t *obj) -{ +void serial_free(serial_t *obj) { // Reset UART and disable clock if (obj->uart == UART_1) { __USART1_FORCE_RESET(); @@ -186,11 +190,13 @@ void serial_free(serial_t *obj) __USART1_CLK_DISABLE(); } +#if defined(USART2_BASE) if (obj->uart == UART_2) { __USART2_FORCE_RESET(); __USART2_RELEASE_RESET(); __USART2_CLK_DISABLE(); } +#endif #if defined USART3_BASE if (obj->uart == UART_3) { @@ -248,14 +254,12 @@ void serial_free(serial_t *obj) serial_irq_ids[obj->index] = 0; } -void serial_baud(serial_t *obj, int baudrate) -{ +void serial_baud(serial_t *obj, int baudrate) { obj->baudrate = baudrate; init_uart(obj); } -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { if (data_bits == 9) { obj->databits = UART_WORDLENGTH_9B; } else { @@ -289,8 +293,7 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b * INTERRUPTS HANDLING ******************************************************************************/ -static void uart_irq(UARTName name, int id) -{ +static void uart_irq(UARTName name, int id) { UartHandle.Instance = (USART_TypeDef *)name; if (serial_irq_ids[id] != 0) { if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) { @@ -304,66 +307,58 @@ static void uart_irq(UARTName name, int id) } } -static void uart1_irq(void) -{ +static void uart1_irq(void) { uart_irq(UART_1, 0); } -static void uart2_irq(void) -{ +#if defined(USART2_BASE) +static void uart2_irq(void) { uart_irq(UART_2, 1); } +#endif #if defined USART3_BASE -static void uart3_irq(void) -{ +static void uart3_irq(void) { uart_irq(UART_3, 2); } #endif #if defined USART4_BASE -static void uart4_irq(void) -{ +static void uart4_irq(void) { uart_irq(UART_4, 3); } #endif #if defined USART5_BASE -static void uart5_irq(void) -{ +static void uart5_irq(void) { uart_irq(UART_5, 4); } #endif #if defined USART6_BASE -static void uart6_irq(void) -{ +static void uart6_irq(void) { uart_irq(UART_6, 5); } #endif #if defined USART7_BASE -static void uart7_irq(void) -{ +static void uart7_irq(void) { uart_irq(UART_7, 6); } #endif #if defined USART8_BASE -static void uart8_irq(void) -{ +static void uart8_irq(void) { uart_irq(UART_8, 7); } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; serial_irq_ids[obj->index] = id; } -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { IRQn_Type irq_n = (IRQn_Type)0; uint32_t vector = 0; @@ -374,10 +369,12 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&uart1_irq; } +#if defined(USART2_BASE) if (obj->uart == UART_2) { irq_n = USART2_IRQn; vector = (uint32_t)&uart2_irq; } +#endif #if defined (TARGET_STM32F091RC) if (obj->uart == UART_3) { @@ -413,15 +410,19 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) #elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) #else +#if defined(USART3_BASE) if (obj->uart == UART_3) { irq_n = USART3_4_IRQn; vector = (uint32_t)&uart3_irq; } +#endif +#if defined(USART4_BASE) if (obj->uart == UART_4) { irq_n = USART3_4_IRQn; vector = (uint32_t)&uart4_irq; } +#endif #endif if (enable) { @@ -458,22 +459,19 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) * READ/WRITE ******************************************************************************/ -int serial_getc(serial_t *obj) -{ +int serial_getc(serial_t *obj) { USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); while (!serial_readable(obj)); return (int)(uart->RDR & (uint16_t)0xFF); } -void serial_putc(serial_t *obj, int c) -{ +void serial_putc(serial_t *obj, int c) { USART_TypeDef *uart = (USART_TypeDef *)(obj->uart); while (!serial_writable(obj)); uart->TDR = (uint32_t)(c & (uint16_t)0xFF); } -int serial_readable(serial_t *obj) -{ +int serial_readable(serial_t *obj) { int status; UartHandle.Instance = (USART_TypeDef *)(obj->uart); // Check if data is received @@ -481,8 +479,7 @@ int serial_readable(serial_t *obj) return status; } -int serial_writable(serial_t *obj) -{ +int serial_writable(serial_t *obj) { int status; UartHandle.Instance = (USART_TypeDef *)(obj->uart); // Check if data is transmitted @@ -490,25 +487,21 @@ int serial_writable(serial_t *obj) return status; } -void serial_clear(serial_t *obj) -{ +void serial_clear(serial_t *obj) { UartHandle.Instance = (USART_TypeDef *)(obj->uart); __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC); __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST); } -void serial_pinout_tx(PinName tx) -{ +void serial_pinout_tx(PinName tx) { pinmap_pinout(tx, PinMap_UART_TX); } -void serial_break_set(serial_t *obj) -{ +void serial_break_set(serial_t *obj) { // [TODO] } -void serial_break_clear(serial_t *obj) -{ +void serial_break_clear(serial_t *obj) { // [TODO] } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c index 8ae2f12334..86b3483578 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,8 +34,7 @@ #include "cmsis.h" #if defined(TARGET_STM32F070RB) -void sleep(void) -{ +void sleep(void) { TIM_HandleTypeDef TimMasterHandle; TimMasterHandle.Instance = TIM1; @@ -51,8 +50,7 @@ void sleep(void) } #elif defined(TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) -void sleep(void) -{ +void sleep(void) { // Stop HAL systick HAL_SuspendTick(); // Request to enter SLEEP mode @@ -64,8 +62,7 @@ void sleep(void) #else static TIM_HandleTypeDef TimMasterHandle; -void sleep(void) -{ +void sleep(void) { TimMasterHandle.Instance = TIM2; // Disable HAL tick interrupt @@ -80,8 +77,7 @@ void sleep(void) #endif #if defined(TARGET_STM32F030R8) || defined (TARGET_STM32F051R8) -void deepsleep(void) -{ +void deepsleep(void) { // Request to enter STOP mode with regulator in low power mode HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); @@ -94,8 +90,7 @@ void deepsleep(void) } #else -void deepsleep(void) -{ +void deepsleep(void) { // Request to enter STOP mode with regulator in low power mode HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c index 3aa5eb402d..cf055232d4 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -39,8 +39,7 @@ static SPI_HandleTypeDef SpiHandle; -static void init_spi(spi_t *obj) -{ +static void init_spi(spi_t *obj) { SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); __HAL_SPI_DISABLE(&SpiHandle); @@ -62,8 +61,7 @@ static void init_spi(spi_t *obj) __HAL_SPI_ENABLE(&SpiHandle); } -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { // Determine the SPI to use SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); @@ -80,9 +78,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel if (obj->spi == SPI_1) { __SPI1_CLK_ENABLE(); } +#if defined(SPI2_BASE) if (obj->spi == SPI_2) { __SPI2_CLK_ENABLE(); } +#endif // Configure the SPI pins pinmap_pinout(mosi, PinMap_SPI_MOSI); @@ -109,8 +109,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel init_spi(obj); } -void spi_free(spi_t *obj) -{ +void spi_free(spi_t *obj) { // Reset SPI and disable clock if (obj->spi == SPI_1) { __SPI1_FORCE_RESET(); @@ -118,11 +117,13 @@ void spi_free(spi_t *obj) __SPI1_CLK_DISABLE(); } +#if defined(SPI2_BASE) if (obj->spi == SPI_2) { __SPI2_FORCE_RESET(); __SPI2_RELEASE_RESET(); __SPI2_CLK_DISABLE(); } +#endif // Configure GPIOs pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -131,8 +132,7 @@ void spi_free(spi_t *obj) pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ +void spi_format(spi_t *obj, int bits, int mode, int slave) { // Save new values if (bits == 16) { obj->bits = SPI_DATASIZE_16BIT; @@ -168,8 +168,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) init_spi(obj); } -void spi_frequency(spi_t *obj, int hz) -{ +void spi_frequency(spi_t *obj, int hz) { // Note: The frequencies are obtained with SPI clock = 48 MHz (APB clock) if (hz < 375000) { obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 188 kHz @@ -192,8 +191,7 @@ void spi_frequency(spi_t *obj, int hz) init_spi(obj); } -static inline int ssp_readable(spi_t *obj) -{ +static inline int ssp_readable(spi_t *obj) { int status; SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); // Check if data is received @@ -201,8 +199,7 @@ static inline int ssp_readable(spi_t *obj) return status; } -static inline int ssp_writeable(spi_t *obj) -{ +static inline int ssp_writeable(spi_t *obj) { int status; SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); // Check if data is transmitted @@ -210,8 +207,7 @@ static inline int ssp_writeable(spi_t *obj) return status; } -static inline void ssp_write(spi_t *obj, int value) -{ +static inline void ssp_write(spi_t *obj, int value) { SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); while (!ssp_writeable(obj)); if (obj->bits == SPI_DATASIZE_8BIT) { @@ -224,8 +220,7 @@ static inline void ssp_write(spi_t *obj, int value) } } -static inline int ssp_read(spi_t *obj) -{ +static inline int ssp_read(spi_t *obj) { SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); while (!ssp_readable(obj)); if (obj->bits == SPI_DATASIZE_8BIT) { @@ -238,27 +233,23 @@ static inline int ssp_read(spi_t *obj) } } -static inline int ssp_busy(spi_t *obj) -{ +static inline int ssp_busy(spi_t *obj) { int status; SpiHandle.Instance = (SPI_TypeDef *)(obj->spi); status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0); return status; } -int spi_master_write(spi_t *obj, int value) -{ +int spi_master_write(spi_t *obj, int value) { ssp_write(obj, value); return ssp_read(obj); } -int spi_slave_receive(spi_t *obj) -{ +int spi_slave_receive(spi_t *obj) { return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); }; -int spi_slave_read(spi_t *obj) -{ +int spi_slave_read(spi_t *obj) { SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); while (!ssp_readable(obj)); if (obj->bits == SPI_DATASIZE_8BIT) { @@ -271,8 +262,7 @@ int spi_slave_read(spi_t *obj) } } -void spi_slave_write(spi_t *obj, int value) -{ +void spi_slave_write(spi_t *obj, int value) { SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi); while (!ssp_writeable(obj)); if (obj->bits == SPI_DATASIZE_8BIT) { @@ -285,8 +275,7 @@ void spi_slave_write(spi_t *obj, int value) } } -int spi_busy(spi_t *obj) -{ +int spi_busy(spi_t *obj) { return ssp_busy(obj); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c index 397d7d9585..91ee9457de 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c @@ -42,8 +42,7 @@ volatile uint32_t SlaveCounter = 0; volatile uint32_t oc_int_part = 0; volatile uint16_t oc_rem_part = 0; -void set_compare(uint16_t count) -{ +void set_compare(uint16_t count) { TimMasterHandle.Instance = TIM_MST; // Set new output compare value __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count); @@ -51,16 +50,14 @@ void set_compare(uint16_t count) __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); } -void us_ticker_init(void) -{ +void us_ticker_init(void) { if (us_ticker_inited) return; us_ticker_inited = 1; HAL_InitTick(0); // The passed value is not used } -uint32_t us_ticker_read() -{ +uint32_t us_ticker_read() { uint32_t counter, counter2; if (!us_ticker_inited) us_ticker_init(); // A situation might appear when Master overflows right after Slave is read and before the @@ -81,8 +78,7 @@ uint32_t us_ticker_read() return counter2; } -void us_ticker_set_interrupt(timestamp_t timestamp) -{ +void us_ticker_set_interrupt(timestamp_t timestamp) { int delta = (int)((uint32_t)timestamp - us_ticker_read()); uint16_t cval = TIM_MST->CNT; @@ -101,14 +97,12 @@ void us_ticker_set_interrupt(timestamp_t timestamp) } } -void us_ticker_disable_interrupt(void) -{ +void us_ticker_disable_interrupt(void) { TimMasterHandle.Instance = TIM_MST; __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); } -void us_ticker_clear_interrupt(void) -{ +void us_ticker_clear_interrupt(void) { TimMasterHandle.Instance = TIM_MST; if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); @@ -131,8 +125,7 @@ static volatile uint32_t SlaveCounter = 0; static volatile uint32_t oc_int_part = 0; static volatile uint16_t oc_rem_part = 0; -void set_compare(uint16_t count) -{ +void set_compare(uint16_t count) { TimMasterHandle.Instance = TIM_MST; // Set new output compare value @@ -142,8 +135,7 @@ void set_compare(uint16_t count) } // Used to increment the slave counter -static void tim_update_irq_handler(void) -{ +static void tim_update_irq_handler(void) { TimMasterHandle.Instance = TIM_MST; // Clear Update interrupt flag @@ -154,8 +146,7 @@ static void tim_update_irq_handler(void) } // Used by interrupt system -static void tim_oc_irq_handler(void) -{ +static void tim_oc_irq_handler(void) { uint16_t cval = TIM_MST->CNT; TimMasterHandle.Instance = TIM_MST; @@ -178,8 +169,7 @@ static void tim_oc_irq_handler(void) } -void us_ticker_init(void) -{ +void us_ticker_init(void) { if (us_ticker_inited) return; us_ticker_inited = 1; @@ -210,8 +200,7 @@ void us_ticker_init(void) HAL_TIM_Base_Start(&TimMasterHandle); } -uint32_t us_ticker_read() -{ +uint32_t us_ticker_read() { uint32_t counter, counter2; if (!us_ticker_inited) us_ticker_init(); // A situation might appear when Master overflows right after Slave is read and before the @@ -232,8 +221,7 @@ uint32_t us_ticker_read() return counter2; } -void us_ticker_set_interrupt(timestamp_t timestamp) -{ +void us_ticker_set_interrupt(timestamp_t timestamp) { int delta = (int)((uint32_t)timestamp - us_ticker_read()); uint16_t cval = TIM_MST->CNT; @@ -252,14 +240,12 @@ void us_ticker_set_interrupt(timestamp_t timestamp) } } -void us_ticker_disable_interrupt(void) -{ +void us_ticker_disable_interrupt(void) { TimMasterHandle.Instance = TIM_MST; __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); } -void us_ticker_clear_interrupt(void) -{ +void us_ticker_clear_interrupt(void) { TimMasterHandle.Instance = TIM_MST; if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) { __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1); @@ -274,8 +260,7 @@ void us_ticker_clear_interrupt(void) static TIM_HandleTypeDef TimMasterHandle; static int us_ticker_inited = 0; -void us_ticker_init(void) -{ +void us_ticker_init(void) { if (us_ticker_inited) return; us_ticker_inited = 1; @@ -284,27 +269,23 @@ void us_ticker_init(void) HAL_InitTick(0); // The passed value is not used } -uint32_t us_ticker_read() -{ +uint32_t us_ticker_read() { if (!us_ticker_inited) us_ticker_init(); return TIM_MST->CNT; } -void us_ticker_set_interrupt(timestamp_t timestamp) -{ +void us_ticker_set_interrupt(timestamp_t timestamp) { // Set new output compare value __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp); // Enable IT __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); } -void us_ticker_disable_interrupt(void) -{ +void us_ticker_disable_interrupt(void) { __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1); } -void us_ticker_clear_interrupt(void) -{ +void us_ticker_clear_interrupt(void) { __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1); } #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PeripheralNames.h new file mode 100644 index 0000000000..8dabf2d47b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PeripheralNames.h @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC1_BASE, + DAC_2 = (int)DAC2_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE +} UARTName; + +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_15 +#define STDIO_UART UART_2 + +typedef enum { + SPI_1 = (int)SPI1_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PeripheralPins.c new file mode 100644 index 0000000000..5ef3a7eb2a --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PeripheralPins.c @@ -0,0 +1,171 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - ARDUINO A0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - ARDUINO A1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO A2 + {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - ARDUINO A3 + {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 - ARDUINO A4 + {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - ARDUINO A5 + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - ARDUINO A7 + + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - ARDUINO D3 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - ARDUINO D6 + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - ARDUINO A3 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - ARDUINO A4 + {PA_6, DAC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC2_OUT1 - ARDUINO A5 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM2 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 +// {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 +// {PA_9, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 +// {PA_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_12, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 +// {PA_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PA_13, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 +// {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)},// TIM17_CH1 + {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - ARDUINO + {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N +// {PB_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 + + {PF_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Warning: LED1 is connected on this pin + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PinNames.h new file mode 100644 index 0000000000..3e21b16b63 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PinNames.h @@ -0,0 +1,164 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\ + ((PUPD & 0x07) << 4) |\ + ((AFNUM & 0x0F) << 7))) + +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\ + ((PUPD & 0x07) << 4) |\ + ((AFNUM & 0x0F) << 7) |\ + ((CHANNEL & 0x0F) << 11) |\ + ((INVERTED & 0x01) << 15))) + +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) + +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + + PF_0 = 0x50, + PF_1 = 0x51, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PA_3, + A3 = PA_4, + A4 = PA_5, + A5 = PA_6, + D0 = PA_10, + D1 = PA_9, + D2 = PA_12, + D3 = PB_0, + D4 = PB_7, + D5 = PB_6, + D6 = PB_1, + D7 = PF_0, + D8 = PF_1, + D9 = PA_8, + D10 = PA_11, + D11 = PB_5, + D12 = PB_4, + D13 = PB_3, + + // Generic signals namings + LED1 = PB_3, + LED2 = PB_3, + LED3 = PB_3, + LED4 = PB_3, + USER_BUTTON = 0x20, // no user button on the board + SERIAL_TX = PA_2, + SERIAL_RX = PA_15, + USBTX = PA_2, + USBRX = PA_15, + I2C_SCL = PB_6, + I2C_SDA = PB_7, + SPI_MOSI = PB_5, + SPI_MISO = PB_4, + SPI_SCK = PB_3, + SPI_CS = PA_11, + PWM_OUT = PA_8, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PortNames.h new file mode 100644 index 0000000000..026326171c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PortNames.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h new file mode 100644 index 0000000000..f842633cf8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h new file mode 100644 index 0000000000..974f6a8066 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h @@ -0,0 +1,114 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint32_t channel; +}; + +struct dac_s { + DACName dac; + PinName pin; + uint32_t channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; + uint32_t channel; + uint32_t inverted; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c index dda0f45670..6b28142bb9 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c @@ -36,6 +36,7 @@ #include "PeripheralPins.h" #define DAC_RANGE (0xFFF) // 12 bits +#define DAC_NB_BITS (12) static DAC_HandleTypeDef DacHandle; @@ -43,8 +44,7 @@ static DAC_HandleTypeDef DacHandle; static int pa4_used = 0; static int pa5_used = 0; -void analogout_init(dac_t *obj, PinName pin) -{ +void analogout_init(dac_t *obj, PinName pin) { DAC_ChannelConfTypeDef sConfig; // Get the peripheral name from the pin and assign it to the object @@ -97,8 +97,7 @@ void analogout_init(dac_t *obj, PinName pin) analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) -{ +void analogout_free(dac_t *obj) { // Reset DAC and disable clock if (obj->pin == PA_4) pa4_used = 0; if (obj->pin == PA_5) pa5_used = 0; @@ -121,22 +120,20 @@ void analogout_free(dac_t *obj) pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } -static inline void dac_write(dac_t *obj, uint16_t value) -{ +static inline void dac_write(dac_t *obj, int value) { if (obj->channel == 1) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); } #if defined(DAC_CHANNEL_2) if (obj->channel == 2) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); } #endif } -static inline int dac_read(dac_t *obj) -{ +static inline int dac_read(dac_t *obj) { if (obj->channel == 1) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); } @@ -148,35 +145,28 @@ static inline int dac_read(dac_t *obj) return 0; } -void analogout_write(dac_t *obj, float value) -{ +void analogout_write(dac_t *obj, float value) { if (value < 0.0f) { dac_write(obj, 0); // Min value } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value + dac_write(obj, (int)DAC_RANGE); // Max value } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); + dac_write(obj, (int)(value * (float)DAC_RANGE)); } } -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> (16 - DAC_NB_BITS)); } -float analogout_read(dac_t *obj) -{ +float analogout_read(dac_t *obj) { uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); + return (float)value * (1.0f / (float)DAC_RANGE); } -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); + return (value << 4) | ((value >> 8) & 0x000F); // Conversion from 12 to 16 bits } #endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c index 9c3b5a6b88..59bf574a43 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c @@ -94,11 +94,13 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) __HAL_RCC_USART2_CONFIG(RCC_USART2CLKSOURCE_SYSCLK); obj->index = 1; } +#if defined(UART3_BASE) if (obj->uart == UART_3) { __USART3_CLK_ENABLE(); __HAL_RCC_USART3_CONFIG(RCC_USART3CLKSOURCE_SYSCLK); obj->index = 2; } +#endif #if defined(UART4_BASE) if (obj->uart == UART_4) { __UART4_CLK_ENABLE(); @@ -155,11 +157,13 @@ void serial_free(serial_t *obj) __USART2_RELEASE_RESET(); __USART2_CLK_DISABLE(); } +#if defined(UART3_BASE) if (obj->uart == UART_3) { __USART3_FORCE_RESET(); __USART3_RELEASE_RESET(); __USART3_CLK_DISABLE(); } +#endif #if defined(UART4_BASE) if (obj->uart == UART_4) { __UART4_FORCE_RESET(); @@ -248,10 +252,12 @@ static void uart2_irq(void) uart_irq(UART_2, 1); } +#if defined(UART3_BASE) static void uart3_irq(void) { uart_irq(UART_3, 2); } +#endif #if defined(UART4_BASE) static void uart4_irq(void) @@ -290,10 +296,12 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&uart2_irq; } +#if defined(UART3_BASE) if (obj->uart == UART_3) { irq_n = USART3_IRQn; vector = (uint32_t)&uart3_irq; } +#endif #if defined(UART4_BASE) if (obj->uart == UART_4) { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralNames.h index 0d579bb21d..93c56d8980 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralNames.h @@ -68,7 +68,7 @@ typedef enum { SPI_3 = (int)SPI3_BASE, SPI_4 = (int)SPI4_BASE, SPI_5 = (int)SPI5_BASE, - SPI_6 = (int)SPI5_BASE + SPI_6 = (int)SPI6_BASE } SPIName; typedef enum { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralNames.h new file mode 100644 index 0000000000..1b9d414f36 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralNames.h @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE, + UART_7 = (int)UART7_BASE, + UART_8 = (int)UART8_BASE +} UARTName; + +#define STDIO_UART_TX PB_10 +#define STDIO_UART_RX PB_11 +#define STDIO_UART UART_3 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE, + SPI_6 = (int)SPI6_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_12 = (int)TIM12_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralPins.c new file mode 100644 index 0000000000..f4596e1e2b --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PeripheralPins.c @@ -0,0 +1,303 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 + {PF_10,ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 + {NC, NC, 0} +}; + + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 1, 0)}, // DAC_OUT1 + {PA_5, DAC_0, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0xFF, 2, 0)}, // DAC_OUT2 + {NC, NC, 0} +}; + + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PA_6, PWM_13,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13,1, 0)}, // TIM13_CH1 +// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7, PWM_14,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14,1, 0)}, // TIM14_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N +// {PB_14, PWM_12,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12,1, 0)}, // TIM12_CH1 +// {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM1_CH3N + {PB_15, PWM_12,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12,2, 0)}, // TIM12_CH2 + + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + + {PF_6, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10,1, 0)}, // TIM10_CH1 + {PF_7, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PF_8, PWM_13,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13,1, 0)}, // TIM13_CH1 + {PF_9, PWM_14,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14,1, 0)}, // TIM14_CH1 + + {PH_6, PWM_12,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12,1, 0)}, // TIM12_CH1 + {PH_9, PWM_12,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12,2, 0)}, // TIM12_CH2 + {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + + {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + // {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + // {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + // {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI6)}, + {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI5)}, + {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h new file mode 100644 index 0000000000..30967992f7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h @@ -0,0 +1,308 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_4 = 0x74, + PH_5 = 0x75, + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + + + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + + + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + + PK_3 = 0xA3, + PK_4 = 0xA4, + PK_5 = 0xA5, + PK_6 = 0xA6, + PK_7 = 0xA7, + + + // Arduino connector namings + A0 = PB_1, + A1 = PC_2, + A2 = PC_3, + A3 = PC_4, + A4 = PC_5, + A5 = PA_4, + D0 = PG_9, + D1 = PG_14, + D2 = PG_13, + D3 = PA_1, + D4 = PG_12, + D5 = PA_2, + D6 = PA_6, + D7 = PG_11, + D8 = PG_10, + D9 = PA_7, + D10 = PH_6, + D11 = PB_15, + D12 = PB_14, + D13 = PD_3, + D14 = PB_9, + D15 = PB_8, + + + // Generic signals namings + LED1 = PG_6, + LED2 = PD_4, + LED3 = PD_5, + LED4 = PK_3, + LED7 = PD_3, + USER_BUTTON = PA_0, + SERIAL_TX = PB_10, + SERIAL_RX = PB_11, + USBTX = PB_10, + USBRX = PB_11, + I2C_SCL = PB_8, + I2C_SDA = PB_9, + SPI_MOSI = PB_15, + SPI_MISO = PB_14, + SPI_SCK = PD_3, + SPI_CS = PH_6, + PWM_OUT = PA_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PortNames.h new file mode 100644 index 0000000000..0c563dd148 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PortNames.h @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7, + PortI = 8, + PortJ = 9, + PortK = 10 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device.h new file mode 100644 index 0000000000..005047957d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/device.h @@ -0,0 +1,71 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 +#define LED_RED LED1 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/objects.h new file mode 100644 index 0000000000..f0b6d09b21 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/objects.h @@ -0,0 +1,113 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint8_t channel; +}; + +struct dac_s { + DACName dac; + uint8_t channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; + uint8_t channel; + uint8_t inverted; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralNames.h new file mode 100644 index 0000000000..68f0eff9d2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralNames.h @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +#define STDIO_UART_TX PA_9 +#define STDIO_UART_RX PA_10 +#define STDIO_UART UART_1 + +typedef enum { + SPI_1 = (int)SPI1_BASE, ELMO_RF_SPI2 = SPI_1, + SPI_2 = (int)SPI2_BASE, ELMO_SPI1 = SPI_2, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c new file mode 100644 index 0000000000..f1f50db2bd --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PeripheralPins.c @@ -0,0 +1,205 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, // Warning: also on SCL + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO +// {PB_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 +// {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 +// {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - ARDUINO +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_8, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM1, 1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11,1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PA_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PA_12, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO + {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, +// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_12, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Warning: also on NSS + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, +// {PB_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI4)}, + {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI5)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Warning: also on SCLK +// {PB_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, // Warning: also on SCLK + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h new file mode 100644 index 0000000000..a36638356c --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h @@ -0,0 +1,196 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0))) +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0))) +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_IT_RISING (6) +#define STM_MODE_IT_FALLING (7) +#define STM_MODE_IT_RISING_FALLING (8) +#define STM_MODE_EVT_RISING (9) +#define STM_MODE_EVT_FALLING (10) +#define STM_MODE_EVT_RISING_FALLING (11) +#define STM_MODE_IT_EVT_RESET (12) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_2 = 0x32, + + PH_0 = 0x70, + PH_1 = 0x71, + + // Not connected + NC = (int)0xFFFFFFFF, + + // Arduino connector namings + A0 = PC_0, + A1 = PC_1, + A2 = PC_2, + A3 = PC_3, + A4 = NC, + A5 = NC, + D0 = PA_3, + D1 = PA_2, + D2 = PA_1, + D3 = PA_0, + D4 = NC, + D5 = NC, + D6 = NC, + D7 = NC, + D8 = NC, + D9 = NC, + D10 = PB_12, + D11 = PB_15, + D12 = PB_14, + D13 = PB_13, + D14 = PC_9, + D15 = PA_8, + + // Generic signals namings + LED1 = PB_0, + LED2 = PB_1, + LED3 = PB_0, + LED4 = PB_1, + USER_BUTTON = PB_7, + SERIAL_TX = PA_9, + SERIAL_RX = PA_10, + USBTX = PA_9, + USBRX = PA_10, + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + RF_SPI_MOSI = PA_7, + RF_SPI_MISO = PA_6, + RF_SPI_SCK = PA_5, + RF_SPI_CS = PA_4, + RF_RESET = PC_4, + RF_DIO0 = PC_10, + RF_DIO1 = PC_11, + RF_DIO2 = PC_12, + RF_DIO3 = PD_2, + RF_DIO4 = PB_5, + RF_DIO5 = PB_6, + RF_RXTX_SW = PC_13 +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PortNames.h new file mode 100644 index 0000000000..d521cd49ce --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PortNames.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortH = 7 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/device.h new file mode 100644 index 0000000000..57a7aa227d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/device.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/objects.h new file mode 100644 index 0000000000..d8b93568f7 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/objects.h @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint8_t channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; + uint8_t channel; + uint8_t inverted; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h index 976952fedd..6f96b68095 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h @@ -141,6 +141,7 @@ typedef enum { XBEE_DIO4 = PA_7, XBEE_DIO5 = PC_1, XBEE_DIO6 = PA_1, + XBEE_DIO7 = PA_0, XBEE_DO8 = PA_6, XBEE_DI8 = PA_11, XBEE_PWM0 = PA_8, diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h index 88f50052f6..3834ab2eaa 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogout_api.c index 0bd8969647..2ca14c5065 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/analogout_api.c @@ -35,13 +35,13 @@ #include "stm32f4xx_hal.h" #include "PeripheralPins.h" -#define RANGE_12BIT (0xFFF) +#define DAC_RANGE (0xFFF) // 12 bits +#define DAC_NB_BITS (12) DAC_HandleTypeDef DacHandle; static DAC_ChannelConfTypeDef sConfig; -void analogout_init(dac_t *obj, PinName pin) -{ +void analogout_init(dac_t *obj, PinName pin) { uint32_t channel ; HAL_StatusTypeDef status; @@ -94,18 +94,16 @@ void analogout_init(dac_t *obj, PinName pin) } -void analogout_free(dac_t *obj) -{ +void analogout_free(dac_t *obj) { } -static inline void dac_write(dac_t *obj, uint16_t value) -{ +static inline void dac_write(dac_t *obj, int value) { HAL_StatusTypeDef status = HAL_ERROR; if (obj->channel == 1) { - status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); + status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, (value & DAC_RANGE)); } else if (obj->channel == 2) { - status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); + status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, (value & DAC_RANGE)); } if ( status != HAL_OK ) { @@ -113,46 +111,37 @@ static inline void dac_write(dac_t *obj, uint16_t value) } } -static inline int dac_read(dac_t *obj) -{ +static inline int dac_read(dac_t *obj) { if (obj->channel == 1) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); } else if (obj->channel == 2) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); } - return 0; /* Just silented warning */ + return 0; /* Just silented warning */ } -void analogout_write(dac_t *obj, float value) -{ +void analogout_write(dac_t *obj, float value) { if (value < 0.0f) { dac_write(obj, 0); // Min value } else if (value > 1.0f) { - dac_write(obj, (uint16_t)RANGE_12BIT); // Max value + dac_write(obj, (int)DAC_RANGE); // Max value } else { - dac_write(obj, (uint16_t)(value * (float)RANGE_12BIT)); + dac_write(obj, (int)(value * (float)DAC_RANGE)); } } -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)RANGE_12BIT) { - value = (uint16_t)RANGE_12BIT; // Max value - } - - dac_write(obj, value); +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> (16 - DAC_NB_BITS)); } -float analogout_read(dac_t *obj) -{ - +float analogout_read(dac_t *obj) { uint32_t value = dac_read(obj); - return (float)value * (1.0f / (float)RANGE_12BIT); + return (float)value * (1.0f / (float)DAC_RANGE); } -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); + return (value << 4) | ((value >> 8) & 0x000F); // Conversion from 12 to 16 bits } #endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/i2c_api.c index 868ffd3d12..7ded748f4d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/i2c_api.c @@ -100,7 +100,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) void i2c_frequency(i2c_t *obj, int hz) { - MBED_ASSERT((hz != 0) && (hz <= 400000)); + MBED_ASSERT((hz > 0) && (hz <= 400000)); I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); int timeout; @@ -135,8 +135,8 @@ inline int i2c_start(i2c_t *obj) // Clear Acknowledge failure flag __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - // Generate the START condition - i2c->CR1 |= I2C_CR1_START; + // Generate the START condition and remove an eventual pending STOP bit + i2c->CR1 = ((i2c->CR1 & ~I2C_CR1_STOP) | I2C_CR1_START); // Wait the START condition has been correctly sent timeout = FLAG_TIMEOUT; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c index e2d647c7cf..e90edd3549 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c @@ -55,6 +55,9 @@ void pwmout_init(pwmout_t* obj, PinName pin) if (obj->pwm == PWM_2) __HAL_RCC_TIM2_CLK_ENABLE(); if (obj->pwm == PWM_3) __HAL_RCC_TIM3_CLK_ENABLE(); if (obj->pwm == PWM_4) __HAL_RCC_TIM4_CLK_ENABLE(); +#if defined(TIM5_BASE) + if (obj->pwm == PWM_5) __HAL_RCC_TIM5_CLK_ENABLE(); +#endif #if defined(TIM8_BASE) if (obj->pwm == PWM_8) __HAL_RCC_TIM8_CLK_ENABLE(); #endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c index 1a119b6dfc..5dccbbcb3d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c @@ -352,7 +352,48 @@ void spi_frequency(spi_t *obj, int hz) } else { // >= 22000000 obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 22.5 MHz } - } + } +#elif defined(TARGET_STM32F469NI) + // Values depend of PCLK2: 84 MHz + if ((obj->spi == SPI_1) || (obj->spi == SPI_4)) { + if (hz < 600000) { + obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 328 kHz + } else if ((hz >= 600000) && (hz < 1000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 656 kHz + } else if ((hz >= 1000000) && (hz < 2000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1.31 MHz + } else if ((hz >= 2000000) && (hz < 5000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2.63 MHz + } else if ((hz >= 5000000) && (hz < 10000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 5.25 MHz + } else if ((hz >= 10000000) && (hz < 20000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 10.5 MHz + } else if ((hz >= 20000000) && (hz < 40000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 21 MHz + } else { // >= 40000000 + obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 42 MHz + } + } + // Values depend of PCLK1: 42 MHz + if ((obj->spi == SPI_2) || (obj->spi == SPI_3)) { + if (hz < 300000) { + obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 164 kHz + } else if ((hz >= 300000) && (hz < 600000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 328 kHz + } else if ((hz >= 600000) && (hz < 1000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 656 kHz + } else if ((hz >= 1000000) && (hz < 2000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1.31 MHz + } else if ((hz >= 2000000) && (hz < 5000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2.63 MHz + } else if ((hz >= 5000000) && (hz < 10000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 5.25 MHz + } else if ((hz >= 10000000) && (hz < 20000000)) { + obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 10.5 MHz + } else { // >= 20000000 + obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 21 MHz + } + } #endif init_spi(obj); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/us_ticker.c index be44198992..fed8dd61b3 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/us_ticker.c @@ -29,7 +29,11 @@ #include "us_ticker_api.h" #include "PeripheralNames.h" +#ifdef TARGET_STM32F469 +#define TIM_MST TIM2 +#else #define TIM_MST TIM5 +#endif static TIM_HandleTypeDef TimMasterHandle; static int us_ticker_inited = 0; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/analogout_api.c index c271ed5ee0..56a3d11f61 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/analogout_api.c @@ -35,13 +35,13 @@ #include "stm32f7xx_hal.h" #include "PeripheralPins.h" -#define RANGE_12BIT (0xFFF) +#define DAC_RANGE (0xFFF) // 12 bits +#define DAC_NB_BITS (12) DAC_HandleTypeDef DacHandle; static DAC_ChannelConfTypeDef sConfig; -void analogout_init(dac_t *obj, PinName pin) -{ +void analogout_init(dac_t *obj, PinName pin) { uint32_t channel ; HAL_StatusTypeDef status; @@ -94,18 +94,16 @@ void analogout_init(dac_t *obj, PinName pin) } -void analogout_free(dac_t *obj) -{ +void analogout_free(dac_t *obj) { } -static inline void dac_write(dac_t *obj, uint16_t value) -{ +static inline void dac_write(dac_t *obj, int value) { HAL_StatusTypeDef status = HAL_ERROR; if (obj->channel == 1) { - status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); + status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, (value & DAC_RANGE)); } else if (obj->channel == 2) { - status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); + status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, (value & DAC_RANGE)); } if (status != HAL_OK) { @@ -113,8 +111,7 @@ static inline void dac_write(dac_t *obj, uint16_t value) } } -static inline int dac_read(dac_t *obj) -{ +static inline int dac_read(dac_t *obj) { if (obj->channel == 1) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); } else if (obj->channel == 2) { @@ -123,36 +120,28 @@ static inline int dac_read(dac_t *obj) return 0; /* Just silented warning */ } -void analogout_write(dac_t *obj, float value) -{ +void analogout_write(dac_t *obj, float value) { if (value < 0.0f) { dac_write(obj, 0); // Min value } else if (value > 1.0f) { - dac_write(obj, (uint16_t)RANGE_12BIT); // Max value + dac_write(obj, (int)DAC_RANGE); // Max value } else { - dac_write(obj, (uint16_t)(value * (float)RANGE_12BIT)); + dac_write(obj, (int)(value * (float)DAC_RANGE)); } } -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)RANGE_12BIT) { - value = (uint16_t)RANGE_12BIT; // Max value - } - - dac_write(obj, value); +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> (16 - DAC_NB_BITS)); } -float analogout_read(dac_t *obj) -{ - +float analogout_read(dac_t *obj) { uint32_t value = dac_read(obj); - return (float)value * (1.0f / (float)RANGE_12BIT); + return (float)value * (1.0f / (float)DAC_RANGE); } -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); + return (value << 4) | ((value >> 8) & 0x000F); // Conversion from 12 to 16 bits } #endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c index 60c7effd0b..ceec3c7222 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c @@ -33,8 +33,6 @@ #include "mbed_error.h" -static int rtc_inited = 0; - static RTC_HandleTypeDef RtcHandle; void rtc_init(void) @@ -42,58 +40,59 @@ void rtc_init(void) RCC_OscInitTypeDef RCC_OscInitStruct; uint32_t rtc_freq = 0; - if (rtc_inited) return; - rtc_inited = 1; + if(RTC->ISR == 7) { // RTC initialization and status register (RTC_ISR), cold start (with no backup domain power) RTC reset value - RtcHandle.Instance = RTC; + RtcHandle.Instance = RTC; - // Enable Power clock - __PWR_CLK_ENABLE(); + // Enable Power clock + __PWR_CLK_ENABLE(); - // Enable access to Backup domain - HAL_PWR_EnableBkUpAccess(); + // Enable access to Backup domain + HAL_PWR_EnableBkUpAccess(); - // Reset Backup domain - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); + // Reset Backup domain + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); - // Enable LSE Oscillator - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { - // Connect LSE to RTC - __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE); - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); - rtc_freq = LSE_VALUE; - } else { - // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + // Enable LSE Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - error("RTC error: LSI clock initialization failed."); + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { + // Connect LSE to RTC + __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE); + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); + rtc_freq = LSE_VALUE; + } else { + // Enable LSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! + RCC_OscInitStruct.LSEState = RCC_LSE_OFF; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("RTC error: LSI clock initialization failed."); + } + // Connect LSI to RTC + __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI); + __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); + // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture + rtc_freq = LSI_VALUE; } - // Connect LSI to RTC - __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI); - __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); - // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture - rtc_freq = LSI_VALUE; - } - // Enable RTC - __HAL_RCC_RTC_ENABLE(); + // Enable RTC + __HAL_RCC_RTC_ENABLE(); - RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; - RtcHandle.Init.AsynchPrediv = 127; - RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; - RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; - RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; + RtcHandle.Init.AsynchPrediv = 127; + RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1; + RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; + RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + + if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { + error("RTC error: RTC initialization failed."); + } - if (HAL_RTC_Init(&RtcHandle) != HAL_OK) { - error("RTC error: RTC initialization failed."); } } @@ -119,13 +118,15 @@ void rtc_free(void) RCC_OscInitStruct.LSIState = RCC_LSI_OFF; RCC_OscInitStruct.LSEState = RCC_LSE_OFF; HAL_RCC_OscConfig(&RCC_OscInitStruct); - - rtc_inited = 0; } int rtc_isenabled(void) { - return rtc_inited; + if(RTC->ISR != 7) { + return 1; + } else { + return 0; + } } /* @@ -180,6 +181,9 @@ void rtc_write(time_t t) RtcHandle.Instance = RTC; + // Enable write access to Backup domain + HAL_PWR_EnableBkUpAccess(); + // Convert the time into a tm struct tm *timeinfo = localtime(&t); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/analogout_api.c index ad8987cf3a..a83c73a54a 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L0/analogout_api.c @@ -36,6 +36,7 @@ #include "PeripheralPins.h" #define DAC_RANGE (0xFFF) // 12 bits +#define DAC_NB_BITS (12) static DAC_HandleTypeDef DacHandle; @@ -43,8 +44,7 @@ static DAC_HandleTypeDef DacHandle; static int channel1_used = 0; static int channel2_used = 0; -void analogout_init(dac_t *obj, PinName pin) -{ +void analogout_init(dac_t *obj, PinName pin) { DAC_ChannelConfTypeDef sConfig; // Get the peripheral name from the pin and assign it to the object @@ -91,8 +91,7 @@ void analogout_init(dac_t *obj, PinName pin) analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) -{ +void analogout_free(dac_t *obj) { // Reset DAC and disable clock if (obj->channel == 1) channel1_used = 0; if (obj->channel == 2) channel2_used = 0; @@ -107,22 +106,20 @@ void analogout_free(dac_t *obj) pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } -static inline void dac_write(dac_t *obj, uint16_t value) -{ +static inline void dac_write(dac_t *obj, int value) { if (obj->channel == 1) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); } #if defined(DAC_CHANNEL_2) if (obj->channel == 2) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); } #endif } -static inline int dac_read(dac_t *obj) -{ +static inline int dac_read(dac_t *obj) { if (obj->channel == 1) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); } @@ -134,35 +131,28 @@ static inline int dac_read(dac_t *obj) return 0; } -void analogout_write(dac_t *obj, float value) -{ +void analogout_write(dac_t *obj, float value) { if (value < 0.0f) { dac_write(obj, 0); // Min value } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value + dac_write(obj, (int)DAC_RANGE); // Max value } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); + dac_write(obj, (int)(value * (float)DAC_RANGE)); } } -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> (16 - DAC_NB_BITS)); } -float analogout_read(dac_t *obj) -{ +float analogout_read(dac_t *obj) { uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); + return (float)value * (1.0f / (float)DAC_RANGE); } -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); + return (value << 4) | ((value >> 8) & 0x000F); // Conversion from 12 to 16 bits } #endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogout_api.c index a1d3b52496..226a04f454 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/analogout_api.c @@ -36,6 +36,7 @@ #include "PeripheralPins.h" #define DAC_RANGE (0xFFF) // 12 bits +#define DAC_NB_BITS (12) static DAC_HandleTypeDef DacHandle; @@ -43,8 +44,7 @@ static DAC_HandleTypeDef DacHandle; static int pa4_used = 0; static int pa5_used = 0; -void analogout_init(dac_t *obj, PinName pin) -{ +void analogout_init(dac_t *obj, PinName pin) { DAC_ChannelConfTypeDef sConfig; DacHandle.Instance = DAC; @@ -77,8 +77,7 @@ void analogout_init(dac_t *obj, PinName pin) analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) -{ +void analogout_free(dac_t *obj) { // Reset DAC and disable clock if (obj->pin == PA_4) pa4_used = 0; if (obj->pin == PA_5) pa5_used = 0; @@ -92,19 +91,17 @@ void analogout_free(dac_t *obj) pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } -static inline void dac_write(dac_t *obj, uint16_t value) -{ +static inline void dac_write(dac_t *obj, int value) { if (obj->pin == PA_4) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); } else { // PA_5 - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); } } -static inline int dac_read(dac_t *obj) -{ +static inline int dac_read(dac_t *obj) { if (obj->pin == PA_4) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); } else { // PA_5 @@ -112,35 +109,28 @@ static inline int dac_read(dac_t *obj) } } -void analogout_write(dac_t *obj, float value) -{ +void analogout_write(dac_t *obj, float value) { if (value < 0.0f) { dac_write(obj, 0); // Min value } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value + dac_write(obj, (int)DAC_RANGE); // Max value } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); + dac_write(obj, (int)(value * (float)DAC_RANGE)); } } -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> (16 - DAC_NB_BITS)); } -float analogout_read(dac_t *obj) -{ +float analogout_read(dac_t *obj) { uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); + return (float)value * (1.0f / (float)DAC_RANGE); } -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); + return (value << 4) | ((value >> 8) & 0x000F); // Conversion from 12 to 16 bits } #endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c index 7698824df8..6d6475e024 100755 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c @@ -95,13 +95,13 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->index = 2; } -#if defined(USART4_BASE) +#if defined(UART4_BASE) if (obj->uart == UART_4) { __UART4_CLK_ENABLE(); obj->index = 3; } #endif -#if defined(USART5_BASE) +#if defined(UART5_BASE) if (obj->uart == UART_5) { __UART5_CLK_ENABLE(); obj->index = 4; @@ -156,14 +156,14 @@ void serial_free(serial_t *obj) __USART3_CLK_DISABLE(); } -#if defined(USART4_BASE) +#if defined(UART4_BASE) if (obj->uart == UART_4) { __UART4_FORCE_RESET(); __UART4_RELEASE_RESET(); __UART4_CLK_DISABLE(); } #endif -#if defined(USART5_BASE) +#if defined(UART5_BASE) if (obj->uart == UART_5) { __UART5_FORCE_RESET(); __UART5_RELEASE_RESET(); @@ -249,14 +249,14 @@ static void uart3_irq(void) uart_irq(UART_3, 2); } -#if defined(USART4_BASE) +#if defined(UART4_BASE) static void uart4_irq(void) { uart_irq(UART_4, 3); } #endif -#if defined(USART5_BASE) +#if defined(UART5_BASE) static void uart5_irq(void) { uart_irq(UART_5, 4); @@ -291,14 +291,14 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&uart3_irq; } -#if defined(USART4_BASE) +#if defined(UART4_BASE) if (obj->uart == UART_4) { irq_n = UART4_IRQn; vector = (uint32_t)&uart4_irq; } #endif -#if defined(USART5_BASE) +#if defined(UART5_BASE) if (obj->uart == UART_5) { irq_n = UART5_IRQn; vector = (uint32_t)&uart5_irq; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralNames.h new file mode 100644 index 0000000000..c1565ae909 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralNames.h @@ -0,0 +1,90 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + LPUART_1 = (int)LPUART1_BASE +} UARTName; + +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralPins.c new file mode 100644 index 0000000000..95f5e5a783 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PeripheralPins.c @@ -0,0 +1,224 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // IN5 - ARDUINO A0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // IN6 - ARDUINO A1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // IN7 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // IN8 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // IN9 - ARDUINO A2 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // IN12 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // IN15 - ARDUINO A3 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // IN16 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // IN1 - ARDUINO A5 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // IN2 - ARDUINO A4 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // IN3 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // IN4 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14 + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin) + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// Warning: TIM5 cannot be used because already used by the us_ticker. +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 (used by us_ticker) + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 (used by us_ticker) +// {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 (used by us_ticker) +// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 (used by us_ticker) +// {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1 + {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 +// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N +// {PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO D3 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D5 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO D10 +// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},// TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 +// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},// TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO D6 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1 +// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2 +// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 +// {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - ARDUINO D9 +// {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 +// {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 +// {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Already used by UART_RX + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, +// {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Already used by UART_TX + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11 + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12 + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13 + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PinNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PinNames.h new file mode 100644 index 0000000000..5e411d7c12 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PinNames.h @@ -0,0 +1,195 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\ + ((PUPD & 0x07) << 4) |\ + ((AFNUM & 0x0F) << 7))) + +#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\ + ((PUPD & 0x07) << 4) |\ + ((AFNUM & 0x0F) << 7) |\ + ((CHANNEL & 0x0F) << 11) |\ + ((INVERTED & 0x01) << 15))) + +#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) +#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) +#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) +#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F) +#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01) + +#define STM_MODE_INPUT (0) +#define STM_MODE_OUTPUT_PP (1) +#define STM_MODE_OUTPUT_OD (2) +#define STM_MODE_AF_PP (3) +#define STM_MODE_AF_OD (4) +#define STM_MODE_ANALOG (5) +#define STM_MODE_ANALOG_ADC_CONTROL (6) +#define STM_MODE_IT_RISING (7) +#define STM_MODE_IT_FALLING (8) +#define STM_MODE_IT_RISING_FALLING (9) +#define STM_MODE_EVT_RISING (10) +#define STM_MODE_EVT_FALLING (11) +#define STM_MODE_EVT_RISING_FALLING (12) +#define STM_MODE_IT_EVT_RESET (13) + +// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) +// Low nibble = pin number +#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF) +#define STM_PIN(X) ((uint32_t)(X) & 0xF) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_2 = 0x32, + + PH_0 = 0x70, + PH_1 = 0x71, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PA_4, + A3 = PB_0, + A4 = PC_1, + A5 = PC_0, + D0 = PA_3, + D1 = PA_2, + D2 = PA_10, + D3 = PB_3, + D4 = PB_5, + D5 = PB_4, + D6 = PB_10, + D7 = PA_8, + D8 = PA_9, + D9 = PC_7, + D10 = PB_6, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PA_5, + LED2 = PA_5, + LED3 = PA_5, + LED4 = PA_5, + USER_BUTTON = PC_13, + SERIAL_TX = PA_2, + SERIAL_RX = PA_3, + USBTX = PA_2, + USBRX = PA_3, + I2C_SCL = PB_8, + I2C_SDA = PB_9, + SPI_MOSI = PA_7, + SPI_MISO = PA_6, + SPI_SCK = PA_5, + SPI_CS = PB_6, + PWM_OUT = PB_3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + OpenDrain = 3, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PortNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PortNames.h new file mode 100644 index 0000000000..a8c8007afb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/PortNames.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortH = 7 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device.h new file mode 100644 index 0000000000..f842633cf8 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/device.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h new file mode 100644 index 0000000000..8e57658d68 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/objects.h @@ -0,0 +1,114 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint32_t channel; +}; + +struct dac_s { + DACName dac; + PinName pin; + uint32_t channel; +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s { + SPIName spi; + uint32_t bits; + uint32_t cpol; + uint32_t cpha; + uint32_t mode; + uint32_t nss; + uint32_t br_presc; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +}; + +struct i2c_s { + I2CName i2c; + uint32_t slave; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period; + uint32_t pulse; + uint32_t channel; + uint32_t inverted; +}; + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/analogout_api.c index f2bf0e767d..d5e3fcc016 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32L4/analogout_api.c @@ -36,6 +36,7 @@ #include "PeripheralPins.h" #define DAC_RANGE (0xFFF) // 12 bits +#define DAC_NB_BITS (12) static DAC_HandleTypeDef DacHandle; @@ -43,8 +44,7 @@ static DAC_HandleTypeDef DacHandle; static int channel1_used = 0; static int channel2_used = 0; -void analogout_init(dac_t *obj, PinName pin) -{ +void analogout_init(dac_t *obj, PinName pin) { DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name from the pin and assign it to the object @@ -94,8 +94,7 @@ void analogout_init(dac_t *obj, PinName pin) analogout_write_u16(obj, 0); } -void analogout_free(dac_t *obj) -{ +void analogout_free(dac_t *obj) { // Reset DAC and disable clock if (obj->channel == 1) channel1_used = 0; if (obj->channel == 2) channel2_used = 0; @@ -110,20 +109,18 @@ void analogout_free(dac_t *obj) pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); } -static inline void dac_write(dac_t *obj, uint16_t value) -{ +static inline void dac_write(dac_t *obj, int value) { if (obj->channel == 1) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); } if (obj->channel == 2) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, (value & DAC_RANGE)); HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); } } -static inline int dac_read(dac_t *obj) -{ +static inline int dac_read(dac_t *obj) { if (obj->channel == 1) { return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); } @@ -133,35 +130,28 @@ static inline int dac_read(dac_t *obj) return 0; } -void analogout_write(dac_t *obj, float value) -{ +void analogout_write(dac_t *obj, float value) { if (value < 0.0f) { dac_write(obj, 0); // Min value } else if (value > 1.0f) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value + dac_write(obj, (int)DAC_RANGE); // Max value } else { - dac_write(obj, (uint16_t)(value * (float)DAC_RANGE)); + dac_write(obj, (int)(value * (float)DAC_RANGE)); } } -void analogout_write_u16(dac_t *obj, uint16_t value) -{ - if (value > (uint16_t)DAC_RANGE) { - dac_write(obj, (uint16_t)DAC_RANGE); // Max value - } else { - dac_write(obj, value); - } +void analogout_write_u16(dac_t *obj, uint16_t value) { + dac_write(obj, value >> (16 - DAC_NB_BITS)); } -float analogout_read(dac_t *obj) -{ +float analogout_read(dac_t *obj) { uint32_t value = dac_read(obj); - return (float)((float)value * (1.0f / (float)DAC_RANGE)); + return (float)value * (1.0f / (float)DAC_RANGE); } -uint16_t analogout_read_u16(dac_t *obj) -{ - return (uint16_t)dac_read(obj); +uint16_t analogout_read_u16(dac_t *obj) { + uint32_t value = dac_read(obj); + return (value << 4) | ((value >> 8) & 0x000F); // Conversion from 12 to 16 bits } #endif // DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/Modules.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/Modules.h index 482f62d368..826891d29e 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/Modules.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/Modules.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file Modules.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_MODULES_H #define MBED_MODULES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralNames.h index b1e7e4fad7..5e4a4d6920 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.c index a77b8f81eb..cfd7cbf63d 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "PeripheralPins.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.h index 383ed49983..915eb475c1 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PinNames.h index f66537153d..a48cabc637 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PinNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PinNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PINNAMES_H #define MBED_PINNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PortNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PortNames.h index dfd60ac107..37dbdb1506 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PortNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PortNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PORTNAMES_H #define MBED_PORTNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device.h index a57a2c070a..12a4894fe8 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device_peripherals.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device_peripherals.h index 37fe368de0..1e86d70c1c 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device_peripherals.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device_peripherals.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device_peripherals.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_PERIPHERALS_H #define MBED_DEVICE_PERIPHERALS_H @@ -32,12 +46,12 @@ /* Clocks */ /* Clock definitions */ -#define LFXO 0 -#define HFXO 1 -#define LFRCO 2 -#define HFRCO 3 +#define LFXO 0 +#define HFXO 1 +#define LFRCO 2 +#define HFRCO 3 #if !defined(_EFM32_GECKO_FAMILY) -#define ULFRCO 4 +#define ULFRCO 4 #endif /* Low Energy peripheral clock source. diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/Modules.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/Modules.h index 5e350a5ba6..01d490b57b 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/Modules.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/Modules.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file Modules.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_MODULES_H #define MBED_MODULES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralNames.h index 4cf8d17119..2e6e607318 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.c index ca370fc70e..34992c3d04 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "PeripheralPins.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.h index 873aacd68a..6999fb20b6 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PinNames.h index ac2d73382f..4347918b8a 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PinNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PinNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PINNAMES_H #define MBED_PINNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PortNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PortNames.h index dfd60ac107..37dbdb1506 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PortNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PortNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PORTNAMES_H #define MBED_PORTNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device.h index f43dbfb52a..89bd008668 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device_peripherals.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device_peripherals.h index 60f684f1c3..ab49fea428 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device_peripherals.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device_peripherals.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device_peripherals.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_PERIPHERALS_H #define MBED_DEVICE_PERIPHERALS_H @@ -32,12 +46,12 @@ /* Clocks */ /* Clock definitions */ -#define LFXO 0 -#define HFXO 1 -#define LFRCO 2 -#define HFRCO 3 +#define LFXO 0 +#define HFXO 1 +#define LFRCO 2 +#define HFRCO 3 #if !defined(_EFM32_GECKO_FAMILY) -#define ULFRCO 4 +#define ULFRCO 4 #endif /* Low Energy peripheral clock source. diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/Modules.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/Modules.h index 482f62d368..826891d29e 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/Modules.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/Modules.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file Modules.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_MODULES_H #define MBED_MODULES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralNames.h index b1e7e4fad7..5e4a4d6920 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.c index a77b8f81eb..cfd7cbf63d 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "PeripheralPins.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.h index 383ed49983..915eb475c1 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h index 984a5b3690..3ca89801ba 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PinNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PINNAMES_H #define MBED_PINNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PortNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PortNames.h index dfd60ac107..37dbdb1506 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PortNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PortNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PORTNAMES_H #define MBED_PORTNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device.h index 25ba028d47..e68891604f 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device_peripherals.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device_peripherals.h index 37fe368de0..1e86d70c1c 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device_peripherals.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device_peripherals.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device_peripherals.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_PERIPHERALS_H #define MBED_DEVICE_PERIPHERALS_H @@ -32,12 +46,12 @@ /* Clocks */ /* Clock definitions */ -#define LFXO 0 -#define HFXO 1 -#define LFRCO 2 -#define HFRCO 3 +#define LFXO 0 +#define HFXO 1 +#define LFRCO 2 +#define HFRCO 3 #if !defined(_EFM32_GECKO_FAMILY) -#define ULFRCO 4 +#define ULFRCO 4 #endif /* Low Energy peripheral clock source. diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/Modules.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/Modules.h index 482f62d368..826891d29e 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/Modules.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/Modules.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file Modules.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_MODULES_H #define MBED_MODULES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralNames.h index b1e7e4fad7..5e4a4d6920 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.c index a77b8f81eb..cfd7cbf63d 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "PeripheralPins.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.h index 383ed49983..915eb475c1 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h index 984a5b3690..3ca89801ba 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PinNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PINNAMES_H #define MBED_PINNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PortNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PortNames.h index dfd60ac107..37dbdb1506 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PortNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PortNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PORTNAMES_H #define MBED_PORTNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device.h index 25ba028d47..e68891604f 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device_peripherals.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device_peripherals.h index 37fe368de0..1e86d70c1c 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device_peripherals.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device_peripherals.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device_peripherals.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_PERIPHERALS_H #define MBED_DEVICE_PERIPHERALS_H @@ -32,12 +46,12 @@ /* Clocks */ /* Clock definitions */ -#define LFXO 0 -#define HFXO 1 -#define LFRCO 2 -#define HFRCO 3 +#define LFXO 0 +#define HFXO 1 +#define LFRCO 2 +#define HFRCO 3 #if !defined(_EFM32_GECKO_FAMILY) -#define ULFRCO 4 +#define ULFRCO 4 #endif /* Low Energy peripheral clock source. diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/Modules.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/Modules.h index 0e5e4e727d..2b3ba49aa7 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/Modules.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/Modules.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file Modules.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_MODULES_H #define MBED_MODULES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralNames.h index bae9a3ae92..457a495cd6 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.c index 52b8b4b44f..d159bdcb4e 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "PeripheralPins.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.h index 873aacd68a..6999fb20b6 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PeripheralPins.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PERIPHERALPINS_H #define MBED_PERIPHERALPINS_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PinNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PinNames.h index 521c422f82..171076557d 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PinNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PinNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PINNAMES_H #define MBED_PINNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PortNames.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PortNames.h index dfd60ac107..37dbdb1506 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PortNames.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PortNames.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file PortNames.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_PORTNAMES_H #define MBED_PORTNAMES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device.h index 657bf62e39..25eec569b1 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device_peripherals.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device_peripherals.h index 6cedfe5f6a..629b4bf970 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device_peripherals.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device_peripherals.h @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file device_peripheral.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #ifndef MBED_DEVICE_PERIPHERALS_H #define MBED_DEVICE_PERIPHERALS_H @@ -29,12 +43,12 @@ /* Clocks */ /* Clock definitions */ -#define LFXO 0 -#define HFXO 1 -#define LFRCO 2 -#define HFRCO 3 +#define LFXO 0 +#define HFXO 1 +#define LFRCO 2 +#define HFRCO 3 #if !defined(_EFM32_GECKO_FAMILY) -#define ULFRCO 4 +#define ULFRCO 4 #endif /* Low Energy peripheral clock source. diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c index 6b80ec25e3..ff3950da04 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file analogin_api.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #if DEVICE_ANALOGIN diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c index e1b340750b..3aee5739d1 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file analogout_aoi.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #if DEVICE_ANALOGOUT diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h index 5693234d81..7dd1daed28 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h @@ -3,7 +3,7 @@ * @brief Clock selection calculations ******************************************************************************* * @section License - * (C) Copyright 2014 Silicon Labs, http://www.silabs.com + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com ******************************************************************************* * * Permission is granted to anyone to use this software for any purpose, @@ -51,8 +51,18 @@ #endif #endif +#if ( LOW_ENERGY_CLOCK_SOURCE == LFXO ) +#define LEUART_USING_LFXO +#if ( defined(CMU_CTRL_HFLE) && (REFERENCE_FREQUENCY > 24000000) ) +#define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 4) +#else +#define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 2) +#endif +#define LEUART_LF_REF_FREQ LFXO_FREQUENCY +#else #if ( defined(CMU_CTRL_HFLE) && (REFERENCE_FREQUENCY > 24000000) ) #define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 4) #else #define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 2) #endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c index 8ca37af6a0..f963ecaba5 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file dma_api.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include #include "dma_api_HAL.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h index 12eb600320..68b6a6dc09 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file dma_api_HAL.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #ifndef MBED_DMA_API_HAL_H #define MBED_DMA_API_HAL_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/error.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/error.h index 3a403586dc..36f0cf1b2e 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/error.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/error.h @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file error.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #ifndef MBED_ERROR_H #define MBED_ERROR_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c index 55a0a374c4..af27c77009 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file gpio_api.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #include "gpio_api.h" #include "pinmap.h" #include "em_cmu.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c index bc78db77fa..a64034cbb9 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file gpio_irq_api.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #if DEVICE_INTERRUPTIN diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c index 35b645c08b..e57df79f72 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file i2c_api.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #include "clocking.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c index 3f89b89992..954e0c7c49 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file lp_ticker.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #if DEVICE_LOWPOWERTIMER diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/mbed_overrides.c index 37ec375ac9..b47c5acf86 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/mbed_overrides.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file mbed_overrides.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #include "em_chip.h" #include "em_device.h" #include "em_cmu.h" @@ -35,11 +50,9 @@ void mbed_sdk_init() /* Set up the clock sources for this chip */ #if( CORE_CLOCK_SOURCE == HFXO) CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); - CMU_ClockSelectSet(cmuClock_HFPER, cmuSelect_HFXO); SystemHFXOClockSet(HFXO_FREQUENCY); #elif( CORE_CLOCK_SOURCE == HFRCO) CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); - CMU_ClockSelectSet(cmuClock_HFPER, cmuSelect_HFRCO); CMU_HFRCOBandSet(HFRCO_FREQUENCY); #else #error "Core clock selection not valid (mbed_overrides.c)" @@ -53,11 +66,8 @@ void mbed_sdk_init() #endif #ifdef CMU_LFBCLKSEL_REG /* cmuClock_LFB (to date) only has LEUART peripherals. - * Do NOT set it up here, as LEUARTs might have been initialized - * before this code is called. (Limitation of the override mechanism of ARMCC) + * This gets set automatically whenever you create serial objects using LEUART */ - //TODO: Look for a more elegant fix. - //CMU_ClockSelectSet(cmuClock_LFB, LFXO); #endif #ifdef CMU_LFECLKSEL_REG CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO); @@ -69,7 +79,7 @@ void mbed_sdk_init() CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFRCO); #endif #ifdef CMU_LFBCLKSEL_REG - //CMU_ClockSelectSet(cmuClock_LFB, LFRCO); + //CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFRCO); #endif #ifdef CMU_LFECLKSEL_REG CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO); diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h index 1dd923e06e..b974e128c9 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file objects.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #ifndef MBED_OBJECTS_H #define MBED_OBJECTS_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap.c index a14f433e21..a0ffce796b 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file pinmap.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #include "pinmap.h" #include "em_gpio.h" #include "em_cmu.h" @@ -27,7 +42,7 @@ void pin_function(PinName pin, int function) void pin_mode(PinName pin, PinMode mode) { - MBED_ASSERT(pin != NC); + MBED_ASSERT((0xFFFFFF00 |pin) != NC); /* Enable GPIO clock if not already done */ if (!gpio_clock_inited) { diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.c index 7ce5aeb73e..c7aa0e2fa2 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file pinmap_function.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "pinmap_function.h" #include "PinNames.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.h index 1148f0e07f..45e6cc14e3 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.h @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file pinmap_function.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #ifndef MBED_PINMAP_FUNCTION_H #define MBED_PINMAP_FUNCTION_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/port_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/port_api.c index 2240f2df8e..971c787949 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/port_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/port_api.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file port_api.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #if DEVICE_PORTOUT diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c index cd8f45f17b..73e454bb55 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file pwmout_api.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #include "clocking.h" diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c index a3d55bbb19..85f73a2ccc 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file rtc_api.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #if DEVICE_RTC @@ -82,11 +96,6 @@ void rtc_init_real(uint32_t flags) useflags |= flags; if (!rtc_inited) { - /* Start LFXO and wait until it is stable */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - - /* Route the LFXO clock to the RTC */ - CMU_ClockSelectSet(cmuClock_LFA, LOW_ENERGY_CLOCK_SOURCE); CMU_ClockEnable(cmuClock_RTC, true); /* Enable clock to the interface of the low energy modules */ @@ -122,10 +131,10 @@ void rtc_free(void) void rtc_free_real(uint32_t flags) { /* Clear use flag */ - flags &= ~flags; + useflags &= ~flags; /* Disable the RTC if it was inited and is no longer in use by anyone. */ - if (rtc_inited && (flags == 0)) { + if (rtc_inited && (useflags == 0)) { NVIC_DisableIRQ(RTC_IRQn); RTC_Reset(); CMU_ClockEnable(cmuClock_RTC, false); diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h index 2da71614ad..733e343a96 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file rtc_api_HAL.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #ifndef MBED_RTC_API_HAL_H #define MBED_RTC_API_HAL_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c index 2094976fa7..55ac789ca3 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file serial_api.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #include "clocking.h" @@ -129,10 +143,11 @@ static void uart_init(serial_t *obj) init.databits = leuartDatabits8; init.parity = leuartNoParity; init.stopbits = leuartStopbits1; - - /* Determine the reference clock, because the correct clock is not set up at init time */ +#ifdef LEUART_USING_LFXO + init.refFreq = LEUART_LF_REF_FREQ; +#else init.refFreq = LEUART_REF_FREQ; - +#endif LEUART_Init(obj->serial.periph.leuart, &init); } else { USART_InitAsync_TypeDef init = USART_INITASYNC_DEFAULT; @@ -410,10 +425,15 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) serial_preinit(obj, tx, rx); if(LEUART_REF_VALID(obj->serial.periph.leuart)) { - // Set up LEUART clock tree to use high-speed clock) + // Set up LEUART clock tree +#ifdef LEUART_USING_LFXO + //set to use LFXO + CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); + CMU_ClockEnable(cmuClock_CORELE, true); +#else + //set to use high-speed clock CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_CORELEDIV2); - CMU_ClockEnable(cmuClock_LFB, true); - CMU_ClockSelectSet(serial_get_clock(obj), cmuSelect_CORELEDIV2); +#endif } CMU_ClockEnable(serial_get_clock(obj), true); @@ -430,6 +450,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) if(LEUART_REF_VALID(obj->serial.periph.leuart)) { obj->serial.periph.leuart->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | (obj->serial.location << _LEUART_ROUTE_LOCATION_SHIFT); obj->serial.periph.leuart->IFC = LEUART_IFC_TXC; + obj->serial.periph.leuart->CTRL |= LEUART_CTRL_RXDMAWU | LEUART_CTRL_TXDMAWU; } else { obj->serial.periph.uart->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | (obj->serial.location << _USART_ROUTE_LOCATION_SHIFT); obj->serial.periph.uart->IFC = USART_IFC_TXC; @@ -477,7 +498,50 @@ void serial_enable(serial_t *obj, uint8_t enable) void serial_baud(serial_t *obj, int baudrate) { if(LEUART_REF_VALID(obj->serial.periph.leuart)) { - LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_REF_FREQ, (uint32_t)baudrate); +#ifdef LEUART_USING_LFXO + + /* check if baudrate is within allowed range */ + MBED_ASSERT(baudrate >= (LEUART_LF_REF_FREQ >> 7)); + + if(baudrate > (LEUART_LF_REF_FREQ >> 1)){ + /* check if baudrate is within allowed range */ + MBED_ASSERT((baudrate <= (LEUART_HF_REF_FREQ >> 1)) && (baudrate > (LEUART_HF_REF_FREQ >> 10))); + + CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_CORELEDIV2); + uint8_t divisor = 1; + + if(baudrate > (LEUART_HF_REF_FREQ >> 7)){ + divisor = 1; + }else if(baudrate > (LEUART_HF_REF_FREQ >> 8)){ + divisor = 2; + }else if(baudrate > (LEUART_HF_REF_FREQ >> 9)){ + divisor = 4; + }else{ + divisor = 8; + } + CMU_ClockDivSet(serial_get_clock(obj), divisor); + LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_HF_REF_FREQ/divisor, (uint32_t)baudrate); + }else{ + CMU_ClockSelectSet(cmuClock_LFB, cmuSelect_LFXO); + CMU_ClockDivSet(serial_get_clock(obj), 1); + LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_LF_REF_FREQ, (uint32_t)baudrate); + } +#else + /* check if baudrate is within allowed range */ + MBED_ASSERT((baudrate > (LEUART_REF_FREQ >> 10)) && (baudrate <= (LEUART_REF_FREQ >> 1))); + uint8_t divisor = 1; + if(baudrate > (LEUART_REF_FREQ >> 7)){ + divisor = 1; + }else if(baudrate > (LEUART_REF_FREQ >> 8)){ + divisor = 2; + }else if(baudrate > (LEUART_REF_FREQ >> 9)){ + divisor = 4; + }else{ + divisor = 8; + } + CMU_ClockDivSet(serial_get_clock(obj), divisor); + LEUART_BaudrateSet(obj->serial.periph.leuart, LEUART_REF_FREQ/divisor, (uint32_t)baudrate); +#endif } else { USART_BaudrateAsyncSet(obj->serial.periph.uart, REFERENCE_FREQUENCY, (uint32_t)baudrate, usartOVS16); } @@ -857,7 +921,7 @@ void serial_pinout_tx(PinName tx) } /************************************************************************************ - * DMA helper functions * + * DMA helper functions * ************************************************************************************/ /****************************************** * static void serial_dmaTransferComplete(uint channel, bool primary, void* user) @@ -987,15 +1051,15 @@ static void serial_dmaSetupChannel(serial_t *obj, bool tx_nrx) * Tries to set the passed DMA state to the requested state. * * requested state possibilities: -* * NEVER: -* if the previous state was always, will deallocate the channel -* * OPPORTUNISTIC: -* If the previous state was always, will reuse that channel but free upon next completion. -* If not, will try to acquire a channel. -* When allocated, state changes to DMA_USAGE_TEMPORARY_ALLOCATED. -* * ALWAYS: -* Will try to allocate a channel and keep it. -* If succesfully allocated, state changes to DMA_USAGE_ALLOCATED. +* * NEVER: +* if the previous state was always, will deallocate the channel +* * OPPORTUNISTIC: +* If the previous state was always, will reuse that channel but free upon next completion. +* If not, will try to acquire a channel. +* When allocated, state changes to DMA_USAGE_TEMPORARY_ALLOCATED. +* * ALWAYS: +* Will try to allocate a channel and keep it. +* If succesfully allocated, state changes to DMA_USAGE_ALLOCATED. ******************************************/ static void serial_dmaTrySetState(DMA_OPTIONS_t *obj, DMAUsage requestedState, serial_t *serialPtr, bool tx_nrx) { @@ -1050,22 +1114,16 @@ static void serial_dmaActivate(serial_t *obj, void* cb, void* buffer, int length channelConfig.hprot = 0; DMA_CfgDescr(obj->serial.dmaOptionsTX.dmaChannel, true, &channelConfig); - if(LEUART_REF_VALID(obj->serial.periph.leuart)) { // Activate TX obj->serial.periph.leuart->CMD = LEUART_CMD_TXEN; - - // Clear TX buffer - obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARTX; + while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD); // Kick off TX DMA DMA_ActivateBasic(obj->serial.dmaOptionsTX.dmaChannel, true, false, (void*) &(obj->serial.periph.leuart->TXDATA), buffer, length - 1); } else { - // Activate TX - obj->serial.periph.uart->CMD = USART_CMD_TXEN; - - // Clear TX buffer - obj->serial.periph.uart->CMD = USART_CMD_CLEARTX; + // Activate TX amd clear TX buffer + obj->serial.periph.uart->CMD = USART_CMD_TXEN | USART_CMD_CLEARTX; // Kick off TX DMA DMA_ActivateBasic(obj->serial.dmaOptionsTX.dmaChannel, true, false, (void*) &(obj->serial.periph.uart->TXDATA), buffer, length - 1); @@ -1085,20 +1143,15 @@ static void serial_dmaActivate(serial_t *obj, void* cb, void* buffer, int length DMA_CfgDescr(obj->serial.dmaOptionsRX.dmaChannel, true, &channelConfig); if(LEUART_REF_VALID(obj->serial.periph.leuart)) { - // Activate RX - obj->serial.periph.leuart->CMD = LEUART_CMD_RXEN; - - // Clear RX buffer - obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARRX; + // Activate RX and clear RX buffer + obj->serial.periph.leuart->CMD = LEUART_CMD_RXEN | LEUART_CMD_CLEARRX; + while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD); // Kick off RX DMA DMA_ActivateBasic(obj->serial.dmaOptionsRX.dmaChannel, true, false, buffer, (void*) &(obj->serial.periph.leuart->RXDATA), length - 1); } else { - // Activate RX - obj->serial.periph.uart->CMD = USART_CMD_RXEN; - - // Clear RX buffer - obj->serial.periph.uart->CMD = USART_CMD_CLEARRX; + // Activate RX and clear RX buffer + obj->serial.periph.uart->CMD = USART_CMD_RXEN | USART_CMD_CLEARRX; // Kick off RX DMA DMA_ActivateBasic(obj->serial.dmaOptionsRX.dmaChannel, true, false, buffer, (void*) &(obj->serial.periph.uart->RXDATA), length - 1); @@ -1107,13 +1160,13 @@ static void serial_dmaActivate(serial_t *obj, void* cb, void* buffer, int length } /************************************************************************************ - * ASYNCHRONOUS HAL * + * ASYNCHRONOUS HAL * ************************************************************************************/ #if DEVICE_SERIAL_ASYNCH /************************************ - * HELPER FUNCTIONS * + * HELPER FUNCTIONS * ***********************************/ /** Configure TX events @@ -1157,11 +1210,6 @@ void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) if(enable) obj->serial.periph.leuart->IEN |= LEUART_IEN_RXOF; else obj->serial.periph.leuart->IEN &= ~LEUART_IEN_RXOF; } - if(event & SERIAL_EVENT_RX_CHARACTER_MATCH) { - /* This is only supported on LEUART in hardware. */ - if(enable) obj->serial.periph.leuart->IEN |= LEUART_IEN_SIGF; - else obj->serial.periph.leuart->IEN &= ~LEUART_IEN_SIGF; - } } else { if(event & SERIAL_EVENT_RX_FRAMING_ERROR) { //FERR interrupt source @@ -1178,13 +1226,6 @@ void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) if(enable) obj->serial.periph.uart->IEN |= USART_IEN_RXOF; else obj->serial.periph.uart->IEN &= ~USART_IEN_RXOF; } - if(event & SERIAL_EVENT_RX_CHARACTER_MATCH) { - /* This is currently unsupported in HW. - * In order to support this, we will have to switch to interrupt-based operation and check every incoming character. - */ - - //TODO: force interrupt-based operation when enabling character match. - } } } @@ -1228,30 +1269,8 @@ void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width) return; } -/** Set character to be matched. If an event is enabled, and received character - * matches the defined char_match, the receiving process is stopped and MATCH event - * is invoked - * - * @param obj The serial object - * @param char_match A character in range 0-254 - */ -void serial_set_char_match(serial_t *obj, uint8_t char_match) -{ - // We only have hardware support for this in LEUART. - // When in USART/UART, we can set up a check in the receiving ISR, but not when using DMA. - if (char_match != SERIAL_RESERVED_CHAR_MATCH) { - obj->char_match = char_match; - - if(LEUART_REF_VALID(obj->serial.periph.leuart)) { - obj->serial.periph.leuart->SIGFRAME = char_match & 0x000000FF; - } - } - - return; -} - /************************************ - * TRANSFER FUNCTIONS * + * TRANSFER FUNCTIONS * ***********************************/ /** Begin asynchronous TX transfer. The used buffer is specified in the serial object, @@ -1276,7 +1295,15 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx serial_tx_enable_event(obj, event, true); // Set up sleepmode +#ifdef LEUART_USING_LFXO + if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){ + blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART); + }else{ + blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); + } +#else blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); +#endif // Determine DMA strategy serial_dmaTrySetState(&(obj->serial.dmaOptionsTX), hint, obj, true); @@ -1295,20 +1322,15 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx NVIC_EnableIRQ(serial_get_tx_irq_index(obj)); if(LEUART_REF_VALID(obj->serial.periph.leuart)) { - // Activate TX and return - obj->serial.periph.leuart->CMD = LEUART_CMD_TXEN; - - // Clear TX buffer - obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARTX; + // Activate TX and clear TX buffer + obj->serial.periph.leuart->CMD = LEUART_CMD_TXEN | LEUART_CMD_CLEARTX; + while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD); // Enable interrupt LEUART_IntEnable(obj->serial.periph.leuart, LEUART_IEN_TXBL); } else { - // Activate TX and return - obj->serial.periph.uart->CMD = USART_CMD_TXEN; - - // Clear TX buffer - obj->serial.periph.uart->CMD = USART_CMD_CLEARTX; + // Activate TX and clear TX buffer + obj->serial.periph.uart->CMD = USART_CMD_TXEN | USART_CMD_CLEARTX; // Enable interrupt USART_IntEnable(obj->serial.periph.uart, USART_IEN_TXBL); @@ -1332,20 +1354,43 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt if(rx_length == 0) return; // Set up buffer - serial_rx_buffer_set(obj, rx, rx_length, rx_width); + serial_rx_buffer_set(obj,(void*) rx, rx_length, rx_width); + + //disable character match if no character is specified + if(char_match == SERIAL_RESERVED_CHAR_MATCH){ + event &= ~SERIAL_EVENT_RX_CHARACTER_MATCH; + } + + /*clear all set interrupts*/ + if(LEUART_REF_VALID(obj->serial.periph.leuart)) { + LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_PERR | LEUART_IFC_FERR | LEUART_IFC_RXOF); + }else{ + USART_IntClear(obj->serial.periph.uart, USART_IFC_PERR | USART_IFC_FERR | USART_IFC_RXOF); + } // Set up events serial_rx_enable_event(obj, SERIAL_EVENT_RX_ALL, false); serial_rx_enable_event(obj, event, true); - serial_set_char_match(obj, char_match); + obj->char_match = char_match; // Set up sleepmode +#ifdef LEUART_USING_LFXO + if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){ + blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART); + }else{ + blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); + } +#else blockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); +#endif // Determine DMA strategy // If character match is enabled, we can't use DMA, sadly. We could when using LEUART though, but that support is not in here yet. + // TODO: add DMA support for character matching with leuart if(!(event & SERIAL_EVENT_RX_CHARACTER_MATCH)) { serial_dmaTrySetState(&(obj->serial.dmaOptionsRX), hint, obj, false); + }else{ + serial_dmaTrySetState(&(obj->serial.dmaOptionsRX), DMA_USAGE_NEVER, obj, false); } // If DMA, kick off DMA @@ -1360,20 +1405,15 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt NVIC_EnableIRQ(serial_get_rx_irq_index(obj)); if(LEUART_REF_VALID(obj->serial.periph.leuart)) { - // Activate RX - obj->serial.periph.leuart->CMD = LEUART_CMD_RXEN; - - // Clear RX buffer - obj->serial.periph.leuart->CMD = LEUART_CMD_CLEARRX; + // Activate RX and clear RX buffer + obj->serial.periph.leuart->CMD = LEUART_CMD_RXEN | LEUART_CMD_CLEARRX; + while(obj->serial.periph.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD); // Enable interrupt LEUART_IntEnable(obj->serial.periph.leuart, LEUART_IEN_RXDATAV); } else { - // Activate RX - obj->serial.periph.uart->CMD = USART_CMD_RXEN; - - // Clear RX buffer - obj->serial.periph.uart->CMD = USART_CMD_CLEARRX; + // Activate RX and clear RX buffer + obj->serial.periph.uart->CMD = USART_CMD_RXEN | USART_CMD_CLEARRX; // Clear RXFULL USART_IntClear(obj->serial.periph.uart, USART_IFC_RXFULL); @@ -1445,23 +1485,40 @@ int serial_tx_irq_handler_asynch(serial_t *obj) /* This interrupt handler is called from USART irq */ uint8_t *buf = obj->tx_buff.buffer; - /* Interrupt has another TX source */ - if(obj->tx_buff.pos >= obj->tx_buff.length) { - /* Transfer complete. Switch off interrupt and return event. */ - serial_tx_abort_asynch(obj); - return SERIAL_EVENT_TX_COMPLETE & obj->serial.events; - } else { - /* There's still data in the buffer that needs to be sent */ - if(LEUART_REF_VALID(obj->serial.periph.leuart)) { + if(LEUART_REF_VALID(obj->serial.periph.leuart)) { + if(obj->serial.periph.leuart->IEN & LEUART_IEN_TXBL){ + /* There is still data to send */ while((LEUART_StatusGet(obj->serial.periph.leuart) & LEUART_STATUS_TXBL) && (obj->tx_buff.pos <= (obj->tx_buff.length - 1))) { + while (obj->serial.periph.leuart->SYNCBUSY); LEUART_Tx(obj->serial.periph.leuart, buf[obj->tx_buff.pos]); obj->tx_buff.pos++; } - } else { + if(obj->tx_buff.pos >= obj->tx_buff.length){ + /* Last byte has been put in TX, set up TXC interrupt */ + LEUART_IntDisable(obj->serial.periph.leuart, LEUART_IEN_TXBL); + LEUART_IntEnable(obj->serial.periph.leuart, LEUART_IEN_TXC); + } + }else if (obj->serial.periph.leuart->IF & LEUART_IF_TXC){ + /* Last byte has been successfully transmitted. Stop the procedure */ + serial_tx_abort_asynch(obj); + return SERIAL_EVENT_TX_COMPLETE & obj->serial.events; + } + } else { + if(obj->serial.periph.uart->IEN & USART_IEN_TXBL){ + /* There is still data to send */ while((USART_StatusGet(obj->serial.periph.uart) & USART_STATUS_TXBL) && (obj->tx_buff.pos <= (obj->tx_buff.length - 1))) { USART_Tx(obj->serial.periph.uart, buf[obj->tx_buff.pos]); obj->tx_buff.pos++; } + if(obj->tx_buff.pos >= obj->tx_buff.length){ + /* Last byte has been put in TX, set up TXC interrupt */ + USART_IntDisable(obj->serial.periph.uart, USART_IEN_TXBL); + USART_IntEnable(obj->serial.periph.uart, USART_IEN_TXC); + } + } else if (obj->serial.periph.uart->IF & USART_IF_TXC) { + /* Last byte has been successfully transmitted. Stop the procedure */ + serial_tx_abort_asynch(obj); + return SERIAL_EVENT_TX_COMPLETE & obj->serial.events; } } return 0; @@ -1503,13 +1560,6 @@ int serial_rx_irq_handler_asynch(serial_t *obj) return SERIAL_EVENT_RX_OVERFLOW; } - if(LEUART_IntGetEnabled(obj->serial.periph.leuart) & LEUART_IF_SIGF) { - /* Char match has occurred, stop RX and return */ - LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_SIGF); - serial_rx_abort_asynch(obj); - return SERIAL_EVENT_RX_CHARACTER_MATCH; - } - if((LEUART_IntGetEnabled(obj->serial.periph.leuart) & LEUART_IF_RXDATAV) || (LEUART_StatusGet(obj->serial.periph.leuart) & LEUART_STATUS_RXDATAV)) { /* Valid data in buffer. Determine course of action: continue receiving or interrupt */ if(obj->rx_buff.pos >= (obj->rx_buff.length - 1)) { @@ -1525,21 +1575,23 @@ int serial_rx_irq_handler_asynch(serial_t *obj) } else { /* There's still space in the receive buffer */ while((LEUART_StatusGet(obj->serial.periph.leuart) & LEUART_STATUS_RXDATAV) && (obj->rx_buff.pos <= (obj->rx_buff.length - 1))) { - + bool aborting = false; buf[obj->rx_buff.pos] = LEUART_RxDataGet(obj->serial.periph.leuart); obj->rx_buff.pos++; /* Check for character match event */ if((buf[obj->rx_buff.pos - 1] == obj->char_match) && (obj->serial.events & SERIAL_EVENT_RX_CHARACTER_MATCH)) { + aborting = true; event |= SERIAL_EVENT_RX_CHARACTER_MATCH; } /* Check for final char event */ if(obj->rx_buff.pos >= (obj->rx_buff.length)) { + aborting = true; event |= SERIAL_EVENT_RX_COMPLETE & obj->serial.events; } - if(event != 0) { + if(aborting) { serial_rx_abort_asynch(obj); return event & obj->serial.events; } @@ -1584,21 +1636,23 @@ int serial_rx_irq_handler_asynch(serial_t *obj) } else { /* There's still space in the receive buffer */ while(((USART_StatusGet(obj->serial.periph.uart) & USART_STATUS_RXDATAV) || (USART_StatusGet(obj->serial.periph.uart) & USART_IF_RXFULL)) && (obj->rx_buff.pos <= (obj->rx_buff.length - 1))) { - + bool aborting = false; buf[obj->rx_buff.pos] = USART_RxDataGet(obj->serial.periph.uart); obj->rx_buff.pos++; /* Check for character match event */ if((buf[obj->rx_buff.pos - 1] == obj->char_match) && (obj->serial.events & SERIAL_EVENT_RX_CHARACTER_MATCH)) { + aborting = true; event |= SERIAL_EVENT_RX_CHARACTER_MATCH; } /* Check for final char event */ if(obj->rx_buff.pos >= (obj->rx_buff.length)) { + aborting = true; event |= SERIAL_EVENT_RX_COMPLETE & obj->serial.events; } - if(event != 0) { + if(aborting) { serial_rx_abort_asynch(obj); return event & obj->serial.events; } @@ -1626,26 +1680,43 @@ int serial_irq_handler_asynch(serial_t *obj) /* Notify CPP land of RX completion */ return SERIAL_EVENT_RX_COMPLETE & obj->serial.events; } else if (serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel]) { - /* Clean up */ - serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel] = false; - serial_tx_abort_asynch(obj); - - /* Notify CPP land of completion */ - return SERIAL_EVENT_TX_COMPLETE & obj->serial.events; + if(LEUART_REF_VALID(obj->serial.periph.leuart)) { + if(obj->serial.periph.leuart->IEN & LEUART_IEN_TXC){ + LEUART_IntDisable(obj->serial.periph.leuart,LEUART_IEN_TXC); + /* Clean up */ + serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel] = false; + serial_tx_abort_asynch(obj); + /* Notify CPP land of completion */ + return SERIAL_EVENT_TX_COMPLETE & obj->serial.events; + }else{ + LEUART_IntEnable(obj->serial.periph.leuart,LEUART_IEN_TXC); + } + }else{ + if(obj->serial.periph.uart->IEN & USART_IEN_TXC){ + USART_IntDisable(obj->serial.periph.leuart,USART_IEN_TXC); + /* Clean up */ + serial_dma_irq_fired[obj->serial.dmaOptionsTX.dmaChannel] = false; + serial_tx_abort_asynch(obj); + /* Notify CPP land of completion */ + return SERIAL_EVENT_TX_COMPLETE & obj->serial.events; + }else{ + USART_IntEnable(obj->serial.periph.leuart,USART_IEN_TXC); + } + } } else { /* Check the NVIC to see which interrupt we're running from * Also make sure to prioritize RX */ if(LEUART_REF_VALID(obj->serial.periph.leuart)) { //Different method of checking tx vs rx for LEUART - if(LEUART_IntGetEnabled(obj->serial.periph.leuart) & (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IF_PERR | LEUART_IF_RXOF | LEUART_IF_SIGF)) { + if(LEUART_IntGetEnabled(obj->serial.periph.leuart) & (LEUART_IF_RXDATAV | LEUART_IF_FERR | LEUART_IF_PERR | LEUART_IF_RXOF)) { return serial_rx_irq_handler_asynch(obj); - } else if(LEUART_StatusGet(obj->serial.periph.leuart) & LEUART_STATUS_TXBL) { + } else if(LEUART_StatusGet(obj->serial.periph.leuart) & (LEUART_STATUS_TXBL | LEUART_STATUS_TXC)) { return serial_tx_irq_handler_asynch(obj); } } else { if(USART_IntGetEnabled(obj->serial.periph.uart) & (USART_IF_RXDATAV | USART_IF_RXOF | USART_IF_PERR | USART_IF_FERR)) { return serial_rx_irq_handler_asynch(obj); - } else { + } else if(USART_StatusGet(obj->serial.periph.uart) & (USART_STATUS_TXBL | USART_STATUS_TXC)){ return serial_tx_irq_handler_asynch(obj); } } @@ -1681,15 +1752,25 @@ void serial_tx_abort_asynch(serial_t *obj) default: /* stop interrupting */ if(LEUART_REF_VALID(obj->serial.periph.leuart)) { - LEUART_IntDisable(obj->serial.periph.leuart, LEUART_IEN_TXBL); + LEUART_IntDisable(obj->serial.periph.leuart, LEUART_IEN_TXC); + LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_TXC); } else { - USART_IntDisable(obj->serial.periph.uart, USART_IEN_TXBL); + USART_IntDisable(obj->serial.periph.uart, USART_IEN_TXC); + USART_IntClear(obj->serial.periph.uart, USART_IFC_TXC); } break; } - /* Unblock EM2 and below */ + /* Say that we can stop using this emode */ +#ifdef LEUART_USING_LFXO + if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){ + unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART); + }else{ + unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); + } +#else unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); +#endif } /** Abort the ongoing RX transaction It disables the enabled interrupt for RX and @@ -1718,15 +1799,30 @@ void serial_rx_abort_asynch(serial_t *obj) default: /* stop interrupting */ if(LEUART_REF_VALID(obj->serial.periph.leuart)) { - LEUART_IntDisable(obj->serial.periph.leuart, LEUART_IEN_RXDATAV | LEUART_IEN_PERR | LEUART_IEN_FERR | LEUART_IEN_RXOF | LEUART_IEN_SIGF); + LEUART_IntDisable(obj->serial.periph.leuart, LEUART_IEN_RXDATAV | LEUART_IEN_PERR | LEUART_IEN_FERR | LEUART_IEN_RXOF); } else { USART_IntDisable(obj->serial.periph.uart, USART_IEN_RXDATAV | USART_IEN_PERR | USART_IEN_FERR | USART_IEN_RXOF); } break; } + /*clear all set interrupts*/ + if(LEUART_REF_VALID(obj->serial.periph.leuart)) { + LEUART_IntClear(obj->serial.periph.leuart, LEUART_IFC_PERR | LEUART_IFC_FERR | LEUART_IFC_RXOF); + }else{ + USART_IntClear(obj->serial.periph.uart, USART_IFC_PERR | USART_IFC_FERR | USART_IFC_RXOF); + } + /* Say that we can stop using this emode */ +#ifdef LEUART_USING_LFXO + if(LEUART_REF_VALID(obj->serial.periph.leuart) && (LEUART_BaudrateGet(obj->serial.periph.leuart) <= (LEUART_LF_REF_FREQ/2))){ + unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE_LEUART); + }else{ + unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); + } +#else unblockSleepMode(SERIAL_LEAST_ACTIVE_SLEEPMODE); +#endif } #endif //DEVICE_SERIAL_ASYNCH diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c index 973e528cd8..c1dd9941bf 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c @@ -1,18 +1,32 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file sleep.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ #include "device.h" #if DEVICE_SLEEP @@ -35,17 +49,20 @@ uint32_t sleep_block_counter[NUM_SLEEP_MODES] = {0}; void sleep(void) { if (sleep_block_counter[0] > 0) { - // Blocked everything below EM0, so just return + /* Blocked everything below EM0, so just return */ return; } else if (sleep_block_counter[1] > 0) { - // Blocked everything below EM1, enter EM1 + /* Blocked everything below EM1, enter EM1 */ EMU_EnterEM1(); } else if (sleep_block_counter[2] > 0) { - // Blocked everything below EM2, enter EM2 + /* Blocked everything below EM2, enter EM2 */ EMU_EnterEM2(true); } else if (sleep_block_counter[3] > 0) { - // Blocked everything below EM3, enter EM3 + /* Blocked everything below EM3, enter EM3 */ EMU_EnterEM3(true); + } else{ + /* Nothing is blocked, enter EM4 */ + EMU_EnterEM4(); } return; } diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h index 2dafe153af..b33ecb6931 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015 ARM Limited +/***************************************************************************//** + * @file sleepmodes.h + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #ifndef MBED_SLEEPMODES_H #define MBED_SLEEPMODES_H diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c index cfa6af238a..0355e89ba1 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file spi_api.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #include "device.h" #include "clocking.h" #if DEVICE_SPI diff --git a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c index 0667adef50..a909990dd4 100644 --- a/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c @@ -1,18 +1,33 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited +/***************************************************************************//** + * @file us_ticker.c + ******************************************************************************* + * @section License + * (C) Copyright 2015 Silicon Labs, http://www.silabs.com + ******************************************************************************* * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: * - * http://www.apache.org/licenses/LICENSE-2.0 + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ + * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no + * obligation to support this Software. Silicon Labs is providing the + * Software "AS IS", with no express or implied warranties of any kind, + * including, but not limited to, any implied warranties of merchantability + * or fitness for any particular purpose or warranties against infringement + * of any proprietary rights of a third party. + * + * Silicon Labs will not be liable for any consequential, incidental, or + * special damages, or any other relief, or for any claim by any third party, + * arising from your use of this Software. + * + ******************************************************************************/ + #include #include "us_ticker_api.h" #include "cmsis.h" diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h index 973ff199b8..41b4642112 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h @@ -43,7 +43,8 @@ typedef enum { typedef enum { UART_0 = (int)W7500x_UART0_BASE, - UART_1 = (int)W7500x_UART1_BASE + UART_1 = (int)W7500x_UART1_BASE, + UART_2 = (int)W7500x_UART2_BASE } UARTName; diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PeripheralPins.c new file mode 100644 index 0000000000..03ad45093e --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PeripheralPins.c @@ -0,0 +1,136 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" +#include "PeripheralNames.h" +#include "pinmap.h" + + +//*** ADC *** +const PinMap PinMap_ADC[] = { + {PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0 + {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1 + {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2 + {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3 + {PC_9 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN6 + {PC_8 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN7 + {NC, NC, 0} +}; + + +//*** SERIAL *** +const PinMap PinMap_UART_TX[] = { + {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PB_2, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, + {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PA_9, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, + {PC_10, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_6, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PB_3, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, + {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PA_10, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, + {PC_11, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_7, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF2)}, + {NC, NC, 0} +}; + +//*** I2C *** +const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PA_6, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC, NC, 0} +}; + +//*** SPI *** +const PinMap PinMap_SPI_SCLK[] = { + {PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC , NC , 0} +}; + +const PinMap PinMap_PWM[] = { + {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_9 , PWM_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_1 , PWM_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_3 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PA_6 , PWM_3, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {NC , NC , 0} +}; + diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PinNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PinNames.h new file mode 100644 index 0000000000..5ad1ce7f8d --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/PinNames.h @@ -0,0 +1,228 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM +#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE) << 8) | ((PUPD) << 4) | ((AFNUM) << 0))) +#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F) +#define WIZ_PIN_AFNUM(X) (((X) >> 0) & 0x0F) +#define WIZ_PIN_MODE(X) (((X) >> 8) & 0x0F) +#define WIZ_MODE_INPUT (0) +#define WIZ_MODE_OUTPUT (1) +#define WIZ_MODE_AF (2) + +#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */ +#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */ +#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */ +#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */ + + +#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D) +#define WIZ_PIN_NUM(X) ((uint32_t)(X) & 0xF) // pin number +#define WIZ_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit + + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + + +typedef enum { + // W7500x PORT[5:4] + PIN[3:0]) + PA_0 = 0x000, + PA_1 = 0x001, + PA_2 = 0x002, + PA_3 = 0x003, + PA_4 = 0x004, + PA_5 = 0x005, + PA_6 = 0x006, + PA_7 = 0x007, + PA_8 = 0x008, + PA_9 = 0x009, + PA_10 = 0x00A, + PA_11 = 0x00B, + PA_12 = 0x00C, + PA_13 = 0x00D, + PA_14 = 0x00E, + PA_15 = 0x00F, + + PB_0 = 0x010, + PB_1 = 0x011, + PB_2 = 0x012, + PB_3 = 0x013, + PB_4 = 0x014, + PB_5 = 0x015, + PB_6 = 0x016, + PB_7 = 0x017, + PB_8 = 0x018, + PB_9 = 0x019, + PB_10 = 0x01A, + PB_11 = 0x01B, + PB_12 = 0x01C, + PB_13 = 0x01D, + PB_14 = 0x01E, + PB_15 = 0x01F, + + PC_0 = 0x020, + PC_1 = 0x021, + PC_2 = 0x022, + PC_3 = 0x023, + PC_4 = 0x024, + PC_5 = 0x025, + PC_6 = 0x026, + PC_7 = 0x027, + PC_8 = 0x028, + PC_9 = 0x029, + + PC_10 = 0x02A, + PC_11 = 0x02B, + PC_12 = 0x02C, + PC_13 = 0x02D, + PC_14 = 0x02E, + PC_15 = 0x02F, + + PD_0 = 0x030, + PD_1 = 0x031, + PD_2 = 0x032, + PD_3 = 0x033, + PD_4 = 0x034, + + PA_00 = PA_0, + PA_01 = PA_1, + PA_02 = PA_2, + PA_03 = PA_3, + PA_04 = PA_4, + PA_05 = PA_5, + PA_06 = PA_6, + PA_07 = PA_7, + PA_08 = PA_8, + PA_09 = PA_9, + + PB_00 = PB_0, + PB_01 = PB_1, + PB_02 = PB_2, + PB_03 = PB_3, + PB_04 = PB_4, + PB_05 = PB_5, + PB_06 = PB_6, + PB_07 = PB_7, + PB_08 = PB_8, + PB_09 = PB_9, + + PC_00 = PC_0, + PC_01 = PC_1, + PC_02 = PC_2, + PC_03 = PC_3, + PC_04 = PC_4, + PC_05 = PC_5, + PC_06 = PC_6, + PC_07 = PC_7, + PC_08 = PC_8, + PC_09 = PC_9, + + PD_00 = PD_0, + PD_01 = PD_1, + PD_02 = PD_2, + PD_03 = PD_3, + PD_04 = PD_4, + + + // Generic signals namings + LED1 = PA_01, + LED2 = PA_02, + LED3 = LED1, + LED4 = LED2, + + USBTX = PC_10, + USBRX = PC_11, + + // For ECO + P5 = PA_5, + P6 = PA_6, + P7 = PA_7, + P8 = PA_8, + P9 = PA_9, + P10 = PA_10, + P11 = PA_11, + P12 = PA_12, + P13 = PA_13, + P14 = PA_14, + P15 = PB_0, + P16 = PB_1, + P17 = PB_2, + P18 = PB_3, + P19 = PC_5, + P20 = PC_4, + P21 = PC_0, + P22 = PC_1, + P23 = PC_2, + P24 = PC_3, + P25 = PC_8, + P26 = PC_9, + P27 = PC_12, + P28 = PC_13, + P29 = PC_14, + P30 = PC_15, + P31 = PC_6, + P32 = PC_7, + + //Use SPI1 + SD_SEL = PB_0, // SPI1_CS + SD_CLK = PB_1, // SPI1_CLK + SD_MISO = PB_2, // MOSI1 + SD_MOSI = PB_3, // MISO1 + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullNone +} PinMode; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device.h new file mode 100644 index 0000000000..2645702c52 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device.h @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 0 + +#define DEVICE_ETHERNET 0 + + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define STDIO_UART_TX PC_10 +#define STDIO_UART_RX PC_11 +#define STDIO_UART UART_2 + + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PeripheralPins.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PeripheralPins.c new file mode 100644 index 0000000000..6af6127131 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PeripheralPins.c @@ -0,0 +1,132 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" +#include "PeripheralNames.h" +#include "pinmap.h" + + +//*** ADC *** +const PinMap PinMap_ADC[] = { + {PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0 + {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1 + {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2 + {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3 + {PC_11, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN4 + {PC_10, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN5 + {PC_9 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN6 + {PC_8 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN7 + {NC, NC, 0} +}; + + +//*** SERIAL *** +const PinMap PinMap_UART_TX[] = { + {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_10, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {PC_11, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)}, + {NC, NC, 0} +}; + +//*** I2C *** +const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PA_6, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_SCLK[] = { + {PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC , NC , 0} +}; + +const PinMap PinMap_PWM[] = { + {PA_0 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_1 , PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)}, + {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}, + {PC_10, PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)}, + {NC , NC , WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)} +}; + diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PinNames.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PinNames.h new file mode 100644 index 0000000000..15b6f4a0f9 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PinNames.h @@ -0,0 +1,230 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM +#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE) << 8) | ((PUPD) << 4) | ((AFNUM) << 0))) +#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F) +#define WIZ_PIN_AFNUM(X) (((X) >> 0) & 0x0F) +#define WIZ_PIN_MODE(X) (((X) >> 8) & 0x0F) +#define WIZ_MODE_INPUT (0) +#define WIZ_MODE_OUTPUT (1) +#define WIZ_MODE_AF (2) + +#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */ +#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */ +#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */ +#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */ + + +#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D) +#define WIZ_PIN_NUM(X) ((uint32_t)(X) & 0xF) // pin number +#define WIZ_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit + + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + + +typedef enum { + // W7500x PORT[5:4] + PIN[3:0]) + PA_0 = 0x000, + PA_1 = 0x001, + PA_2 = 0x002, + PA_3 = 0x003, + PA_4 = 0x004, + PA_5 = 0x005, + PA_6 = 0x006, + PA_7 = 0x007, + PA_8 = 0x008, + PA_9 = 0x009, + PA_10 = 0x00A, + PA_11 = 0x00B, + PA_12 = 0x00C, + PA_13 = 0x00D, + PA_14 = 0x00E, + PA_15 = 0x00F, + + PB_0 = 0x010, + PB_1 = 0x011, + PB_2 = 0x012, + PB_3 = 0x013, + PB_4 = 0x014, + PB_5 = 0x015, + PB_6 = 0x016, + PB_7 = 0x017, + PB_8 = 0x018, + PB_9 = 0x019, + PB_10 = 0x01A, + PB_11 = 0x01B, + PB_12 = 0x01C, + PB_13 = 0x01D, + PB_14 = 0x01E, + PB_15 = 0x01F, + + PC_0 = 0x020, + PC_1 = 0x021, + PC_2 = 0x022, + PC_3 = 0x023, + PC_4 = 0x024, + PC_5 = 0x025, + PC_6 = 0x026, + PC_7 = 0x027, + PC_8 = 0x028, + PC_9 = 0x029, + + PC_10 = 0x02A, + PC_11 = 0x02B, + PC_12 = 0x02C, + PC_13 = 0x02D, + PC_14 = 0x02E, + PC_15 = 0x02F, + + PD_0 = 0x030, + PD_1 = 0x031, + PD_2 = 0x032, + PD_3 = 0x033, + PD_4 = 0x034, + + PA_00 = PA_0, + PA_01 = PA_1, + PA_02 = PA_2, + PA_03 = PA_3, + PA_04 = PA_4, + PA_05 = PA_5, + PA_06 = PA_6, + PA_07 = PA_7, + PA_08 = PA_8, + PA_09 = PA_9, + + PB_00 = PB_0, + PB_01 = PB_1, + PB_02 = PB_2, + PB_03 = PB_3, + PB_04 = PB_4, + PB_05 = PB_5, + PB_06 = PB_6, + PB_07 = PB_7, + PB_08 = PB_8, + PB_09 = PB_9, + + PC_00 = PC_0, + PC_01 = PC_1, + PC_02 = PC_2, + PC_03 = PC_3, + PC_04 = PC_4, + PC_05 = PC_5, + PC_06 = PC_6, + PC_07 = PC_7, + PC_08 = PC_8, + PC_09 = PC_9, + + PD_00 = PD_0, + PD_01 = PD_1, + PD_02 = PD_2, + PD_03 = PD_3, + PD_04 = PD_4, + + // Arduino connector namings + A0 = PC_15, // AIN0 + A1 = PC_14, // AIN1 + A2 = PC_13, // AIN2 + A3 = PC_12, // AIN3 + A4 = PC_9, // AIN4 + A5 = PC_8, // AIN5 + + D0 = PA_14, + D1 = PA_13, + D2 = PC_3, + D3 = PC_2, + D4 = PA_2, + D5 = PA_1, + D6 = PA_0, + D7 = PA_12, + D8 = PA_11, + D9 = PC_1, + D10 = PA_5, + D11 = PA_8, + D12 = PA_7, + D13 = PA_6, + D14 = PA_10, + D15 = PA_9, + + // Generic signals namings + LED_RED = PC_0, + LED_GREEN = PC_4, + LED_BLUE = PC_5, + + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_BLUE, + + LEDR = LED_RED, + LEDG = LED_GREEN, + LEDB = LED_BLUE, + + USBTX = PC_10, + USBRX = PC_11, + + //Use SPI1 + SD_SEL = PB_0, // SPI1_CS + SD_CLK = PB_1, // SPI1_CLK + SD_MISO = PB_2, // MOSI1 + SD_MOSI = PB_3, // MISO1 + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullNone +} PinMode; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device.h new file mode 100644 index 0000000000..3052f21daf --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device.h @@ -0,0 +1,78 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 0 + +#define DEVICE_ETHERNET 0 + + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define STDIO_UART_TX PC_10 +#define STDIO_UART_RX PC_11 +#define STDIO_UART UART_2 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c index fb90e393f9..560e154980 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c @@ -208,13 +208,24 @@ void S_UART_DeInit() uint32_t S_UART_Init(uint32_t baud) { uint32_t tmpreg=0x00; - uint32_t uartclock = 0x00, integer_baud = 0x00; - assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode)); + S_UART_SetBaud(baud); + + tmpreg = UART2->CTRL; + tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); + tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); + UART2->CTRL = tmpreg; + + return 0; +} + +void S_UART_SetBaud(uint32_t baud) +{ + uint32_t uartclock = 0x00, integer_baud = 0x00; if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK) { - uartclock = INTERN_XTAL; + uartclock = INTERN_XTAL; } else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK) { @@ -227,18 +238,11 @@ uint32_t S_UART_Init(uint32_t baud) integer_baud = (uint32_t)(uartclock / baud); UART2->BAUDDIV = integer_baud; - - tmpreg = UART2->CTRL; - tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); - tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); - UART2->CTRL = tmpreg; - - return 0; } void S_UART_SendData(uint16_t Data) { - while(UART2->STATE & S_UART_STATE_TX_BUF_FULL); + while(UART2->STATE & S_UART_STATE_TX_BUF_FULL); UART2->DATA = Data; } @@ -248,13 +252,13 @@ uint16_t S_UART_ReceiveData() } -FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_FLAG) +FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_STATE) { FlagStatus bitstatus = RESET; - assert_param(IS_S_UART_FLAG(S_UART_FLAG)); + assert_param(IS_S_UART_STATE(S_UART_STATE)); - if ((UART2->STATE & S_UART_FLAG) != (uint16_t)RESET) + if ((UART2->STATE & S_UART_STATE) != (FlagStatus)RESET) { bitstatus = SET; } @@ -266,28 +270,40 @@ FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_FLAG) return bitstatus; } - -void S_UART_ITConfig(uint16_t S_UART_IT, FunctionalState NewState) +void S_UART_SetCTRL(uint16_t S_UART_CTRL, FunctionalState NewState) { - assert_param(IS_S_UART_IT_FLAG(S_UART_IT)); + if ( NewState != DISABLE ) + { + UART2->CTRL |= S_UART_CTRL; + } + else + { + UART2->CTRL &= ~(S_UART_CTRL); + } +} + + +void S_UART_ITConfig(uint16_t S_UART_CTRL, FunctionalState NewState) +{ + assert_param(IS_S_UART_CTRL_FLAG(S_UART_CTRL)); if ( NewState != DISABLE ) { - UART2->CTRL |= S_UART_IT; + UART2->CTRL |= S_UART_CTRL; } else { - UART2->CTRL &= ~(S_UART_IT); + UART2->CTRL &= ~(S_UART_CTRL); } } -ITStatus S_UART_GetITStatus(uint16_t S_UART_IT) +ITStatus S_UART_GetITStatus(uint16_t S_UART_INTSTATUS) { ITStatus bitstatus = RESET; - assert_param(IS_S_UART_IT_FLAG(S_UART_IT)); + assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS)); - if ((UART2->INT.STATUS & (S_UART_IT >> 2)) != (uint16_t) RESET) + if ((UART2->INT.STATUS & (S_UART_INTSTATUS)) != (uint16_t) RESET) { bitstatus = SET; } @@ -299,11 +315,11 @@ ITStatus S_UART_GetITStatus(uint16_t S_UART_IT) return bitstatus; } -void S_UART_ClearITPendingBit(uint16_t S_UART_IT) +void S_UART_ClearITPendingBit(uint16_t S_UART_INTSTATUS) { - assert_param(IS_S_UART_IT_FLAG(S_UART_IT)); + assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS)); - UART2->INT.CLEAR |= (S_UART_IT >> 2); + UART2->INT.CLEAR |= (S_UART_INTSTATUS); } diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h index 791978b237..cc0b897b35 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h @@ -224,12 +224,32 @@ typedef struct /** @addtogroup S_UART_Flags * @{ */ -#define S_UART_FLAG_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */ -#define S_UART_FLAG_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */ -#define S_UART_FLAG_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */ -#define S_UART_FLAG_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */ -#define IS_S_UART_FLAG(FLAG) (((FLAG) == S_UART_FLAG_RXO) || ((FLAG) == S_UART_FLAG_TXO) || \ - ((FLAG) == S_UART_FLAG_RXF) || ((FLAG) == S_UART_FLAG_TXF)) +#define S_UART_STATE_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */ +#define S_UART_STATE_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */ +#define S_UART_STATE_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */ +#define S_UART_STATE_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */ +#define IS_S_UART_STATE(FLAG) (((FLAG) == S_UART_STATE_RXO) || ((FLAG) == S_UART_STATE_TXO) || \ + ((FLAG) == S_UART_STATE_RXF) || ((FLAG) == S_UART_STATE_TXF)) +/** + * @} + */ + + +/** @addtogroup S_UART_CTRL_Flags + * @{ + */ + +#define S_UART_CTRL_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */ +#define S_UART_CTRL_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */ +#define S_UART_CTRL_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */ +#define S_UART_CTRL_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */ +#define S_UART_CTRL_RX ((uint16_t)0x01UL << 1) /*!< RX */ +#define S_UART_CTRL_TX ((uint16_t)0x01UL << 0) /*!< TX */ + + +#define IS_S_UART_CTRL_FLAG(FLAG) (((FLAG) == S_UART_CTRL_FLAG_RXOI) || ((FLAG) == S_UART_CTRL_FLAG_TXOI) || \ + ((FLAG) == S_UART_CTRL_FLAG_RXI) || ((FLAG) == S_UART_CTRL_FLAG_TXI) || \ + ((FLAG) == S_UART_CTRL_FLAG_RX) || ((FLAG) == S_UART_CTRL_FLAG_TX)) /** * @} */ @@ -239,13 +259,12 @@ typedef struct * @{ */ -#define S_UART_IT_FLAG_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */ -#define S_UART_IT_FLAG_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */ -#define S_UART_IT_FLAG_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */ -#define S_UART_IT_FLAG_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */ -#define IS_S_UART_IT_FLAG(FLAG) (((FLAG) == S_UART_IT_FLAG_RXOI) || ((FLAG) == S_UART_IT_FLAG_TXOI) || \ - ((FLAG) == S_UART_IT_FLAG_RXI) || ((FLAG) == S_UART_IT_FLAG_TXI)) - +#define S_UART_INTSTATUS_RXOI ((uint16_t)0x01UL << 3) /*!< RX overrun interrupt */ +#define S_UART_INTSTATUS_TXOI ((uint16_t)0x01UL << 2) /*!< TX overrun interrupt */ +#define S_UART_INTSTATUS_RXI ((uint16_t)0x01UL << 1) /*!< RX interrupt */ +#define S_UART_INTSTATUS_TXI ((uint16_t)0x01UL << 0) /*!< TX interrupt */ +#define IS_S_UART_INTSTATUS(FLAG) (((FLAG) == S_UART_INTSTATUS_RXOI) || ((FLAG) == S_UART_INTSTATUS_TXOI) || \ + ((FLAG) == S_UART_INTSTATUS_RXI) || ((FLAG) == S_UART_INTSTATUS_TXI)) /** * @} */ @@ -263,21 +282,26 @@ void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, Func ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT); void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT); - -void S_UART_DeInit(void); -uint32_t S_UART_Init(uint32_t baud); -void S_UART_SendData(uint16_t Data); -uint16_t S_UART_ReceiveData(void); - - - uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch); void UartPuts (UART_TypeDef* UARTx, uint8_t *str); uint8_t UartGetc (UART_TypeDef* UARTx); -uint8_t S_UartPutc(uint8_t ch); -void S_UartPuts(uint8_t *str); -uint8_t S_UartGetc(void); +void S_UART_DeInit (void); +uint32_t S_UART_Init (uint32_t baud); +void S_UART_SetBaud (uint32_t baud); +void S_UART_SetCTRL (uint16_t S_UART_CTRL, FunctionalState NewState); +void S_UART_SendData (uint16_t Data); +uint16_t S_UART_ReceiveData(void); + +uint8_t S_UartPutc (uint8_t ch); +void S_UartPuts (uint8_t *str); +uint8_t S_UartGetc (void); + +FlagStatus S_UART_GetFlagStatus (uint16_t S_UART_STATE); +void S_UART_ITConfig (uint16_t S_UART_CTRL, FunctionalState NewState); + +ITStatus S_UART_GetITStatus (uint16_t S_UART_IT); +void S_UART_ClearITPendingBit(uint16_t S_UART_IT); #ifdef __cplusplus diff --git a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c index ab29cd73f9..ec4fbb6292 100644 --- a/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c @@ -39,9 +39,9 @@ #include "PeripheralPins.h" #include "W7500x_uart.h" -#define UART_NUM (2) +#define UART_NUM (3) -static uint32_t serial_irq_ids[UART_NUM] = {0, 0}; +static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; static uart_irq_handler irq_handler; @@ -55,23 +55,46 @@ serial_t stdio_uart; static void init_uart(serial_t *obj) { - UART = (UART_TypeDef *)(obj->uart); - UART_InitStructure.UART_BaudRate = obj->baudrate; - UART_InitStructure.UART_WordLength = obj->databits; - UART_InitStructure.UART_StopBits = obj->stopbits; - UART_InitStructure.UART_Parity = obj->parity; - UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + if(obj->index == 2) // For UART2, It is simple UART. + { + SystemCoreClockUpdate(); + //S_UART_Init(obj->baudrate); + S_UART_SetCTRL((S_UART_CTRL_RX_EN|S_UART_CTRL_TX_EN), DISABLE); + S_UART_SetBaud(obj->baudrate); - - if (obj->pin_rx == NC) { - UART_InitStructure.UART_Mode = UART_Mode_Tx; - } else if (obj->pin_tx == NC) { - UART_InitStructure.UART_Mode = UART_Mode_Rx; - } else { - UART_InitStructure.UART_Mode = (UART_Mode_Rx | UART_Mode_Tx); + if(obj->pin_rx == NC) + { + S_UART_SetCTRL(S_UART_CTRL_TX_EN, ENABLE); + } + else if(obj->pin_tx == NC) + { + S_UART_SetCTRL(S_UART_CTRL_RX_EN, ENABLE); + } + else + { + S_UART_SetCTRL((S_UART_CTRL_TX_EN|S_UART_CTRL_RX_EN),ENABLE); + } } + else // For UART0 and UART1. + { + UART = (UART_TypeDef *)(obj->uart); + UART_InitStructure.UART_BaudRate = obj->baudrate; + UART_InitStructure.UART_WordLength = obj->databits; + UART_InitStructure.UART_StopBits = obj->stopbits; + UART_InitStructure.UART_Parity = obj->parity; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; - UART_Init(UART,&UART_InitStructure); + + if (obj->pin_rx == NC) { + UART_InitStructure.UART_Mode = UART_Mode_Tx; + } else if (obj->pin_tx == NC) { + UART_InitStructure.UART_Mode = UART_Mode_Rx; + } else { + UART_InitStructure.UART_Mode = (UART_Mode_Rx | UART_Mode_Tx); + } + + UART_Init(UART,&UART_InitStructure); + } } void serial_init(serial_t *obj, PinName tx, PinName rx) @@ -94,6 +117,10 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->index = 1; } + if (obj->uart == UART_2) { + obj->index = 2; + } + // Configure the UART pins pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); @@ -131,11 +158,8 @@ void serial_free(serial_t *obj) if (obj->uart == UART_1) { } - - - // Configure GPIOs -// pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); -// pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); + if (obj->uart == UART_2) { + } serial_irq_ids[obj->index] = 0; } @@ -195,6 +219,20 @@ static void uart_irq(UARTName name, int id) } } +static void uart2_irq() +{ + if(serial_irq_ids[2] != 0){ + if( S_UART_GetITStatus(S_UART_INTSTATUS_TXI) != RESET ){ + S_UART_ClearITPendingBit(S_UART_INTSTATUS_TXI); + irq_handler(serial_irq_ids[2], TxIrq); + } + if( S_UART_GetITStatus(S_UART_INTSTATUS_RXI) != RESET ) { + S_UART_ClearITPendingBit(S_UART_INTSTATUS_RXI); + irq_handler(serial_irq_ids[2], RxIrq); + } + } +} + #ifdef __cplusplus extern "C"{ #endif @@ -207,6 +245,11 @@ void UART1_Handler() { uart_irq(UART_1, 1); } + +void UART2_Handler() +{ + uart2_irq(); +} #ifdef __cplusplus } #endif @@ -222,28 +265,49 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { IRQn_Type irq_n = (IRQn_Type)0; - UART = (UART_TypeDef *)(obj->uart); - if (obj->uart == UART_0) { - irq_n = UART0_IRQn; + if (obj->uart == UART_2) + { + irq_n = UART2_IRQn; + + if (enable){ + if (irq == RxIrq){ + S_UART_ITConfig(S_UART_CTRL_RXI,ENABLE); + } else { + S_UART_ITConfig(S_UART_CTRL_TXI,ENABLE); + } + NVIC_ClearPendingIRQ(irq_n); + NVIC_EnableIRQ(irq_n); + } else { // disable + S_UART_ITConfig((S_UART_CTRL_RXI|S_UART_CTRL_TXI),DISABLE); + NVIC_DisableIRQ(irq_n); + } } - - if (obj->uart == UART_1) { - irq_n = UART1_IRQn; - } - - if (enable) { - if (irq == RxIrq) { - UART_ITConfig(UART,UART_IT_FLAG_RXI,ENABLE); - } else { // TxIrq - UART_ITConfig(UART,UART_IT_FLAG_TXI,ENABLE); + else + { + UART = (UART_TypeDef *)(obj->uart); + + if (obj->uart == UART_0) { + irq_n = UART0_IRQn; } - NVIC_ClearPendingIRQ(irq_n); - NVIC_EnableIRQ(irq_n); - } else { // disable - UART_ITConfig(UART,(UART_IT_FLAG_RXI|UART_IT_FLAG_TXI),DISABLE); - NVIC_DisableIRQ(irq_n); + if (obj->uart == UART_1) { + irq_n = UART1_IRQn; + } + + if (enable) { + if (irq == RxIrq) { + UART_ITConfig(UART,UART_IT_FLAG_RXI,ENABLE); + } else { // TxIrq + UART_ITConfig(UART,UART_IT_FLAG_TXI,ENABLE); + } + + NVIC_ClearPendingIRQ(irq_n); + NVIC_EnableIRQ(irq_n); + } else { // disable + UART_ITConfig(UART,(UART_IT_FLAG_RXI|UART_IT_FLAG_TXI),DISABLE); + NVIC_DisableIRQ(irq_n); + } } } @@ -253,36 +317,74 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) int serial_getc(serial_t *obj) { - UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); -// while(!serial_readable(obj)); - while(uart->FR & UART_FR_RXFE); + if (obj->uart == UART_2) + { + S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart); - return (uart->DR & 0xFF); + while( (uart->STATE & S_UART_STATE_RX_BUF_FULL) == 0 ); + return (uint16_t)(uart->DATA); + } + else + { + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + while(uart->FR & UART_FR_RXFE); + + return (uart->DR & 0xFF); + } } void serial_putc(serial_t *obj, int c) { - UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + if (obj->uart == UART_2) + { + S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart); - uart->DR = (uint32_t)(c & (uint16_t)0xFF); - while(uart->FR & UART_FR_BUSY); + while(uart->STATE & S_UART_STATE_TX_BUF_FULL); + uart->DATA = (uint32_t)(c & (uint16_t)0xFF); + } + else + { + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + + uart->DR = (uint32_t)(c & (uint16_t)0xFF); + while(uart->FR & UART_FR_BUSY); + } } int serial_readable(serial_t *obj) { int status; - UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); - // Check if data is received - status = ((uart->FR & UART_FR_RXFE) ? 0: 1); + + if (obj->uart == UART_2) + { + S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart); + status = ((uart->STATE & S_UART_STATE_RX_BUF_FULL) ? 1 : 0); + } + else + { + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + // Check if data is received + status = ((uart->FR & UART_FR_RXFE) ? 0: 1); + } + return status; } int serial_writable(serial_t *obj) { int status; - UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); - // Check if data is transmitted - status = ((uart->FR & UART_FR_BUSY) ? 0: 1); + + if (obj->uart == UART_2) + { + S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart); + status = ((uart->STATE & S_UART_STATE_TX_BUF_FULL) ? 0 : 1); + } + else + { + UART_TypeDef *uart = (UART_TypeDef *)(obj->uart); + // Check if data is transmitted + status = ((uart->FR & UART_FR_BUSY) ? 0: 1); + } return status; } diff --git a/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c b/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c index ee72285ce3..40b339d856 100644 --- a/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c +++ b/libraries/net/eth/lwip-eth/arch/TARGET_RZ_A1H/rza1_emac.c @@ -24,33 +24,38 @@ static void rza1_recv_task(void *arg) { struct eth_hdr *ethhdr; u16_t recv_size; struct pbuf *p; + int cnt; while (1) { sys_arch_sem_wait(&recv_ready_sem, 0); - recv_size = ethernet_receive(); - if (recv_size != 0) { - p = pbuf_alloc(PBUF_RAW, recv_size, PBUF_RAM); - if (p != NULL) { - (void)ethernet_read((char *)p->payload, p->len); - ethhdr = p->payload; - switch (htons(ethhdr->type)) { - case ETHTYPE_IP: - case ETHTYPE_ARP: + for (cnt = 0; cnt < 16; cnt++) { + recv_size = ethernet_receive(); + if (recv_size != 0) { + p = pbuf_alloc(PBUF_RAW, recv_size, PBUF_RAM); + if (p != NULL) { + (void)ethernet_read((char *)p->payload, p->len); + ethhdr = p->payload; + switch (htons(ethhdr->type)) { + case ETHTYPE_IP: + case ETHTYPE_ARP: #if PPPOE_SUPPORT - case ETHTYPE_PPPOEDISC: - case ETHTYPE_PPPOE: + case ETHTYPE_PPPOEDISC: + case ETHTYPE_PPPOE: #endif /* PPPOE_SUPPORT */ - /* full packet send to tcpip_thread to process */ - if (netif->input(p, netif) != ERR_OK) { - /* Free buffer */ + /* full packet send to tcpip_thread to process */ + if (netif->input(p, netif) != ERR_OK) { + /* Free buffer */ + pbuf_free(p); + } + break; + default: + /* Return buffer */ pbuf_free(p); - } - break; - default: - /* Return buffer */ - pbuf_free(p); - break; + break; + } } + } else { + break; } } } diff --git a/libraries/net/lwip/lwip-sys/arch/sys_arch.c b/libraries/net/lwip/lwip-sys/arch/sys_arch.c index 78f9827aa3..8eead45b27 100644 --- a/libraries/net/lwip/lwip-sys/arch/sys_arch.c +++ b/libraries/net/lwip/lwip-sys/arch/sys_arch.c @@ -285,7 +285,11 @@ void sys_sem_free(sys_sem_t *sem) {} * @return a new mutex */ err_t sys_mutex_new(sys_mutex_t *mutex) { #ifdef CMSIS_OS_RTX +#ifdef __MBED_CMSIS_RTOS_CA9 + memset(mutex->data, 0, sizeof(int32_t)*4); +#else memset(mutex->data, 0, sizeof(int32_t)*3); +#endif mutex->def.mutex = mutex->data; #endif mutex->id = osMutexCreate(&mutex->def); diff --git a/libraries/net/lwip/lwip-sys/arch/sys_arch.h b/libraries/net/lwip/lwip-sys/arch/sys_arch.h index 909532eb2f..620b734b30 100644 --- a/libraries/net/lwip/lwip-sys/arch/sys_arch.h +++ b/libraries/net/lwip/lwip-sys/arch/sys_arch.h @@ -40,8 +40,12 @@ typedef struct { osMutexId id; osMutexDef_t def; #ifdef CMSIS_OS_RTX +#ifdef __MBED_CMSIS_RTOS_CA9 + int32_t data[4]; +#else int32_t data[3]; #endif +#endif } sys_mutex_t; // === MAIL BOX === diff --git a/libraries/rtos/rtos/Mutex.h b/libraries/rtos/rtos/Mutex.h index 2a8a7fe4be..5275339113 100644 --- a/libraries/rtos/rtos/Mutex.h +++ b/libraries/rtos/rtos/Mutex.h @@ -57,8 +57,12 @@ private: osMutexId _osMutexId; osMutexDef_t _osMutexDef; #ifdef CMSIS_OS_RTX +#ifdef __MBED_CMSIS_RTOS_CA9 + int32_t _mutex_data[4]; +#else int32_t _mutex_data[3]; #endif +#endif }; } diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/HAL_CA.c b/libraries/rtos/rtx/TARGET_CORTEX_A/HAL_CA.c index 295a64fb87..b57b188fab 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/HAL_CA.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/HAL_CA.c @@ -91,18 +91,16 @@ void rt_init_stack (P_TCB p_TCB, FUNCP task_body) { static __inline U32 *rt_ret_regs (P_TCB p_TCB) { /* Get pointer to task return value registers (R0..R3) in Stack */ -#if (__TARGET_FPU_VFP) - if (p_TCB->stack_frame & 0x2) { - /* Extended Stack Frame: S0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */ - return (U32 *)(p_TCB->tsk_stack + 8*4 + 34*4); + if (p_TCB->stack_frame & 0x4) { + /* NEON/D32 Stack Frame: D0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */ + return (U32 *)(p_TCB->tsk_stack + 8*4 + 2*4 + 32*8); + } else if (p_TCB->stack_frame & 0x2) { + /* VFP/D16 Stack Frame: D0-D15/S0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */ + return (U32 *)(p_TCB->tsk_stack + 8*4 + 2*4 + 32*4); } else { /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */ return (U32 *)(p_TCB->tsk_stack + 8*4); } -#else - /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */ - return (U32 *)(p_TCB->tsk_stack + 8*4); -#endif } void rt_ret_val (P_TCB p_TCB, U32 v0) { diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h index 3d95aac0cc..13cee6613f 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RTX_CM_LIB.H * Purpose: RTX Kernel System Configuration - * Rev.: V4.60 + * Rev.: V4.73 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -50,14 +50,14 @@ #define _declare_box(pool,size,cnt) uint32_t pool[(((size)+3)/4)*(cnt) + 3] #define _declare_box8(pool,size,cnt) uint64_t pool[(((size)+7)/8)*(cnt) + 2] -#define OS_TCB_SIZE 48 +#define OS_TCB_SIZE 52 #define OS_TMR_SIZE 8 #if defined (__CC_ARM) && !defined (__MICROLIB) typedef void *OS_ID; typedef uint32_t OS_TID; -typedef uint32_t OS_MUT[3]; +typedef uint32_t OS_MUT[4]; typedef uint32_t OS_RESULT; #define runtask_id() rt_tsk_self() @@ -104,10 +104,15 @@ uint32_t const os_stackinfo = (OS_STKCHECK<<24)| (OS_IDLESTKSIZE*4); uint32_t const os_stackinfo = (OS_STKCHECK<<24)| (OS_PRIV_CNT<<16) | (OS_STKSIZE*4); #endif uint32_t const os_rrobin = (OS_ROBIN << 16) | OS_ROBINTOUT; +uint32_t const os_tickfreq = OS_CLOCK; +uint16_t const os_tickus_i = OS_CLOCK/1000000; +uint16_t const os_tickus_f = (((uint64_t)(OS_CLOCK-1000000*(OS_CLOCK/1000000)))<<16)/1000000; uint32_t const os_trv = OS_TRV; uint8_t const os_flags = OS_RUNPRIV; /* Export following defines to uVision debugger. */ +__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS; +__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX; __USED uint32_t const os_clockrate = OS_TICK; __USED uint32_t const os_timernum = 0; @@ -258,7 +263,6 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 1, 4*OS_ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 1, 4*OS_MAINSTKSIZE }; #endif - #if defined (__CC_ARM) #ifdef __MICROLIB diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Config.h b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Config.h index 9b42ab48ea..054ca65ef4 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Config.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/RTX_Config.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RTX_CONFIG.H * Purpose: Exported functions of RTX_Config.c - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -67,6 +67,8 @@ extern U8 const os_fifo_size; /* Functions */ extern void os_idle_demon (void); extern int os_tick_init (void); +extern U32 os_tick_val (void); +extern U32 os_tick_ovf (void); extern void os_tick_irqack (void); extern void os_tmr_call (U16 info); extern void os_error (U32 err_code); diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c index eaca180825..526b3570d1 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: HAL_CA9.c * Purpose: Hardware Abstraction Layer for Cortex-A9 - * Rev.: 3 Sept 2013 + * Rev.: 8 April 2015 *---------------------------------------------------------------------------- * - * Copyright (c) 2012 - 2013 ARM Limited + * Copyright (c) 2012 - 2015 ARM Limited * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -114,6 +114,7 @@ __asm void SVC_Handler (void) { IMPORT SVC_Table IMPORT rt_stk_check IMPORT FPUEnable + IMPORT scheduler_suspended ; flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler Mode_SVC EQU 0x13 @@ -159,7 +160,7 @@ Mode_SVC EQU 0x13 /* Here we will be in SVC mode (even if coming in from PendSV_Handler or OS_Tick_Handler) */ Sys_Switch LDR LR,=__cpp(&os_tsk) - LDM LR,{R4,LR} ; os_tsk.run, os_tsk.new + LDM LR,{R4,LR} ; os_tsk.run, os_tsk.new_tsk CMP R4,LR BNE switching @@ -170,7 +171,13 @@ Sys_Switch PUSH {R12, LR} ; Store stack adjustment and dummy LR to SVC stack CPSID i + ; Do not unlock scheduler if it has just been suspended by rt_suspend() + LDR R1,=scheduler_suspended + LDRB R0, [R1] + CMP R0, #1 + BEQ dont_unlock BLX rt_tsk_unlock +dont_unlock POP {R12, LR} ; Get stack adjustment & discard dummy LR ADD SP, SP, R12 ; Unadjust stack @@ -188,7 +195,7 @@ switching PUSH {R8-R11} //R4 and LR already stacked MOV R10,R4 ; Preserve os_tsk.run - MOV R11,LR ; Preserve os_tsk.new + MOV R11,LR ; Preserve os_tsk.new_tsk ADD R8,SP,#16 ; Unstack R4,LR LDMIA R8,{R4,LR} @@ -204,21 +211,22 @@ switching SUB R8,R8,#4 ; No writeback for store of User LR STMDB R8!,{R0-R3,R12} ; User R0-R3,R12 MOV R3,R10 ; os_tsk.run - MOV LR,R11 ; os_tsk.new + MOV LR,R11 ; os_tsk.new_tsk POP {R9-R12} ADD SP,SP,#12 ; Fix up SP for unstack of R4, LR & SPSR STMDB R8!,{R4-R7,R9-R12} ; User R4-R11 - //If applicable, stack VFP state + //If applicable, stack VFP/NEON state MRC p15,0,R1,c1,c0,2 ; VFP/NEON access enabled? (CPACR) AND R2,R1,#0x00F00000 CMP R2,#0x00F00000 BNE no_outgoing_vfp VMRS R2,FPSCR STMDB R8!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment - VSTMDB R8!,{S0-S31} - LDRB R2,[R3,#TCB_STACKF] ; Record in TCB that VFP state is stacked - ORR R2,#2 + VSTMDB R8!,{D0-D15} + VSTMDB R8!,{D16-D31} + LDRB R2,[R3,#TCB_STACKF] ; Record in TCB that NEON/D32 state is stacked + ORR R2,#4 STRB R2,[R3,#TCB_STACKF] no_outgoing_vfp @@ -238,8 +246,8 @@ no_outgoing_vfp MOV LR,R4 -SVC_Next //R4 == os_tsk.run, LR == os_tsk.new, R0-R3, R5-R12 corruptible - LDR R1,=__cpp(&os_tsk) ; os_tsk.run = os_tsk.new +SVC_Next //R4 == os_tsk.run, LR == os_tsk.new_tsk, R0-R3, R5-R12 corruptible + LDR R1,=__cpp(&os_tsk) ; os_tsk.run = os_tsk.new_tsk STR LR,[R1] LDRB R1,[LR,#TCB_TID] ; os_tsk.run->task_id LSL R1,#8 ; Store PROCID @@ -247,16 +255,17 @@ SVC_Next //R4 == os_tsk.run, LR == os_tsk.new, R0-R3, R5-R12 corruptible LDR R0,[LR,#TCB_TSTACK] ; os_tsk.run->tsk_stack - //Does incoming task have VFP state in stack? + //Does incoming task have VFP/NEON state in stack? LDRB R3,[LR,#TCB_STACKF] - TST R3,#0x2 + ANDS R3, R3, #0x6 MRC p15,0,R1,c1,c0,2 ; Read CPACR - ANDEQ R1,R1,#0xFF0FFFFF ; Disable VFP access if incoming task does not have stacked VFP state - ORRNE R1,R1,#0x00F00000 ; Enable VFP access if incoming task does have stacked VFP state + ANDEQ R1,R1,#0xFF0FFFFF ; Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state + ORRNE R1,R1,#0x00F00000 ; Enable VFP/NEON access if incoming task does have stacked VFP/NEON state MCR p15,0,R1,c1,c0,2 ; Write CPACR BEQ no_incoming_vfp - ISB ; We only need the sync if we enabled, otherwise we will context switch before next VFP instruction anyway - VLDMIA R0!,{S0-S31} + ISB ; We only need the sync if we enabled, otherwise we will context switch before next VFP/NEON instruction anyway + VLDMIA R0!,{D16-D31} + VLDMIA R0!,{D0-D15} LDR R2,[R0] VMSR FPSCR,R2 ADD R0,R0,#8 @@ -343,7 +352,8 @@ __asm void PendSV_Handler (U32 IRQn) { ARM IMPORT rt_tsk_lock - IMPORT IRQNestLevel + IMPORT IRQNestLevel ; Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR. + IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment) @@ -355,6 +365,11 @@ __asm void PendSV_Handler (U32 IRQn) { LDR R1, [R1, #0] STR R0, [R1, #0x10] + ; If it was interrupt ID0, clear the seen flag, otherwise return as normal + CMP R0, #0 + LDREQ R1, =seen_id0_active + STRBEQ R0, [R1] ; Clear the seen flag, using R0 (which is 0), to save loading another register + LDR R0, =IRQNestLevel ; Get address of nesting counter LDR R1, [R0] SUB R1, R1, #1 ; Decrement nesting counter @@ -380,7 +395,8 @@ __asm void OS_Tick_Handler (U32 IRQn) { ARM IMPORT rt_tsk_lock - IMPORT IRQNestLevel + IMPORT IRQNestLevel ; Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR. + IMPORT seen_id0_active ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment) @@ -391,6 +407,11 @@ __asm void OS_Tick_Handler (U32 IRQn) { LDR R1, [R1, #0] STR R0, [R1, #0x10] + ; If it was interrupt ID0, clear the seen flag, otherwise return as normal + CMP R0, #0 + LDREQ R1, =seen_id0_active + STRBEQ R0, [R1] ; Clear the seen flag, using R0 (which is 0), to save loading another register + LDR R0, =IRQNestLevel ; Get address of nesting counter LDR R1, [R0] SUB R1, R1, #1 ; Decrement nesting counter diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S index 1c1ddc91bb..931ffeb856 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S @@ -3,10 +3,10 @@ ; *---------------------------------------------------------------------------- ; * Name: SVC_TABLE.S ; * Purpose: Pre-defined SVC Table for Cortex-M -; * Rev.: V4.60 +; * Rev.: V4.70 ; *---------------------------------------------------------------------------- ; * -; * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH +; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH ; * All rights reserved. ; * Redistribution and use in source and binary forms, with or without ; * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/HAL_CA9.S b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/HAL_CA9.S index c0e9836c7e..ae2e761636 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/HAL_CA9.S +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/HAL_CA9.S @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: HAL_CA9.c * Purpose: Hardware Abstraction Layer for Cortex-A9 - * Rev.: 3 Sept 2013 + * Rev.: 8 April 2015 *---------------------------------------------------------------------------- * - * Copyright (c) 2012 - 2013 ARM Limited + * Copyright (c) 2012 - 2015 ARM Limited * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -36,9 +36,11 @@ .global rt_get_PSP .global _alloc_box .global _free_box + .global SVC_Handler .global PendSV_Handler .global OS_Tick_Handler +/* macro defines form rt_HAL_CA.h */ .EQU CPSR_T_BIT, 0x20 .EQU CPSR_I_BIT, 0x80 .EQU CPSR_F_BIT, 0x40 @@ -51,9 +53,11 @@ .EQU MODE_UND, 0x1B .EQU MODE_SYS, 0x1F +/* macro defines form rt_TypeDef.h */ .EQU TCB_TID, 3 /* 'task id' offset */ - .EQU TCB_STACKF, 32 /* 'stack_frame' offset */ - .EQU TCB_TSTACK, 36 /* 'tsk_stack' offset */ + .EQU TCB_STACKF, 37 /* 'stack_frame' offset */ + .EQU TCB_TSTACK, 44 /* 'tsk_stack' offset for LARGE_STACK */ + .extern rt_alloc_box .extern os_tsk @@ -62,14 +66,16 @@ .extern os_tick_irqack .extern rt_systick + .text + /*---------------------------------------------------------------------------- * Functions *---------------------------------------------------------------------------*/ - .text + @ For A-class, set USR/SYS stack @ __asm void rt_set_PSP (U32 stack) { rt_set_PSP: - .arm + .ARM MRS R1, CPSR CPS #MODE_SYS @no effect in USR mode @@ -84,7 +90,7 @@ rt_set_PSP: @ For A-class, get USR/SYS stack @ __asm U32 rt_get_PSP (void) { rt_get_PSP: - .arm + .ARM MRS R1, CPSR CPS #MODE_SYS @no effect in USR mode @@ -93,16 +99,15 @@ rt_get_PSP: MSR CPSR_c, R1 @no effect in USR mode ISB BX LR - @ } /*--------------------------- _alloc_box ------------------------------------*/ @ __asm void *_alloc_box (void *box_mem) { _alloc_box: /* Function wrapper for Unprivileged/Privileged mode. */ - .arm + .ARM - LDR R12,=rt_alloc_box @ __cpp(rt_alloc_box) + LDR R12,=rt_alloc_box MRS R2, CPSR LSLS R2, #28 BXNE R12 @@ -115,9 +120,9 @@ _alloc_box: @ __asm int _free_box (void *box_mem, void *box) { _free_box: /* Function wrapper for Unprivileged/Privileged mode. */ - .arm + .ARM - LDR R12,=rt_free_box @ __cpp(rt_free_box) + LDR R12,=rt_free_box MRS R2, CPSR LSLS R2, #28 BXNE R12 @@ -131,25 +136,23 @@ _free_box: @ #pragma push @ #pragma arm @ __asm void SVC_Handler (void) { - - .type SVC_Handler, %function - .global SVC_Handler SVC_Handler: -@ PRESERVE8 - .arm + .eabi_attribute Tag_ABI_align8_preserved,1 + .ARM + .extern rt_tsk_lock .extern rt_tsk_unlock .extern SVC_Count .extern SVC_Table .extern rt_stk_check .extern FPUEnable + .extern scheduler_suspended @ flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler .EQU Mode_SVC, 0x13 - SRSDB SP!, #Mode_SVC @ Push LR_SVC and SPRS_SVC onto SVC mode stack + SRSDB SP!, #Mode_SVC @ Push LR_SVC and SPRS_SVC onto SVC mode stack @ Use SRSDB because SRSFD isn't supported by GCC-ARM. PUSH {R4} @ Push R4 so we can use it as a temp - MRS R4,SPSR @ Get SPSR TST R4,#CPSR_T_BIT @ Check Thumb Bit LDRNEH R4,[LR,#-2] @ Thumb: Load Halfword @@ -188,8 +191,8 @@ SVC_Handler: /* Here we will be in SVC mode (even if coming in from PendSV_Handler or OS_Tick_Handler) */ Sys_Switch: - LDR LR,=os_tsk @ __cpp(&os_tsk) - LDM LR,{R4,LR} @ os_tsk.run, os_tsk.new + LDR LR,=os_tsk + LDM LR,{R4,LR} @ os_tsk.run, os_tsk.new_tsk CMP R4,LR BNE switching @@ -200,7 +203,13 @@ Sys_Switch: PUSH {R12, LR} @ Store stack adjustment and dummy LR to SVC stack CPSID i + @ Do not unlock scheduler if it has just been suspended by rt_suspend() + LDR R1,=scheduler_suspended + LDRB R0, [R1] + CMP R0, #1 + BEQ dont_unlock BLX rt_tsk_unlock +dont_unlock: POP {R12, LR} @ Get stack adjustment & discard dummy LR ADD SP, SP, R12 @ Unadjust stack @@ -218,7 +227,7 @@ switching: PUSH {R8-R11} @ R4 and LR already stacked MOV R10,R4 @ Preserve os_tsk.run - MOV R11,LR @ Preserve os_tsk.new + MOV R11,LR @ Preserve os_tsk.new_tsk ADD R8,SP,#16 @ Unstack R4,LR LDMIA R8,{R4,LR} @@ -234,21 +243,22 @@ switching: SUB R8,R8,#4 @ No writeback for store of User LR STMDB R8!,{R0-R3,R12} @ User R0-R3,R12 MOV R3,R10 @ os_tsk.run - MOV LR,R11 @ os_tsk.new + MOV LR,R11 @ os_tsk.new_tsk POP {R9-R12} ADD SP,SP,#12 @ Fix up SP for unstack of R4, LR & SPSR STMDB R8!,{R4-R7,R9-R12} @ User R4-R11 - @ If applicable, stack VFP state + @ If applicable, stack VFP/NEON state MRC p15,0,R1,c1,c0,2 @ VFP/NEON access enabled? (CPACR) AND R2,R1,#0x00F00000 CMP R2,#0x00F00000 BNE no_outgoing_vfp VMRS R2,FPSCR STMDB R8!,{R2,R4} @ Push FPSCR, maintain 8-byte alignment - VSTMDB R8!,{S0-S31} - LDRB R2,[R3,#TCB_STACKF] @ Record in TCB that VFP state is stacked - ORR R2,#2 + VSTMDB R8!,{D0-D15} + VSTMDB R8!,{D16-D31} + LDRB R2,[R3,#TCB_STACKF] @ Record in TCB that NEON/D32 state is stacked + ORR R2,#4 STRB R2,[R3,#TCB_STACKF] no_outgoing_vfp: @@ -268,8 +278,8 @@ no_outgoing_vfp: MOV LR,R4 -SVC_Next: @ R4 == os_tsk.run, LR == os_tsk.new, R0-R3, R5-R12 corruptible - LDR R1,=os_tsk @ __cpp(&os_tsk), os_tsk.run = os_tsk.new +SVC_Next: @ R4 == os_tsk.run, LR == os_tsk.new_tsk, R0-R3, R5-R12 corruptible + LDR R1,=os_tsk @ os_tsk.run = os_tsk.new_tsk STR LR,[R1] LDRB R1,[LR,#TCB_TID] @ os_tsk.run->task_id LSL R1,#8 @ Store PROCID @@ -277,16 +287,17 @@ SVC_Next: @ R4 == os_tsk.run, LR == os_tsk.new, R0-R3, R5-R12 corruptible LDR R0,[LR,#TCB_TSTACK] @ os_tsk.run->tsk_stack - @ Does incoming task have VFP state in stack? + @ Does incoming task have VFP/NEON state in stack? LDRB R3,[LR,#TCB_STACKF] - TST R3,#0x2 + ANDS R3, R3, #0x6 MRC p15,0,R1,c1,c0,2 @ Read CPACR - ANDEQ R1,R1,#0xFF0FFFFF @ Disable VFP access if incoming task does not have stacked VFP state - ORRNE R1,R1,#0x00F00000 @ Enable VFP access if incoming task does have stacked VFP state + ANDEQ R1,R1,#0xFF0FFFFF @ Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state + ORRNE R1,R1,#0x00F00000 @ Enable VFP/NEON access if incoming task does have stacked VFP/NEON state MCR p15,0,R1,c1,c0,2 @ Write CPACR BEQ no_incoming_vfp - ISB @ We only need the sync if we enabled, otherwise we will context switch before next VFP instruction anyway - VLDMIA R0!,{S0-S31} + ISB @ We only need the sync if we enabled, otherwise we will context switch before next VFP/NEON instruction anyway + VLDMIA R0!,{D16-D31} + VLDMIA R0!,{D0-D15} LDR R2,[R0] VMSR FPSCR,R2 ADD R0,R0,#8 @@ -364,20 +375,18 @@ SVC_Done: POP {R0-R3,R12,LR} POP {R4} RFEFD SP! @ Return from exception - @ } - @ #pragma pop - @ #pragma push @ #pragma arm @ __asm void PendSV_Handler (U32 IRQn) { PendSV_Handler: - .arm + .ARM .extern rt_tsk_lock - .extern IRQNestLevel + .extern IRQNestLevel @ Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR. + .extern seen_id0_active @ Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s ADD SP,SP,#8 @ fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment) @@ -385,16 +394,21 @@ PendSV_Handler: PUSH {R0, R1} BLX rt_tsk_lock POP {R0, R1} - LDR R1, =GICInterface_BASE @ __cpp(&GICInterface_BASE) + LDR R1, =GICInterface_BASE LDR R1, [R1, #0] STR R0, [R1, #0x10] + @ If it was interrupt ID0, clear the seen flag, otherwise return as normal + CMP R0, #0 + LDREQ R1, =seen_id0_active + STREQB R0, [R1] @ Clear the seen flag, using R0 (which is 0), to save loading another register + LDR R0, =IRQNestLevel @ Get address of nesting counter LDR R1, [R0] SUB R1, R1, #1 @ Decrement nesting counter STR R1, [R0] - BLX rt_pop_req @ __cpp(rt_pop_req) + BLX rt_pop_req POP {R1, LR} @ Get stack adjustment & discard dummy LR ADD SP, SP, R1 @ Unadjust stack @@ -407,28 +421,38 @@ PendSV_Handler: @ } @ #pragma pop + @ #pragma push @ #pragma arm @ __asm void OS_Tick_Handler (U32 IRQn) { OS_Tick_Handler: - .arm + .ARM + + .extern rt_tsk_lock + .extern IRQNestLevel @ Flag indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR. + .extern seen_id0_active @ Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s ADD SP,SP,#8 @ fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment) PUSH {R0, R1} BLX rt_tsk_lock POP {R0, R1} - LDR R1, =GICInterface_BASE @ __cpp(&GICInterface_BASE) + LDR R1, =GICInterface_BASE LDR R1, [R1, #0] STR R0, [R1, #0x10] + @ If it was interrupt ID0, clear the seen flag, otherwise return as normal + CMP R0, #0 + LDREQ R1, =seen_id0_active + STREQB R0, [R1] @ Clear the seen flag, using R0 (which is 0), to save loading another register + LDR R0, =IRQNestLevel @ Get address of nesting counter LDR R1, [R0] SUB R1, R1, #1 @ Decrement nesting counter STR R1, [R0] - BLX os_tick_irqack @ __cpp(os_tick_irqack) - BLX rt_systick @ __cpp(rt_systick) + BLX os_tick_irqack + BLX rt_systick POP {R1, LR} @ Get stack adjustment & discard dummy LR ADD SP, SP, R1 @ Unadjust stack @@ -441,32 +465,6 @@ OS_Tick_Handler: @ } @ #pragma pop - .global __set_PSP -@ __STATIC_ASM void __set_PSP(uint32_t topOfProcStack) -@ { -__set_PSP: -@ PRESERVE8 - .arm - - BIC R0, R0, #7 @ensure stack is 8-byte aligned - MRS R1, CPSR - CPS #MODE_SYS @no effect in USR mode - MOV SP, R0 - MSR CPSR_c, R1 @no effect in USR mode - ISB - BX LR - -@ } - - .global __set_CPS_USR -@ __STATIC_ASM void __set_CPS_USR(void) -@ { -__set_CPS_USR: - .arm - - CPS #MODE_USR - BX LR -@ } .END /*---------------------------------------------------------------------------- diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/SVC_Table.S b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/SVC_Table.S index 85c030f91e..77e48db867 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/SVC_Table.S +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_GCC/SVC_Table.S @@ -34,23 +34,20 @@ .section SVC_TABLE @, CODE, READONLY - .align 5 .global SVC_Count .EQU SVC_Cnt, (SVC_End-SVC_Table)/4 - -SVC_Count: - .word SVC_Cnt +SVC_Count: .word SVC_Cnt @ Import user SVC functions here. @ .extern __SVC_1 + .global SVC_Table SVC_Table: @ Insert user SVC functions here. SVC 0 used by RTL Kernel. @ .word __SVC_1 @ InitMemorySubsystem -@SVC_End SVC_End: .END diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h b/libraries/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h index 2d8ef23d88..ae679afa7f 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h @@ -1,6 +1,6 @@ /* ---------------------------------------------------------------------- - * $Date: 5. June 2012 - * $Revision: V1.01 + * $Date: 5. February 2013 + * $Revision: V1.02 * * Project: CMSIS-RTOS API * Title: cmsis_os.h RTX header file @@ -18,9 +18,13 @@ * - const attribute added to the osXxxxDef macros * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet *---------------------------------------------------------------------------- * - * Copyright (c) 2012 ARM LIMITED + * Copyright (c) 2013 ARM LIMITED * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -127,13 +131,13 @@ used throughout the whole project. #define _CMSIS_OS_H /// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. -#define osCMSIS 0x10001 ///< API version (main [31:16] .sub [15:0]) +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) /// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. -#define osCMSIS_RTX ((4<<16)|61) ///< RTOS identification and version (main [31:16] .sub [15:0]) +#define osCMSIS_RTX ((4<<16)|74) ///< RTOS identification and version (main [31:16] .sub [15:0]) /// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. -#define osKernelSystemId "RTX V4.61" ///< RTOS identification string +#define osKernelSystemId "RTX V4.74" ///< RTOS identification string #define CMSIS_OS_RTX #define CMSIS_OS_RTX_CA /* new define for Coretex-A */ @@ -155,6 +159,7 @@ used throughout the whole project. #define osFeature_Signals 16 ///< maximum number of Signal Flags available per thread #define osFeature_Semaphore 65535 ///< maximum count for \ref osSemaphoreCreate function #define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available #if defined (__CC_ARM) #define os_InRegs __value_in_regs // Compiler specific: force struct in registers @@ -345,6 +350,30 @@ osStatus osKernelStart (void); /// \return 0 RTOS is not started, 1 RTOS is started. int32_t osKernelRunning(void); +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +extern uint32_t const os_tickfreq; +extern uint16_t const os_tickus_i; +extern uint16_t const os_tickus_f; + +/// Get the RTOS kernel system timer counter. +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz. +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency os_tickfreq + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +/* +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) +*/ +#define osKernelSysTickMicroSec(microsec) ((microsec * os_tickus_i) + ((microsec * os_tickus_f) >> 16)) + +#endif // System Timer available // ==== Thread Management ==== @@ -504,12 +533,6 @@ int32_t osSignalSet (osThreadId thread_id, int32_t signals); /// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. int32_t osSignalClear (osThreadId thread_id, int32_t signals); -/// Get Signal Flags status of an active thread. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. -/// \note MUST REMAIN UNCHANGED: \b osSignalGet shall be consistent in every CMSIS-RTOS. -int32_t osSignalGet (osThreadId thread_id); - /// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. /// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. /// \param[in] millisec timeout value or 0 in case of no time-out. @@ -529,7 +552,7 @@ os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec); extern const osMutexDef_t os_mutex_def_##name #else // define the object #define osMutexDef(name) \ -uint32_t os_mutex_cb_##name[3]; \ +uint32_t os_mutex_cb_##name[4] = { 0 }; \ const osMutexDef_t os_mutex_def_##name = { (os_mutex_cb_##name) } #endif @@ -579,7 +602,7 @@ osStatus osMutexDelete (osMutexId mutex_id); extern const osSemaphoreDef_t os_semaphore_def_##name #else // define the object #define osSemaphoreDef(name) \ -uint32_t os_semaphore_cb_##name[2]; \ +uint32_t os_semaphore_cb_##name[2] = { 0 }; \ const osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) } #endif @@ -689,7 +712,7 @@ osStatus osPoolFree (osPoolId pool_id, void *block); extern const osMessageQDef_t os_messageQ_def_##name #else // define the object #define osMessageQDef(name, queue_sz, type) \ -uint32_t os_messageQ_q_##name[4+(queue_sz)]; \ +uint32_t os_messageQ_q_##name[4+(queue_sz)] = { 0 }; \ const osMessageQDef_t os_messageQ_def_##name = \ { (queue_sz), (os_messageQ_q_##name) } #endif @@ -741,7 +764,7 @@ os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); extern const osMailQDef_t os_mailQ_def_##name #else // define the object #define osMailQDef(name, queue_sz, type) \ -uint32_t os_mailQ_q_##name[4+(queue_sz)]; \ +uint32_t os_mailQ_q_##name[4+(queue_sz)] = { 0 }; \ uint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \ void * os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \ const osMailQDef_t os_mailQ_def_##name = \ @@ -800,6 +823,15 @@ osStatus osMailFree (osMailQId queue_id, void *mail); #endif // Mail Queues available +// ==== RTX Extensions ==== + +/// os_suspend: http://www.keil.com/support/man/docs/rlarm/rlarm_os_suspend.htm +uint32_t os_suspend (void); + +/// os_resume: http://www.keil.com/support/man/docs/rlarm/rlarm_os_resume.htm +void os_resume (uint32_t sleep_time); + + #ifdef __cplusplus } #endif diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c index b50aecc73e..5a132250a6 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: rt_CMSIS.c * Purpose: CMSIS RTOS API - * Rev.: V4.60 + * Rev.: V4.74 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -100,6 +100,14 @@ static __inline t __##f (void) { \ return _##f(f); \ } +#define SVC_1_0(f,t,t1,...) \ +__svc_indirect(0) t _##f (t(*)(t1),t1); \ + t f (t1 a1); \ +__attribute__((always_inline)) \ +static __inline t __##f (t1 a1) { \ + _##f(f,a1); \ +} + #define SVC_1_1(f,t,t1,...) \ __svc_indirect(0) t _##f (t(*)(t1),t1); \ t f (t1 a1); \ @@ -280,6 +288,13 @@ static inline t __##f (void) { \ return (t) rv; \ } +#define SVC_1_0(f,t,t1) \ +__attribute__((always_inline)) \ +static inline t __##f (t1 a1) { \ + SVC_Arg1(t1); \ + SVC_Call(f); \ +} + #define SVC_1_1(f,t,t1,rv) \ __attribute__((always_inline)) \ static inline t __##f (t1 a1) { \ @@ -353,6 +368,14 @@ static inline t __##f (void) { \ return _##f(); \ } +#define SVC_1_0(f,t,t1,...) \ +t f (t1 a1); \ +_Pragma("swi_number=0") __swi t _##f (t1 a1); \ +static inline t __##f (t1 a1) { \ + SVC_Setup(f); \ + _##f(a1); \ +} + #define SVC_1_1(f,t,t1,...) \ t f (t1 a1); \ _Pragma("swi_number=0") __swi t _##f (t1 a1); \ @@ -539,6 +562,7 @@ uint8_t os_running; // Kernel Running flag SVC_0_1(svcKernelInitialize, osStatus, RET_osStatus) SVC_0_1(svcKernelStart, osStatus, RET_osStatus) SVC_0_1(svcKernelRunning, int32_t, RET_int32_t) +SVC_0_1(svcKernelSysTick, uint32_t, RET_uint32_t) static void sysThreadError (osStatus status); osThreadId svcThreadCreate (const osThreadDef_t *thread_def, void *argument); @@ -577,6 +601,7 @@ osStatus svcKernelInitialize (void) { sysThreadError(osOK); os_initialized = 1; + os_running = 0; return osOK; } @@ -586,8 +611,10 @@ osStatus svcKernelStart (void) { if (os_running) return osOK; - rt_tsk_prio(0, 0); // Lowest priority - __set_PSP(os_tsk.run->tsk_stack + 8*4); // New context + rt_tsk_prio(0, os_tsk.run->prio_base); // Restore priority + if (os_tsk.run->task_id == 0xFF) { // Idle Thread + __set_PSP(os_tsk.run->tsk_stack + 8*4); // Setup PSP + } os_tsk.run = NULL; // Force context switch rt_sys_start(); @@ -602,6 +629,22 @@ int32_t svcKernelRunning(void) { return os_running; } +/// Get the RTOS kernel system timer counter +uint32_t svcKernelSysTick (void) { + uint32_t tick, tick0; + + tick = os_tick_val(); + if (os_tick_ovf()) { + tick0 = os_tick_val(); + if (tick0 < tick) tick = tick0; + tick += (os_trv + 1) * (os_time + 1); + } else { + tick += (os_trv + 1) * os_time; + } + + return tick; +} + // Kernel Control Public API /// Initialize the RTOS Kernel for creating objects @@ -642,6 +685,12 @@ int32_t osKernelRunning(void) { } } +/// Get the RTOS kernel system timer counter +uint32_t osKernelSysTick (void) { + if (__exceptional_mode()) return 0; // Not allowed in ISR + return __svcKernelSysTick(); +} + // ==== Thread Management ==== @@ -1047,6 +1096,7 @@ osTimerId svcTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, voi return NULL; } + pt->next = NULL; pt->state = osTimerStopped; pt->type = (uint8_t)type; pt->arg = argument; @@ -1176,6 +1226,30 @@ void sysTimerTick (void) { } } +/// Get user timers wake-up time +uint32_t sysUserTimerWakeupTime (void) { + + if (os_timer_head) { + return os_timer_head->tcnt; + } + return 0xFFFF; +} + +/// Update user timers on resume +void sysUserTimerUpdate (uint32_t sleep_time) { + + while (os_timer_head && sleep_time) { + if (sleep_time >= os_timer_head->tcnt) { + sleep_time -= os_timer_head->tcnt; + os_timer_head->tcnt = 1; + sysTimerTick(); + } else { + os_timer_head->tcnt -= sleep_time; + break; + } + } +} + // Timer Management Public API @@ -1237,7 +1311,6 @@ __NO_RETURN void osTimerThread (void const *argument) { // Signal Service Calls declarations SVC_2_1(svcSignalSet, int32_t, osThreadId, int32_t, RET_int32_t) SVC_2_1(svcSignalClear, int32_t, osThreadId, int32_t, RET_int32_t) -SVC_1_1(svcSignalGet, int32_t, osThreadId, RET_int32_t) SVC_2_3(svcSignalWait, os_InRegs osEvent, int32_t, uint32_t, RET_osEvent) // Signal Service Calls @@ -1276,16 +1349,6 @@ int32_t svcSignalClear (osThreadId thread_id, int32_t signals) { return sig; } -/// Get Signal Flags status of an active thread -int32_t svcSignalGet (osThreadId thread_id) { - P_TCB ptcb; - - ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer - if (ptcb == NULL) return 0x80000000; - - return ptcb->events; // Return event flags -} - /// Wait for one or more Signal Flags to become signaled for the current RUNNING thread os_InRegs osEvent_type svcSignalWait (int32_t signals, uint32_t millisec) { OS_RESULT res; @@ -1361,12 +1424,6 @@ int32_t osSignalClear (osThreadId thread_id, int32_t signals) { return __svcSignalClear(thread_id, signals); } -/// Get Signal Flags status of an active thread -int32_t osSignalGet (osThreadId thread_id) { - if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR - return __svcSignalGet(thread_id); -} - /// Wait for one or more Signal Flags to become signaled for the current RUNNING thread os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) { osEvent ret; @@ -1960,7 +2017,6 @@ osMailQId svcMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) { rt_mbx_init(pmcb, 4*(queue_def->queue_sz + 4)); - return queue_def->pool; } @@ -2020,7 +2076,7 @@ osStatus sysMailFree (osMailQId queue_id, void *mail, uint32_t isr) { if (res != 0) return osErrorValue; - if (pmcb->state == 3) { + if ((pmcb->p_lnk != NULL) && (pmcb->state == 3)) { // Task is waiting to allocate a message if (isr) { rt_psq_enq (pmcb, (U32)pool); @@ -2029,9 +2085,6 @@ osStatus sysMailFree (osMailQId queue_id, void *mail, uint32_t isr) { mem = rt_alloc_box(pool); if (mem != NULL) { ptcb = rt_get_first((P_XCB)pmcb); - if (pmcb->p_lnk == NULL) { - pmcb->state = 0; - } rt_ret_val(ptcb, (U32)mem); rt_rmv_dly(ptcb); rt_dispatch(ptcb); @@ -2111,3 +2164,23 @@ os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { #ifdef __CC_ARM #pragma pop #endif // __arm__ + + +// ==== RTX Extensions ==== + +// Service Calls declarations +SVC_0_1(rt_suspend, uint32_t, RET_uint32_t) +SVC_1_0(rt_resume, void, uint32_t) + + +// Public API + +/// Suspends the OS task scheduler +uint32_t os_suspend (void) { + return __rt_suspend(); +} + +/// Resumes the OS task scheduler +void os_resume (uint32_t sleep_time) { + __rt_resume(sleep_time); +} diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Event.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Event.c index 1ea088fad7..c9e85fd90a 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Event.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Event.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_EVENT.C * Purpose: Implements waits and wake-ups for event flags - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Event.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Event.h index 8b92f3c4c4..b21223ac5d 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Event.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Event.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_EVENT.H * Purpose: Implements waits and wake-ups for event flags - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h index 57d0cf13cb..1a5fdf5cc9 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h @@ -1,9 +1,9 @@ /*---------------------------------------------------------------------------- * RL-ARM - RTX *---------------------------------------------------------------------------- - * Name: RT_HAL_CM.H + * Name: RT_HAL_CA.H * Purpose: Hardware Abstraction Layer for Cortex-A definitions - * Rev.: 21 Aug 2013 + * Rev.: 14th Jan 2014 *---------------------------------------------------------------------------- * * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH @@ -169,6 +169,18 @@ __inline static void rt_systick_init (void) { /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */ } +__inline static U32 rt_systick_val (void) { + /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */ + /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */ + return 0; +} + +__inline static U32 rt_systick_ovf (void) { + /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */ + /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */ + return 0; +} + __inline static void rt_svc_init (void) { /* Register pendSV - through SGI */ volatile char *reg; diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h index eade36dcd2..2c989928ff 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_HAL_CM.H * Purpose: Hardware Abstraction Layer for Cortex-M definitions - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -40,7 +40,7 @@ #if defined (__CC_ARM) /* ARM Compiler */ -#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS) +#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !defined(NO_EXCLUSIVE_ACCESS)) #define __USE_EXCLUSIVE_ACCESS #else #undef __USE_EXCLUSIVE_ACCESS @@ -228,6 +228,14 @@ __inline static void rt_systick_init (void) { NVIC_SYS_PRI3 |= 0xFF000000; } +__inline static U32 rt_systick_val (void) { + return (os_trv - NVIC_ST_CURRENT); +} + +__inline static U32 rt_systick_ovf (void) { + return ((NVIC_INT_CTRL >> 26) & 1); +} + __inline static void rt_svc_init (void) { #if !(__TARGET_ARCH_6S_M) int sh,prigroup; @@ -262,7 +270,7 @@ extern void dbg_task_switch (U32 task_id); #ifdef DBG_MSG #define DBG_INIT() dbg_init() #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create) -#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new!=os_tsk.run)) \ +#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk!=os_tsk.run)) \ dbg_task_switch(task_id) #else #define DBG_INIT() diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_List.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_List.c index 7dede12b31..51c7be1966 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_List.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_List.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_LIST.C * Purpose: Functions for the management of different lists - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_List.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_List.h index cb3008e713..510ca7a70a 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_List.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_List.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_LIST.H * Purpose: Functions for the management of different lists - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c index 81a00b9b70..a32f08c731 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_MAILBOX.C * Purpose: Implements waits and wake-ups for mailbox messages - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h index 0c8e2f39b2..29997bb06b 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_MAILBOX.H * Purpose: Implements waits and wake-ups for mailbox messages - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c index ad5ced1ee3..5d0388ebbf 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_MEMBOX.C * Purpose: Interface functions for fixed memory block management system - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h index c10a1cbe70..755190a5cc 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_MEMBOX.H * Purpose: Interface functions for fixed memory block management system - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Memory.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Memory.c index f6499fb736..008ae4c42c 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Memory.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Memory.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_MEMORY.C * Purpose: Interface functions for Dynamic Memory Management System - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Memory.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Memory.h index 28466cbafc..ceafa40f38 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Memory.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Memory.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_MEMORY.H * Purpose: Interface functions for Dynamic Memory Management System - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c index 4b2fbf87c7..d3ba4d964d 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_MUTEX.C * Purpose: Implements mutex synchronization objects - * Rev.: V4.60 + * Rev.: V4.73 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -56,10 +56,10 @@ void rt_mut_init (OS_ID mutex) { P_MUCB p_MCB = mutex; p_MCB->cb_type = MUCB; - p_MCB->prio = 0; p_MCB->level = 0; p_MCB->p_lnk = NULL; p_MCB->owner = NULL; + p_MCB->p_mlnk = NULL; } @@ -70,14 +70,47 @@ OS_RESULT rt_mut_delete (OS_ID mutex) { /* Delete a mutex object */ P_MUCB p_MCB = mutex; P_TCB p_TCB; + P_MUCB p_mlnk; + U8 prio; __DMB(); /* Restore owner task's priority. */ if (p_MCB->level != 0) { - p_MCB->owner->prio = p_MCB->prio; - if (p_MCB->owner != os_tsk.run) { - rt_resort_prio (p_MCB->owner); + + p_TCB = p_MCB->owner; + + /* Remove mutex from task mutex owner list. */ + p_mlnk = p_TCB->p_mlnk; + if (p_mlnk == p_MCB) { + p_TCB->p_mlnk = p_MCB->p_mlnk; } + else { + while (p_mlnk) { + if (p_mlnk->p_mlnk == p_MCB) { + p_mlnk->p_mlnk = p_MCB->p_mlnk; + break; + } + p_mlnk = p_mlnk->p_mlnk; + } + } + + /* Restore owner task's priority. */ + prio = p_TCB->prio_base; + p_mlnk = p_TCB->p_mlnk; + while (p_mlnk) { + if (p_mlnk->p_lnk && (p_mlnk->p_lnk->prio > prio)) { + /* A task with higher priority is waiting for mutex. */ + prio = p_mlnk->p_lnk->prio; + } + p_mlnk = p_mlnk->p_mlnk; + } + if (p_TCB->prio != prio) { + p_TCB->prio = prio; + if (p_TCB != os_tsk.run) { + rt_resort_prio (p_TCB); + } + } + } while (p_MCB->p_lnk != NULL) { @@ -109,6 +142,8 @@ OS_RESULT rt_mut_release (OS_ID mutex) { /* Release a mutex object */ P_MUCB p_MCB = mutex; P_TCB p_TCB; + P_MUCB p_mlnk; + U8 prio; if (p_MCB->level == 0 || p_MCB->owner != os_tsk.run) { /* Unbalanced mutex release or task is not the owner */ @@ -118,8 +153,34 @@ OS_RESULT rt_mut_release (OS_ID mutex) { if (--p_MCB->level != 0) { return (OS_R_OK); } + + /* Remove mutex from task mutex owner list. */ + p_mlnk = os_tsk.run->p_mlnk; + if (p_mlnk == p_MCB) { + os_tsk.run->p_mlnk = p_MCB->p_mlnk; + } + else { + while (p_mlnk) { + if (p_mlnk->p_mlnk == p_MCB) { + p_mlnk->p_mlnk = p_MCB->p_mlnk; + break; + } + p_mlnk = p_mlnk->p_mlnk; + } + } + /* Restore owner task's priority. */ - os_tsk.run->prio = p_MCB->prio; + prio = os_tsk.run->prio_base; + p_mlnk = os_tsk.run->p_mlnk; + while (p_mlnk) { + if (p_mlnk->p_lnk && (p_mlnk->p_lnk->prio > prio)) { + /* A task with higher priority is waiting for mutex. */ + prio = p_mlnk->p_lnk->prio; + } + p_mlnk = p_mlnk->p_mlnk; + } + os_tsk.run->prio = prio; + if (p_MCB->p_lnk != NULL) { /* A task is waiting for mutex. */ p_TCB = rt_get_first ((P_XCB)p_MCB); @@ -132,7 +193,8 @@ OS_RESULT rt_mut_release (OS_ID mutex) { /* A waiting task becomes the owner of this mutex. */ p_MCB->level = 1; p_MCB->owner = p_TCB; - p_MCB->prio = p_TCB->prio; + p_MCB->p_mlnk = p_TCB->p_mlnk; + p_TCB->p_mlnk = p_MCB; /* Priority inversion, check which task continues. */ if (os_tsk.run->prio >= rt_rdy_prio()) { rt_dispatch (p_TCB); @@ -147,7 +209,7 @@ OS_RESULT rt_mut_release (OS_ID mutex) { } } else { - /* Check if own priority raised by priority inversion. */ + /* Check if own priority lowered by priority inversion. */ if (rt_rdy_prio() > os_tsk.run->prio) { rt_put_prio (&os_rdy, os_tsk.run); os_tsk.run->state = READY; @@ -166,7 +228,8 @@ OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout) { if (p_MCB->level == 0) { p_MCB->owner = os_tsk.run; - p_MCB->prio = os_tsk.run->prio; + p_MCB->p_mlnk = os_tsk.run->p_mlnk; + os_tsk.run->p_mlnk = p_MCB; goto inc; } if (p_MCB->owner == os_tsk.run) { @@ -181,7 +244,7 @@ inc:p_MCB->level++; } /* Raise the owner task priority if lower than current priority. */ /* This priority inversion is called priority inheritance. */ - if (p_MCB->prio < os_tsk.run->prio) { + if (p_MCB->owner->prio < os_tsk.run->prio) { p_MCB->owner->prio = os_tsk.run->prio; rt_resort_prio (p_MCB->owner); } diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h index bf15c4d56c..109e2d2baf 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_MUTEX.H * Purpose: Implements mutex synchronization objects - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Robin.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Robin.c index 66b1d89b65..e1653fbe12 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Robin.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Robin.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_ROBIN.C * Purpose: Round Robin Task switching - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Robin.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Robin.h index 3ccbffcffd..b043bb92d0 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Robin.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Robin.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_ROBIN.H * Purpose: Round Robin Task switching definitions - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c index 192fdbb13e..033f427ee9 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_SEMAPHORE.C * Purpose: Implements binary and counting semaphores - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -152,7 +152,7 @@ OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout) { /*--------------------------- isr_sem_send ----------------------------------*/ void isr_sem_send (OS_ID semaphore) { - /* Same function as "os_sem"send", but to be called by ISRs */ + /* Same function as "os_sem_send", but to be called by ISRs */ P_SCB p_SCB = semaphore; rt_psq_enq (p_SCB, 0); diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h index ec4548000b..b78ac9da45 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_SEMAPHORE.H * Purpose: Implements binary and counting semaphores - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_System.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_System.c index db8c32b02e..4cfa8c2d42 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_System.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_System.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_SYSTEM.C * Purpose: System Task Manager - * Rev.: V4.60 + * Rev.: 8 April 2015 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -54,6 +54,7 @@ *---------------------------------------------------------------------------*/ int os_tick_irqn; +U8 scheduler_suspended = 0; // flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler /*---------------------------------------------------------------------------- * Local Variables @@ -68,29 +69,40 @@ static U8 pend_flags; * Global Functions *---------------------------------------------------------------------------*/ +#define RL_RTX_VER 0x473 + #if defined (__CC_ARM) __asm void $$RTX$$version (void) { /* Export a version number symbol for a version control. */ EXPORT __RL_RTX_VER -__RL_RTX_VER EQU 0x450 +__RL_RTX_VER EQU RL_RTX_VER } #endif /*--------------------------- rt_suspend ------------------------------------*/ +extern U32 sysUserTimerWakeupTime(void); + U32 rt_suspend (void) { /* Suspend OS scheduler */ U32 delta = 0xFFFF; +#ifdef __CMSIS_RTOS + U32 sleep; +#endif rt_tsk_lock(); + scheduler_suspended = 1; if (os_dly.p_dlnk) { delta = os_dly.delta_time; } -#ifndef __CMSIS_RTOS +#ifdef __CMSIS_RTOS + sleep = sysUserTimerWakeupTime(); + if (sleep < delta) delta = sleep; +#else if (os_tmr.next) { if (os_tmr.tcnt < delta) delta = os_tmr.tcnt; } @@ -102,6 +114,8 @@ U32 rt_suspend (void) { /*--------------------------- rt_resume -------------------------------------*/ +extern void sysUserTimerUpdate (U32 sleep_time); + void rt_resume (U32 sleep_time) { /* Resume OS scheduler after suspend */ P_TCB next; @@ -133,8 +147,10 @@ void rt_resume (U32 sleep_time) { os_time += sleep_time; } -#ifndef __CMSIS_RTOS /* Check the user timers. */ +#ifdef __CMSIS_RTOS + sysUserTimerUpdate(sleep_time); +#else if (os_tmr.next) { delta = sleep_time; if (delta >= os_tmr.tcnt) { @@ -155,6 +171,7 @@ void rt_resume (U32 sleep_time) { next = rt_get_first (&os_rdy); rt_switch_req (next); + scheduler_suspended = 0; rt_tsk_unlock(); } @@ -163,6 +180,9 @@ void rt_resume (U32 sleep_time) { void rt_tsk_lock (void) { /* Prevent task switching by locking out scheduler */ + if (os_lock == __TRUE) // don't lock again if already locked + return; + if (os_tick_irqn < 0) { OS_LOCK(); os_lock = __TRUE; @@ -250,6 +270,19 @@ __weak int os_tick_init (void) { return (-1); /* Return IRQ number of SysTick timer */ } +/*--------------------------- os_tick_val -----------------------------------*/ + +__weak U32 os_tick_val (void) { + /* Get SysTick timer current value (0 .. OS_TRV). */ + return rt_systick_val(); +} + +/*--------------------------- os_tick_ovf -----------------------------------*/ + +__weak U32 os_tick_ovf (void) { + /* Get SysTick timer overflow flag */ + return rt_systick_ovf(); +} /*--------------------------- os_tick_irqack --------------------------------*/ diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_System.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_System.h index 91db6487e0..25ca286e64 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_System.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_System.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_SYSTEM.H * Purpose: System Task Manager definitions - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Task.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Task.c index ce2455a027..beb0463834 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Task.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Task.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_TASK.C * Purpose: Task functions and system start up. - * Rev.: V4.60 + * Rev.: V4.73 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -79,10 +79,12 @@ static void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) { p_TCB->cb_type = TCB; p_TCB->state = READY; p_TCB->prio = priority; + p_TCB->prio_base = priority; p_TCB->p_lnk = NULL; p_TCB->p_rlnk = NULL; p_TCB->p_dlnk = NULL; p_TCB->p_blnk = NULL; + p_TCB->p_mlnk = NULL; p_TCB->delta_time = 0; p_TCB->interval_time = 0; p_TCB->events = 0; @@ -101,7 +103,7 @@ static void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) { void rt_switch_req (P_TCB p_new) { /* Switch to next task (identified by "p_new"). */ - os_tsk.new = p_new; + os_tsk.new_tsk = p_new; p_new->state = RUNNING; DBG_TASK_SWITCH(p_new->task_id); } @@ -188,6 +190,7 @@ OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio) { if (task_id == 0) { /* Change execution priority of calling task. */ os_tsk.run->prio = new_prio; + os_tsk.run->prio_base = new_prio; run:if (rt_rdy_prio() > new_prio) { rt_put_prio (&os_rdy, os_tsk.run); os_tsk.run->state = READY; @@ -203,6 +206,7 @@ run:if (rt_rdy_prio() > new_prio) { } p_task = os_active_TCB[task_id-1]; p_task->prio = new_prio; + p_task->prio_base = new_prio; if (p_task == os_tsk.run) { goto run; } @@ -254,12 +258,40 @@ OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv) { OS_RESULT rt_tsk_delete (OS_TID task_id) { /* Terminate the task identified with "task_id". */ P_TCB task_context; + P_TCB p_TCB; + P_MUCB p_MCB, p_MCB0; if (task_id == 0 || task_id == os_tsk.run->task_id) { /* Terminate itself. */ os_tsk.run->state = INACTIVE; os_tsk.run->tsk_stack = rt_get_PSP (); rt_stk_check (); + p_MCB = os_tsk.run->p_mlnk; + while (p_MCB) { + /* Release mutexes owned by this task */ + if (p_MCB->p_lnk) { + /* A task is waiting for mutex. */ + p_TCB = rt_get_first ((P_XCB)p_MCB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 0/*osOK*/); +#else + rt_ret_val(p_TCB, OS_R_MUT); +#endif + rt_rmv_dly (p_TCB); + p_TCB->state = READY; + rt_put_prio (&os_rdy, p_TCB); + /* A waiting task becomes the owner of this mutex. */ + p_MCB0 = p_MCB; + p_MCB->level = 1; + p_MCB->owner = p_TCB; + p_MCB->p_mlnk = p_TCB->p_mlnk; + p_TCB->p_mlnk = p_MCB; + p_MCB = p_MCB0->p_mlnk; + } + else { + p_MCB = p_MCB->p_mlnk; + } + } os_active_TCB[os_tsk.run->task_id-1] = NULL; rt_free_box (mp_stk, os_tsk.run->stack); os_tsk.run->stack = NULL; @@ -278,11 +310,43 @@ OS_RESULT rt_tsk_delete (OS_TID task_id) { task_context = os_active_TCB[task_id-1]; rt_rmv_list (task_context); rt_rmv_dly (task_context); + p_MCB = task_context->p_mlnk; + while (p_MCB) { + /* Release mutexes owned by this task */ + if (p_MCB->p_lnk) { + /* A task is waiting for mutex. */ + p_TCB = rt_get_first ((P_XCB)p_MCB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 0/*osOK*/); +#else + rt_ret_val(p_TCB, OS_R_MUT); +#endif + rt_rmv_dly (p_TCB); + p_TCB->state = READY; + rt_put_prio (&os_rdy, p_TCB); + /* A waiting task becomes the owner of this mutex. */ + p_MCB0 = p_MCB; + p_MCB->level = 1; + p_MCB->owner = p_TCB; + p_MCB->p_mlnk = p_TCB->p_mlnk; + p_TCB->p_mlnk = p_MCB; + p_MCB = p_MCB0->p_mlnk; + } + else { + p_MCB = p_MCB->p_mlnk; + } + } os_active_TCB[task_id-1] = NULL; rt_free_box (mp_stk, task_context->stack); task_context->stack = NULL; DBG_TASK_NOTIFY(task_context, __FALSE); rt_free_box (mp_tcb, task_context); + if (rt_rdy_prio() > os_tsk.run->prio) { + /* Ready task has higher priority than running task. */ + os_tsk.run->state = READY; + rt_put_prio (&os_rdy, os_tsk.run); + rt_dispatch (NULL); + } } return (OS_R_OK); } diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Task.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Task.h index 6d7bc2fa63..822ef81cfb 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Task.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Task.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_TASK.H * Purpose: Task functions and system start up. - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Time.c b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Time.c index d99dc7564f..e7f0112a61 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Time.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Time.c @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_TIME.C * Purpose: Delay and interval wait functions - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Time.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Time.h index 27706373d5..f400ffc2db 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Time.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Time.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_TIME.H * Purpose: Delay and interval wait functions definitions - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Timer.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Timer.h index e627b0de22..66027fd4ce 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Timer.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_Timer.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_TIMER.H * Purpose: User timer functions - * Rev.: V4.60 + * Rev.: V4.70 *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h index 9f5d91e26e..18b45b9169 100644 --- a/libraries/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h @@ -3,10 +3,10 @@ *---------------------------------------------------------------------------- * Name: RT_TYPEDEF.H * Purpose: Type Definitions - * Rev.: V4.60 + * Rev.: V4.73 (plus large stack) *---------------------------------------------------------------------------- * - * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -64,11 +64,13 @@ typedef struct OS_TCB { U16 events; /* Event flags */ U16 waits; /* Wait flags */ void **msg; /* Direct message passing when task waits */ + struct OS_MUCB *p_mlnk; /* Link pointer for mutex owner list */ + U8 prio_base; /* Base priority */ /* Hardware dependant part: specific for Cortex processor */ - U8 stack_frame; /* Stack frame: 0x1 Basic/Extended, 0x2 FP stacked/not stacked */ - U8 reserved; - U16 priv_stack; /* Private stack size, 0= system assigned */ + U8 stack_frame; /* Stack frame: 0x0 Basic, 0x1 Extended, 0x2 VFP/D16 stacked, 0x4 NEON/D32 stacked */ + U16 reserved; /* Reserved (padding) */ + U32 priv_stack; /* Private stack size for LARGE_STACK, 0= system assigned */ U32 tsk_stack; /* Current task Stack pointer (R13) */ U32 *stack; /* Pointer to Task Stack memory block */ @@ -76,8 +78,8 @@ typedef struct OS_TCB { FUNCP ptask; /* Task entry address */ } *P_TCB; #define TCB_TID 3 /* 'task id' offset */ -#define TCB_STACKF 32 /* 'stack_frame' offset */ -#define TCB_TSTACK 36 /* 'tsk_stack' offset */ +#define TCB_STACKF 37 /* 'stack_frame' offset */ +#define TCB_TSTACK 44 /* 'tsk_stack' offset for LARGE_STACK */ typedef struct OS_PSFE { /* Post Service Fifo Entry */ void *id; /* Object Identification */ @@ -94,7 +96,7 @@ typedef struct OS_PSQ { /* Post Service Queue */ typedef struct OS_TSK { P_TCB run; /* Current running task */ - P_TCB new; /* Scheduled task to run */ + P_TCB new_tsk; /* Scheduled task to run */ } *P_TSK; typedef struct OS_ROBIN { /* Round Robin Control */ @@ -133,10 +135,10 @@ typedef struct OS_SCB { typedef struct OS_MUCB { U8 cb_type; /* Control Block Type */ - U8 prio; /* Owner task default priority */ U16 level; /* Call nesting level */ struct OS_TCB *p_lnk; /* Chain of tasks waiting for mutex */ struct OS_TCB *owner; /* Mutex owner task */ + struct OS_MUCB *p_mlnk; /* Chain of mutexes by owner task */ } *P_MUCB; typedef struct OS_XTMR { diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h index faff3a09c6..789a18f747 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h @@ -304,6 +304,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_STM32F303RE) #define INITIAL_SP (0x20010000UL) +#elif defined(TARGET_STM32F303K8) +#define INITIAL_SP (0x20003000UL) + #elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600) #define INITIAL_SP (0x20008000UL) @@ -322,6 +325,15 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL} #elif defined(TARGET_STM32F070RB) || defined(TARGET_STM32F030R8) #define INITIAL_SP (0x20002000UL) +#elif defined(TARGET_STM32L476VG) +#define INITIAL_SP (0x20018000UL) + +#elif defined(TARGET_STM32L476RG) +#define INITIAL_SP (0x20018000UL) + +#elif defined(TARGET_STM32F469NI) +#define INITIAL_SP (0x20050000UL) + #else #error "no target defined" diff --git a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c index 1401cd1e46..d0d0754f90 100755 --- a/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c +++ b/libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c @@ -52,9 +52,9 @@ # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) || defined(TARGET_TEENSY3_1) \ - || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) + || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) # define OS_TASKCNT 14 -# elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ +# elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL26Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) \ || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32SC151) \ @@ -70,14 +70,14 @@ # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\ || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \ || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600) || defined(TARGET_TEENSY3_1) \ - || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) + || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F446RE) || defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) || defined(TARGET_STM32F469NI) # define OS_SCHEDULERSTKSIZE 256 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \ || defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL26Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \ || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32SC151) \ || defined(TARGET_SSCI824) || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB) # define OS_SCHEDULERSTKSIZE 128 -# elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) +# elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) # define OS_SCHEDULERSTKSIZE 112 # else # error "no target defined" @@ -126,6 +126,9 @@ # elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32F303RE) || defined(TARGET_TEENSY3_1) # define OS_CLOCK 72000000 +# elif defined(TARGET_STM32F303K8) +# define OS_CLOCK 64000000 + # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) \ || defined(TARGET_KL26Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) # define OS_CLOCK 48000000 @@ -190,6 +193,12 @@ #elif defined(TARGET_STM32F070RB) # define OS_CLOCK 48000000 +#elif defined(TARGET_STM32L476VG) || defined(TARGET_STM32L476RG) +# define OS_CLOCK 80000000 + +#elif defined(TARGET_STM32F469NI) +# define OS_CLOCK 168000000 + # else # error "no target defined" # endif diff --git a/libraries/tests/mbed/analog/main.cpp b/libraries/tests/mbed/analog/main.cpp index 454e84b25c..b35095c573 100644 --- a/libraries/tests/mbed/analog/main.cpp +++ b/libraries/tests/mbed/analog/main.cpp @@ -50,14 +50,22 @@ AnalogOut out(PA_4); AnalogIn in(PC_3); AnalogOut out(PA_5); +#elif defined(TARGET_DISCO_F469NI) +AnalogIn in(PC_5); +AnalogOut out(PA_4); + #elif defined(TARGET_MAX32600MBED) AnalogIn in(AIN_7P); AnalogOut out(AOUT_DO); -#elif defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMD21J18A) || defined(TARGET_SAML21J18A) AnalogIn in(PA04); AnalogOut out(PA02); +#elif defined(TARGET_SAMD21G18A) +AnalogIn in(PB02); +AnalogOut out(PA02); + #else AnalogIn in(p17); AnalogOut out(p18); diff --git a/libraries/tests/mbed/bus/main.cpp b/libraries/tests/mbed/bus/main.cpp index 49e16be9c2..0faa0990a9 100644 --- a/libraries/tests/mbed/bus/main.cpp +++ b/libraries/tests/mbed/bus/main.cpp @@ -5,10 +5,14 @@ BusOut bus1(PA06, PA07, PA13, PA28, PA18, PA19, PA22, PA23, PA16, PA17, PA05, PA04); BusOut bus2(PB03, PB22, PB02, PB23); -#elif defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) BusOut bus1(PA06, PA07, PA13, PA28, PA18, PA19, PA22, PA23, PA16, PA17, PA05, PA04); BusOut bus2(PB03, PB22, PB02, PB23); +#elif defined(TARGET_SAML21J18A) +BusOut bus1(PA02, PA03, PA04, PA05, PA06, PA07, PA08, PA09, PA10, PA11, PA16, PA17); +BusOut bus2(PB10, PB11, PB12, PB13); + #else BusOut bus1(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15); BusOut bus2(A5, A4, A3, A2, A1, A0); diff --git a/libraries/tests/mbed/digitalin_digitalout/main.cpp b/libraries/tests/mbed/digitalin_digitalout/main.cpp index 1c212de168..23d0a406d9 100644 --- a/libraries/tests/mbed/digitalin_digitalout/main.cpp +++ b/libraries/tests/mbed/digitalin_digitalout/main.cpp @@ -10,6 +10,10 @@ DigitalIn in(dp2); DigitalOut out(D7); DigitalIn in(D2); +#elif defined(TARGET_DISCO_F469NI) +DigitalOut out(PB_1); +DigitalIn in(PG_9); + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ @@ -27,6 +31,11 @@ DigitalIn in(D2); DigitalOut out(PC_7); DigitalIn in(PB_8); +#elif defined(TARGET_NUCLEO_F031K6) || \ + defined(TARGET_NUCLEO_F042K6) +DigitalOut out(A4); +DigitalIn in(A5); + #elif defined(TARGET_ARCH_MAX) || \ defined(TARGET_DISCO_F407VG) || \ defined(TARGET_DISCO_F429ZI)|| \ @@ -58,7 +67,11 @@ DigitalIn in(PC1); DigitalOut out(PE10); DigitalIn in(PC1); -#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) +DigitalOut out(PB02); +DigitalIn in(PB03); + +#elif defined(TARGET_SAML21J18A) DigitalOut out(PA06); DigitalIn in(PA07); diff --git a/libraries/tests/mbed/digitalinout/main.cpp b/libraries/tests/mbed/digitalinout/main.cpp index 2d10245c3a..75016db12e 100644 --- a/libraries/tests/mbed/digitalinout/main.cpp +++ b/libraries/tests/mbed/digitalinout/main.cpp @@ -27,6 +27,11 @@ DigitalInOut d2(D7); DigitalInOut d1(PC_7); DigitalInOut d2(PB_8); +#elif defined(TARGET_NUCLEO_F031K6) || \ + defined(TARGET_NUCLEO_F042K6) +DigitalInOut d1(A4); +DigitalInOut d2(A5); + #elif defined(TARGET_ARCH_MAX) || \ defined(TARGET_DISCO_F407VG) || \ defined(TARGET_DISCO_F429ZI)|| \ @@ -58,7 +63,11 @@ DigitalInOut d2(PC1); DigitalInOut d1(PE10); DigitalInOut d2(PC1); -#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) +DigitalInOut d1(PB02); +DigitalInOut d2(PB03); + +#elif defined(TARGET_SAML21J18A)) DigitalInOut d1(PA06); DigitalInOut d2(PA07); diff --git a/libraries/tests/mbed/echo_flow_control/main.cpp b/libraries/tests/mbed/echo_flow_control/main.cpp index 468d5d5795..4f3dc60507 100644 --- a/libraries/tests/mbed/echo_flow_control/main.cpp +++ b/libraries/tests/mbed/echo_flow_control/main.cpp @@ -14,13 +14,20 @@ #define FLOW_CONTROL_CTS PA07 #define RTS_CHECK_PIN PB03 -#elif defined(TARGET_SAMD21J18A) -#define UART_TX PA22 -#define UART_RX PA23 +#elif defined(TARGET_SAMD21J18A) /*USB debug port is not having RTS and CTS pins in expansion connectors in D21 Xplained Pro Board*/ +#define UART_TX PA22 /* Short this pin to PA04 */ +#define UART_RX PA23 /* Short this pin to PA05 */ #define FLOW_CONTROL_RTS PA24 #define FLOW_CONTROL_CTS PA25 #define RTS_CHECK_PIN PB03 +#elif defined(TARGET_SAMD21G18A) /*USB debug port is not having RTS and CTS pins in expansion connectors in W25 Xplained Pro Board*/ +#define UART_TX PA16 /* Short this pin to PB10 */ +#define UART_RX PA17 /* Short this pin to PB11 */ +#define FLOW_CONTROL_RTS PA18 +#define FLOW_CONTROL_CTS PA19 +#define RTS_CHECK_PIN PB03 + #else #error This test is not supported on this target #endif diff --git a/libraries/tests/mbed/i2c_master/main.cpp b/libraries/tests/mbed/i2c_master/main.cpp index 917b0ca56a..bd3162ebe7 100644 --- a/libraries/tests/mbed/i2c_master/main.cpp +++ b/libraries/tests/mbed/i2c_master/main.cpp @@ -26,7 +26,7 @@ I2C i2c(TEST_SDA_PIN, TEST_SCL_PIN); #define TEST_SDA_PIN PA16 #define TEST_SCL_PIN PA17 I2C i2c(TEST_SDA_PIN, TEST_SCL_PIN); -#elif defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A) #define TEST_SDA_PIN PA08 #define TEST_SCL_PIN PA09 I2C i2c(TEST_SDA_PIN, TEST_SCL_PIN); diff --git a/libraries/tests/mbed/i2c_slave/main.cpp b/libraries/tests/mbed/i2c_slave/main.cpp index eb3bd60cf5..09c7d715d6 100644 --- a/libraries/tests/mbed/i2c_slave/main.cpp +++ b/libraries/tests/mbed/i2c_slave/main.cpp @@ -10,7 +10,7 @@ I2CSlave slave(PTE0, PTE1); I2CSlave slave(p9, p10); #elif defined(TARGET_SAMR21G18A) I2CSlave slave(PA16, PA17); -#elif defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A) I2CSlave slave(PA08, PA09); #else I2CSlave slave(p28, p27); diff --git a/libraries/tests/mbed/interrupt_chaining/main.cpp b/libraries/tests/mbed/interrupt_chaining/main.cpp index 890f884267..ef5d848836 100644 --- a/libraries/tests/mbed/interrupt_chaining/main.cpp +++ b/libraries/tests/mbed/interrupt_chaining/main.cpp @@ -11,8 +11,10 @@ #define TIMER_IRQ LPTimer_IRQn #elif defined(TARGET_LPC2368) || defined(TARGET_LPC2460) #define TIMER_IRQ TIMER3_IRQn -#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) #define TIMER_IRQ TC4_IRQn +#elif defined(TARGET_SAML21J18A) +#define TIMER_IRQ TC0_IRQn #else #error This test can't run on this target. #endif @@ -46,6 +48,8 @@ Sender s2(pc, '2'); # define LED_NAME LED2 #elif defined(TARGET_KL05Z) # define LED_NAME LED2 +#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A) /*to avoid build errors*/ +# define LED_NAME LED2 /*Only 1 LED available*/ #else # define LED_NAME PTE31 #endif diff --git a/libraries/tests/mbed/interruptin/main.cpp b/libraries/tests/mbed/interruptin/main.cpp index af9d9d8512..52ba179f0e 100644 --- a/libraries/tests/mbed/interruptin/main.cpp +++ b/libraries/tests/mbed/interruptin/main.cpp @@ -52,6 +52,11 @@ void in_handler() { #define PIN_IN PB_8 #define PIN_OUT PC_7 +#elif defined(TARGET_NUCLEO_F031K6) || \ + defined(TARGET_NUCLEO_F042K6) +#define PIN_IN A4 +#define PIN_OUT A5 + #elif defined(TARGET_ARCH_MAX) || \ defined(TARGET_DISCO_F407VG) || \ defined(TARGET_DISCO_F429ZI)|| \ @@ -87,9 +92,13 @@ void in_handler() { #define PIN_OUT PE10 #define PIN_IN PC1 -#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) -#define PIN_OUT PA06 -#define PIN_IN PA07 +#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) +#define PIN_OUT PB02 +#define PIN_IN PB03 + +#elif defined(TARGET_SAML21J18A) +#define PIN_OUT PA02 +#define PIN_IN PA03 #else #define PIN_IN (p5) diff --git a/libraries/tests/mbed/interruptin_2/main.cpp b/libraries/tests/mbed/interruptin_2/main.cpp index add888af85..a418d35755 100644 --- a/libraries/tests/mbed/interruptin_2/main.cpp +++ b/libraries/tests/mbed/interruptin_2/main.cpp @@ -56,6 +56,34 @@ InterruptIn button9(PA28); DigitalOut led(LED1); DigitalOut flash(PA27); /*1 LED Available*/ +#elif defined(TARGET_SAMD21G18A) +InterruptIn button (PB23); /*SW0*/ +InterruptIn button1(PA02); +InterruptIn button2(PA03); +InterruptIn button3(PA10); +InterruptIn button4(PA11); +InterruptIn button5(PA20); +InterruptIn button6(PA21); +InterruptIn button7(PA09); +InterruptIn button8(PA16); +InterruptIn button9(PA17); +DigitalOut led(LED1); +DigitalOut flash(PA19); /*1 LED Available*/ + +#elif defined(TARGET_SAML21J18A) +InterruptIn button (PA02); /*SW0*/ +InterruptIn button1(PA16); +InterruptIn button2(PA17); +InterruptIn button3(PA15); +InterruptIn button4(PA19); +InterruptIn button5(PA04); +InterruptIn button6(PA05); +InterruptIn button7(PA06); +InterruptIn button8(PA07); +InterruptIn button9(PB08); +DigitalOut led(LED1); +DigitalOut flash(PA27); /*1 LED Available*/ + #else InterruptIn button(p30); InterruptIn button1(p29); diff --git a/libraries/tests/mbed/pin_toggling/main.cpp b/libraries/tests/mbed/pin_toggling/main.cpp index 83b04a96be..91896ee831 100644 --- a/libraries/tests/mbed/pin_toggling/main.cpp +++ b/libraries/tests/mbed/pin_toggling/main.cpp @@ -1,7 +1,7 @@ #include "mbed.h" -#if defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) -DigitalOut out(PA06); +#if defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A) +DigitalOut out(PB02); #else DigitalOut out(p5); #endif diff --git a/libraries/tests/mbed/portinout/main.cpp b/libraries/tests/mbed/portinout/main.cpp index fb7fca20f3..8900cf7eac 100644 --- a/libraries/tests/mbed/portinout/main.cpp +++ b/libraries/tests/mbed/portinout/main.cpp @@ -138,6 +138,24 @@ #define P2_2 (1 << 3) /*PB03*/ #define PORT_2 PortB +#elif defined(TARGET_SAMD21G18A) +#define P1_1 (1 << 2) /*PA02*/ +#define P1_2 (1 << 3) /*PA03*/ +#define PORT_1 PortA + +#define P2_1 (1 << 2) /*PB02*/ +#define P2_2 (1 << 3) /*PB03*/ +#define PORT_2 PortB + +#elif defined(TARGET_SAML21J18A) +#define P1_1 (1 << 4) /*PA04*/ +#define P1_2 (1 << 5) /*PA05*/ +#define PORT_1 PortA + +#define P2_1 (1 << 0) /*PB00*/ +#define P2_2 (1 << 1) /*PB01*/ +#define PORT_2 PortB + #endif #define MASK_1 (P1_1 | P1_2) diff --git a/libraries/tests/mbed/portout/main.cpp b/libraries/tests/mbed/portout/main.cpp index 11e288ccb6..3b106c98d6 100644 --- a/libraries/tests/mbed/portout/main.cpp +++ b/libraries/tests/mbed/portout/main.cpp @@ -36,8 +36,21 @@ # define LED2 0 # define LED3 0 # define LED4 0 +# elif defined(TARGET_SAMD21G18A) +# define LED_PORT PortA +# define LED1 (1 << 23) /*PA23*/ +# define LED2 0 +# define LED3 0 +# define LED4 0 +# elif defined(TARGET_SAML21J18A) +# define LED_PORT PortB +# define LED1 (1 << 10) /*PB10*/ +# define LED2 0 +# define LED3 0 +# define LED4 0 # endif + #define LED_MASK (LED1|LED2|LED3|LED4) int mask[4] = { diff --git a/libraries/tests/mbed/portout_portin/main.cpp b/libraries/tests/mbed/portout_portin/main.cpp index dc5929f942..ea9649c0bc 100644 --- a/libraries/tests/mbed/portout_portin/main.cpp +++ b/libraries/tests/mbed/portout_portin/main.cpp @@ -81,6 +81,16 @@ #define P2_2 (1 << 6) // P4_6 #define PORT_2 Port4 +#elif defined(TARGET_DISCO_F469NI) + +#define P1_1 (1 << 2) // PC_2 +#define P1_2 (1 << 3) // PC_3 +#define PORT_1 PortC + +#define P2_1 (1 << 1) // PA_1 +#define P2_2 (1 << 2) // PA_2 +#define PORT_2 PortA + #elif defined(TARGET_NUCLEO_F030R8) || \ defined(TARGET_NUCLEO_F070RB) || \ defined(TARGET_NUCLEO_F072RB) || \ @@ -138,6 +148,24 @@ #define P2_2 (1 << 3) /*PB03*/ #define PORT_2 PortB +#elif defined(TARGET_SAMD21G18A) +#define P1_1 (1 << 2) /*PA02*/ +#define P1_2 (1 << 3) /*PA03*/ +#define PORT_1 PortA + +#define P2_1 (1 << 2) /*PB02*/ +#define P2_2 (1 << 3) /*PB03*/ +#define PORT_2 PortB + +#elif defined(TARGET_SAML21J18A) +#define P1_1 (1 << 4) /*PA04*/ +#define P1_2 (1 << 5) /*PA05*/ +#define PORT_1 PortA + +#define P2_1 (1 << 0) /*PB00*/ +#define P2_2 (1 << 1) /*PB01*/ +#define PORT_2 PortB + #endif #define MASK_1 (P1_1 | P1_2) diff --git a/libraries/tests/mbed/pwm/main.cpp b/libraries/tests/mbed/pwm/main.cpp index bb023cb7cf..2e5754f790 100644 --- a/libraries/tests/mbed/pwm/main.cpp +++ b/libraries/tests/mbed/pwm/main.cpp @@ -166,7 +166,7 @@ int main() { printf("Initialize PWM on pin P1.2 with duty cycle: %.2f\n", pwm_1.read()); printf("Initialize PWM on pin P1.3 with duty cycle: %.2f\n", pwm_2.read()); -#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A) PwmOut pwm(LED1); pwm.period_ms(1000); diff --git a/libraries/tests/mbed/pwm_led/pwm.cpp b/libraries/tests/mbed/pwm_led/pwm.cpp index 7b8978946b..0d64087135 100644 --- a/libraries/tests/mbed/pwm_led/pwm.cpp +++ b/libraries/tests/mbed/pwm_led/pwm.cpp @@ -28,7 +28,7 @@ #elif defined (TARGET_DISCO_F407VG) #define TEST_LED LED1 -#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A) #define TEST_LED LED1 #else diff --git a/libraries/tests/mbed/serial_interrupt_2/main.cpp b/libraries/tests/mbed/serial_interrupt_2/main.cpp index 98c55fd144..edbbc11f28 100644 --- a/libraries/tests/mbed/serial_interrupt_2/main.cpp +++ b/libraries/tests/mbed/serial_interrupt_2/main.cpp @@ -6,7 +6,7 @@ Serial pc(USBTX, USBRX); Serial uart(P4_22, P4_23); #elif defined(TARGET_MAXWSNENV) Serial uart(P0_1, P0_0); -#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) Serial uart(PA16, PA17); #else Serial uart(p9, p10); diff --git a/libraries/tests/mbed/sleep/main.cpp b/libraries/tests/mbed/sleep/main.cpp index 39537bdcf2..40d6bbb3a9 100644 --- a/libraries/tests/mbed/sleep/main.cpp +++ b/libraries/tests/mbed/sleep/main.cpp @@ -10,6 +10,10 @@ InterruptIn wkp(P0_16); InterruptIn wkp(PA28); #elif defined(TARGET_SAMD21J18A) InterruptIn wkp(PA15); +#elif defined(TARGET_SAMD21G18A) +InterruptIn wkp(PB23); +#elif defined(TARGET_SAML21J18A) +InterruptIn wkp(PA02); #else InterruptIn wkp(p14); #endif diff --git a/libraries/tests/mbed/spi/main.cpp b/libraries/tests/mbed/spi/main.cpp index 69b92c5e4b..ceef120f01 100644 --- a/libraries/tests/mbed/spi/main.cpp +++ b/libraries/tests/mbed/spi/main.cpp @@ -3,7 +3,7 @@ #if defined(TARGET_SAMR21G18A) SPI spi(PB22, PB02, PB23); // mosi, miso, sclk DigitalOut latchpin(PB03); -#elif defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A) SPI spi(PA18, PA16, PA19); // mosi, miso, sclk DigitalOut latchpin(PA17); #else diff --git a/libraries/tests/mbed/spi_master/main.cpp b/libraries/tests/mbed/spi_master/main.cpp index 6ffd57f376..aa29bf43c7 100644 --- a/libraries/tests/mbed/spi_master/main.cpp +++ b/libraries/tests/mbed/spi_master/main.cpp @@ -10,6 +10,9 @@ DigitalOut cs(PTB1); #elif defined(TARGET_KL46Z) SPI spi(PTD2, PTD3, PTD1); // mosi, miso, sclk DigitalOut cs(PTA13); +#elif defined(TARGET_ELMO_F411RE) +SPI spi(PB_15, PB_14, PB_13); // mosi, miso, sclk +DigitalOut cs(PB_12); #elif defined(TARGET_FF_ARDUINO) SPI spi(D11, D12, D13); // mosi, miso, sclk DigitalOut cs(D10); @@ -25,7 +28,7 @@ DigitalOut cs(PE13); #elif defined(TARGET_SAMR21G18A) SPI spi(PB22, PB02, PB23); // mosi, miso, sclk DigitalOut cs(PB03); -#elif defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A) SPI spi(PA18, PA16, PA19); // mosi, miso, sclk DigitalOut cs(PA17); #else diff --git a/libraries/tests/mbed/spi_slave/main.cpp b/libraries/tests/mbed/spi_slave/main.cpp index 32f7fae6e3..22830d2cf3 100644 --- a/libraries/tests/mbed/spi_slave/main.cpp +++ b/libraries/tests/mbed/spi_slave/main.cpp @@ -12,7 +12,7 @@ SPISlave device(D11, D12, D13, D10); // mosi, miso, sclk, ssel SPISlave device(dp2, dp1, dp6, dp25); // mosi, miso, sclk, ssel #elif defined(TARGET_SAMR21G18A) SPISlave device(PB22, PB02, PB23, PB03); // mosi, miso, sclk, ssel -#elif defined(TARGET_SAMD21J18A) +#elif defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) || defined(TARGET_SAML21J18A) SPISlave device(PA18, PA16, PA19, PA17); // mosi, miso, sclk, ssel #else SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel diff --git a/libraries/tests/mbed/vtor_reloc/main.cpp b/libraries/tests/mbed/vtor_reloc/main.cpp index 07f6728a29..25249a95d8 100644 --- a/libraries/tests/mbed/vtor_reloc/main.cpp +++ b/libraries/tests/mbed/vtor_reloc/main.cpp @@ -6,11 +6,16 @@ #include "cmsis_nvic.h" #include -#if defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) -#define PIN_IN (PA06) -#define PIN_OUT (PA07) +#if defined(TARGET_SAMR21G18A) || defined(TARGET_SAMD21J18A) || defined(TARGET_SAMD21G18A) +#define PIN_IN (PB02) +#define PIN_OUT (PB03) #define NUM_VECTORS (16+28) +#elif defined(TARGET_SAML21J18A) +#define PIN_IN (PB00) +#define PIN_OUT (PB01) +#define NUM_VECTORS (16+29) + #else #define PIN_IN (p5) #define PIN_OUT (p25) diff --git a/libraries/tests/rtos/mbed/mutex/main.cpp b/libraries/tests/rtos/mbed/mutex/main.cpp index f32f4eb0a3..17d99867ce 100644 --- a/libraries/tests/rtos/mbed/mutex/main.cpp +++ b/libraries/tests/rtos/mbed/mutex/main.cpp @@ -24,6 +24,8 @@ #define STACK_SIZE DEFAULT_STACK_SIZE/2 #elif defined(TARGET_STM32F302R8) && defined(TOOLCHAIN_IAR) #define STACK_SIZE DEFAULT_STACK_SIZE/2 +#elif defined(TARGET_STM32F303K8) && defined(TOOLCHAIN_IAR) + #define STACK_SIZE DEFAULT_STACK_SIZE/2 #else #define STACK_SIZE DEFAULT_STACK_SIZE #endif diff --git a/libraries/tests/rtos/mbed/semaphore/main.cpp b/libraries/tests/rtos/mbed/semaphore/main.cpp index 37218c3d00..51534c7bbd 100644 --- a/libraries/tests/rtos/mbed/semaphore/main.cpp +++ b/libraries/tests/rtos/mbed/semaphore/main.cpp @@ -27,6 +27,8 @@ #define STACK_SIZE DEFAULT_STACK_SIZE/2 #elif defined(TARGET_STM32F302R8) && defined(TOOLCHAIN_IAR) #define STACK_SIZE DEFAULT_STACK_SIZE/2 +#elif defined(TARGET_STM32F303K8) && defined(TOOLCHAIN_IAR) + #define STACK_SIZE DEFAULT_STACK_SIZE/4 #else #define STACK_SIZE DEFAULT_STACK_SIZE #endif diff --git a/requirements.txt b/requirements.txt index 09f78ec5ab..9facf86158 100644 --- a/requirements.txt +++ b/requirements.txt @@ -2,4 +2,5 @@ colorama pyserial prettytable Jinja2 -IntelHex \ No newline at end of file +IntelHex +mbed-ls \ No newline at end of file diff --git a/workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader.bin b/workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader.bin index cba01d00c1..e5c640df1c 100755 Binary files a/workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader.bin and b/workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader.bin differ diff --git a/workspace_tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin b/workspace_tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin index c4c53eec23..5a270bc7a4 100755 Binary files a/workspace_tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin and b/workspace_tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin differ diff --git a/workspace_tools/build.py b/workspace_tools/build.py index 98d2fd52df..969ca03b6b 100755 --- a/workspace_tools/build.py +++ b/workspace_tools/build.py @@ -77,7 +77,7 @@ if __name__ == '__main__': action="store_true", dest="fat", default=False, - help="Compile FS ad SD card file system library") + help="Compile FS and SD card file system library") parser.add_option("-b", "--ublox", action="store_true", diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py old mode 100755 new mode 100644 index 962e4e0187..6653f32555 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -61,16 +61,20 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('TEENSY3_1', ('ARM', 'GCC_ARM')), ('NUCLEO_F030R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), + ('NUCLEO_F031K6', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), + ('NUCLEO_F042K6', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F070RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F072RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F091RC', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F103RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F302R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), + ('NUCLEO_F303K8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F303RE', ('ARM', 'uARM', 'IAR')), ('NUCLEO_F334R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F401RE', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F411RE', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_F446RE', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), + ('ELMO_F411RE', ('ARM', 'uARM', 'GCC_ARM')), ('NUCLEO_L053R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('NUCLEO_L152RE', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('MTS_MDOT_F405RG', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), @@ -78,7 +82,10 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('MTS_DRAGONFLY_F411RE', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('DISCO_L053C8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('DISCO_F334C8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), -# ('DISCO_F746NG', ('ARM', 'uARM', 'IAR')), + ('DISCO_F469NI', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), + ('DISCO_F746NG', ('ARM', 'uARM')), + ('DISCO_L476VG', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), + ('NUCLEO_L476RG', ('ARM', 'uARM', 'IAR', 'GCC_ARM')), ('ARCH_MAX', ('ARM', 'GCC_ARM')), @@ -103,6 +110,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('ARM_MPS2_M3' , ('ARM',)), ('ARM_MPS2_M4' , ('ARM',)), ('ARM_MPS2_M7' , ('ARM',)), + ('ARM_MPS2_BEID' , ('ARM',)), ('RZ_A1H' , ('ARM', 'GCC_ARM')), @@ -116,6 +124,8 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('MAX32600MBED', ('ARM', 'GCC_ARM', 'IAR')), ('WIZWIKI_W7500', ('ARM', 'uARM')), + ('WIZWIKI_W7500P',('ARM', 'uARM')), + ('WIZWIKI_W7500ECO',('ARM', 'uARM')), ) diff --git a/workspace_tools/build_travis.py b/workspace_tools/build_travis.py index e9d4423a00..23f5e25814 100644 --- a/workspace_tools/build_travis.py +++ b/workspace_tools/build_travis.py @@ -38,15 +38,23 @@ build_list = ( { "target": "NUCLEO_L053R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_L152RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F030R8", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NUCLEO_F031K6", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NUCLEO_F042K6", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "NUCLEO_F070RB", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "NUCLEO_F072RB", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F091RC", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F103RB", "toolchains": "GCC_ARM", "libs": ["rtos", "fat"] }, { "target": "NUCLEO_F302R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + { "target": "NUCLEO_F303K8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F303RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F334R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F401RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + { "target": "NUCLEO_L476RG", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NUCLEO_L073RZ", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NUCLEO_F446RE", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + + { "target": "ELMO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "MTS_MDOT_F405RG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos"] }, { "target": "MTS_MDOT_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos"] }, @@ -58,6 +66,7 @@ build_list = ( { "target": "DISCO_F401VC", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "DISCO_F407VG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "DISCO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, + { "target": "DISCO_F469NI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "DISCO_F746NG", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "LPC1114", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, @@ -78,12 +87,25 @@ build_list = ( { "target": "ARCH_PRO", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "LPC1549", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] }, { "target": "NRF51822", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "DELTA_DFCM_NNN40", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NRF51_DK", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "NRF51_MICROBIT", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, { "target": "EFM32ZG_STK3200", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "EFM32HG_STK3400", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "EFM32LG_STK3600", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "EFM32GG_STK3700", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "EFM32WG_STK3800", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + + { "target": "MAXWSNENV", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "MAX32600MBED", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + + { "target": "RZ_A1H", "toolchains": "GCC_ARM", "libs": ["fat"] }, + + { "target": "SAMR21G18A", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "SAMD21J18A", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "SAMD21G18A", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, + { "target": "SAML21J18A", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] }, ) ################################################################################ diff --git a/workspace_tools/export/coide.py b/workspace_tools/export/coide.py index 16285fff63..08d1fbda1b 100755 --- a/workspace_tools/export/coide.py +++ b/workspace_tools/export/coide.py @@ -32,11 +32,13 @@ class CoIDE(Exporter): 'NUCLEO_L053R8', 'NUCLEO_L152RE', 'NUCLEO_F030R8', + 'NUCLEO_F042K6', 'NUCLEO_F070RB', 'NUCLEO_F072RB', 'NUCLEO_F091RC', 'NUCLEO_F103RB', 'NUCLEO_F302R8', + 'NUCLEO_F303K8', 'NUCLEO_F303RE', 'NUCLEO_F334R8', 'NUCLEO_F401RE', @@ -50,6 +52,7 @@ class CoIDE(Exporter): 'DISCO_F401VC', 'DISCO_F407VG', 'DISCO_F429ZI', + 'DISCO_F469NI', 'MTS_MDOT_F405RG', 'MTS_MDOT_F411RE', 'MOTE_L152RC', diff --git a/workspace_tools/export/coide_nucleo_f042k6.coproj.tmpl b/workspace_tools/export/coide_nucleo_f042k6.coproj.tmpl new file mode 100644 index 0000000000..8d150d0653 --- /dev/null +++ b/workspace_tools/export/coide_nucleo_f042k6.coproj.tmpl @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + {% for file in source_files %} + + {% endfor %} + {% for file in header_files %} + + {% endfor %} + + diff --git a/workspace_tools/export/ds5_5.py b/workspace_tools/export/ds5_5.py index 8a0e4814f1..b6b9d3efe1 100644 --- a/workspace_tools/export/ds5_5.py +++ b/workspace_tools/export/ds5_5.py @@ -27,6 +27,7 @@ class DS5_5(Exporter): 'LPC812', 'UBLOX_C027', 'ARCH_PRO', + 'RZ_A1H', ] USING_MICROLIB = [ diff --git a/workspace_tools/export/ds5_5_rz_a1h.cproject.tmpl b/workspace_tools/export/ds5_5_rz_a1h.cproject.tmpl new file mode 100644 index 0000000000..44e66cad21 --- /dev/null +++ b/workspace_tools/export/ds5_5_rz_a1h.cproject.tmpl @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/workspace_tools/export/ds5_5_rz_a1h.launch.tmpl b/workspace_tools/export/ds5_5_rz_a1h.launch.tmpl new file mode 100644 index 0000000000..a4bee75246 --- /dev/null +++ b/workspace_tools/export/ds5_5_rz_a1h.launch.tmpl @@ -0,0 +1,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/workspace_tools/export/ds5_5_rz_a1h.project.tmpl b/workspace_tools/export/ds5_5_rz_a1h.project.tmpl new file mode 100644 index 0000000000..eee5209b75 --- /dev/null +++ b/workspace_tools/export/ds5_5_rz_a1h.project.tmpl @@ -0,0 +1,83 @@ + + + {{name}}_ds5_rz_a1h + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/ds5_rz_a1h/Build} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/workspace_tools/export/gcc_arm_disco_f469ni.tmpl b/workspace_tools/export/gcc_arm_disco_f469ni.tmpl new file mode 100644 index 0000000000..6e616cc884 --- /dev/null +++ b/workspace_tools/export/gcc_arm_disco_f469ni.tmpl @@ -0,0 +1 @@ +{% extends "gcc_arm_common.tmpl" %} diff --git a/workspace_tools/export/gcc_arm_nucleo_f031k6.tmpl b/workspace_tools/export/gcc_arm_nucleo_f031k6.tmpl new file mode 100644 index 0000000000..6e616cc884 --- /dev/null +++ b/workspace_tools/export/gcc_arm_nucleo_f031k6.tmpl @@ -0,0 +1 @@ +{% extends "gcc_arm_common.tmpl" %} diff --git a/workspace_tools/export/gcc_arm_nucleo_f042k6.tmpl b/workspace_tools/export/gcc_arm_nucleo_f042k6.tmpl new file mode 100644 index 0000000000..6e616cc884 --- /dev/null +++ b/workspace_tools/export/gcc_arm_nucleo_f042k6.tmpl @@ -0,0 +1 @@ +{% extends "gcc_arm_common.tmpl" %} diff --git a/workspace_tools/export/gcc_arm_nucleo_f303k8.tmpl b/workspace_tools/export/gcc_arm_nucleo_f303k8.tmpl new file mode 100644 index 0000000000..6e616cc884 --- /dev/null +++ b/workspace_tools/export/gcc_arm_nucleo_f303k8.tmpl @@ -0,0 +1 @@ +{% extends "gcc_arm_common.tmpl" %} diff --git a/workspace_tools/export/gcc_arm_rblab_blenano.tmpl b/workspace_tools/export/gcc_arm_rblab_blenano.tmpl new file mode 100644 index 0000000000..c65eb03956 --- /dev/null +++ b/workspace_tools/export/gcc_arm_rblab_blenano.tmpl @@ -0,0 +1,14 @@ +{% extends "gcc_arm_common.tmpl" %} + +{% block additional_variables %} +SOFTDEVICE = mbed/TARGET_RBLAB_BLENANO/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_softdevice.hex +{% endblock %} + +{% block additional_executables %} +SREC_CAT = srec_cat +{% endblock %} + +{% block additional_targets %} +merge: + $(SREC_CAT) $(SOFTDEVICE) -intel $(PROJECT).hex -intel -o combined.hex -intel --line-length=44 +{% endblock %} diff --git a/workspace_tools/export/gcc_arm_samd21g18a.tmpl b/workspace_tools/export/gcc_arm_samd21g18a.tmpl new file mode 100644 index 0000000000..09f43e63f0 --- /dev/null +++ b/workspace_tools/export/gcc_arm_samd21g18a.tmpl @@ -0,0 +1,72 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m0plus -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gcc_arm_saml21j18a.tmpl b/workspace_tools/export/gcc_arm_saml21j18a.tmpl new file mode 100644 index 0000000000..09f43e63f0 --- /dev/null +++ b/workspace_tools/export/gcc_arm_saml21j18a.tmpl @@ -0,0 +1,72 @@ +# This file was automagically generated by mbed.org. For more information, +# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded + +GCC_BIN = +PROJECT = {{name}} +OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %} +SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %} +INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %} +LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %} +LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %} +LINKER_SCRIPT = {{linker_script}} + +############################################################################### +AS = $(GCC_BIN)arm-none-eabi-as +CC = $(GCC_BIN)arm-none-eabi-gcc +CPP = $(GCC_BIN)arm-none-eabi-g++ +LD = $(GCC_BIN)arm-none-eabi-gcc +OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy +OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump +SIZE = $(GCC_BIN)arm-none-eabi-size + +CPU = -mcpu=cortex-m0plus -mthumb +CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer +CC_FLAGS += -MMD -MP +CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %} + +LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main +LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref +LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys + +ifeq ($(DEBUG), 1) + CC_FLAGS += -DDEBUG -O0 +else + CC_FLAGS += -DNDEBUG -Os +endif + +all: $(PROJECT).bin $(PROJECT).hex + +clean: + rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS) + +.s.o: + $(AS) $(CPU) -o $@ $< + +.c.o: + $(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $< + +.cpp.o: + $(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $< + + +$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS) + $(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS) + $(SIZE) $@ + +$(PROJECT).bin: $(PROJECT).elf + @$(OBJCOPY) -O binary $< $@ + +$(PROJECT).hex: $(PROJECT).elf + @$(OBJCOPY) -O ihex $< $@ + +$(PROJECT).lst: $(PROJECT).elf + @$(OBJDUMP) -Sdh $< > $@ + +lst: $(PROJECT).lst + +size: + $(SIZE) $(PROJECT).elf + +DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d) +-include $(DEPS) + diff --git a/workspace_tools/export/gccarm.py b/workspace_tools/export/gccarm.py index dd9e069b1b..43026c8abd 100755 --- a/workspace_tools/export/gccarm.py +++ b/workspace_tools/export/gccarm.py @@ -56,6 +56,7 @@ class GccArm(Exporter): 'NRF51822', 'HRM1017', 'RBLAB_NRF51822', + 'RBLAB_BLENANO', 'LPC2368', 'LPC2460', 'LPCCAPPUCCINO', @@ -67,18 +68,24 @@ class GccArm(Exporter): 'NUCLEO_F446RE', 'ARCH_MAX', 'DISCO_F429ZI', + 'DISCO_F469NI', 'NUCLEO_F030R8', + 'NUCLEO_F031K6', + 'NUCLEO_F042K6', 'NUCLEO_F070RB', 'NUCLEO_F072RB', 'NUCLEO_F091RC', 'NUCLEO_F103RB', 'NUCLEO_F302R8', + 'NUCLEO_F303K8', 'NUCLEO_F303RE', 'NUCLEO_F334R8', 'DISCO_L053C8', 'NUCLEO_L053R8', 'NUCLEO_L073RZ', + 'NUCLEO_L476RG', 'DISCO_F334C8', + 'DISCO_F469NI', 'MAX32600MBED', 'MAXWSNENV', 'MTS_MDOT_F405RG', @@ -100,6 +107,8 @@ class GccArm(Exporter): 'SAMR21G18A', 'TEENSY3_1', 'SAMD21J18A', + 'SAMD21G18A', + 'SAML21J18A', ] DOT_IN_RELATIVE_PATH = True diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py index 9d3d986f28..315bfd8a81 100755 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -47,11 +47,14 @@ class IAREmbeddedWorkbench(Exporter): 'K22F', 'K64F', 'NUCLEO_F030R8', + 'NUCLEO_F031K6', + 'NUCLEO_F042K6', 'NUCLEO_F070RB', 'NUCLEO_F072RB', 'NUCLEO_F091RC', 'NUCLEO_F103RB', 'NUCLEO_F302R8', + 'NUCLEO_F303K8', 'NUCLEO_F303RE', 'NUCLEO_F334R8', 'NUCLEO_F401RE', @@ -60,8 +63,10 @@ class IAREmbeddedWorkbench(Exporter): 'NUCLEO_L053R8', 'NUCLEO_L073RZ', 'NUCLEO_L152RE', + 'NUCLEO_L476RG', 'DISCO_L053C8', 'DISCO_F334C8', + 'DISCO_F469NI', 'DISCO_F746NG', 'DISCO_L476VG', #'STM32F407', Fails to build same for GCC diff --git a/workspace_tools/export/iar_disco_f469ni.ewd.tmpl b/workspace_tools/export/iar_disco_f469ni.ewd.tmpl new file mode 100644 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b/workspace_tools/export/iar_nucleo_f303k8.ewp.tmpl @@ -0,0 +1,1871 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 24 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + 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'NUCLEO_F303K8', 'NUCLEO_F303RE', 'NUCLEO_F334R8', 'NUCLEO_F401RE', @@ -54,6 +57,7 @@ class Uvision4(Exporter): 'NUCLEO_L053R8', 'NUCLEO_L073RZ', 'NUCLEO_L152RE', + 'NUCLEO_L476RG', 'UBLOX_C027', 'LPC1549', 'LPC11U68', @@ -67,6 +71,7 @@ class Uvision4(Exporter): 'DISCO_F407VG', 'DISCO_L053C8', 'DISCO_F334C8', + 'DISCO_F469NI', 'DISCO_F746NG', 'DISCO_L476VG', 'MTS_GAMBIT', @@ -81,6 +86,10 @@ class Uvision4(Exporter): 'MAX32600MBED', 'MOTE_L152RC', 'NZ32SC151', + 'SAMR21G18A', + 'SAMD21J18A', + 'SAMD21G18A', + 'SAML21J18A', ] USING_MICROLIB = [ @@ -89,11 +98,14 @@ class Uvision4(Exporter): 'LPC11C24', 'LPC812', 'NUCLEO_F030R8', + 'NUCLEO_F031K6', + 'NUCLEO_F042K6', 'NUCLEO_F070RB', 'NUCLEO_F072RB', 'NUCLEO_F091RC', 'NUCLEO_F103RB', 'NUCLEO_F302R8', + 'NUCLEO_F303K8', 'NUCLEO_F303RE', 'NUCLEO_F334R8', 'NUCLEO_F401RE', @@ -102,8 +114,10 @@ class Uvision4(Exporter): 'NUCLEO_L053R8', 'NUCLEO_L073RZ', 'NUCLEO_L152RE', + 'NUCLEO_L476RG', 'DISCO_L053C8', 'DISCO_F334C8', + 'DISCO_F469NI', 'DISCO_F746NG', 'DISCO_L476VG', 'LPC1549', @@ -113,6 +127,10 @@ class Uvision4(Exporter): 'LPC11U37H_401', 'MOTE_L152RC', 'NZ32SC151', + 'SAMR21G18A', + 'SAMD21J18A', + 'SAMD21G18A', + 'SAML21J18A', ] FILE_TYPES = { diff --git a/workspace_tools/export/uvision4_disco_f469ni.uvopt.tmpl b/workspace_tools/export/uvision4_disco_f469ni.uvopt.tmpl new file mode 100644 index 0000000000..11fb558708 --- /dev/null +++ b/workspace_tools/export/uvision4_disco_f469ni.uvopt.tmpl @@ -0,0 +1,205 @@ + + + + 1.0 + +
      ### uVision Project, (C) Keil Software
      + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + mbed_DISCO_F469NI + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U066FFF485149874987105040 -O206 -S1 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32F469NIHx$CMSIS\Flash\STM32F4xx_2048.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC1000 -FD20000000 -FF0STM32F4xx_2048 -FF1STM32F469_Quad_SPI -FL0200000 -FL12000000 -FS08000000 -FS190000000 -FP0($$Device:STM32F469NIHx$CMSIS\Flash\STM32F4xx_2048.FLM) -FP1($$Device:STM32F469NIHx$CMSIS\Flash\STM32F469_Quad_SPI.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + src + 0 + 0 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + main.cpp + main.cpp + 0 + 0 + + + +       diff --git a/workspace_tools/export/uvision4_disco_f469ni.uvproj.tmpl b/workspace_tools/export/uvision4_disco_f469ni.uvproj.tmpl new file mode 100644 index 0000000000..72c88c499b --- /dev/null +++ b/workspace_tools/export/uvision4_disco_f469ni.uvproj.tmpl @@ -0,0 +1,455 @@ + + + + 2.1 + +
      ### uVision Project, (C) Keil Software
      + + + + mbed_DISCO_F469NI + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + + + STM32F469NIHx + STMicroelectronics + Keil.STM32F4xx_DFP.2.3.7 + http://www.keil.com/pack + IROM(0x08000000,0x200000) IRAM(0x20000000,0x50000) IRAM2(0x10000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FF1STM32F469_Quad_SPI -FS190000000 -FL12000000 -FP0($$Device:STM32F469NIHx$CMSIS\Flash\STM32F4xx_2048.FLM) -FP1($$Device:STM32F469NIHx$CMSIS\Flash\STM32F469_Quad_SPI.FLM)) + 0 + $$Device:STM32F469NIHx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin -o build\{{name}}_NUCLEO_F302R8.bin build\{{name}}.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x50000 + + + 1 + 0x8000000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x50000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + + + {% endfor %} + + + {% endfor %} + + + + +       diff --git a/workspace_tools/export/uvision4_nucleo_f031k6.uvopt.tmpl b/workspace_tools/export/uvision4_nucleo_f031k6.uvopt.tmpl new file mode 100644 index 0000000000..2392aa1d52 --- /dev/null +++ b/workspace_tools/export/uvision4_nucleo_f031k6.uvopt.tmpl @@ -0,0 +1,218 @@ + + + + 1.0 + +
      ### uVision Project, (C) Keil Software
      + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed NUCLEO_F031K6 + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 13 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U0673FF545656726767125017 -I0 -O10446 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_32.FLM -FS08000000 -FL08000 -FP0($$Device:STM32F031K6$Flash\STM32F0xx_32.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_32 -FS08000000 -FL08000 -FP0($$Device:STM32F031K6$Flash\STM32F0xx_32.FLM)) + + + 0 + ULP2CM3 + -U -O207 -S8 -C0 -P00 -TO18 -TC10000000 -TP18 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32L1xx_256 -FS08000000 -FL040000 + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P128_48MHZ -FS00 -FL020000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + 0 + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + main.cpp + main.cpp + 0 + 0 + + + +       diff --git a/workspace_tools/export/uvision4_nucleo_f031k6.uvproj.tmpl b/workspace_tools/export/uvision4_nucleo_f031k6.uvproj.tmpl new file mode 100644 index 0000000000..3f979007ad --- /dev/null +++ b/workspace_tools/export/uvision4_nucleo_f031k6.uvproj.tmpl @@ -0,0 +1,440 @@ + + + + 1.1 + +
      ### uVision Project, (C) Keil Software
      + + + + mbed NUCLEO_F031K6 + 0x4 + ARM-ADS + + + STM32F031K6 + STMicroelectronics + Keil.STM32F0xx_DFP.1.4.0 + http://www.keil.com/pack/ + IRAM(0x20000000-0x20000FFF) IROM(0x8000000-0x8007FFF) CLOCK(8000000) CPUTYPE("Cortex-M0") + + "Startup\ST\STM32F0xx\startup_stm32f031.s" ("STM32F031 Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F0xx_32 -FS08000000 -FL08000) + 6560 + stm32f0xx.h + + + + + + + -DSTM32F031 + + + SFD\ST\STM32F0xx\STM32F0xx.sfr + 0 + 0 + + + + ST\STM32F0xx\ + ST\STM32F0xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_NUCLEO_F031K6.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 13 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4103 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1000 + + + 1 + 0x8000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + + + {% endfor %} + + + {% endfor %} + + + + +       diff --git a/workspace_tools/export/uvision4_nucleo_f042k6.uvopt.tmpl b/workspace_tools/export/uvision4_nucleo_f042k6.uvopt.tmpl new file mode 100644 index 0000000000..b32e88d6bc --- /dev/null +++ b/workspace_tools/export/uvision4_nucleo_f042k6.uvopt.tmpl @@ -0,0 +1,200 @@ + + + + 1.0 + +
      ### uVision Project, (C) Keil Software
      + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + mbed_NUCLEO_F042K6 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U066EFF575256867067012050 -O206 -S1 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_32.FLM -FS08000000 -FL08000 -FP0($$Device:STM32F042K6$Flash\STM32F0xx_32.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F0xx_32 -FL08000 -FS08000000 -FP0($$Device:STM32F042K6$Flash\STM32F0xx_32.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + + + src + 0 + 0 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + main.cpp + main.cpp + 0 + 0 + + + +       diff --git a/workspace_tools/export/uvision4_nucleo_f042k6.uvproj.tmpl b/workspace_tools/export/uvision4_nucleo_f042k6.uvproj.tmpl new file mode 100644 index 0000000000..13b2917f3e --- /dev/null +++ b/workspace_tools/export/uvision4_nucleo_f042k6.uvproj.tmpl @@ -0,0 +1,455 @@ + + + + 2.1 + +
      ### uVision Project, (C) Keil Software
      + + + + mbed_NUCLEO_F042K6 + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + + + STM32F042K6 + STMicroelectronics + Keil.STM32F0xx_DFP.1.4.0 + http://www.keil.com/pack/ + IROM(0x08000000,0x8000) IRAM(0x20000000,0x1800) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_32 -FS08000000 -FL08000 -FP0($$Device:STM32F042K6$Flash\STM32F0xx_32.FLM)) + 0 + $$Device:STM32F042K6$Device\Include\stm32f0xx.h + + + + + + + + + + $$Device:STM32F042K6$SVD\STM32F042x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_NUCLEO_F042K6.bin build\{{name}}.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1800 + + + 1 + 0x8000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + + + {% endfor %} + + + {% endfor %} + + + + +       diff --git a/workspace_tools/export/uvision4_nucleo_f302r8.uvproj.tmpl b/workspace_tools/export/uvision4_nucleo_f302r8.uvproj.tmpl index 73961b05d4..cce8bcbcf2 100644 --- a/workspace_tools/export/uvision4_nucleo_f302r8.uvproj.tmpl +++ b/workspace_tools/export/uvision4_nucleo_f302r8.uvproj.tmpl @@ -74,7 +74,7 @@ 0 - 0 + 1 0 fromelf --bin -o build\{{name}}_NUCLEO_F302R8.bin build\{{name}}.axf diff --git a/workspace_tools/export/uvision4_nucleo_f303k8.uvopt.tmpl b/workspace_tools/export/uvision4_nucleo_f303k8.uvopt.tmpl new file mode 100644 index 0000000000..21ff215a70 --- /dev/null +++ b/workspace_tools/export/uvision4_nucleo_f303k8.uvopt.tmpl @@ -0,0 +1,213 @@ + + + + 1.0 + +
      ### uVision Project, (C) Keil Software
      + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed NUCLEO_F303K8 + 0x4 + ARM-ADS + + 72000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 18 + + + 0 + STM32F3-Discovery Web Page (STM32F3-Discovery) + http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF254044 + + + 1 + STM32303C-EVAL Web Page (STM32303C-EVAL) + http://www.st.com/web/en/catalog/tools/PF252996 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 11 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U0667FF575256867067021844 -O206 -S1 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F3xx_256.FLM -FS08000000 -FL010000 -FP0($$Device:STM32F303K8$Flash\STM32F3xx_256.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F3xx_256 -FS08000000 -FL010000 -FP0($$Device:STM32F303K8$Flash\STM32F3xx_256.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + 0 + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + main.cpp + main.cpp + 0 + 0 + + + +       diff --git a/workspace_tools/export/uvision4_nucleo_f303k8.uvproj.tmpl b/workspace_tools/export/uvision4_nucleo_f303k8.uvproj.tmpl new file mode 100644 index 0000000000..18843b0b6e --- /dev/null +++ b/workspace_tools/export/uvision4_nucleo_f303k8.uvproj.tmpl @@ -0,0 +1,438 @@ + + + + 1.1 + +
      ### uVision Project, (C) Keil Software
      + + + + mbed NUCLEO_F303K8 + 0x4 + ARM-ADS + + + STM32F303K8 + STMicroelectronics + IROM(0x08000000,0x00010000) IRAM(0x20000000,0x00003000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F3xx_256 -FS08000000 -FL010000 -FP0($$Device:STM32F303K8$Flash\STM32F3xx_256.FLM)) + 0 + $$Device:STM32F303K8$Device\Include\stm32f3xx.h + + + + + + + + + + $$Device:STM32F303K8$SVD\STM32F303x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_NUCLEO_F303K8.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 11 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x3000 + + + 1 + 0x8000000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x3000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + + + {% endfor %} + + + {% endfor %} + + + + +       diff --git a/workspace_tools/export/uvision4_nucleo_f303re.uvproj.tmpl b/workspace_tools/export/uvision4_nucleo_f303re.uvproj.tmpl index 242baa9f57..78e6346584 100644 --- a/workspace_tools/export/uvision4_nucleo_f303re.uvproj.tmpl +++ b/workspace_tools/export/uvision4_nucleo_f303re.uvproj.tmpl @@ -74,9 +74,9 @@ 0 - 0 + 1 0 - fromelf --bin -o build\{{name}}_NUCLEO_F302R8.bin build\{{name}}.axf + fromelf --bin -o build\{{name}}_NUCLEO_F303RE.bin build\{{name}}.axf 0 0 diff --git a/workspace_tools/export/uvision4_nucleo_f334r8.uvproj.tmpl b/workspace_tools/export/uvision4_nucleo_f334r8.uvproj.tmpl index 02358bed09..5d00b8d1ab 100644 --- a/workspace_tools/export/uvision4_nucleo_f334r8.uvproj.tmpl +++ b/workspace_tools/export/uvision4_nucleo_f334r8.uvproj.tmpl @@ -74,7 +74,7 @@ 0 - 0 + 1 0 fromelf --bin -o build\{{name}}_NUCLEO_F334R8.bin build\{{name}}.axf diff --git a/workspace_tools/export/uvision4_samd21g18a.uvopt.tmpl b/workspace_tools/export/uvision4_samd21g18a.uvopt.tmpl new file mode 100644 index 0000000000..2b51d83533 --- /dev/null +++ b/workspace_tools/export/uvision4_samd21g18a.uvopt.tmpl @@ -0,0 +1,204 @@ + + + + 1.0 + +
      ### uVision Project, (C) Keil Software
      + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed SAMD21J18A + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 14 + + + 0 + Datasheet + datashts\Atmel\SAMD21\NotYetAvailable.pdf + + + 1 + Technical Reference Manual + datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF + + + 2 + Generic User Guide + datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-O207 -O207 -S9 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0ATSAMD21_256 -FL040000 -FS00 + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + +       diff --git a/workspace_tools/export/uvision4_samd21g18a.uvproj.tmpl b/workspace_tools/export/uvision4_samd21g18a.uvproj.tmpl new file mode 100644 index 0000000000..9ee921c987 --- /dev/null +++ b/workspace_tools/export/uvision4_samd21g18a.uvproj.tmpl @@ -0,0 +1,424 @@ + + + + 1.1 + +
      ### uVision Project, (C) Keil Software
      + + + + SAMD21G18A + 0x4 + ARM-ADS + + + SAMR21G18A + Atmel + IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0003FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") + + "Startup\Atmel\SAMD21\startup_SAMD21.s" ("Atmel SAMD21 Startup Code") + UL2CM3(-O207 -S9 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0ATSAMD21_256 -FS00 -FL040000) + 7341 + samd21.h + + + + + + + -D__SAMD21G18A__ + + + SFD\Atmel\SAMD21\ATSAMD21G18A.SFR + 0 + 0 + + + + Atmel\SAMD21\ + Atmel\SAMD21\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_SAMD21G18A.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + +       diff --git a/workspace_tools/export/uvision4_samd21j18a.uvopt.tmpl b/workspace_tools/export/uvision4_samd21j18a.uvopt.tmpl new file mode 100644 index 0000000000..7534de7329 --- /dev/null +++ b/workspace_tools/export/uvision4_samd21j18a.uvopt.tmpl @@ -0,0 +1,204 @@ + + + + 1.0 + +
      ### uVision Project, (C) Keil Software
      + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed SAMD21G18A + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 16 + + + 0 + Datasheet + datashts\Atmel\SAMD21\NotYetAvailable.pdf + + + 1 + Technical Reference Manual + datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF + + + 2 + Generic User Guide + datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-O207 -O207 -S9 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0ATSAMD21_256 -FL040000 -FS00 + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + +       diff --git a/workspace_tools/export/uvision4_samd21j18a.uvproj.tmpl b/workspace_tools/export/uvision4_samd21j18a.uvproj.tmpl new file mode 100644 index 0000000000..b623074161 --- /dev/null +++ b/workspace_tools/export/uvision4_samd21j18a.uvproj.tmpl @@ -0,0 +1,424 @@ + + + + 1.1 + +
      ### uVision Project, (C) Keil Software
      + + + + SAMD21G18A + 0x4 + ARM-ADS + + + SAMD21J18A + Atmel + IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0003FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") + + "Startup\Atmel\SAMD21\startup_SAMD21.s" ("Atmel SAMD21 Startup Code") + UL2CM3(-O207 -S9 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0ATSAMD21_256 -FS00 -FL040000) + 7346 + samd21.h + + + + + + + -D__SAMD21J18A__ + + + SFD\Atmel\SAMD21\ATSAMD21J18A.SFR + 0 + 0 + + + + Atmel\SAMD21\ + Atmel\SAMD21\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_SAMD21G18A.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + +       diff --git a/workspace_tools/export/uvision4_saml21j18a.uvopt.tmpl b/workspace_tools/export/uvision4_saml21j18a.uvopt.tmpl new file mode 100644 index 0000000000..9c442fc333 --- /dev/null +++ b/workspace_tools/export/uvision4_saml21j18a.uvopt.tmpl @@ -0,0 +1,204 @@ + + + + 1.0 + +
      ### uVision Project, (C) Keil Software
      + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed SAML21G18A + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 16 + + + 0 + Datasheet + datashts\Atmel\SAML21\NotYetAvailable.pdf + + + 1 + Technical Reference Manual + datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF + + + 2 + Generic User Guide + datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0ATSAML21_256 -FS00 -FL040000 -FF1ATSAML21_256_EEPROM -FS1400000 -FL12000 -FP0($$Device:ATSAML21J18A$Flash\ATSAML21_256.FLM) -FP1($$Device:ATSAML21J18A$Flash\ATSAML21_256_EEPROM.FLM)) + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + +       diff --git a/workspace_tools/export/uvision4_saml21j18a.uvproj.tmpl b/workspace_tools/export/uvision4_saml21j18a.uvproj.tmpl new file mode 100644 index 0000000000..1f195bd68f --- /dev/null +++ b/workspace_tools/export/uvision4_saml21j18a.uvproj.tmpl @@ -0,0 +1,424 @@ + + + + 1.1 + +
      ### uVision Project, (C) Keil Software
      + + + + SAMD21G18A + 0x4 + ARM-ADS + + + ATSAML21J18A + Atmel + IROM(0x00000000,0x40000) IRAM(0x20000000,0x08000) IRAM2(0x30000000,0x02000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + "Startup\Atmel\SAMD21\startup_SAMD21.s" ("Atmel SAMD21 Startup Code") + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0ATSAML21_256 -FS00 -FL040000 -FF1ATSAML21_256_EEPROM -FS1400000 -FL12000 -FP0($$Device:ATSAML21J18A$Flash\ATSAML21_256.FLM) -FP1($$Device:ATSAML21J18A$Flash\ATSAML21_256_EEPROM.FLM)) + 7346 + $$Device:ATSAML21J18A$Device\SAML21\Include\saml21.h + + + + + + + -D__SAML21J18A__ + + + $$Device:ATSAML21J18A$SVD\SAML21\ATSAML21J18A.svd + 0 + 0 + + + + Atmel\SAMD21\ + Atmel\SAMD21\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_SAMD21G18A.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + +       diff --git a/workspace_tools/export/uvision4_samr21g18a.uvopt.tmpl b/workspace_tools/export/uvision4_samr21g18a.uvopt.tmpl new file mode 100644 index 0000000000..94d61c23b4 --- /dev/null +++ b/workspace_tools/export/uvision4_samr21g18a.uvopt.tmpl @@ -0,0 +1,204 @@ + + + + 1.0 + +
      ### uVision Project, (C) Keil Software
      + + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed SAMR21G18A + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 14 + + + 0 + Datasheet + datashts\Atmel\SAMD21\NotYetAvailable.pdf + + + 1 + Technical Reference Manual + datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF + + + 2 + Generic User Guide + datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ULP2CM3 + -O207 -O207 -S9 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0ATSAMR21_256 -FL040000 -FS00 + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + +       diff --git a/workspace_tools/export/uvision4_samr21g18a.uvproj.tmpl b/workspace_tools/export/uvision4_samr21g18a.uvproj.tmpl new file mode 100644 index 0000000000..c400145e37 --- /dev/null +++ b/workspace_tools/export/uvision4_samr21g18a.uvproj.tmpl @@ -0,0 +1,424 @@ + + + + 1.1 + +
      ### uVision Project, (C) Keil Software
      + + + + SAMR21G18A + 0x4 + ARM-ADS + + + SAMR21G18A + Atmel + IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0003FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") + + "Startup\Atmel\SAMR21\startup_SAMR21.s" ("Atmel SAMR21 Startup Code") + UL2CM3(-O207 -S9 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0ATSAMR21_256 -FS00 -FL040000) + 7537 + samr21.h + + + + + + + -D__SAMR21G18A__ + + + SFD\Atmel\SAMR21\ATSAMR21G18A.SFR + 0 + 0 + + + + Atmel\SAMR21\ + Atmel\SAMR21\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_SAMR21G18A.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + +       diff --git a/workspace_tools/export_test.py b/workspace_tools/export_test.py old mode 100755 new mode 100644 index 16d118d46e..3e989d8674 --- a/workspace_tools/export_test.py +++ b/workspace_tools/export_test.py @@ -105,6 +105,7 @@ if __name__ == '__main__': ('coide', 'NUCLEO_F401RE'), ('coide', 'NUCLEO_F411RE'), ('coide', 'DISCO_F429ZI'), + ('coide', 'DISCO_F469NI'), ('coide', 'NUCLEO_F334R8'), ('coide', 'MTS_MDOT_F405RG'), ('coide', 'MTS_MDOT_F411RE'), @@ -120,11 +121,14 @@ if __name__ == '__main__': ('uvision', 'HRM1017'), ('uvision', 'NUCLEO_F030R8'), + ('uvision', 'NUCLEO_F031K6'), + ('uvision', 'NUCLEO_F042K6'), ('uvision', 'NUCLEO_F070RB'), ('uvision', 'NUCLEO_F072RB'), ('uvision', 'NUCLEO_F091RC'), ('uvision', 'NUCLEO_F103RB'), ('uvision', 'NUCLEO_F302R8'), + ('uvision', 'NUCLEO_F303K8'), ('uvision', 'NUCLEO_F303RE'), ('uvision', 'NUCLEO_F334R8'), ('uvision', 'NUCLEO_F401RE'), @@ -133,12 +137,14 @@ if __name__ == '__main__': ('uvision', 'NUCLEO_L053R8'), ('uvision', 'NUCLEO_L073RZ'), ('uvision', 'NUCLEO_L152RE'), + ('uvision', 'NUCLEO_L476RG'), ('uvision', 'MTS_MDOT_F405RG'), ('uvision', 'MAXWSNENV'), ('uvision', 'MAX32600MBED'), ('uvision', 'DISCO_L053C8'), ('uvision', 'DISCO_F334C8'), ('uvision', 'DISCO_F746NG'), + ('uvision', 'DISCO_F469NI'), ('uvision', 'DISCO_L476VG'), ('lpcxpresso', 'LPC1768'), @@ -177,12 +183,17 @@ if __name__ == '__main__': ('gcc_arm', 'DISCO_F334C8'), ('gcc_arm', 'DISCO_L053C8'), ('gcc_arm', 'DISCO_F746NG'), + ('gcc_arm', 'NUCLEO_F031K6'), + ('gcc_arm', 'NUCLEO_F042K6'), ('gcc_arm', 'NRF51822'), + ('gcc_arm', 'RBLAB_BLENANO') ('gcc_arm', 'HRM1017'), ('gcc_arm', 'NUCLEO_F401RE'), ('gcc_arm', 'NUCLEO_F411RE'), ('gcc_arm', 'NUCLEO_F446RE'), + ('gcc_arm', 'ELMO_F411RE'), ('gcc_arm', 'DISCO_F429ZI'), + ('gcc_arm', 'DISCO_F469NI'), ('gcc_arm', 'NUCLEO_F334R8'), ('gcc_arm', 'MAX32600MBED'), ('gcc_arm', 'MTS_MDOT_F405RG'), @@ -207,17 +218,22 @@ if __name__ == '__main__': ('gcc_arm', 'EFM32ZG_STK3200'), ('gcc_arm', 'EFM32HG_STK3400'), - ('ds5_5', 'LPC1768'), ('ds5_5', 'LPC11U24'), + ('ds5_5', 'LPC1768'), + ('ds5_5', 'LPC11U24'), + ('ds5_5', 'RZ_A1H'), ('iar', 'LPC1768'), ('iar', 'LPC4088_DM'), ('iar', 'LPC1347'), ('iar', 'NUCLEO_F030R8'), + ('iar', 'NUCLEO_F031K6'), + ('iar', 'NUCLEO_F042K6'), ('iar', 'NUCLEO_F070RB'), ('iar', 'NUCLEO_F072RB'), ('iar', 'NUCLEO_F091RC'), ('iar', 'NUCLEO_F302R8'), + ('iar', 'NUCLEO_F303K8'), ('iar', 'NUCLEO_F303RE'), ('iar', 'NUCLEO_F334R8'), ('iar', 'NUCLEO_F401RE'), @@ -226,8 +242,10 @@ if __name__ == '__main__': ('iar', 'NUCLEO_L053R8'), ('iar', 'NUCLEO_L073RZ'), ('iar', 'NUCLEO_L152RE'), + ('iar', 'NUCLEO_L476RG'), ('iar', 'DISCO_L053C8'), ('iar', 'DISCO_F334C8'), + ('iar', 'DISCO_F469NI'), ('iar', 'DISCO_F746NG'), ('iar', 'DISCO_L476VG'), ('iar', 'STM32F407'), diff --git a/workspace_tools/host_tests/host_test.py b/workspace_tools/host_tests/host_test.py index d11a40de4d..103df83924 100644 --- a/workspace_tools/host_tests/host_test.py +++ b/workspace_tools/host_tests/host_test.py @@ -35,6 +35,8 @@ import host_tests_plugins # we can find packages we want from the same level as other files do import sys sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), '../..'))) +from workspace_tools.test_api import get_autodetected_MUTS_list +from workspace_tools.test_api import get_module_avail class Mbed: @@ -89,6 +91,12 @@ class Mbed: type="int", help="When forcing a reset using option -r you can set up after reset timeout in seconds") + parser.add_option('', '--auto', + dest='auto_detect', + metavar=False, + action="store_true", + help='Use mbed-ls module to detect all connected mbed devices') + (self.options, _) = parser.parse_args() self.DEFAULT_RESET_TOUT = 0 @@ -126,6 +134,25 @@ class Mbed: serial_baud = serial_baud if serial_baud is not None else self.serial_baud serial_timeout = serial_timeout if serial_timeout is not None else self.serial_timeout + if get_module_avail('mbed_lstools') and self.options.auto_detect: + # Ensure serial port is up-to-date (try to find it 60 times) + found = False + + for i in range(0, 60): + print('Looking for %s with MBEDLS' % self.options.micro) + muts_list = get_autodetected_MUTS_list(platform_name_filter=[self.options.micro]) + + if 1 in muts_list: + mut = muts_list[1] + self.port = mut['port'] + found = True + break + else: + sleep(3) + + if not found: + return False + # Clear serial port if self.serial: self.serial.close() @@ -243,7 +270,6 @@ class Mbed: copy_method = copy_method if copy_method is not None else self.copy_method # Call proper copy method result = self.copy_image_raw(image_path, disk, copy_method) - sleep(self.program_cycle_s) return result def copy_image_raw(self, image_path=None, disk=None, copy_method=None): @@ -258,7 +284,7 @@ class Mbed: else: copy_method = 'shell' - result = host_tests_plugins.call_plugin('CopyMethod', copy_method, image_path=image_path, destination_disk=disk) + result = host_tests_plugins.call_plugin('CopyMethod', copy_method, image_path=image_path, destination_disk=disk, program_cycle_s=self.program_cycle_s, target_mcu=self.options.micro) return result; def flush(self): diff --git a/workspace_tools/host_tests/host_tests_plugins/__init__.py b/workspace_tools/host_tests/host_tests_plugins/__init__.py index 913da02648..c05241ae08 100644 --- a/workspace_tools/host_tests/host_tests_plugins/__init__.py +++ b/workspace_tools/host_tests/host_tests_plugins/__init__.py @@ -21,13 +21,19 @@ import host_test_registry import module_copy_mbed import module_copy_shell import module_copy_silabs + +try: + import module_copy_smart +except: + pass + #import module_copy_firefox -#import module_copy_mps2 +import module_copy_mps2 # Plugins used to reset certain platform import module_reset_mbed import module_reset_silabs -#import module_reset_mps2 +import module_reset_mps2 # Plugin registry instance @@ -37,12 +43,18 @@ HOST_TEST_PLUGIN_REGISTRY = host_test_registry.HostTestRegistry() # Some plugins are commented out if they are not stable or not commonly used HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_mbed.load_plugin()) HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_shell.load_plugin()) + +try: + HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_smart.load_plugin()) +except: + pass + HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_reset_mbed.load_plugin()) #HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_firefox.load_plugin()) # Extra platforms support -#HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_mps2.load_plugin()) -#HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_reset_mps2.load_plugin()) +HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_mps2.load_plugin()) +HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_reset_mps2.load_plugin()) HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_copy_silabs.load_plugin()) HOST_TEST_PLUGIN_REGISTRY.register_plugin(module_reset_silabs.load_plugin()) diff --git a/workspace_tools/host_tests/host_tests_plugins/module_copy_mbed.py b/workspace_tools/host_tests/host_tests_plugins/module_copy_mbed.py index 2b9527e95f..913ff3c425 100644 --- a/workspace_tools/host_tests/host_tests_plugins/module_copy_mbed.py +++ b/workspace_tools/host_tests/host_tests_plugins/module_copy_mbed.py @@ -17,6 +17,7 @@ limitations under the License. from shutil import copy from host_test_plugins import HostTestPluginBase +from time import sleep class HostTestPluginCopyMethod_Mbed(HostTestPluginBase): @@ -42,7 +43,7 @@ class HostTestPluginCopyMethod_Mbed(HostTestPluginBase): type = 'CopyMethod' stable = True capabilities = ['shutil', 'default'] - required_parameters = ['image_path', 'destination_disk'] + required_parameters = ['image_path', 'destination_disk', 'program_cycle_s'] def setup(self, *args, **kwargs): """ Configure plugin, this function should be called before plugin execute() method is used. @@ -60,9 +61,14 @@ class HostTestPluginCopyMethod_Mbed(HostTestPluginBase): if capability == 'shutil': image_path = kwargs['image_path'] destination_disk = kwargs['destination_disk'] + program_cycle_s = kwargs['program_cycle_s'] # Wait for mount point to be ready self.check_mount_point_ready(destination_disk) # Blocking result = self.generic_mbed_copy(image_path, destination_disk) + + # Allow mbed to cycle + sleep(program_cycle_s) + return result diff --git a/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py b/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py index f7768873f9..1d99f6e945 100644 --- a/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py +++ b/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py @@ -16,8 +16,10 @@ limitations under the License. """ import re +import os, shutil from os.path import join from host_test_plugins import HostTestPluginBase +from time import sleep class HostTestPluginCopyMethod_MPS2(HostTestPluginBase): @@ -77,10 +79,36 @@ class HostTestPluginCopyMethod_MPS2(HostTestPluginBase): # TODO: implement USB MSD restart detection pass + def copy_file(self, file, disk): + if not file: + return + + _, ext = os.path.splitext(file) + ext = ext.lower() + dfile = disk + "/SOFTWARE/mbed" + ext + + if os.path.isfile(dfile): + print('Remove old binary %s' % dfile) + os.remove(dfile) + + shutil.copy(file, dfile) + return True + + def touch_file(self, file): + """ Touch file and set timestamp to items + """ + tfile = file+'.tmp' + fhandle = open(tfile, 'a') + try: + fhandle.close() + finally: + os.rename(tfile, file) + return True + # Plugin interface name = 'HostTestPluginCopyMethod_MPS2' type = 'CopyMethod' - capabilities = ['mps2'] + capabilities = ['mps2-copy'] required_parameters = ['image_path', 'destination_disk'] def setup(self, *args, **kwargs): @@ -95,9 +123,24 @@ class HostTestPluginCopyMethod_MPS2(HostTestPluginBase): """ result = False if self.check_parameters(capabilitity, *args, **kwargs) is True: - if capabilitity == 'mps2': - # TODO: Implement MPS2 firmware setup here - pass + file = kwargs['image_path'] + disk = kwargs['destination_disk'] + + """ Add a delay in case there a test just finished + Prevents interface firmware hiccups + """ + sleep(10) + if capabilitity == 'mps2-copy' and self.copy_file(file, disk): + sleep(1) + if self.touch_file(disk + 'reboot.txt'): + """ Add a delay after the board was rebooted. + The actual reboot time is 20 seconds, but using 15 seconds + allows us to open the COM port and save a board reset. + This also prevents interface firmware hiccups. + """ + sleep(16) + result = True + return result diff --git a/workspace_tools/host_tests/host_tests_plugins/module_copy_shell.py b/workspace_tools/host_tests/host_tests_plugins/module_copy_shell.py index dbbc7365c0..18ca062a23 100644 --- a/workspace_tools/host_tests/host_tests_plugins/module_copy_shell.py +++ b/workspace_tools/host_tests/host_tests_plugins/module_copy_shell.py @@ -18,6 +18,7 @@ limitations under the License. import os from os.path import join, basename from host_test_plugins import HostTestPluginBase +from time import sleep class HostTestPluginCopyMethod_Shell(HostTestPluginBase): @@ -27,7 +28,7 @@ class HostTestPluginCopyMethod_Shell(HostTestPluginBase): type = 'CopyMethod' stable = True capabilities = ['shell', 'cp', 'copy', 'xcopy'] - required_parameters = ['image_path', 'destination_disk'] + required_parameters = ['image_path', 'destination_disk', 'program_cycle_s'] def setup(self, *args, **kwargs): """ Configure plugin, this function should be called before plugin execute() method is used. @@ -43,6 +44,7 @@ class HostTestPluginCopyMethod_Shell(HostTestPluginBase): if self.check_parameters(capability, *args, **kwargs) is True: image_path = kwargs['image_path'] destination_disk = kwargs['destination_disk'] + program_cycle_s = kwargs['program_cycle_s'] # Wait for mount point to be ready self.check_mount_point_ready(destination_disk) # Blocking # Prepare correct command line parameter values @@ -59,6 +61,10 @@ class HostTestPluginCopyMethod_Shell(HostTestPluginBase): result = self.run_command(["sync"]) else: result = self.run_command(cmd) + + # Allow mbed to cycle + sleep(program_cycle_s) + return result diff --git a/workspace_tools/host_tests/host_tests_plugins/module_copy_silabs.py b/workspace_tools/host_tests/host_tests_plugins/module_copy_silabs.py index 1572bbc6ee..494bcf494e 100644 --- a/workspace_tools/host_tests/host_tests_plugins/module_copy_silabs.py +++ b/workspace_tools/host_tests/host_tests_plugins/module_copy_silabs.py @@ -16,6 +16,7 @@ limitations under the License. """ from host_test_plugins import HostTestPluginBase +from time import sleep class HostTestPluginCopyMethod_Silabs(HostTestPluginBase): @@ -24,7 +25,7 @@ class HostTestPluginCopyMethod_Silabs(HostTestPluginBase): name = 'HostTestPluginCopyMethod_Silabs' type = 'CopyMethod' capabilities = ['eACommander', 'eACommander-usb'] - required_parameters = ['image_path', 'destination_disk'] + required_parameters = ['image_path', 'destination_disk', 'program_cycle_s'] def setup(self, *args, **kwargs): """ Configure plugin, this function should be called before plugin execute() method is used. @@ -41,6 +42,7 @@ class HostTestPluginCopyMethod_Silabs(HostTestPluginBase): if self.check_parameters(capabilitity, *args, **kwargs) is True: image_path = kwargs['image_path'] destination_disk = kwargs['destination_disk'] + program_cycle_s = kwargs['program_cycle_s'] if capabilitity == 'eACommander': cmd = [self.EACOMMANDER_CMD, '--serialno', destination_disk, @@ -52,6 +54,10 @@ class HostTestPluginCopyMethod_Silabs(HostTestPluginBase): '--usb', destination_disk, '--flash', image_path] result = self.run_command(cmd) + + # Allow mbed to cycle + sleep(program_cycle_s) + return result diff --git a/workspace_tools/host_tests/host_tests_plugins/module_copy_smart.py b/workspace_tools/host_tests/host_tests_plugins/module_copy_smart.py new file mode 100644 index 0000000000..9fb5970d46 --- /dev/null +++ b/workspace_tools/host_tests/host_tests_plugins/module_copy_smart.py @@ -0,0 +1,118 @@ +""" +mbed SDK +Copyright (c) 2011-2013 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +import os +import sys +from os.path import join, basename, exists, abspath, dirname +from time import sleep +from host_test_plugins import HostTestPluginBase + +sys.path.append(abspath(join(dirname(__file__), "../../../"))) +from workspace_tools.test_api import get_autodetected_MUTS_list + +class HostTestPluginCopyMethod_Smart(HostTestPluginBase): + + # Plugin interface + name = 'HostTestPluginCopyMethod_Smart' + type = 'CopyMethod' + stable = True + capabilities = ['smart'] + required_parameters = ['image_path', 'destination_disk', 'target_mcu'] + + def setup(self, *args, **kwargs): + """ Configure plugin, this function should be called before plugin execute() method is used. + """ + return True + + def execute(self, capability, *args, **kwargs): + """ Executes capability by name. + Each capability may directly just call some command line + program or execute building pythonic function + """ + result = False + if self.check_parameters(capability, *args, **kwargs) is True: + image_path = kwargs['image_path'] + destination_disk = kwargs['destination_disk'] + target_mcu = kwargs['target_mcu'] + # Wait for mount point to be ready + self.check_mount_point_ready(destination_disk) # Blocking + # Prepare correct command line parameter values + image_base_name = basename(image_path) + destination_path = join(destination_disk, image_base_name) + if capability == 'smart': + if os.name == 'posix': + cmd = ['cp', image_path, destination_path] + result = self.run_command(cmd, shell=False) + + cmd = ['sync'] + result = self.run_command(cmd, shell=False) + elif os.name == 'nt': + cmd = ['copy', image_path, destination_path] + result = self.run_command(cmd, shell=True) + + # Give the OS and filesystem time to settle down + sleep(3) + + platform_name_filter = [target_mcu] + muts_list = {} + + remount_complete = False + + for i in range(0, 60): + print('Looking for %s with MBEDLS' % target_mcu) + muts_list = get_autodetected_MUTS_list(platform_name_filter=platform_name_filter) + + if 1 in muts_list: + mut = muts_list[1] + destination_disk = mut['disk'] + destination_path = join(destination_disk, image_base_name) + + if mut['mcu'] == 'LPC1768' or mut['mcu'] == 'LPC11U24': + if exists(destination_disk) and exists(destination_path): + remount_complete = True + break; + else: + if exists(destination_disk) and not exists(destination_path): + remount_complete = True + break; + + sleep(1) + + if remount_complete: + print('Remount complete') + else: + print('Remount FAILED') + + if exists(destination_disk): + print('Disk exists') + else: + print('Disk does not exist') + + if exists(destination_path): + print('Image exists') + else: + print('Image does not exist') + + result = None + + + return result + +def load_plugin(): + """ Returns plugin available in this module + """ + return HostTestPluginCopyMethod_Smart() diff --git a/workspace_tools/host_tests/host_tests_plugins/module_reset_mps2.py b/workspace_tools/host_tests/host_tests_plugins/module_reset_mps2.py index 22938090bb..40ff267659 100644 --- a/workspace_tools/host_tests/host_tests_plugins/module_reset_mps2.py +++ b/workspace_tools/host_tests/host_tests_plugins/module_reset_mps2.py @@ -17,6 +17,7 @@ limitations under the License. import os from host_test_plugins import HostTestPluginBase +from time import sleep # Note: This plugin is not fully functional, needs improvements @@ -27,16 +28,21 @@ class HostTestPluginResetMethod_MPS2(HostTestPluginBase): shutdown.txt - shutdown from run mode. reset.txt - reset FPGA during run mode. """ - def touch_file(self, path): + def touch_file(self, file): """ Touch file and set timestamp to items """ - with open(path, 'a'): - os.utime(path, None) + tfile = file+'.tmp' + fhandle = open(tfile, 'a') + try: + fhandle.close() + finally: + os.rename(tfile, file) + return True # Plugin interface name = 'HostTestPluginResetMethod_MPS2' type = 'ResetMethod' - capabilities = ['reboot.txt', 'shutdown.txt', 'reset.txt'] + capabilities = ['mps2-reboot', 'mps2-reset'] required_parameters = ['disk'] def setup(self, *args, **kwargs): @@ -51,20 +57,18 @@ class HostTestPluginResetMethod_MPS2(HostTestPluginBase): Each capability may directly just call some command line program or execute building pythonic function """ + return True result = False if self.check_parameters(capabilitity, *args, **kwargs) is True: + disk = kwargs['disk'] + + if capabilitity == 'mps2-reboot' and self.touch_file(disk + 'reboot.txt'): + sleep(20) + result = True - if capabilitity == 'reboot.txt': - # TODO: Implement touch file for reboot - pass - - elif capabilitity == 'shutdown.txt': - # TODO: Implement touch file for shutdown - pass - - elif capabilitity == 'reset.txt': - # TODO: Implement touch file for reset - pass + elif capabilitity == 'mps2-reset' and self.touch_file(disk + 'reboot.txt'): + sleep(20) + result = True return result diff --git a/workspace_tools/singletest.py b/workspace_tools/singletest.py index afc856fdcf..ba9695ac1b 100644 --- a/workspace_tools/singletest.py +++ b/workspace_tools/singletest.py @@ -71,7 +71,7 @@ from workspace_tools.test_api import get_avail_tests_summary_table from workspace_tools.test_api import get_default_test_options_parser from workspace_tools.test_api import print_muts_configuration_from_json from workspace_tools.test_api import print_test_configuration_from_json -from workspace_tools.test_api import get_autodetected_MUTS +from workspace_tools.test_api import get_autodetected_MUTS_list from workspace_tools.test_api import get_autodetected_TEST_SPEC from workspace_tools.test_api import get_module_avail from workspace_tools.test_exporters import ReportExporter, ResultExporterType @@ -146,13 +146,12 @@ if __name__ == '__main__': # parameters like 'toolchains_filter' are also set. print "MBEDLS: Detecting connected mbed-enabled devices... " - if get_module_avail('mbed_lstools'): - mbeds = mbed_lstools.create() - muts_list = mbeds.list_mbeds_ext() if hasattr(mbeds, 'list_mbeds_ext') else mbeds.list_mbeds() - for mut in muts_list: - print "MBEDLS: Detected %s, port: %s, mounted: %s"% (mut['platform_name_unique'] if 'platform_name_unique' in mut else mut['platform_name'], - mut['serial_port'], - mut['mount_point']) + MUTs = get_autodetected_MUTS_list() + + for mut in MUTs.values(): + print "MBEDLS: Detected %s, port: %s, mounted: %s"% (mut['mcu_unique'] if 'mcu_unique' in mut else mut['mcu'], + mut['port'], + mut['disk']) # Set up parameters for test specification filter function (we need to set toolchains per target here) use_default_toolchain = 'default' in opts.toolchains_filter.split(',') if opts.toolchains_filter is not None else True @@ -160,17 +159,16 @@ if __name__ == '__main__': toolchain_filter = opts.toolchains_filter platform_name_filter = opts.general_filter_regex.split(',') if opts.general_filter_regex is not None else opts.general_filter_regex # Test specification with information about each target and associated toolchain - test_spec = get_autodetected_TEST_SPEC(muts_list, + test_spec = get_autodetected_TEST_SPEC(MUTs.values(), use_default_toolchain=use_default_toolchain, use_supported_toolchains=use_supported_toolchains, toolchain_filter=toolchain_filter, platform_name_filter=platform_name_filter) - # MUTs configuration auto-detection - MUTs = get_autodetected_MUTS(muts_list) else: # Open file with test specification # test_spec_filename tells script which targets and their toolchain(s) # should be covered by the test scenario + opts.auto_detect = False test_spec = get_json_data_from_file(opts.test_spec_filename) if opts.test_spec_filename else None if test_spec is None: if not opts.test_spec_filename: @@ -254,7 +252,8 @@ if __name__ == '__main__': _opts_jobs=opts.jobs, _opts_waterfall_test=opts.waterfall_test, _opts_consolidate_waterfall_test=opts.consolidate_waterfall_test, - _opts_extend_test_timeout=opts.extend_test_timeout) + _opts_extend_test_timeout=opts.extend_test_timeout, + _opts_auto_detect=opts.auto_detect) # Runs test suite in CLI mode if (singletest_in_cli_mode(single_test)): diff --git a/workspace_tools/synch.py b/workspace_tools/synch.py index a9102a6e02..fa6ee5f2f9 100644 --- a/workspace_tools/synch.py +++ b/workspace_tools/synch.py @@ -47,7 +47,7 @@ commit_msg = '' # Tuple data: (repo_name, list_of_code_dirs, [team]) # team is optional - if not specified, the code is published under mbed_official OFFICIAL_CODE = ( - ("mbed-src" , "mbed"), + ("mbed-dev" , "mbed"), ("mbed-rtos", "rtos"), ("mbed-dsp" , "dsp"), ("mbed-rpc" , "rpc"), diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 0f7c0a07da..b234197a22 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -562,6 +562,26 @@ class NUCLEO_F030R8(Target): self.supported_form_factors = ["ARDUINO", "MORPHO"] self.detect_code = ["0725"] +class NUCLEO_F031K6(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['STM', 'STM32F0', 'STM32F031K6'] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + self.detect_code = ["0791"] + +class NUCLEO_F042K6(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['STM', 'STM32F0', 'STM32F042K6'] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + self.detect_code = ["0785"] + class NUCLEO_F070RB(Target): def __init__(self): Target.__init__(self) @@ -612,6 +632,17 @@ class NUCLEO_F302R8(Target): self.supported_form_factors = ["ARDUINO", "MORPHO"] self.detect_code = ["0705"] +class NUCLEO_F303K8(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F3', 'STM32F303K8'] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + self.detect_code = ["0775"] + + class NUCLEO_F303RE(Target): def __init__(self): Target.__init__(self) @@ -651,6 +682,16 @@ class NUCLEO_F411RE(Target): self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO", "MORPHO"] self.detect_code = ["0740"] + +class ELMO_F411RE(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE'] + self.supported_toolchains = ["ARM", "uARM", "GCC_ARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + self.detect_code = ["----"] class NUCLEO_F446RE(Target): def __init__(self): @@ -692,6 +733,16 @@ class NUCLEO_L152RE(Target): self.supported_form_factors = ["ARDUINO", "MORPHO"] self.detect_code = ["0710"] +class NUCLEO_L476RG(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32L4', 'STM32L476RG'] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO", "MORPHO"] + self.detect_code = ["0765"] + class STM32F3XX(Target): def __init__(self): Target.__init__(self) @@ -767,6 +818,16 @@ class DISCO_F429ZI(Target): self.supported_toolchains = ["GCC_ARM", "IAR"] self.default_toolchain = "GCC_ARM" +class DISCO_F469NI(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M4F" + self.extra_labels = ['STM', 'STM32F4', 'STM32F469', 'STM32F469NI'] + self.supported_toolchains = ["ARM", "uARM", "IAR", "GCC_ARM"] + self.default_toolchain = "uARM" + self.supported_form_factors = ["ARDUINO"] + self.detect_code = ["0788"] + class DISCO_L053C8(Target): def __init__(self): Target.__init__(self) @@ -1068,23 +1129,39 @@ class MCU_NRF51_16K(MCU_NRF51_16K_BASE): self.extra_labels += ['MCU_NRF51_16K_S130'] self.macros += ['TARGET_MCU_NRF51_16K_S130'] -class MCU_NRF51_16K_S110(MCU_NRF51_16K_BASE): +class MCU_NRF51_S110: + """ Interface for overwriting the default SoftDevices """ def __init__(self): - MCU_NRF51_16K_BASE.__init__(self) + self.EXPECTED_SOFTDEVICES_WITH_OFFSETS = [ + { + 'name' : 's110_nrf51822_8.0.0_softdevice.hex', + 'boot' : 's110_nrf51822_8.0.0_bootloader.hex', + 'offset' : 0x18000 + }, + { + 'name' : 's110_nrf51822_7.1.0_softdevice.hex', + 'boot' : 's110_nrf51822_7.1.0_bootloader.hex', + 'offset' : 0x16000 + } + ] self.extra_labels += ['MCU_NRF51_16K_S110'] self.macros += ['TARGET_MCU_NRF51_16K_S110'] +class MCU_NRF51_16K_S110(MCU_NRF51_16K_BASE, MCU_NRF51_S110): + def __init__(self): + MCU_NRF51_16K_BASE.__init__(self) + MCU_NRF51_S110.__init__(self) + class MCU_NRF51_16K_BOOT(MCU_NRF51_16K_BOOT_BASE): def __init__(self): MCU_NRF51_16K_BOOT_BASE.__init__(self) self.extra_labels += ['MCU_NRF51_16K_S130'] self.macros += ['TARGET_MCU_NRF51_16K_S130'] -class MCU_NRF51_16K_BOOT_S110(MCU_NRF51_16K_BOOT_BASE): +class MCU_NRF51_16K_BOOT_S110(MCU_NRF51_16K_BOOT_BASE, MCU_NRF51_S110): def __init__(self): MCU_NRF51_16K_BOOT_BASE.__init__(self) - self.extra_labels += ['MCU_NRF51_16K_S110'] - self.macros += ['TARGET_MCU_NRF51_16K_S110'] + MCU_NRF51_S110.__init__(self) class MCU_NRF51_16K_OTA(MCU_NRF51_16K_OTA_BASE): def __init__(self): @@ -1092,11 +1169,10 @@ class MCU_NRF51_16K_OTA(MCU_NRF51_16K_OTA_BASE): self.extra_labels += ['MCU_NRF51_16K_S130'] self.macros += ['TARGET_MCU_NRF51_16K_S130'] -class MCU_NRF51_16K_OTA_S110(MCU_NRF51_16K_OTA_BASE): +class MCU_NRF51_16K_OTA_S110(MCU_NRF51_16K_OTA_BASE, MCU_NRF51_S110): def __init__(self): MCU_NRF51_16K_OTA_BASE.__init__(self) - self.extra_labels += ['MCU_NRF51_16K_S110'] - self.macros += ['TARGET_MCU_NRF51_16K_S110'] + MCU_NRF51_S110.__init__(self) # 32KB MCU version, e.g. Nordic nRF51-DK, nRF51-Dongle, etc. @@ -1307,7 +1383,7 @@ class NRF51_DK(MCU_NRF51_32K): class NRF51_DK_BOOT(MCU_NRF51_32K_BOOT): def __init__(self): MCU_NRF51_32K_BOOT.__init__(self) - self.extra_labels = ['NRF51_DK'] + self.extra_labels += ['NRF51_DK'] self.macros += ['TARGET_NRF51_DK'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.supported_form_factors = ["ARDUINO"] @@ -1315,7 +1391,7 @@ class NRF51_DK_BOOT(MCU_NRF51_32K_BOOT): class NRF51_DK_OTA(MCU_NRF51_32K_OTA): def __init__(self): MCU_NRF51_32K_OTA.__init__(self) - self.extra_labels = ['NRF51_DK'] + self.extra_labels += ['NRF51_DK'] self.macros += ['TARGET_NRF51_DK'] self.supported_toolchains = ["ARM", "GCC_ARM"] self.supported_form_factors = ["ARDUINO"] @@ -1327,30 +1403,18 @@ class NRF51_DONGLE(MCU_NRF51_32K): class NRF51_DONGLE_BOOT(MCU_NRF51_32K_BOOT): def __init__(self): MCU_NRF51_32K_BOOT.__init__(self) - self.extra_labels = ['NRF51_DONGLE'] + self.extra_labels += ['NRF51_DONGLE'] self.macros += ['TARGET_NRF51_DONGLE'] class NRF51_DONGLE_OTA(MCU_NRF51_32K_OTA): def __init__(self): MCU_NRF51_32K_OTA.__init__(self) - self.extra_labels = ['NRF51_DONGLE'] + self.extra_labels += ['NRF51_DONGLE'] self.macros += ['TARGET_NRF51_DONGLE'] class NRF51_MICROBIT(MCU_NRF51_16K_S110): def __init__(self): MCU_NRF51_16K_S110.__init__(self) - self.EXPECTED_SOFTDEVICES_WITH_OFFSETS = [ - { - 'name' : 's110_nrf51822_8.0.0_softdevice.hex', - 'boot' : 's110_nrf51822_8.0.0_bootloader.hex', - 'offset' : 0x18000 - }, - { - 'name' : 's110_nrf51822_7.1.0_softdevice.hex', - 'boot' : 's110_nrf51822_7.1.0_bootloader.hex', - 'offset' : 0x16000 - } - ] self.macros += ['TARGET_NRF_LFCLK_RC'] class NRF51_MICROBIT_BOOT(MCU_NRF51_16K_BOOT_S110): @@ -1389,16 +1453,6 @@ class NRF51_MICROBIT_B_OTA(MCU_NRF51_16K_OTA): class ARM_MPS2_Target(Target): def __init__(self): Target.__init__(self) - self.OUTPUT_EXT = 'axf' - - def init_hooks(self, hook, toolchain_name): - hook.hook_add_binary("replace", self.output_axf) - - @staticmethod - def output_axf(t_self, resources, elf, bin): - shutil.copy(elf, bin) - t_self.debug("Passing ELF file %s" % bin) - class ARM_MPS2_M0(ARM_MPS2_Target): def __init__(self): @@ -1453,6 +1507,15 @@ class ARM_MPS2_M7(ARM_MPS2_Target): self.macros = ['CMSDK_CM7'] self.supported_toolchains = ["ARM"] self.default_toolchain = "ARM" + +class ARM_MPS2_BEID(ARM_MPS2_Target): + def __init__(self): + ARM_MPS2_Target.__init__(self) + self.core = "Cortex-M3" + self.extra_labels = ['ARM_SSG', 'MPS2', 'MPS2_BEID'] + self.macros = ['CMSDK_BEID'] + self.supported_toolchains = ["ARM"] + self.default_toolchain = "ARM" class ARM_MPS2(ARM_MPS2_M4): pass @@ -1556,24 +1619,59 @@ class WIZWIKI_W7500(Target): self.default_toolchain = "ARM" self.supported_form_factors = ["ARDUINO"] +class WIZWIKI_W7500P(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500P'] + self.supported_toolchains = ["uARM", "ARM"] + self.default_toolchain = "ARM" + self.supported_form_factors = ["ARDUINO"] +class WIZWIKI_W7500ECO(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0" + self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500ECO'] + self.supported_toolchains = ["uARM", "ARM"] + self.default_toolchain = "ARM" + class SAMR21G18A(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M0+" - self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMR21'] + self.extra_labels = ['Atmel', 'SAM_CortexM0P', 'SAMR21'] self.macros = ['__SAMR21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true'] - self.supported_toolchains = ["GCC_ARM"] - self.default_toolchain = "GCC_ARM" + self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"] + self.default_toolchain = "ARM" class SAMD21J18A(Target): def __init__(self): Target.__init__(self) self.core = "Cortex-M0+" - self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMD21'] + self.extra_labels = ['Atmel', 'SAM_CortexM0P', 'SAMD21'] self.macros = ['__SAMD21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true'] - self.supported_toolchains = ["GCC_ARM"] - self.default_toolchain = "GCC_ARM" + self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"] + self.default_toolchain = "ARM" + +class SAMD21G18A(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['Atmel', 'SAM_CortexM0P', 'SAMD21'] + self.macros = ['__SAMD21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true'] + self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"] + self.default_toolchain = "ARM" + +class SAML21J18A(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['Atmel', 'SAM_CortexM0P', 'SAML21'] + self.macros = ['__SAML21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true'] + self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"] + self.default_toolchain = "ARM" + # Get a single instance for each target TARGETS = [ @@ -1628,19 +1726,24 @@ TARGETS = [ ### STMicro ### NUCLEO_F030R8(), + NUCLEO_F031K6(), + NUCLEO_F042K6(), NUCLEO_F070RB(), NUCLEO_F072RB(), NUCLEO_F091RC(), NUCLEO_F103RB(), NUCLEO_F302R8(), + NUCLEO_F303K8(), NUCLEO_F303RE(), NUCLEO_F334R8(), NUCLEO_F401RE(), NUCLEO_F411RE(), + ELMO_F411RE(), NUCLEO_F446RE(), NUCLEO_L053R8(), NUCLEO_L073RZ(), NUCLEO_L152RE(), + NUCLEO_L476RG(), STM32F3XX(), STM32F407(), DISCO_F051R8(), @@ -1651,6 +1754,7 @@ TARGETS = [ DISCO_F407VG(), # STM32F407 ARCH_MAX(), # STM32F407 DISCO_F429ZI(), + DISCO_F469NI(), DISCO_L053C8(), DISCO_L476VG(), MTS_MDOT_F405RG(), @@ -1697,7 +1801,11 @@ TARGETS = [ NRF51_DONGLE_BOOT(), # nRF51_32K NRF51_DONGLE_OTA(), # nRF51_32K NRF51_MICROBIT(), # nRF51_16K - S110 - NRF51_MICROBIT_B(), # nRF51_16K - default + NRF51_MICROBIT_BOOT(), # nRF51_16K - S110 + NRF51_MICROBIT_OTA(), # nRF51_16K - S110 + NRF51_MICROBIT_B(), # nRF51_16K - default + NRF51_MICROBIT_B_BOOT(),# nRF51_16K - default + NRF51_MICROBIT_B_OTA(), # nRF51_16K - default ### ARM ### @@ -1707,6 +1815,7 @@ TARGETS = [ ARM_MPS2_M3(), ARM_MPS2_M4(), ARM_MPS2_M7(), + ARM_MPS2_BEID(), ARM_MPS2(), ### Renesas ### @@ -1725,10 +1834,14 @@ TARGETS = [ ### WIZnet ### WIZWIKI_W7500(), + WIZWIKI_W7500P(), + WIZWIKI_W7500ECO(), ### Atmel ### SAMR21G18A(), SAMD21J18A(), + SAMD21G18A(), + SAML21J18A(), ] # Map each target name to its unique instance diff --git a/workspace_tools/test_api.py b/workspace_tools/test_api.py index 16302613c8..53cf938fa7 100644 --- a/workspace_tools/test_api.py +++ b/workspace_tools/test_api.py @@ -27,6 +27,7 @@ import random import optparse import datetime import threading +import ctypes from types import ListType from colorama import Fore, Back, Style from prettytable import PrettyTable @@ -180,7 +181,8 @@ class SingleTestRunner(object): _opts_jobs=None, _opts_waterfall_test=None, _opts_consolidate_waterfall_test=None, - _opts_extend_test_timeout=None): + _opts_extend_test_timeout=None, + _opts_auto_detect=None): """ Let's try hard to init this object """ from colorama import init @@ -240,6 +242,7 @@ class SingleTestRunner(object): self.opts_consolidate_waterfall_test = _opts_consolidate_waterfall_test self.opts_extend_test_timeout = _opts_extend_test_timeout self.opts_clean = _clean + self.opts_auto_detect = _opts_auto_detect # File / screen logger initialization self.logger = CLITestLogger(file_name=self.opts_log_file_name) # Default test logger @@ -855,26 +858,9 @@ class SingleTestRunner(object): print "Error: No Mbed available: MUT[%s]" % data['mcu'] return None - disk = mut.get('disk') - port = mut.get('port') - - if disk is None or port is None: - return None - - target_by_mcu = TARGET_MAP[mut['mcu']] - target_name_unique = mut['mcu_unique'] if 'mcu_unique' in mut else mut['mcu'] - # Some extra stuff can be declared in MUTs structure - reset_type = mut.get('reset_type') # reboot.txt, reset.txt, shutdown.txt - reset_tout = mut.get('reset_tout') # COPY_IMAGE -> RESET_PROC -> SLEEP(RESET_TOUT) - image_dest = mut.get('image_dest') # Image file destination DISK + IMAGE_DEST + BINARY_NAME - images_config = mut.get('images_config') # Available images selection via config file - mobo_config = mut.get('mobo_config') # Available board configuration selection e.g. core selection etc. + mcu = mut['mcu'] copy_method = mut.get('copy_method') # Available board configuration selection e.g. core selection etc. - # When the build and test system were separate, this was relative to a - # base network folder base path: join(NETWORK_BASE_PATH, ) - image_path = image - if self.db_logger: self.db_logger.reconnect() @@ -886,6 +872,46 @@ class SingleTestRunner(object): detailed_test_results = {} # { Loop_number: { results ... } } for test_index in range(test_loops): + + # If mbedls is available and we are auto detecting MUT info, + # update MUT info (mounting may changed) + if get_module_avail('mbed_lstools') and self.opts_auto_detect: + platform_name_filter = [mcu] + muts_list = {} + found = False + + for i in range(0, 60): + print('Looking for %s with MBEDLS' % mcu) + muts_list = get_autodetected_MUTS_list(platform_name_filter=platform_name_filter) + + if 1 not in muts_list: + sleep(3) + else: + found = True + break + + if not found: + print "Error: mbed not found with MBEDLS: %s" % data['mcu'] + return None + else: + mut = muts_list[1] + + disk = mut.get('disk') + port = mut.get('port') + + if disk is None or port is None: + return None + + target_by_mcu = TARGET_MAP[mut['mcu']] + target_name_unique = mut['mcu_unique'] if 'mcu_unique' in mut else mut['mcu'] + # Some extra stuff can be declared in MUTs structure + reset_type = mut.get('reset_type') # reboot.txt, reset.txt, shutdown.txt + reset_tout = mut.get('reset_tout') # COPY_IMAGE -> RESET_PROC -> SLEEP(RESET_TOUT) + + # When the build and test system were separate, this was relative to a + # base network folder base path: join(NETWORK_BASE_PATH, ) + image_path = image + # Host test execution start_host_exec_time = time() @@ -955,7 +981,7 @@ class SingleTestRunner(object): if self.db_logger: self.db_logger.disconnect() - return (self.shape_global_test_loop_result(test_all_result), + return (self.shape_global_test_loop_result(test_all_result, self.opts_waterfall_test and self.opts_consolidate_waterfall_test), target_name_unique, toolchain_name, test_id, @@ -1003,12 +1029,16 @@ class SingleTestRunner(object): test_loop_ok_result = test_all_result.count(self.TEST_RESULT_OK) return "%d/%d"% (test_loop_ok_result, test_loop_count) - def shape_global_test_loop_result(self, test_all_result): + def shape_global_test_loop_result(self, test_all_result, waterfall_and_consolidate): """ Reformats list of results to simple string """ result = self.TEST_RESULT_FAIL + if all(test_all_result[0] == res for res in test_all_result): result = test_all_result[0] + elif waterfall_and_consolidate and any(res == self.TEST_RESULT_OK for res in test_all_result): + result = self.TEST_RESULT_OK + return result def run_host_test(self, name, image_path, disk, port, duration, @@ -1066,6 +1096,9 @@ class SingleTestRunner(object): '-t', str(duration), '-C', str(program_cycle_s)] + if get_module_avail('mbed_lstools') and self.opts_auto_detect: + cmd += ['--auto'] + # Add extra parameters to host_test if copy_method is not None: cmd += ["-c", copy_method] @@ -1642,6 +1675,20 @@ def get_module_avail(module_name): return module_name in sys.modules.keys() +def get_autodetected_MUTS_list(platform_name_filter=None): + oldError = None + if os.name == 'nt': + # Disable Windows error box temporarily + oldError = ctypes.windll.kernel32.SetErrorMode(1) #note that SEM_FAILCRITICALERRORS = 1 + + mbeds = mbed_lstools.create() + detect_muts_list = mbeds.list_mbeds() + + if os.name == 'nt': + ctypes.windll.kernel32.SetErrorMode(oldError) + + return get_autodetected_MUTS(detect_muts_list, platform_name_filter=platform_name_filter) + def get_autodetected_MUTS(mbeds_list, platform_name_filter=None): """ Function detects all connected to host mbed-enabled devices and generates artificial MUTS file. If function fails to auto-detect devices it will return empty dictionary. @@ -1658,6 +1705,11 @@ def get_autodetected_MUTS(mbeds_list, platform_name_filter=None): # mbeds_list = [{'platform_name': 'NUCLEO_F302R8', 'mount_point': 'E:', 'target_id': '07050200623B61125D5EF72A', 'serial_port': u'COM34'}] index = 1 for mut in mbeds_list: + # Filter the MUTS if a filter is specified + + if platform_name_filter and not mut['platform_name'] in platform_name_filter: + continue + # For mcu_unique - we are assigning 'platform_name_unique' value from mbedls output (if its existing) # if not we are creating our own unique value (last few chars from platform's target_id). m = {'mcu': mut['platform_name'], @@ -1688,8 +1740,8 @@ def get_autodetected_TEST_SPEC(mbeds_list, result = {'targets': {} } for mut in mbeds_list: - mcu = mut['platform_name'] - if platform_name_filter is None or (platform_name_filter and mut['platform_name'] in platform_name_filter): + mcu = mut['mcu'] + if platform_name_filter is None or (platform_name_filter and mut['mcu'] in platform_name_filter): if mcu in TARGET_MAP: default_toolchain = TARGET_MAP[mcu].default_toolchain supported_toolchains = TARGET_MAP[mcu].supported_toolchains diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 08b5a7328b..e71118c0f4 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -144,7 +144,7 @@ TESTS = [ "automated": True, "peripherals": ["analog_loop"], "mcu": ["LPC1768", "LPC2368", "LPC2460", "KL25Z", "K64F", "K22F", "LPC4088", "LPC1549", - "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303RE", + "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303K8", "NUCLEO_F303RE", "NUCLEO_F334R8", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE", "NUCLEO_F411RE", "NUCLEO_F446RE", "DISCO_F407VG", "DISCO_F746NG", "ARCH_MAX", "MAX32600MBED"] }, @@ -654,10 +654,10 @@ TESTS = [ #"host_test": "wait_us_auto", "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", - "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", + "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", - "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], + "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], }, { "id": "RTOS_2", "description": "Mutex resource lock", @@ -667,10 +667,10 @@ TESTS = [ "automated": True, "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", - "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", + "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", - "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], + "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], }, { "id": "RTOS_3", "description": "Semaphore resource lock", @@ -680,10 +680,10 @@ TESTS = [ "automated": True, "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", - "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", + "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", - "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], + "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], }, { "id": "RTOS_4", "description": "Signals messaging", @@ -692,10 +692,10 @@ TESTS = [ "automated": True, "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", - "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", + "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", - "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], + "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], }, { "id": "RTOS_5", "description": "Queue messaging", @@ -704,10 +704,10 @@ TESTS = [ "automated": True, "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", - "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", + "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", - "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], + "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], }, { "id": "RTOS_6", "description": "Mail messaging", @@ -716,10 +716,10 @@ TESTS = [ "automated": True, "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", - "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", + "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", - "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], + "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], }, { "id": "RTOS_7", "description": "Timer", @@ -730,10 +730,10 @@ TESTS = [ #"host_test": "wait_us_auto", "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", - "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", + "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", - "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], + "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], }, { "id": "RTOS_8", "description": "ISR (Queue)", @@ -742,10 +742,10 @@ TESTS = [ "automated": True, "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "LPC2460", "LPC824", "SSCI824", "KL25Z", "KL05Z", "K64F", "KL46Z", - "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", + "RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F030R8", "NUCLEO_F070RB", - "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", - "DISCO_F401VC", "NUCLEO_F303RE", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], + "NUCLEO_L053R8", "DISCO_L053C8", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG"], }, { "id": "RTOS_9", "description": "SD File write-read", @@ -755,7 +755,7 @@ TESTS = [ "peripherals": ["SD"], "mcu": ["LPC1768", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H", - "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE"], + "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F401RE", "DISCO_F469NI"], }, # Networking Tests @@ -1049,6 +1049,7 @@ TESTS = [ "automated": True, #"host_test" : "detect_auto", }, + ] # Group tests with the same goals into categories diff --git a/workspace_tools/toolchains/gcc.py b/workspace_tools/toolchains/gcc.py index 637a057d77..d6746ccc4b 100644 --- a/workspace_tools/toolchains/gcc.py +++ b/workspace_tools/toolchains/gcc.py @@ -52,7 +52,7 @@ class GCC(mbedToolchain): self.cpu.append("-mthumb-interwork") self.cpu.append("-marm") self.cpu.append("-march=armv7-a") - self.cpu.append("-mfpu=vfpv3-d16") + self.cpu.append("-mfpu=vfpv3") self.cpu.append("-mfloat-abi=hard") self.cpu.append("-mno-unaligned-access") @@ -186,7 +186,7 @@ class GCC_ARM(GCC): self.ld.append("--specs=nano.specs") if target.name in ["LPC1768", "LPC4088", "LPC4088_DM", "LPC4330", "UBLOX_C027", "LPC2368"]: self.ld.extend(["-u _printf_float", "-u _scanf_float"]) - elif target.name in ["RZ_A1H", "ARCH_MAX", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F411RE", "NUCLEO_F446RE"]: + elif target.name in ["RZ_A1H", "ARCH_MAX", "DISCO_F407VG", "DISCO_F429ZI", "DISCO_F469NI", "NUCLEO_F401RE", "NUCLEO_F411RE", "NUCLEO_F446RE", "ELMO_F411RE", "MTS_MDOT_F411RE", "MTS_DRAGONFLY_F411RE"]: self.ld.extend(["-u_printf_float", "-u_scanf_float"]) self.sys_libs.append("nosys") diff --git a/workspace_tools/upload_results.py b/workspace_tools/upload_results.py new file mode 100644 index 0000000000..d93822bd2f --- /dev/null +++ b/workspace_tools/upload_results.py @@ -0,0 +1,178 @@ +""" +mbed SDK +Copyright (c) 2011-2013 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" +import sys +import argparse +import xml.etree.ElementTree as ET +import requests +import urlparse + +def create_headers(args): + return { 'X-Api-Key': args.api_key } + +def finish_command(command, response): + print(command, response.status_code, response.reason) + print(response.text) + + if response.status_code < 400: + sys.exit(0) + else: + sys.exit(2) + +def create_build(args): + build = {} + build['buildType'] = args.build_type + build['number'] = args.build_number + build['source'] = args.build_source + build['status'] = 'running' + + if build['buildType'] == 'Pull_Request': + build['buildType'] = 'Pull Request' + + r = requests.post(urlparse.urljoin(args.url, "api/builds"), headers=create_headers(args), json=build) + + if r.status_code < 400: + if args.property_file_format: + print("MBED_BUILD_ID=" + r.text) + else: + print(r.text) + + sys.exit(0) + else: + sys.exit(2) + +def finish_build(args): + data = {} + data['status'] = 'completed' + + r = requests.put(urlparse.urljoin(args.url, "api/builds/" + args.build_id), headers=create_headers(args), json=data) + finish_command('finish-build', r) + +def abort_build(args): + data = {} + data['status'] = 'aborted' + + r = requests.put(urlparse.urljoin(args.url, "api/builds/" + args.build_id), headers=create_headers(args), json=data) + finish_command('abort-build', r) + +def add_test_runs(args): + tree = None + + try: + tree = ET.parse(args.test_report) + except: + print(sys.exc_info()[0]) + print('Invalid path to test report.') + sys.exit(1) + + test_suites = tree.getroot() + + ts_data = {} + ts_data['testRuns'] = [] + + platforms_set = set() + toolchains_set = set() + testIds_set = set() + hostOses_set = set() + + hostOses_set.add(args.host_os) + + for test_suite in test_suites: + platform = "" + toolchain = "" + for properties in test_suite.findall('properties'): + for property in properties.findall('property'): + if property.attrib['name'] == 'target': + platform = property.attrib['value'] + platforms_set.add(platform) + elif property.attrib['name'] == 'toolchain': + toolchain = property.attrib['value'] + toolchains_set.add(toolchain) + + for test_case in test_suite.findall('testcase'): + testRun = {} + testRun['build'] = args.build_id + testRun['hostOs'] = args.host_os + testRun['platform'] = platform + testRun['toolchain'] = toolchain + testRun['test'] = test_case.attrib['classname'].split('.')[-1] + + testIds_set.add(testRun['test']) + + system_outs = test_case.findall('system-out') + + if system_outs: + testRun['output'] = system_outs[0].text + else: + testRun['output'] = "" + + errors = test_case.findall('error') + failures = test_case.findall('failure') + + if errors: + testRun['pass'] = False + testRun['result'] = errors[0].attrib['message'] + elif failures: + testRun['pass'] = False + testRun['result'] = failures[0].attrib['message'] + else: + testRun['pass'] = True + testRun['result'] = 'OK' + + ts_data['testRuns'].append(testRun) + + ts_data['platforms'] = list(platforms_set) + ts_data['toolchains'] = list(toolchains_set) + ts_data['testIds'] = list(testIds_set) + ts_data['hostOses'] = list(hostOses_set) + + r = requests.post(urlparse.urljoin(args.url, "api/testRuns"), headers=create_headers(args), json=ts_data) + finish_command('add-test-runs', r) + +def main(arguments): + # Register and parse command line arguments + parser = argparse.ArgumentParser() + parser.add_argument('-u', '--url', required=True, help='url to ci site') + parser.add_argument('-k', '--api-key', required=True, help='api-key for posting data') + + subparsers = parser.add_subparsers(help='subcommand help') + + create_build_parser = subparsers.add_parser('create-build', help='create a new build') + create_build_parser.add_argument('-b', '--build-number', required=True, help='build number') + create_build_parser.add_argument('-T', '--build-type', choices=['Nightly', 'Limited', 'Pull_Request'], required=True, help='type of build') + create_build_parser.add_argument('-s', '--build-source', required=True, help='url to source of build') + create_build_parser.add_argument('-p', '--property-file-format', action='store_true', help='print result in the property file format') + create_build_parser.set_defaults(func=create_build) + + finish_build_parser = subparsers.add_parser('finish-build', help='finish a running build') + finish_build_parser.add_argument('-b', '--build-id', required=True, help='build id') + finish_build_parser.set_defaults(func=finish_build) + + abort_build_parser = subparsers.add_parser('abort-build', help='abort a running build') + abort_build_parser.add_argument('-b', '--build-id', required=True, help='build id') + abort_build_parser.set_defaults(func=abort_build) + + add_test_runs_parser = subparsers.add_parser('add-test-runs', help='add test runs to a build') + add_test_runs_parser.add_argument('-b', '--build-id', required=True, help='build id') + add_test_runs_parser.add_argument('-t', '--test-report', required=True, help='path to junit xml test report') + add_test_runs_parser.add_argument('-o', '--host-os', required=True, help='host os on which test was run') + add_test_runs_parser.set_defaults(func=add_test_runs) + + args = parser.parse_args(arguments) + args.func(args) + +if __name__ == '__main__': + main(sys.argv[1:])